Merge tag 'amd-drm-next-5.14-2021-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.14-2021-06-09: amdgpu: - SR-IOV fixes - Smartshift updates - GPUVM TLB flush updates - 16bpc fixed point display fix for DCE11 - BACO cleanups and core refactoring - Aldebaran updates - Initial Yellow Carp support - RAS fixes - PM API cleanup - DC visual confirm updates - DC DP MST fixes - DC DML fixes - Misc code cleanups and bug fixes amdkfd: - Initial Yellow Carp support radeon: - memcpy_to/from_io fixes UAPI: - Add Yellow Carp chip family id Used internally in the kernel driver and by mesa Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210610031649.4006-1-alexander.deucher@amd.com
author: Dave Airlie <airlied@redhat.com> 2021-06-10 13:47:12 +1000
committer: Dave Airlie <airlied@redhat.com> 2021-06-10 13:47:13 +1000
commit: c707b73f0cfb1acc94a20389aecde65e6385349b (patch)
tree: be2d0069c38a87c4f2e6c4d3e7097d5ee672a3bb
parent: Merge tag 'drm-intel-next-2021-06-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (diff)
parent: drm/amdgpu/vcn: drop gfxoff control for VCN2+ (diff)
download: linux-dev-c707b73f0cfb1acc94a20389aecde65e6385349b.tar.xz
linux-dev-c707b73f0cfb1acc94a20389aecde65e6385349b.zip
220 files changed, 216987 insertions, 823 deletions
diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 2062a6023678..364680cdad2e 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -300,4 +300,25 @@ pcie_replay_count
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
    :doc: pcie_replay_count
 
++GPU SmartShift Information
+============================
+
+GPU SmartShift information via sysfs
+
+smartshift_apu_power
+--------------------
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+   :doc: smartshift_apu_power
 
+smartshift_dgpu_power
+---------------------
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+   :doc: smartshift_dgpu_power
+
+smartshift_bias
+---------------
+
+.. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
+   :doc: smartshift_bias
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6cf0fe871d6c..c56320e78c0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -75,7 +75,7 @@ amdgpu-y += \
 	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \
 	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \
 	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o \
-	beige_goby_reg_init.o
+	beige_goby_reg_init.o yellow_carp_reg_init.o
 
 # add DF block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 267e9e147a6c..c0316eaba547 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -211,6 +211,7 @@ extern int amdgpu_discovery;
 extern int amdgpu_mes;
 extern int amdgpu_noretry;
 extern int amdgpu_force_asic_type;
+extern int amdgpu_smartshift_bias;
 #ifdef CONFIG_HSA_AMD
 extern int sched_policy;
 extern bool debug_evictions;
@@ -268,6 +269,10 @@ extern int amdgpu_num_kcq;
 #define CIK_CURSOR_WIDTH 128
 #define CIK_CURSOR_HEIGHT 128
 
+/* smasrt shift bias level limits */
+#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
+#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
+
 struct amdgpu_device;
 struct amdgpu_ib;
 struct amdgpu_cs_parser;
@@ -1280,6 +1285,11 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
 int amdgpu_device_baco_enter(struct drm_device *dev);
 int amdgpu_device_baco_exit(struct drm_device *dev);
 
+void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring);
+void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring);
+
 /* atpx handler */
 #if defined(CONFIG_VGA_SWITCHEROO)
 void amdgpu_register_atpx_handler(void);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index cf62f43a03da..db16b3e83694 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -269,7 +269,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
 		uint64_t *size);
 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
+		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, bool *table_freed);
 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
 		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
 int amdgpu_amdkfd_gpuvm_sync_memory(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
index d39cff4a1fe3..1f5620cc3570 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c
@@ -95,8 +95,8 @@ static void program_sh_mem_settings_v10_3(struct kgd_dev *kgd, uint32_t vmid,
 
 	lock_srbm(kgd, 0, 0, 0, vmid);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+	WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+	WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
 	/* APE1 no longer exists on GFX9 */
 
 	unlock_srbm(kgd);
@@ -129,7 +129,7 @@ static int init_interrupts_v10_3(struct kgd_dev *kgd, uint32_t pipe_id)
 
 	lock_srbm(kgd, mec, pipe, 0, 0);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+	WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
 		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
 		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
 
@@ -212,10 +212,10 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 
 		pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
 			mec, pipe, queue_id);
-		value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
+		value = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
 		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
 			((mec << 5) | (pipe << 3) | queue_id | 0x80));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);
+		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, value);
 	}
 
 	/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
@@ -224,13 +224,13 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 
 	for (reg = hqd_base;
 	     reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
-		WREG32(reg, mqd_hqd[reg - hqd_base]);
+		WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
 
 
 	/* Activate doorbell logic before triggering WPTR poll. */
 	data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
 			     CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
 
 	if (wptr) {
 		/* Don't read wptr with get_user because the user
@@ -259,17 +259,17 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 		guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
 		guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
 
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
 		       lower_32_bits(guessed_wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
 		       upper_32_bits(guessed_wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
 		       lower_32_bits((uint64_t)wptr));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 		       upper_32_bits((uint64_t)wptr));
 		pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
 			 (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
-		WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+		WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
 		       (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
 	}
 
@@ -279,7 +279,7 @@ static int hqd_load_v10_3(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 			     CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
 
 	data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
+	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
 
 	release_queue(kgd);
 
@@ -350,7 +350,7 @@ static int hqd_dump_v10_3(struct kgd_dev *kgd,
 		if (WARN_ON_ONCE(i >= HQD_N_REGS))	\
 			break;				\
 		(*dump)[i][0] = (addr) << 2;		\
-		(*dump)[i++][1] = RREG32(addr);		\
+		(*dump)[i++][1] = RREG32_SOC15_IP(GC, addr);		\
 	} while (0)
 
 	*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -482,13 +482,13 @@ static bool hqd_is_occupied_v10_3(struct kgd_dev *kgd, uint64_t queue_address,
 	uint32_t low, high;
 
 	acquire_queue(kgd, pipe_id, queue_id);
-	act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+	act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 	if (act) {
 		low = lower_32_bits(queue_address >> 8);
 		high = upper_32_bits(queue_address >> 8);
 
-		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
-		   high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
+		if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
+		   high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
 			retval = true;
 	}
 	release_queue(kgd);
@@ -542,11 +542,11 @@ static int hqd_destroy_v10_3(struct kgd_dev *kgd, void *mqd,
 		break;
 	}
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
+	WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
 
 	end_jiffies = (utimeout * HZ / 1000) + jiffies;
 	while (true) {
-		temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+		temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
 		if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
 			break;
 		if (time_after(jiffies, end_jiffies)) {
@@ -626,7 +626,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
 
 	mutex_lock(&adev->grbm_idx_mutex);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
 	WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
 
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
@@ -636,7 +636,7 @@ static int wave_control_execute_v10_3(struct kgd_dev *kgd,
 	data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
 		SE_BROADCAST_WRITES, 1);
 
-	WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
+	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
 	mutex_unlock(&adev->grbm_idx_mutex);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 668a28b80a62..fdee98fae2ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -278,7 +278,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
 	write_seqcount_end(&resv->seq);
 
 	/* Drop the references to the removed fences or move them to ef_list */
-	for (i = j, k = 0; i < old->shared_count; ++i) {
+	for (i = j; i < old->shared_count; ++i) {
 		struct dma_fence *f;
 
 		f = rcu_dereference_protected(new->shared[i],
@@ -1070,7 +1070,8 @@ static void unmap_bo_from_gpuvm(struct kgd_mem *mem,
 
 static int update_gpuvm_pte(struct kgd_mem *mem,
 			    struct kfd_mem_attachment *entry,
-			    struct amdgpu_sync *sync)
+			    struct amdgpu_sync *sync,
+			    bool *table_freed)
 {
 	struct amdgpu_bo_va *bo_va = entry->bo_va;
 	struct amdgpu_device *adev = entry->adev;
@@ -1081,7 +1082,7 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
 		return ret;
 
 	/* Update the page tables  */
-	ret = amdgpu_vm_bo_update(adev, bo_va, false);
+	ret = amdgpu_vm_bo_update(adev, bo_va, false, table_freed);
 	if (ret) {
 		pr_err("amdgpu_vm_bo_update failed\n");
 		return ret;
@@ -1093,7 +1094,8 @@ static int update_gpuvm_pte(struct kgd_mem *mem,
 static int map_bo_to_gpuvm(struct kgd_mem *mem,
 			   struct kfd_mem_attachment *entry,
 			   struct amdgpu_sync *sync,
-			   bool no_update_pte)
+			   bool no_update_pte,
+			   bool *table_freed)
 {
 	int ret;
 
@@ -1110,7 +1112,7 @@ static int map_bo_to_gpuvm(struct kgd_mem *mem,
 	if (no_update_pte)
 		return 0;
 
-	ret = update_gpuvm_pte(mem, entry, sync);
+	ret = update_gpuvm_pte(mem, entry, sync, table_freed);
 	if (ret) {
 		pr_err("update_gpuvm_pte() failed\n");
 		goto update_gpuvm_pte_failed;
@@ -1608,7 +1610,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
 }
 
 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
-		struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv)
+		struct kgd_dev *kgd, struct kgd_mem *mem,
+		void *drm_priv, bool *table_freed)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
 	struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv);
@@ -1696,7 +1699,7 @@ int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
 			 entry->va, entry->va + bo_size, entry);
 
 		ret = map_bo_to_gpuvm(mem, entry, ctx.sync,
-				      is_invalid_userptr);
+				      is_invalid_userptr, table_freed);
 		if (ret) {
 			pr_err("Failed to map bo to gpuvm\n");
 			goto out_unreserve;
@@ -2146,7 +2149,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info)
 				continue;
 
 			kfd_mem_dmaunmap_attachment(mem, attachment);
-			ret = update_gpuvm_pte(mem, attachment, &sync);
+			ret = update_gpuvm_pte(mem, attachment, &sync, NULL);
 			if (ret) {
 				pr_err("%s: update PTE failed\n", __func__);
 				/* make sure this gets validated again */
@@ -2352,7 +2355,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
 				continue;
 
 			kfd_mem_dmaunmap_attachment(mem, attachment);
-			ret = update_gpuvm_pte(mem, attachment, &sync_obj);
+			ret = update_gpuvm_pte(mem, attachment, &sync_obj, NULL);
 			if (ret) {
 				pr_debug("Memory eviction: update PTE failed. Try again\n");
 				goto validate_map_fail;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index f6a8f0c5a52f..1476236f5c7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -662,7 +662,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
  * @error:	error number
  * @backoff:	indicator to backoff the reservation
  *
- * If error is set than unvalidate buffer, otherwise just free memory
+ * If error is set then unvalidate buffer, otherwise just free memory
  * used by parsing context.
  **/
 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
@@ -781,7 +781,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 	if (r)
 		return r;
 
-	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
+	r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false, NULL);
 	if (r)
 		return r;
 
@@ -792,7 +792,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 	if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 		bo_va = fpriv->csa_va;
 		BUG_ON(!bo_va);
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			return r;
 
@@ -811,7 +811,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 		if (bo_va == NULL)
 			continue;
 
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 736b8c121979..6a242ec3f7ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -84,6 +84,7 @@ MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/vangogh_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_gpu_info.bin");
 
 #define AMDGPU_RESUME_MS		2000
 
@@ -122,6 +123,7 @@ const char *amdgpu_asic_name[] = {
 	"VANGOGH",
 	"DIMGREY_CAVEFISH",
 	"BEIGE_GOBY",
+	"YELLOW_CARP",
 	"LAST",
 };
 
@@ -313,9 +315,9 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
 		if (write) {
 			memcpy_toio(addr, buf, count);
 			mb();
-			amdgpu_asic_flush_hdp(adev, NULL);
+			amdgpu_device_flush_hdp(adev, NULL);
 		} else {
-			amdgpu_asic_invalidate_hdp(adev, NULL);
+			amdgpu_device_invalidate_hdp(adev, NULL);
 			mb();
 			memcpy_fromio(buf, addr, count);
 		}
@@ -1884,6 +1886,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 		chip_name = "vangogh";
 		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
 	}
 
 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
@@ -2062,8 +2067,11 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
 	case  CHIP_DIMGREY_CAVEFISH:
 	case  CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		if (adev->asic_type == CHIP_VANGOGH)
 			adev->family = AMDGPU_FAMILY_VGH;
+		else if (adev->asic_type == CHIP_YELLOW_CARP)
+			adev->family = AMDGPU_FAMILY_YC;
 		else
 			adev->family = AMDGPU_FAMILY_NV;
 
@@ -3146,6 +3154,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 #endif
 		return amdgpu_dc != 0;
 #endif
@@ -5475,4 +5484,31 @@ bool amdgpu_device_load_pci_state(struct pci_dev *pdev)
 	return true;
 }
 
+void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring)
+{
+#ifdef CONFIG_X86_64
+	if (adev->flags & AMD_IS_APU)
+		return;
+#endif
+	if (adev->gmc.xgmi.connected_to_cpu)
+		return;
+
+	if (ring && ring->funcs->emit_hdp_flush)
+		amdgpu_ring_emit_hdp_flush(ring);
+	else
+		amdgpu_asic_flush_hdp(adev, ring);
+}
+
+void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
+		struct amdgpu_ring *ring)
+{
+#ifdef CONFIG_X86_64
+	if (adev->flags & AMD_IS_APU)
+		return;
+#endif
+	if (adev->gmc.xgmi.connected_to_cpu)
+		return;
 
+	amdgpu_asic_invalidate_hdp(adev, ring);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index ac7b37dfff5e..2b6a66c849d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -1056,7 +1056,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev,
 
 	return 0;
 err:
-	drm_err(dev, "Failed to init gem fb: %d\n", ret);
+	drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret);
 	rfb->base.obj[0] = NULL;
 	return ret;
 }
@@ -1090,7 +1090,7 @@ int amdgpu_display_gem_fb_verify_and_init(
 
 	return 0;
 err:
-	drm_err(dev, "Failed to verify and init gem fb: %d\n", ret);
+	drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret);
 	rfb->base.obj[0] = NULL;
 	return ret;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 809aa7641d7e..c080ba15ae77 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -173,6 +173,7 @@ int amdgpu_tmz = -1; /* auto */
 uint amdgpu_freesync_vid_mode;
 int amdgpu_reset_method = -1; /* auto */
 int amdgpu_num_kcq = -1;
+int amdgpu_smartshift_bias;
 
 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
index 8d1ad294cb02..2ca3c329de6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
@@ -121,6 +121,9 @@ static const struct file_operations amdgpu_fw_attestation_debugfs_ops = {
 
 static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev)
 {
+	if (adev->flags & AMD_IS_APU)
+		return 0;
+
 	if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 		return 1;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 34243e122d11..1313784605b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -250,7 +250,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
 		}
 	}
 	mb();
-	amdgpu_asic_flush_hdp(adev, NULL);
+	amdgpu_device_flush_hdp(adev, NULL);
 	for (i = 0; i < adev->num_vmhubs; i++)
 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 
@@ -337,7 +337,7 @@ void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
 	int i;
 
 	mb();
-	amdgpu_asic_flush_hdp(adev, NULL);
+	amdgpu_device_flush_hdp(adev, NULL);
 	for (i = 0; i < adev->num_vmhubs; i++)
 		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 1c3e3b608332..9cf4beaf646c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -612,7 +612,7 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
 
 	if (operation == AMDGPU_VA_OP_MAP ||
 	    operation == AMDGPU_VA_OP_REPLACE) {
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			goto error;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
index 66ebc2e3b2ad..beabab515836 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
@@ -34,6 +34,7 @@ struct amdgpu_gfxhub_funcs {
 	void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value);
 	void (*init)(struct amdgpu_device *adev);
 	int (*get_xgmi_info)(struct amdgpu_device *adev);
+	void (*utcl2_harvest)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_gfxhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 85b8bfb8857b..0174f7817ce2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -785,3 +785,22 @@ uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo
 {
 	return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
 }
+
+void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev)
+{
+	/* Some ASICs need to reserve a region of video memory to avoid access
+	 * from driver */
+	adev->mman.stolen_reserved_offset = 0;
+	adev->mman.stolen_reserved_size = 0;
+
+	switch (adev->asic_type) {
+	case CHIP_YELLOW_CARP:
+		if (amdgpu_discovery == 0) {
+			adev->mman.stolen_reserved_offset = 0x1ffb0000;
+			adev->mman.stolen_reserved_size = 64 * PAGE_SIZE;
+		}
+		break;
+	default:
+		break;
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 6aa1d52d3aee..e55201134a01 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -332,6 +332,7 @@ amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
 			      bool enable);
 
 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev);
+void amdgpu_gmc_get_reserved_allocation(struct amdgpu_device *adev);
 
 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev);
 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 77baf9b48d67..ec65ab0ddf89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -214,15 +214,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (job && ring->funcs->init_cond_exec)
 		patch_offset = amdgpu_ring_init_cond_exec(ring);
 
-#ifdef CONFIG_X86_64
-	if (!(adev->flags & AMD_IS_APU))
-#endif
-	{
-		if (ring->funcs->emit_hdp_flush)
-			amdgpu_ring_emit_hdp_flush(ring);
-		else
-			amdgpu_asic_flush_hdp(adev, ring);
-	}
+	amdgpu_device_flush_hdp(adev, ring);
 
 	if (need_ctx_switch)
 		status |= AMDGPU_HAVE_CTX_SWITCH;
@@ -259,10 +251,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 	if (job && ring->funcs->emit_frame_cntl)
 		amdgpu_ring_emit_frame_cntl(ring, false, secure);
 
-#ifdef CONFIG_X86_64
-	if (!(adev->flags & AMD_IS_APU))
-#endif
-		amdgpu_asic_invalidate_hdp(adev, ring);
+	amdgpu_device_invalidate_hdp(adev, ring);
 
 	if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE)
 		fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index c83f116edde2..b7a2070d90af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -76,7 +76,7 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
 		kfree(ubo->metadata);
 	}
 
-	kfree(bo);
+	kvfree(bo);
 }
 
 /**
@@ -541,7 +541,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 	BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
 
 	*bo_ptr = NULL;
-	bo = kzalloc(bp->bo_ptr_size, GFP_KERNEL);
+	bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
 	if (bo == NULL)
 		return -ENOMEM;
 	drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 3ff76cbaec8d..6046123d0562 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -118,6 +118,10 @@ static int psp_early_init(void *handle)
 	case CHIP_ALDEBARAN:
 		psp_v13_0_set_psp_funcs(psp);
 		break;
+	case CHIP_YELLOW_CARP:
+		psp_v13_0_set_psp_funcs(psp);
+		psp->autoload_supported = true;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -179,6 +183,12 @@ static int psp_sw_init(void *handle)
 			DRM_ERROR("Failed to load psp firmware!\n");
 			return ret;
 		}
+	} else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
+		ret = psp_init_ta_microcode(psp, "aldebaran");
+		if (ret) {
+			DRM_ERROR("Failed to initialize ta microcode!\n");
+			return ret;
+		}
 	}
 
 	ret = psp_memory_training_init(psp);
@@ -282,7 +292,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		goto exit;
 	}
 
-	amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+	amdgpu_device_invalidate_hdp(psp->adev, NULL);
 	while (*((unsigned int *)psp->fence_buf) != index) {
 		if (--timeout == 0)
 			break;
@@ -295,7 +305,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
 		if (ras_intr)
 			break;
 		usleep_range(10, 100);
-		amdgpu_asic_invalidate_hdp(psp->adev, NULL);
+		amdgpu_device_invalidate_hdp(psp->adev, NULL);
 	}
 
 	/* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
@@ -684,6 +694,8 @@ int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 
 	psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 	ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
+	if (ret)
+		DRM_ERROR("PSP failed to program reg id %d", reg);
 
 	kfree(cmd);
 	return ret;
@@ -2319,11 +2331,20 @@ static int psp_load_fw(struct amdgpu_device *adev)
 	if (!psp->cmd)
 		return -ENOMEM;
 
-	ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
-					AMDGPU_GEM_DOMAIN_GTT,
-					&psp->fw_pri_bo,
-					&psp->fw_pri_mc_addr,
-					&psp->fw_pri_buf);
+	if (amdgpu_sriov_vf(adev)) {
+		ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
+						AMDGPU_GEM_DOMAIN_VRAM,
+						&psp->fw_pri_bo,
+						&psp->fw_pri_mc_addr,
+						&psp->fw_pri_buf);
+	} else {
+		ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
+						AMDGPU_GEM_DOMAIN_GTT,
+						&psp->fw_pri_bo,
+						&psp->fw_pri_mc_addr,
+						&psp->fw_pri_buf);
+	}
+
 	if (ret)
 		goto failed;
 
@@ -2696,7 +2717,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
 	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
 	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 	write_frame->fence_value = index;
-	amdgpu_asic_flush_hdp(adev, NULL);
+	amdgpu_device_flush_hdp(adev, NULL);
 
 	/* Update the write Pointer in DWORDs */
 	psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5d0c57b9917f..80dff29f2bc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1725,6 +1725,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 				       NULL);
 	if (r)
 		return r;
+	r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset,
+				       adev->mman.stolen_reserved_size,
+				       AMDGPU_GEM_DOMAIN_VRAM,
+				       &adev->mman.stolen_reserved_memory,
+				       NULL);
+	if (r)
+		return r;
 
 	DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
 		 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
@@ -1794,6 +1801,9 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
 	amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
 	/* return the IP Discovery TMR memory back to VRAM */
 	amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
+	if (adev->mman.stolen_reserved_size)
+		amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory,
+				      NULL, NULL);
 	amdgpu_ttm_fw_reserve_vram_fini(adev);
 
 	amdgpu_vram_mgr_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 74a7021592c3..e69f3e8e06e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -84,6 +84,10 @@ struct amdgpu_mman {
 	struct amdgpu_bo	*stolen_extended_memory;
 	bool			keep_stolen_vga_memory;
 
+	struct amdgpu_bo	*stolen_reserved_memory;
+	uint64_t		stolen_reserved_offset;
+	uint64_t		stolen_reserved_size;
+
 	/* discovery */
 	uint8_t				*discovery_bin;
 	uint32_t			discovery_tmr_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 8b502ffd58dd..5eb84de588eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -404,6 +404,7 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_ALDEBARAN:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		if (!load_type)
 			return AMDGPU_FW_LOAD_DIRECT;
 		else
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index b812938c9322..647d2c31e8bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -50,6 +50,7 @@
 #define FIRMWARE_DIMGREY_CAVEFISH	"amdgpu/dimgrey_cavefish_vcn.bin"
 #define FIRMWARE_ALDEBARAN	"amdgpu/aldebaran_vcn.bin"
 #define FIRMWARE_BEIGE_GOBY	"amdgpu/beige_goby_vcn.bin"
+#define FIRMWARE_YELLOW_CARP	"amdgpu/yellow_carp_vcn.bin"
 
 MODULE_FIRMWARE(FIRMWARE_RAVEN);
 MODULE_FIRMWARE(FIRMWARE_PICASSO);
@@ -66,6 +67,7 @@ MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
+MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
 
 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
 
@@ -160,6 +162,12 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
 			adev->vcn.indirect_sram = true;
 		break;
+	case CHIP_YELLOW_CARP:
+		fw_name = FIRMWARE_YELLOW_CARP;
+		if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
+		    (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
+			adev->vcn.indirect_sram = true;
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -385,7 +393,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
 	}
 
 	if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
-		amdgpu_gfx_off_ctrl(adev, true);
 		amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
 		       AMD_PG_STATE_GATE);
 		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
@@ -405,7 +412,6 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 	atomic_inc(&adev->vcn.total_submission_cnt);
 
 	if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
-		amdgpu_gfx_off_ctrl(adev, false);
 		r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
 				true);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 777e8922ecf3..18246b5b6ee3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -910,7 +910,7 @@ static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
 		return r;
 
 	bo = &(*vmbo)->bo;
-	if (vm->is_compute_context && (adev->flags & AMD_IS_APU)) {
+	if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
 		(*vmbo)->shadow = NULL;
 		return 0;
 	}
@@ -1713,8 +1713,8 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 	if (r)
 		goto error_unlock;
 
-	amdgpu_res_first(res, offset, (last - start + 1) * AMDGPU_GPU_PAGE_SIZE,
-			 &cursor);
+	amdgpu_res_first(pages_addr ? NULL : res, offset,
+			 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
 	while (cursor.remaining) {
 		uint64_t tmp, num_entries, addr;
 
@@ -1764,12 +1764,12 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 
 		amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
 		start = tmp;
-	};
+	}
 
 	r = vm->update_funcs->commit(&params, fence);
 
 	if (table_freed)
-		*table_freed = params.table_freed;
+		*table_freed = *table_freed || params.table_freed;
 
 error_unlock:
 	amdgpu_vm_eviction_unlock(vm);
@@ -1827,6 +1827,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
  * @adev: amdgpu_device pointer
  * @bo_va: requested BO and VM object
  * @clear: if true clear the entries
+ * @table_freed: return true if page table is freed
  *
  * Fill in the page table entries for @bo_va.
  *
@@ -1834,7 +1835,7 @@ void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
  * 0 for success, -EINVAL for failure.
  */
 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
-			bool clear)
+			bool clear, bool *table_freed)
 {
 	struct amdgpu_bo *bo = bo_va->base.bo;
 	struct amdgpu_vm *vm = bo_va->base.vm;
@@ -1913,7 +1914,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
 						resv, mapping->start,
 						mapping->last, update_flags,
 						mapping->offset, mem,
-						pages_addr, last_update, NULL);
+						pages_addr, last_update, table_freed);
 		if (r)
 			return r;
 	}
@@ -2165,7 +2166,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 
 	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
 		/* Per VM BOs never need to bo cleared in the page tables */
-		r = amdgpu_vm_bo_update(adev, bo_va, false);
+		r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
 		if (r)
 			return r;
 	}
@@ -2184,7 +2185,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
 		else
 			clear = true;
 
-		r = amdgpu_vm_bo_update(adev, bo_va, clear);
+		r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL);
 		if (r)
 			return r;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index bee439dd673a..1f089da1e615 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -413,7 +413,7 @@ int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
 				struct dma_fence **fence, bool *free_table);
 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 			struct amdgpu_bo_va *bo_va,
-			bool clear);
+			bool clear, bool *table_freed);
 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
 			     struct amdgpu_bo *bo, bool evicted);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index 03a44be50dd7..e3fbf0f10add 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -110,7 +110,7 @@ static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
 {
 	/* Flush HDP */
 	mb();
-	amdgpu_asic_flush_hdp(p->adev, NULL);
+	amdgpu_device_flush_hdp(p->adev, NULL);
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 102f31526204..2d56b60bc058 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -173,6 +173,9 @@
 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 
+#define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
+#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
+
 #define GFX_RLCG_GC_WRITE_OLD	(0x8 << 28)
 #define GFX_RLCG_GC_WRITE	(0x0 << 28)
 #define GFX_RLCG_GC_READ	(0x1 << 28)
@@ -239,6 +242,13 @@ MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
+
 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
@@ -1485,8 +1495,15 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
 		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
 	scratch_reg3 = adev->rmmio +
 		       (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
-	spare_int = adev->rmmio +
-		    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
+
+	if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
+		spare_int = adev->rmmio +
+			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
+			     + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
+	} else {
+		spare_int = adev->rmmio +
+			    (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
+	}
 
 	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
 	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
@@ -3370,6 +3387,30 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
 };
 
+static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
+{
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
+};
+
 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
 {
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
@@ -3659,6 +3700,11 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
 						golden_settings_gc_10_3_vangogh,
 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
 		break;
+	case CHIP_YELLOW_CARP:
+		soc15_program_register_sequence(adev,
+						golden_settings_gc_10_3_3,
+						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
+		break;
 	case CHIP_DIMGREY_CAVEFISH:
 		soc15_program_register_sequence(adev,
                                                 golden_settings_gc_10_3_4,
@@ -3855,6 +3901,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.cp_fw_write_wait = true;
 		break;
 	default:
@@ -3972,6 +4019,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
 	case CHIP_BEIGE_GOBY:
 		chip_name = "beige_goby";
 		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
 	default:
 		BUG();
 	}
@@ -4541,6 +4591,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.config.max_hw_contexts = 8;
 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
@@ -4666,6 +4717,7 @@ static int gfx_v10_0_sw_init(void *handle)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.me.num_me = 1;
 		adev->gfx.me.num_pipe_per_me = 1;
 		adev->gfx.me.num_queue_per_pipe = 1;
@@ -4898,7 +4950,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
-			if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+			if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+				(adev->asic_type == CHIP_YELLOW_CARP)) &&
 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
 				continue;
 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
@@ -6174,6 +6227,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
@@ -6310,6 +6364,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 		case CHIP_VANGOGH:
 		case CHIP_DIMGREY_CAVEFISH:
 		case CHIP_BEIGE_GOBY:
+		case CHIP_YELLOW_CARP:
 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
 			break;
 		default:
@@ -6323,6 +6378,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
 		case CHIP_VANGOGH:
 		case CHIP_DIMGREY_CAVEFISH:
 		case CHIP_BEIGE_GOBY:
+		case CHIP_YELLOW_CARP:
 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
@@ -6420,6 +6476,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
 		tmp &= 0xffffff00;
 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
@@ -7148,6 +7205,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
 		}
 		break;
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		return true;
 	default:
 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
@@ -7182,6 +7240,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
@@ -7406,9 +7465,15 @@ static int gfx_v10_0_hw_fini(void *handle)
 	if (amdgpu_sriov_vf(adev)) {
 		gfx_v10_0_cp_gfx_enable(adev, false);
 		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
-		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
-		tmp &= 0xffffff00;
-		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+		if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
+			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
+			tmp &= 0xffffff00;
+			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
+		} else {
+			tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
+			tmp &= 0xffffff00;
+			WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
+		}
 
 		return 0;
 	}
@@ -7492,6 +7557,7 @@ static int gfx_v10_0_soft_reset(void *handle)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
 							GRBM_SOFT_RESET,
@@ -7545,6 +7611,7 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
 	mutex_lock(&adev->gfx.gpu_clock_mutex);
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
 			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
 		break;
@@ -7602,6 +7669,7 @@ static int gfx_v10_0_early_init(void *handle)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
 		break;
 	default:
@@ -7659,6 +7727,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 
 		/* wait for RLC_SAFE_MODE */
@@ -7694,6 +7763,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
 		break;
 	default:
@@ -7996,12 +8066,23 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
 	 * in refclk count. Note that RLC FW is modified to take 16 bits from
 	 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
 	 *
-	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
-	 * as part of CGPG enablement starting point.
+	 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
+	 * of CGPG enablement starting point.
+	 * Power/performance team will optimize it and might give a new value later.
 	 */
-	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
-		data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
-		WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+		switch (adev->asic_type) {
+		case CHIP_VANGOGH:
+			data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+			break;
+		case CHIP_YELLOW_CARP:
+			data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
+			WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
+			break;
+		default:
+			break;
+		}
 	}
 }
 
@@ -8065,6 +8146,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
 		amdgpu_gfx_off_ctrl(adev, enable);
 		break;
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		gfx_v10_cntl_pg(adev, enable);
 		amdgpu_gfx_off_ctrl(adev, enable);
 		break;
@@ -8091,6 +8173,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		gfx_v10_0_update_gfx_clock_gating(adev,
 						 state == AMD_CG_STATE_GATE);
 		break;
@@ -9197,14 +9280,15 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_NAVI10:
 	case CHIP_NAVI14:
-	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
 		break;
 	case CHIP_NAVI12:
+	case CHIP_SIENNA_CICHLID:
 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
 		break;
 	default:
@@ -9287,7 +9371,8 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
-			if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
+			if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
+				(adev->asic_type == CHIP_YELLOW_CARP)) &&
 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
 				continue;
 			mask = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fe5908f708cc..044076ec1d03 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -790,7 +790,8 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f
 static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
 			       u32 v, u32 acc_flags, u32 hwip)
 {
-	if (amdgpu_sriov_fullaccess(adev)) {
+	if ((acc_flags & AMDGPU_REGS_RLC) &&
+	    amdgpu_sriov_fullaccess(adev)) {
 		gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
 
 		return;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index a03fdd41212b..bda1542ef1dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -321,18 +321,6 @@ static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 
 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 {
-	if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) {
-		/*
-		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-		 * VF copy registers so vbios post doesn't program them, for
-		 * SRIOV driver need to program them
-		 */
-		WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE,
-			     adev->gmc.vram_start >> 24);
-		WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP,
-			     adev->gmc.vram_end >> 24);
-	}
-
 	/* GART Enable. */
 	gfxhub_v1_0_init_gart_aperture_regs(adev);
 	gfxhub_v1_0_init_system_aperture_regs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
index 41807817de7d..1a374ec0514a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
@@ -31,6 +31,9 @@
 
 #include "soc15_common.h"
 
+#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP				0x16f8
+#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX	0
+
 static const char *gfxhub_client_ids[] = {
 	"CB/DB",
 	"Reserved",
@@ -531,6 +534,42 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
 	return 0;
 }
 
+static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
+{
+	int i;
+	u32 tmp = 0, disabled_sa = 0;
+	u32 efuse_setting, vbios_setting;
+
+	u32 max_sa_mask = amdgpu_gfx_create_bitmask(
+		adev->gfx.config.max_sh_per_se *
+		adev->gfx.config.max_shader_engines);
+
+	if (adev->asic_type == CHIP_YELLOW_CARP) {
+		/* Get SA disabled bitmap from eFuse setting */
+		efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
+		efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
+		efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
+
+		/* Get SA disabled bitmap from VBIOS setting */
+		vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
+		vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
+		vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
+
+		disabled_sa |= efuse_setting | vbios_setting;
+		/* Make sure not to report harvested SAs beyond the max SA count */
+		disabled_sa &= max_sa_mask;
+
+		for (i = 0; disabled_sa > 0; i++) {
+			if (disabled_sa & 1)
+				tmp |= 0x3 << (i * 2);
+			disabled_sa >>= 1;
+		}
+		disabled_sa = tmp;
+
+		WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
+	}
+}
+
 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
 	.get_fb_location = gfxhub_v2_1_get_fb_location,
 	.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
@@ -540,4 +579,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
 	.set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,
 	.init = gfxhub_v2_1_init,
 	.get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
+	.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index db154bf083e2..4523df2785d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -675,6 +675,7 @@ static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
 {
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		adev->mmhub.funcs = &mmhub_v2_3_funcs;
 		break;
 	default:
@@ -691,6 +692,7 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
 		break;
 	default:
@@ -807,6 +809,7 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 		case CHIP_VANGOGH:
 		case CHIP_DIMGREY_CAVEFISH:
 		case CHIP_BEIGE_GOBY:
+		case CHIP_YELLOW_CARP:
 		default:
 			adev->gmc.gart_size = 512ULL << 20;
 			break;
@@ -875,6 +878,7 @@ static int gmc_v10_0_sw_init(void *handle)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->num_vmhubs = 2;
 		/*
 		 * To fulfill 4-level page support,
@@ -932,6 +936,7 @@ static int gmc_v10_0_sw_init(void *handle)
 		return r;
 
 	amdgpu_gmc_get_vbios_allocations(adev);
+	amdgpu_gmc_get_reserved_allocation(adev);
 
 	/* Memory manager */
 	r = amdgpu_bo_init(adev);
@@ -990,6 +995,7 @@ static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		break;
 	default:
 		break;
@@ -1053,6 +1059,13 @@ static int gmc_v10_0_hw_init(void *handle)
 	/* The sequence of these two function calls matters.*/
 	gmc_v10_0_init_golden_registers(adev);
 
+	/*
+	 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
+	 * register setup within GMC, or else system hang when harvesting SA.
+	 */
+	if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
+		adev->gfxhub.funcs->utcl2_harvest(adev);
+
 	r = gmc_v10_0_gart_enable(adev);
 	if (r)
 		return r;
@@ -1145,7 +1158,7 @@ static int gmc_v10_0_set_clockgating_state(void *handle,
 		return r;
 
 	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
-	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
+	    adev->asic_type <= CHIP_YELLOW_CARP)
 		return athub_v2_1_set_clockgating(adev, state);
 	else
 		return athub_v2_0_set_clockgating(adev, state);
@@ -1158,7 +1171,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
 	adev->mmhub.funcs->get_clockgating(adev, flags);
 
 	if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
-	    adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
+	    adev->asic_type <= CHIP_YELLOW_CARP)
 		athub_v2_1_get_clockgating(adev, flags);
 	else
 		athub_v2_0_get_clockgating(adev, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 68e6b6b8989a..7eb70d69f760 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1288,10 +1288,7 @@ static int gmc_v9_0_late_init(void *handle)
 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 					struct amdgpu_gmc *mc)
 {
-	u64 base = 0;
-
-	if (!amdgpu_sriov_vf(adev))
-		base = adev->mmhub.funcs->get_fb_location(adev);
+	u64 base = adev->mmhub.funcs->get_fb_location(adev);
 
 	/* add the xgmi offset of the physical node */
 	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index bd77794315bc..01c242c5abc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -49,10 +49,13 @@ static int jpeg_v3_0_set_powergating_state(void *handle,
 static int jpeg_v3_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-	u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
 
-	if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
-		return -ENOENT;
+	if (adev->asic_type != CHIP_YELLOW_CARP) {
+		u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
+
+		if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
+			return -ENOENT;
+	}
 
 	adev->jpeg.num_jpeg_inst = 1;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
index 6264934b67ac..f80a14a1b82d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
@@ -111,6 +111,9 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 	WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
+	if (amdgpu_sriov_vf(adev))
+		return;
+
 	/* Program the system aperture low logical page number. */
 	WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
@@ -129,8 +132,6 @@ static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 		WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 	}
-	if (amdgpu_sriov_vf(adev))
-		return;
 
 	/* Set default page address. */
 	value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
@@ -332,18 +333,6 @@ static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
 
 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
 {
-	if (amdgpu_sriov_vf(adev)) {
-		/*
-		 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
-		 * VF copy registers so vbios post doesn't program them, for
-		 * SRIOV driver need to program them
-		 */
-		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE,
-			     adev->gmc.vram_start >> 24);
-		WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP,
-			     adev->gmc.vram_end >> 24);
-	}
-
 	/* GART Enable. */
 	mmhub_v1_7_init_gart_aperture_regs(adev);
 	mmhub_v1_7_init_system_aperture_regs(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index 709ac576ac7e..88e457a150e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -92,6 +92,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
 		status);
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index baa2fd119e6e..530011622801 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -120,11 +120,23 @@ force_update_wptr_for_self_int(struct amdgpu_device *adev,
 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
 				   RB_USED_INT_THRESHOLD, threshold);
 
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
+			return;
+	} else {
+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);
+	}
+
 	ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);
 	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,
 				   RB_USED_INT_THRESHOLD, threshold);
-	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2, ih_rb_cntl))
+			return;
+	} else {
+		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);
+	}
+
 	WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl);
 }
 
@@ -153,10 +165,8 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
 		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
 
 	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
-		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
-			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
 			return -ETIMEDOUT;
-		}
 	} else {
 		WREG32(ih_regs->ih_rb_cntl, tmp);
 	}
@@ -328,6 +338,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
 			case CHIP_VANGOGH:
 			case CHIP_DIMGREY_CAVEFISH:
 			case CHIP_BEIGE_GOBY:
+			case CHIP_YELLOW_CARP:
 				ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid);
 				ih_chicken = REG_SET_FIELD(ih_chicken,
 						IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 598ce0e93627..8f2a315e7c73 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -28,6 +28,25 @@
 #include "nbio/nbio_7_2_0_sh_mask.h"
 #include <uapi/linux/kfd_ioctl.h>
 
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC				0x0015
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX		2
+#define regBIF_BX0_BIF_FB_EN_YC								0x0100
+#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX					2
+#define regBIF1_PCIE_MST_CTRL_3								0x4601c6
+#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX					5
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
+			0x1b
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
+			0x1c
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
+			0x08000000L
+#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
+			0x30000000L
+#define regBIF1_PCIE_TX_POWER_CTRL_1						0x460187
+#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX				5
+#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK		0x00000001L
+#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK	0x00000008L
+
 static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
 {
 	WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
@@ -38,7 +57,12 @@ static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
 
 static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 {
-	u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+	u32 tmp;
+
+	if (adev->asic_type == CHIP_YELLOW_CARP)
+		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
+	else
+		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
 
 	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
 	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -49,11 +73,19 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
 	if (enable)
-		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
-			     BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
-			     BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+		if (adev->asic_type == CHIP_YELLOW_CARP)
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
+				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+		else
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
+				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
 	else
-		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+		if (adev->asic_type == CHIP_YELLOW_CARP)
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
+		else
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
 }
 
 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
@@ -92,13 +124,13 @@ static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do
 
 	if (use_doorbell) {
 		doorbell_range = REG_SET_FIELD(doorbell_range,
-					       GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
-					       doorbell_index);
+							GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
+							doorbell_index);
 		doorbell_range = REG_SET_FIELD(doorbell_range,
-					       GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
+							GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
 	} else {
 		doorbell_range = REG_SET_FIELD(doorbell_range,
-					       GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
+							GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
 	}
 
 	WREG32_PCIE_PORT(reg, doorbell_range);
@@ -123,22 +155,22 @@ static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
 
 	if (enable) {
 		tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-				    DOORBELL_SELFRING_GPA_APER_EN, 1) |
-		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-				    DOORBELL_SELFRING_GPA_APER_MODE, 1) |
-		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-				    DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+				DOORBELL_SELFRING_GPA_APER_EN, 1) |
+			REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+			REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 
 		WREG32_SOC15(NBIO, 0,
-			     regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
-			     lower_32_bits(adev->doorbell.base));
+			regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
+			lower_32_bits(adev->doorbell.base));
 		WREG32_SOC15(NBIO, 0,
-			     regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
-			     upper_32_bits(adev->doorbell.base));
+			regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+			upper_32_bits(adev->doorbell.base));
 	}
 
 	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
-		     tmp);
+		tmp);
 }
 
 
@@ -218,19 +250,42 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 {
 	uint32_t def, data;
 
-	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
-	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
-		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
-			 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
-			 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+	if (adev->asic_type == CHIP_YELLOW_CARP) {
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+			data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
+		else
+			data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
+
+		data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
+		def = data;
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+			data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
+				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
+		else
+			data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
+				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
+				data);
 	} else {
-		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
-			  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
-			  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
+			data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+				 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+				 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+		else
+			data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
+				  PCIE_CNTL2__MST_MEM_LS_EN_MASK |
+				  PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
 	}
-
-	if (def != data)
-		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
 }
 
 static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
@@ -297,14 +352,25 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
 {
 	uint32_t def, data;
-
-	def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
-	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
-	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
-
-	if (def != data)
-		WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
-				 data);
+	if (adev->asic_type == CHIP_YELLOW_CARP) {
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
+		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
+	} else {
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
+		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
+			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+		if (def != data)
+			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
+	}
 }
 
 const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 27ba0408a2aa..455d0425787c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -329,6 +329,7 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 	case CHIP_NAVY_FLOUNDER:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		if (encode)
 			*codecs = &nv_video_codecs_encode;
 		else
@@ -633,6 +634,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_VANGOGH:
+	case CHIP_YELLOW_CARP:
 		return AMD_RESET_METHOD_MODE2;
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
@@ -782,6 +784,9 @@ legacy_init:
 	case CHIP_BEIGE_GOBY:
 		beige_goby_reg_base_init(adev);
 		break;
+	case CHIP_YELLOW_CARP:
+		yellow_carp_reg_base_init(adev);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -985,6 +990,26 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 		break;
+	case CHIP_YELLOW_CARP:
+		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
+		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
+		if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+			amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+		amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
+		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
+			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
+#if defined(CONFIG_DRM_AMD_DC)
+		else if (amdgpu_device_has_dc_support(adev))
+			amdgpu_device_ip_block_add(adev, &dm_ip_block);
+#endif
+		amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+		amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -1309,6 +1334,32 @@ static int nv_common_early_init(void *handle)
 			AMD_PG_SUPPORT_MMHUB;
 		adev->external_rev_id = adev->rev_id + 0x46;
 		break;
+	case CHIP_YELLOW_CARP:
+		adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_MGLS |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_GFX_3D_CGCG |
+			AMD_CG_SUPPORT_GFX_3D_CGLS |
+			AMD_CG_SUPPORT_GFX_RLC_LS |
+			AMD_CG_SUPPORT_GFX_CP_LS |
+			AMD_CG_SUPPORT_GFX_FGCG |
+			AMD_CG_SUPPORT_MC_MGCG |
+			AMD_CG_SUPPORT_MC_LS |
+			AMD_CG_SUPPORT_SDMA_LS |
+			AMD_CG_SUPPORT_HDP_MGCG |
+			AMD_CG_SUPPORT_HDP_LS |
+			AMD_CG_SUPPORT_ATHUB_MGCG |
+			AMD_CG_SUPPORT_ATHUB_LS |
+			AMD_CG_SUPPORT_IH_CG |
+			AMD_CG_SUPPORT_VCN_MGCG |
+			AMD_CG_SUPPORT_JPEG_MGCG;
+		adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
+			AMD_PG_SUPPORT_VCN |
+			AMD_PG_SUPPORT_VCN_DPG |
+			AMD_PG_SUPPORT_JPEG;
+		adev->external_rev_id = adev->rev_id + 0x01;
+		break;
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.h b/drivers/gpu/drm/amd/amdgpu/nv.h
index 330438388fde..eb9aff1e7253 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/nv.h
@@ -37,4 +37,6 @@ int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);
 void vangogh_reg_base_init(struct amdgpu_device *adev);
 int dimgrey_cavefish_reg_base_init(struct amdgpu_device *adev);
 int beige_goby_reg_base_init(struct amdgpu_device *adev);
+int yellow_carp_reg_base_init(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index fcdce46445d6..c8949add88f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -31,6 +31,9 @@
 
 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
 
 static int psp_v13_0_init_microcode(struct psp_context *psp)
 {
@@ -42,17 +45,37 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
 	case CHIP_ALDEBARAN:
 		chip_name = "aldebaran";
 		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
+	default:
+		BUG();
+	}
+	switch (adev->asic_type) {
+	case CHIP_ALDEBARAN:
+		err = psp_init_sos_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_ta_microcode(&adev->psp, chip_name);
+		if (err)
+			return err;
+		break;
+	case CHIP_YELLOW_CARP:
+		err = psp_init_asd_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_toc_microcode(psp, chip_name);
+		if (err)
+			return err;
+		err = psp_init_ta_microcode(psp, chip_name);
+		if (err)
+			return err;
+		break;
 	default:
 		BUG();
 	}
 
-	err = psp_init_sos_microcode(psp, chip_name);
-	if (err)
-		return err;
-
-	err = psp_init_ta_microcode(&adev->psp, chip_name);
-
-	return err;
+	return 0;
 }
 
 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 98059bce692f..7486e5306786 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -50,6 +50,7 @@ MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
 
 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
+MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
 
 #define SDMA1_REG_OFFSET 0x600
 #define SDMA3_REG_OFFSET 0x400
@@ -94,6 +95,7 @@ static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		break;
 	default:
 		break;
@@ -165,6 +167,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 	case CHIP_BEIGE_GOBY:
 		chip_name = "beige_goby";
 		break;
+	case CHIP_YELLOW_CARP:
+		chip_name = "yellow_carp";
+		break;
 	default:
 		BUG();
 	}
@@ -495,12 +500,12 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 		amdgpu_ttm_set_buffer_funcs_status(adev, false);
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
-		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
-		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 	}
 }
 
@@ -558,11 +563,11 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 		if (enable && amdgpu_sdma_phase_quantum) {
-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 			       phase_quantum);
-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 			       phase_quantum);
-			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
+			WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 			       phase_quantum);
 		}
 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
@@ -620,62 +625,62 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		ring = &adev->sdma.instance[i].ring;
 		wb_offset = (ring->rptr_offs * 4);
 
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 
 		/* Set ring buffer size in dwords */
 		rb_bufsz = order_base_2(ring->ring_size / 4);
-		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+		rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 #ifdef __BIG_ENDIAN
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
 #endif
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
 		/* Initialize the ring buffer's read and write pointers */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 
 		/* setup the wptr shadow polling */
 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 		       lower_32_bits(wptr_gpu_addr));
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 		       upper_32_bits(wptr_gpu_addr));
-		wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
+		wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
 							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 					       F32_POLL_ENABLE, 1);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 		       wptr_poll_cntl);
 
 		/* set the wb address whether it's enabled or not */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 
 		ring->wptr = 0;
 
 		/* before programing wptr to a less value, need set minor_ptr_update first */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 
 		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 		}
 
-		doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
-		doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
+		doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
+		doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 
 		if (ring->use_doorbell) {
 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
@@ -684,8 +689,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		} else {
 			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 		}
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 
 		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 						      ring->doorbell_index,
@@ -695,7 +700,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 			sdma_v5_2_ring_set_wptr(ring);
 
 		/* set minor_ptr_update to 0 after wptr programed */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 
 		/* set utc l1 enable flag always to 1 */
 		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
@@ -706,19 +711,19 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 
 		/* Set up RESP_MODE to non-copy addresses */
-		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
+		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 
 		/* program default cache read and write policy */
-		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
+		temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 		/* clean read policy and write policy bits */
 		temp &= 0xFF0FFF;
 		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 			 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 
 		if (!amdgpu_sriov_vf(adev)) {
 			/* unhalt engine */
@@ -729,15 +734,15 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 
 		/* enable DMA RB */
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 
-		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+		ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 #ifdef __BIG_ENDIAN
 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 #endif
 		/* enable DMA IBs */
-		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+		WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 
 		ring->sched.ready = true;
 
@@ -1229,6 +1234,7 @@ static int sdma_v5_2_early_init(void *handle)
 		break;
 	case CHIP_VANGOGH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		adev->sdma.num_instances = 1;
 		break;
 	default:
@@ -1630,6 +1636,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		sdma_v5_2_update_medium_grain_clock_gating(adev,
 				state == AMD_CG_STATE_GATE);
 		sdma_v5_2_update_medium_grain_light_sleep(adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index c781808e4dc3..0eeb5e073be8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -28,12 +28,12 @@
 #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
 
 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
-	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
+	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_wreg) ? \
 	 adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
 	 WREG32(reg, value))
 
 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
-	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
+	((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->rlcg_rreg) ? \
 	 adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
 	 RREG32(reg))
 
diff --git a/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c b/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c
new file mode 100644
index 000000000000..3d89421275ed
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/yellow_carp_reg_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "amdgpu.h"
+#include "nv.h"
+
+#include "soc15_common.h"
+#include "soc15_hw_ip.h"
+#include "yellow_carp_offset.h"
+
+int yellow_carp_reg_base_init(struct amdgpu_device *adev)
+{
+	/* HW has more IP blocks,  only initialized the block needed by driver */
+	uint32_t i;
+	for (i = 0 ; i < MAX_INSTANCE ; ++i) {
+		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
+		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
+		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
+		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
+		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
+		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
+		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
+		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
+		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
+		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
+		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
+		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
+		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
+		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
+	}
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 059c3f1ca27d..cf483c0db687 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -1393,6 +1393,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
 	long err = 0;
 	int i;
 	uint32_t *devices_arr = NULL;
+	bool table_freed = false;
 
 	dev = kfd_device_by_id(GET_GPU_ID(args->handle));
 	if (!dev)
@@ -1450,7 +1451,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
 			goto get_mem_obj_from_handle_failed;
 		}
 		err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
-			peer->kgd, (struct kgd_mem *)mem, peer_pdd->drm_priv);
+			peer->kgd, (struct kgd_mem *)mem,
+			peer_pdd->drm_priv, &table_freed);
 		if (err) {
 			pr_err("Failed to map to gpu %d/%d\n",
 			       i, args->n_devices);
@@ -1468,16 +1470,17 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
 	}
 
 	/* Flush TLBs after waiting for the page table updates to complete */
-	for (i = 0; i < args->n_devices; i++) {
-		peer = kfd_device_by_id(devices_arr[i]);
-		if (WARN_ON_ONCE(!peer))
-			continue;
-		peer_pdd = kfd_get_process_device_data(peer, p);
-		if (WARN_ON_ONCE(!peer_pdd))
-			continue;
-		kfd_flush_tlb(peer_pdd);
+	if (table_freed) {
+		for (i = 0; i < args->n_devices; i++) {
+			peer = kfd_device_by_id(devices_arr[i]);
+			if (WARN_ON_ONCE(!peer))
+				continue;
+			peer_pdd = kfd_get_process_device_data(peer, p);
+			if (WARN_ON_ONCE(!peer_pdd))
+				continue;
+			kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
+		}
 	}
-
 	kfree(devices_arr);
 
 	return err;
@@ -1563,6 +1566,7 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
 			       i, args->n_devices);
 			goto unmap_memory_from_gpu_failed;
 		}
+		kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
 		args->n_success = i+1;
 	}
 	kfree(devices_arr);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 3251fe224f86..c6b02aee4993 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -746,6 +746,54 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = {
 	},
 };
 
+static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 6,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 2048,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 6,
+	},
+};
+
 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
 		struct crat_subtype_computeunit *cu)
 {
@@ -1383,6 +1431,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 		pcache_info = beige_goby_cache_info;
 		num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
 		break;
+	case CHIP_YELLOW_CARP:
+		pcache_info = yellow_carp_cache_info;
+		num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
+		break;
 	default:
 		return -EINVAL;
 	}
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
index dd1b1a464c28..6b57dfd2cd2a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
@@ -83,6 +83,7 @@ static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
 	[CHIP_VANGOGH] = &gfx_v10_3_kfd2kgd,
 	[CHIP_DIMGREY_CAVEFISH] = &gfx_v10_3_kfd2kgd,
 	[CHIP_BEIGE_GOBY] = &gfx_v10_3_kfd2kgd,
+	[CHIP_YELLOW_CARP] = &gfx_v10_3_kfd2kgd,
 };
 
 #ifdef KFD_SUPPORT_IOMMU_V2
@@ -577,6 +578,23 @@ static const struct kfd_device_info beige_goby_device_info = {
 	.num_sdma_queues_per_engine = 8,
 };
 
+static const struct kfd_device_info yellow_carp_device_info = {
+	.asic_family = CHIP_YELLOW_CARP,
+	.asic_name = "yellow_carp",
+	.max_pasid_bits = 16,
+	.max_no_of_hqd  = 24,
+	.doorbell_size  = 8,
+	.ih_ring_entry_size = 8 * sizeof(uint32_t),
+	.event_interrupt_class = &event_interrupt_class_v9,
+	.num_of_watch_points = 4,
+	.mqd_size_aligned = MQD_SIZE_ALIGNED,
+	.needs_iommu_device = false,
+	.supports_cwsr = true,
+	.needs_pci_atomics = false,
+	.num_sdma_engines = 1,
+	.num_xgmi_sdma_engines = 0,
+	.num_sdma_queues_per_engine = 2,
+};
 
 /* For each entry, [0] is regular and [1] is virtualisation device. */
 static const struct kfd_device_info *kfd_supported_devices[][2] = {
@@ -606,6 +624,7 @@ static const struct kfd_device_info *kfd_supported_devices[][2] = {
 	[CHIP_VANGOGH] = {&vangogh_device_info, NULL},
 	[CHIP_DIMGREY_CAVEFISH] = {&dimgrey_cavefish_device_info, &dimgrey_cavefish_device_info},
 	[CHIP_BEIGE_GOBY] = {&beige_goby_device_info, &beige_goby_device_info},
+	[CHIP_YELLOW_CARP] = {&yellow_carp_device_info, NULL},
 };
 
 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index 5914e38a9f72..edb14e4a9f33 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -248,7 +248,7 @@ static int allocate_vmid(struct device_queue_manager *dqm,
 			qpd->vmid,
 			qpd->page_table_base);
 	/* invalidate the VM context after pasid and vmid mapping is set up */
-	kfd_flush_tlb(qpd_to_pdd(qpd));
+	kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
 
 	if (dqm->dev->kfd2kgd->set_scratch_backing_va)
 		dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->kgd,
@@ -284,7 +284,7 @@ static void deallocate_vmid(struct device_queue_manager *dqm,
 		if (flush_texture_cache_nocpsch(q->device, qpd))
 			pr_err("Failed to flush TC\n");
 
-	kfd_flush_tlb(qpd_to_pdd(qpd));
+	kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
 
 	/* Release the vmid mapping */
 	set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
@@ -760,7 +760,7 @@ static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
 				dqm->dev->kgd,
 				qpd->vmid,
 				qpd->page_table_base);
-		kfd_flush_tlb(pdd);
+		kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
 	}
 
 	/* Take a safe reference to the mm_struct, which may otherwise
@@ -1937,6 +1937,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		device_queue_manager_init_v10_navi10(&dqm->asic_ops);
 		break;
 	default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
index 0e5f5c5daf76..91c50739b756 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
@@ -425,6 +425,7 @@ int kfd_init_apertures(struct kfd_process *process)
 			case CHIP_VANGOGH:
 			case CHIP_DIMGREY_CAVEFISH:
 			case CHIP_BEIGE_GOBY:
+			case CHIP_YELLOW_CARP:
 				kfd_init_apertures_v9(pdd, id);
 				break;
 			default:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
index 9f9b1dfb9c37..12d91e53556c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
@@ -249,8 +249,13 @@ static void event_interrupt_wq_v9(struct kfd_dev *dev,
 		   client_id == SOC15_IH_CLIENTID_SDMA5 ||
 		   client_id == SOC15_IH_CLIENTID_SDMA6 ||
 		   client_id == SOC15_IH_CLIENTID_SDMA7) {
-		if (source_id == SOC15_INTSRC_SDMA_TRAP)
+		if (source_id == SOC15_INTSRC_SDMA_TRAP) {
 			kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28);
+		} else if (source_id == SOC15_INTSRC_SDMA_ECC) {
+			kfd_signal_poison_consumed_event(dev, pasid);
+			amdgpu_amdkfd_gpu_reset(dev->kgd);
+			return;
+		}
 	} else if (client_id == SOC15_IH_CLIENTID_VMC ||
 		   client_id == SOC15_IH_CLIENTID_VMC1 ||
 		   client_id == SOC15_IH_CLIENTID_UTCL2) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 5f10dbfa58ee..d8e940f03102 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -250,6 +250,7 @@ int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		pm->pmf = &kfd_v9_pm_funcs;
 		break;
 	case CHIP_ALDEBARAN:
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index daa9d47514c6..329684ee5d6e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -1146,7 +1146,7 @@ void kfd_signal_reset_event(struct kfd_dev *dev);
 
 void kfd_signal_poison_consumed_event(struct kfd_dev *dev, u32 pasid);
 
-void kfd_flush_tlb(struct kfd_process_device *pdd);
+void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type);
 
 int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p);
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index 2f8d352e0069..f1f40bba5c60 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -35,7 +35,6 @@
 #include <linux/pm_runtime.h>
 #include "amdgpu_amdkfd.h"
 #include "amdgpu.h"
-#include "kfd_svm.h"
 
 struct mm_struct;
 
@@ -672,7 +671,8 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd,
 	if (err)
 		goto err_alloc_mem;
 
-	err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem, pdd->drm_priv);
+	err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(kdev->kgd, mem,
+			pdd->drm_priv, NULL);
 	if (err)
 		goto err_map_mem;
 
@@ -1838,7 +1838,7 @@ int kfd_reserved_mem_mmap(struct kfd_dev *dev, struct kfd_process *process,
 			       KFD_CWSR_TBA_TMA_SIZE, vma->vm_page_prot);
 }
 
-void kfd_flush_tlb(struct kfd_process_device *pdd)
+void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type)
 {
 	struct kfd_dev *dev = pdd->dev;
 
@@ -1851,7 +1851,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd)
 							pdd->qpd.vmid);
 	} else {
 		amdgpu_amdkfd_flush_gpu_tlb_pasid(dev->kgd,
-					pdd->process->pasid, TLB_FLUSH_LEGACY);
+					pdd->process->pasid, type);
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 0d57ef9e73eb..da569d417d1d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1153,7 +1153,7 @@ svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 
 	prange->mapping.start = prange->start;
 	prange->mapping.last = prange->last;
-	prange->mapping.offset = prange->offset;
+	prange->mapping.offset = prange->ttm_res ? prange->offset : 0;
 	pte_flags = svm_range_get_pte_flags(adev, prange);
 
 	r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false, NULL,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 9be66ba24af9..f668b8cc2b57 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1399,6 +1399,7 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 	case CHIP_VANGOGH:
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
+	case CHIP_YELLOW_CARP:
 		dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
 			HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
diff --git a/drivers/gpu/drm/amd/amdkfd/soc15_int.h b/drivers/gpu/drm/amd/amdkfd/soc15_int.h
index 0bc0b25cb410..daf3c44547d3 100644
--- a/drivers/gpu/drm/amd/amdkfd/soc15_int.h
+++ b/drivers/gpu/drm/amd/amdkfd/soc15_int.h
@@ -30,6 +30,7 @@
 #define SOC15_INTSRC_SQ_INTERRUPT_MSG	239
 #define SOC15_INTSRC_VMC_FAULT		0
 #define SOC15_INTSRC_SDMA_TRAP		224
+#define SOC15_INTSRC_SDMA_ECC		220
 
 
 #define SOC15_CLIENT_ID_FROM_IH_ENTRY(entry) (le32_to_cpu(entry[0]) & 0xff)
diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
index 7dffc04a557e..5b5f36c80efb 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -31,6 +31,13 @@ config DRM_AMD_DC_SI
 	  by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
 	  Hainan is not supported by AMD DC and it has no physical DCE6.
 
+config DRM_AMD_DC_DCN3_1
+        bool "DCN 3.1 family"
+        depends on DRM_AMD_DC_DCN
+        help
+            Choose this option if you want to have
+            DCN3.1 family support for display engine
+
 config DEBUG_KERNEL_DC
 	bool "Enable kgdb break in DC"
 	depends on DRM_AMD_DC
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ae519f929c57..6fda0dfb78f8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -109,6 +109,10 @@ MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
+MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
+#endif
 
 #define FIRMWARE_RAVEN_DMCU		"amdgpu/raven_dmcu.bin"
 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
@@ -1151,6 +1155,11 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		init_data.flags.gpu_vm_support = true;
 		break;
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case CHIP_YELLOW_CARP:
+		init_data.flags.gpu_vm_support = true;
+		break;
+#endif
 	default:
 		break;
 	}
@@ -1407,6 +1416,9 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case CHIP_YELLOW_CARP:
+#endif
 		return 0;
 	case CHIP_NAVI12:
 		fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1525,6 +1537,12 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
 		dmub_asic = DMUB_ASIC_DCN303;
 		fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
 		break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case CHIP_YELLOW_CARP:
+		dmub_asic = DMUB_ASIC_DCN31;
+		fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
+		break;
+#endif
 
 	default:
 		/* ASIC doesn't support DMUB. */
@@ -2219,6 +2237,15 @@ static int dm_resume(void *handle)
 					= 0xffffffff;
 			}
 		}
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		/*
+		 * Resource allocation happens for link encoders for newer ASIC in
+		 * dc_validate_global_state, so we need to revalidate it.
+		 *
+		 * This shouldn't fail (it passed once before), so warn if it does.
+		 */
+		WARN_ON(dc_validate_global_state(dm->dc, dc_state, false) != DC_OK);
+#endif
 
 		WARN_ON(!dc_commit_state(dm->dc, dc_state));
 
@@ -3764,6 +3791,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	switch (adev->asic_type) {
 	case CHIP_SIENNA_CICHLID:
 	case CHIP_NAVY_FLOUNDER:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case CHIP_YELLOW_CARP:
+#endif
 	case CHIP_RENOIR:
 		if (register_outbox_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
@@ -3868,6 +3898,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 	case CHIP_DIMGREY_CAVEFISH:
 	case CHIP_BEIGE_GOBY:
 	case CHIP_VANGOGH:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case CHIP_YELLOW_CARP:
+#endif
 		if (dcn10_register_irq_handlers(dm->adev)) {
 			DRM_ERROR("DM: Failed to initialize IRQ\n");
 			goto fail;
@@ -4039,6 +4072,13 @@ static int dm_early_init(void *handle)
 		adev->mode_info.num_hpd = 6;
 		adev->mode_info.num_dig = 6;
 		break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case CHIP_YELLOW_CARP:
+		adev->mode_info.num_crtc = 4;
+		adev->mode_info.num_hpd = 4;
+		adev->mode_info.num_dig = 4;
+		break;
+#endif
 	case CHIP_NAVI14:
 	case CHIP_DIMGREY_CAVEFISH:
 		adev->mode_info.num_crtc = 5;
@@ -4276,6 +4316,9 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
 	    adev->asic_type == CHIP_NAVY_FLOUNDER ||
 	    adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
 	    adev->asic_type == CHIP_BEIGE_GOBY ||
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	    adev->asic_type == CHIP_YELLOW_CARP ||
+#endif
 	    adev->asic_type == CHIP_VANGOGH)
 		tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 }
@@ -4695,6 +4738,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
 		break;
 	case AMDGPU_FAMILY_NV:
 	case AMDGPU_FAMILY_VGH:
+	case AMDGPU_FAMILY_YC:
 		if (adev->asic_type >= CHIP_SIENNA_CICHLID)
 			add_gfx10_3_modifiers(adev, mods, &size, &capacity);
 		else
@@ -9633,7 +9677,8 @@ skip_modeset:
 	BUG_ON(dm_new_crtc_state->stream == NULL);
 
 	/* Scaling or underscan settings */
-	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
+	if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
+				drm_atomic_crtc_needs_modeset(new_crtc_state))
 		update_stream_scaling_settings(
 			&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 721c8b49730c..22730e554209 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -456,6 +456,7 @@ struct dsc_preferred_settings {
 	uint32_t dsc_num_slices_v;
 	uint32_t dsc_num_slices_h;
 	uint32_t dsc_bits_per_pixel;
+	bool dsc_force_disable_passthrough;
 };
 
 struct amdgpu_dm_connector {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 9fbbd0159119..f1145086a468 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -887,6 +887,47 @@ unlock:
 	return res;
 }
 
+/*
+ * Example usage:
+ * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
+ *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
+ * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
+ *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
+ */
+static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
+				 size_t size, loff_t *pos)
+{
+	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+	char *wr_buf = NULL;
+	uint32_t wr_buf_size = 42;
+	int max_param_num = 1;
+	long param;
+	uint8_t param_nums = 0;
+
+	if (size == 0)
+		return -EINVAL;
+
+	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
+
+	if (!wr_buf) {
+		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
+		return -ENOSPC;
+	}
+
+	if (parse_write_buffer_into_params(wr_buf, size,
+					   &param, buf,
+					   max_param_num,
+					   &param_nums)) {
+		kfree(wr_buf);
+		return -EINVAL;
+	}
+
+	aconnector->dsc_settings.dsc_force_disable_passthrough = param;
+
+	kfree(wr_buf);
+	return 0;
+}
+
 #ifdef CONFIG_DRM_AMD_DC_HDCP
 /*
  * Returns the HDCP capability of the Display (1.4 for now).
@@ -2535,6 +2576,12 @@ static const struct file_operations dp_max_bpc_debugfs_fops = {
 	.llseek = default_llseek
 };
 
+static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
+	.owner = THIS_MODULE,
+	.write = dp_dsc_passthrough_set,
+	.llseek = default_llseek
+};
+
 static const struct {
 	char *name;
 	const struct file_operations *fops;
@@ -2559,7 +2606,8 @@ static const struct {
 		{"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
 		{"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
 		{"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
-		{"max_bpc", &dp_max_bpc_debugfs_fops}
+		{"max_bpc", &dp_max_bpc_debugfs_fops},
+		{"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
 };
 
 #ifdef CONFIG_DRM_AMD_DC_HDCP
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 666796a0067c..64c6ed50990d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -222,10 +222,23 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work,
 			 struct amdgpu_dm_connector *aconnector)
 {
 	struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index];
+	struct drm_connector_state *conn_state = aconnector->base.state;
 
 	mutex_lock(&hdcp_w->mutex);
 	hdcp_w->aconnector = aconnector;
 
+	/* the removal of display will invoke auth reset -> hdcp destroy and
+	 * we'd expect the Content Protection (CP) property changed back to
+	 * DESIRED if at the time ENABLED. CP property change should occur
+	 * before the element removed from linked list.
+	 */
+	if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
+		conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
+
+		DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n",
+			 aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms);
+	}
+
 	mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output);
 
 	process_output(hdcp_w);
@@ -454,6 +467,13 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	display->dig_fe = config->dig_fe;
 	link->dig_be = config->dig_be;
 	link->ddc_line = aconnector->dc_link->ddc_hw_inst + 1;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	display->stream_enc_idx = config->stream_enc_idx;
+	link->link_enc_idx = config->link_enc_idx;
+	link->phy_idx = config->phy_idx;
+	link->hdcp_supported_informational = dc_link_is_hdcp14(aconnector->dc_link,
+			aconnector->dc_sink->sink_signal) ? 1 : 0;
+#endif
 	link->dp.rev = aconnector->dc_link->dpcd_caps.dpcd_rev.raw;
 	link->dp.assr_enabled = config->assr_enabled;
 	link->dp.mst_enabled = config->mst_enabled;
@@ -462,7 +482,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config)
 	link->adjust.hdcp1.disable = 0;
 	conn_state = aconnector->base.state;
 
-	pr_debug("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
+	DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index,
 			(!!aconnector->base.state) ? aconnector->base.state->content_protection : -1,
 			(!!aconnector->base.state) ? aconnector->base.state->hdcp_content_type : -1);
 
@@ -637,6 +657,12 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct
 		INIT_DELAYED_WORK(&hdcp_work[i].property_validate_dwork, event_property_validate);
 
 		hdcp_work[i].hdcp.config.psp.handle = &adev->psp;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		if (dc->ctx->dce_version == DCN_VERSION_3_1) {
+			hdcp_work[i].hdcp.config.psp.caps.dtm_v3_supported = 1;
+			hdcp_work[i].hdcp.config.psp.caps.opm_state_query_supported = false;
+		}
+#endif
 		hdcp_work[i].hdcp.config.ddc.handle = dc_get_link_at_index(dc, i);
 		hdcp_work[i].hdcp.config.ddc.funcs.write_i2c = lp_write_i2c;
 		hdcp_work[i].hdcp.config.ddc.funcs.read_i2c = lp_read_i2c;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 4646b0d02939..6fee12c91ef5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -655,6 +655,12 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
 	/* TODO: something */
 }
 
+void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
+{
+	// TODO:
+	//amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
+}
+
 void *dm_helpers_allocate_gpu_mem(
 		struct dc_context *ctx,
 		enum dc_gpu_mem_alloc_type type,
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 505158a5fcc1..95aca9b0ef7f 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -34,6 +34,9 @@ DC_LIBS += dcn30
 DC_LIBS += dcn301
 DC_LIBS += dcn302
 DC_LIBS += dcn303
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+DC_LIBS += dcn31
+endif
 endif
 
 DC_LIBS += dce120
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 49126a0f66af..7d1c1b76d8d0 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -576,6 +576,13 @@ static struct device_id device_type_from_device_id(uint16_t device_id)
 		result_device_id.device_type = DEVICE_TYPE_LCD;
 		result_device_id.enum_id = 1;
 		break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+
+	case ATOM_DISPLAY_LCD2_SUPPORT:
+		result_device_id.device_type = DEVICE_TYPE_LCD;
+		result_device_id.enum_id = 2;
+		break;
+#endif
 
 	case ATOM_DISPLAY_DFP1_SUPPORT:
 		result_device_id.device_type = DEVICE_TYPE_DFP;
@@ -2155,6 +2162,107 @@ static enum bp_result get_integrated_info_v2_1(
 	return BP_RESULT_OK;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+static enum bp_result get_integrated_info_v2_2(
+	struct bios_parser *bp,
+	struct integrated_info *info)
+{
+	struct atom_integrated_system_info_v2_2 *info_v2_2;
+	uint32_t i;
+
+	info_v2_2 = GET_IMAGE(struct atom_integrated_system_info_v2_2,
+					DATA_TABLES(integratedsysteminfo));
+
+	if (info_v2_2 == NULL)
+		return BP_RESULT_BADBIOSTABLE;
+
+	info->gpu_cap_info =
+	le32_to_cpu(info_v2_2->gpucapinfo);
+	/*
+	* system_config: Bit[0] = 0 : PCIE power gating disabled
+	*                       = 1 : PCIE power gating enabled
+	*                Bit[1] = 0 : DDR-PLL shut down disabled
+	*                       = 1 : DDR-PLL shut down enabled
+	*                Bit[2] = 0 : DDR-PLL power down disabled
+	*                       = 1 : DDR-PLL power down enabled
+	*/
+	info->system_config = le32_to_cpu(info_v2_2->system_config);
+	info->cpu_cap_info = le32_to_cpu(info_v2_2->cpucapinfo);
+	info->memory_type = info_v2_2->memorytype;
+	info->ma_channel_number = info_v2_2->umachannelnumber;
+	info->dp_ss_control =
+		le16_to_cpu(info_v2_2->reserved1);
+
+	for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
+		info->ext_disp_conn_info.gu_id[i] =
+				info_v2_2->extdispconninfo.guid[i];
+	}
+
+	for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; ++i) {
+		info->ext_disp_conn_info.path[i].device_connector_id =
+		object_id_from_bios_object_id(
+		le16_to_cpu(info_v2_2->extdispconninfo.path[i].connectorobjid));
+
+		info->ext_disp_conn_info.path[i].ext_encoder_obj_id =
+		object_id_from_bios_object_id(
+			le16_to_cpu(
+			info_v2_2->extdispconninfo.path[i].ext_encoder_objid));
+
+		info->ext_disp_conn_info.path[i].device_tag =
+			le16_to_cpu(
+				info_v2_2->extdispconninfo.path[i].device_tag);
+		info->ext_disp_conn_info.path[i].device_acpi_enum =
+		le16_to_cpu(
+			info_v2_2->extdispconninfo.path[i].device_acpi_enum);
+		info->ext_disp_conn_info.path[i].ext_aux_ddc_lut_index =
+			info_v2_2->extdispconninfo.path[i].auxddclut_index;
+		info->ext_disp_conn_info.path[i].ext_hpd_pin_lut_index =
+			info_v2_2->extdispconninfo.path[i].hpdlut_index;
+		info->ext_disp_conn_info.path[i].channel_mapping.raw =
+			info_v2_2->extdispconninfo.path[i].channelmapping;
+		info->ext_disp_conn_info.path[i].caps =
+				le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
+	}
+
+	info->ext_disp_conn_info.checksum =
+		info_v2_2->extdispconninfo.checksum;
+
+	info->edp1_info.edp_backlight_pwm_hz =
+	le16_to_cpu(info_v2_2->edp1_info.edp_backlight_pwm_hz);
+	info->edp1_info.edp_ss_percentage =
+	le16_to_cpu(info_v2_2->edp1_info.edp_ss_percentage);
+	info->edp1_info.edp_ss_rate_10hz =
+	le16_to_cpu(info_v2_2->edp1_info.edp_ss_rate_10hz);
+	info->edp1_info.edp_pwr_on_off_delay =
+		info_v2_2->edp1_info.edp_pwr_on_off_delay;
+	info->edp1_info.edp_pwr_on_vary_bl_to_blon =
+		info_v2_2->edp1_info.edp_pwr_on_vary_bl_to_blon;
+	info->edp1_info.edp_pwr_down_bloff_to_vary_bloff =
+		info_v2_2->edp1_info.edp_pwr_down_bloff_to_vary_bloff;
+	info->edp1_info.edp_panel_bpc =
+		info_v2_2->edp1_info.edp_panel_bpc;
+	info->edp1_info.edp_bootup_bl_level =
+
+	info->edp2_info.edp_backlight_pwm_hz =
+	le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
+	info->edp2_info.edp_ss_percentage =
+	le16_to_cpu(info_v2_2->edp2_info.edp_ss_percentage);
+	info->edp2_info.edp_ss_rate_10hz =
+	le16_to_cpu(info_v2_2->edp2_info.edp_ss_rate_10hz);
+	info->edp2_info.edp_pwr_on_off_delay =
+		info_v2_2->edp2_info.edp_pwr_on_off_delay;
+	info->edp2_info.edp_pwr_on_vary_bl_to_blon =
+		info_v2_2->edp2_info.edp_pwr_on_vary_bl_to_blon;
+	info->edp2_info.edp_pwr_down_bloff_to_vary_bloff =
+		info_v2_2->edp2_info.edp_pwr_down_bloff_to_vary_bloff;
+	info->edp2_info.edp_panel_bpc =
+		info_v2_2->edp2_info.edp_panel_bpc;
+	info->edp2_info.edp_bootup_bl_level =
+		info_v2_2->edp2_info.edp_bootup_bl_level;
+
+	return BP_RESULT_OK;
+}
+#endif
 /*
  * construct_integrated_info
  *
@@ -2202,6 +2310,11 @@ static enum bp_result construct_integrated_info(
 			case 1:
 				result = get_integrated_info_v2_1(bp, info);
 				break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+			case 2:
+				result = get_integrated_info_v2_2(bp, info);
+				break;
+#endif
 			default:
 				return result;
 			}
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
index 53d7513b5083..adc710fe4a45 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c
@@ -82,9 +82,6 @@ void bios_set_scratch_critical_state(
 uint32_t bios_get_vga_enabled_displays(
 	struct dc_bios *bios)
 {
-	uint32_t active_disp = 1;
-
-	active_disp = REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
-	return active_disp;
+	return REG_READ(BIOS_SCRATCH_3) & 0XFFFF;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
index 6d2fb112ad9f..3ac4dc01f8e1 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
@@ -72,6 +72,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
 	case DCN_VERSION_2_1:
 	case DCN_VERSION_3_0:
 	case DCN_VERSION_3_01:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case DCN_VERSION_3_1:
+		*h = dal_cmd_tbl_helper_dce112_get_table2();
+		return true;
+#endif
 	case DCN_VERSION_3_02:
 	case DCN_VERSION_3_03:
 		*h = dal_cmd_tbl_helper_dce112_get_table2();
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index ff96bee57bfc..713251547d1c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -136,3 +136,14 @@ AMD_DAL_CLK_MGR_DCN301 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn301/,$(CLK_MGR_
 
 AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN301)
 endif
+
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+###############################################################################
+# DCN31
+###############################################################################
+CLK_MGR_DCN31 = dcn31_smu.o dcn31_clk_mgr.o
+
+AMD_DAL_CLK_MGR_DCN31 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31)
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index dd52ebf56d62..f652f491c419 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -41,6 +41,9 @@
 #include "dcn21/rn_clk_mgr.h"
 #include "dcn30/dcn30_clk_mgr.h"
 #include "dcn301/vg_clk_mgr.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#include "dcn31/dcn31_clk_mgr.h"
+#endif
 
 
 int clk_mgr_helper_get_active_display_cnt(
@@ -90,15 +93,20 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_m
 	struct dc_link *edp_links[MAX_NUM_EDP];
 	struct dc_link *edp_link = NULL;
 	int edp_num;
+	unsigned int panel_inst;
 
 	get_edp_links(dc, edp_links, &edp_num);
 	if (dc->hwss.exit_optimized_pwr_state)
 		dc->hwss.exit_optimized_pwr_state(dc, dc->current_state);
 
 	if (edp_num) {
-		edp_link = edp_links[0];
-		clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
-		dc_link_set_psr_allow_active(edp_link, false, false, false);
+		for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
+			edp_link = edp_links[panel_inst];
+			if (!edp_link->psr_settings.psr_feature_enabled)
+				continue;
+			clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;
+			dc_link_set_psr_allow_active(edp_link, false, false, false);
+		}
 	}
 
 }
@@ -108,12 +116,17 @@ void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr)
 	struct dc_link *edp_links[MAX_NUM_EDP];
 	struct dc_link *edp_link = NULL;
 	int edp_num;
+	unsigned int panel_inst;
 
 	get_edp_links(dc, edp_links, &edp_num);
 	if (edp_num) {
-		edp_link = edp_links[0];
-		dc_link_set_psr_allow_active(edp_link,
-				clk_mgr->psr_allow_active_cache, false, false);
+		for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {
+			edp_link = edp_links[panel_inst];
+			if (!edp_link->psr_settings.psr_feature_enabled)
+				continue;
+			dc_link_set_psr_allow_active(edp_link,
+					clk_mgr->psr_allow_active_cache, false, false);
+		}
 	}
 
 	if (dc->hwss.optimize_pwr_state)
@@ -261,6 +274,26 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
 		}
 		break;
 #endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case FAMILY_YELLOW_CARP: {
+		struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
+
+		if (clk_mgr == NULL) {
+			BREAK_TO_DEBUGGER();
+			return NULL;
+		}
+		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev)) {
+			/* TODO: to add DCN31 clk_mgr support, once CLK IP header files are available,
+			 * for now use DCN3.0 clk mgr.
+			 */
+			dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+			return &clk_mgr->base.base;
+		}
+		return &clk_mgr->base.base;
+	}
+#endif
+
 	default:
 		ASSERT(0); /* Unknown Asic */
 		break;
@@ -292,6 +325,13 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
 			vg_clk_mgr_destroy(clk_mgr);
 		break;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case FAMILY_YELLOW_CARP:
+		if (ASICREV_IS_YELLOW_CARP(clk_mgr_base->ctx->asic_id.hw_internal_rev))
+			dcn31_clk_mgr_destroy(clk_mgr);
+		break;
+#endif
+
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 372d53b5a34d..59d17195bc22 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -324,6 +324,10 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
 	// Both fclk and ref_dppclk run on the same scemi clock.
 	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	/* TODO: set dtbclk in correct place */
+	clk_mgr->clks.dtbclk_en = false;
+#endif
 	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 416a24db17a9..c6f494f0dcea 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -835,66 +835,47 @@ static struct wm_table lpddr4_wm_table_rn = {
 	}
 };
 
-static unsigned int find_max_fclk_for_voltage(struct dpm_clocks *clock_table,
-		unsigned int voltage)
+static unsigned int find_socclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 {
 	int i;
-	uint32_t max_clk = 0;
 
-	for (i = 0; i < PP_SMU_NUM_FCLK_DPM_LEVELS; i++) {
-		if (clock_table->FClocks[i].Vol <= voltage) {
-			max_clk = clock_table->FClocks[i].Freq > max_clk ?
-				clock_table->FClocks[i].Freq : max_clk;
-		}
-	}
-
-	return max_clk;
-}
-
-static unsigned int find_max_memclk_for_voltage(struct dpm_clocks *clock_table,
-		unsigned int voltage)
-{
-	int i;
-	uint32_t max_clk = 0;
-
-	for (i = 0; i < PP_SMU_NUM_MEMCLK_DPM_LEVELS; i++) {
-		if (clock_table->MemClocks[i].Vol <= voltage) {
-			max_clk = clock_table->MemClocks[i].Freq > max_clk ?
-				clock_table->MemClocks[i].Freq : max_clk;
-		}
+	for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
+		if (clock_table->SocClocks[i].Vol == voltage)
+			return clock_table->SocClocks[i].Freq;
 	}
 
-	return max_clk;
+	ASSERT(0);
+	return 0;
 }
 
-static unsigned int find_max_socclk_for_voltage(struct dpm_clocks *clock_table,
-		unsigned int voltage)
+static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 {
 	int i;
-	uint32_t max_clk = 0;
 
-	for (i = 0; i < PP_SMU_NUM_SOCCLK_DPM_LEVELS; i++) {
-		if (clock_table->SocClocks[i].Vol <= voltage) {
-			max_clk = clock_table->SocClocks[i].Freq > max_clk ?
-				clock_table->SocClocks[i].Freq : max_clk;
-		}
+	for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
+		if (clock_table->DcfClocks[i].Vol == voltage)
+			return clock_table->DcfClocks[i].Freq;
 	}
 
-	return max_clk;
+	ASSERT(0);
+	return 0;
 }
 
 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 {
 	int i, j = 0;
-	unsigned int volt;
 
 	j = -1;
 
-	/* Find max DPM */
-	for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; ++i) {
-		if (clock_table->DcfClocks[i].Freq != 0 &&
-				clock_table->DcfClocks[i].Vol != 0)
+	ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
+
+	/* Find lowest DPM, FCLK is filled in reverse order*/
+
+	for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
+		if (clock_table->FClocks[i].Freq != 0 && clock_table->FClocks[i].Vol != 0) {
 			j = i;
+			break;
+		}
 	}
 
 	if (j == -1) {
@@ -905,18 +886,13 @@ static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params
 
 	bw_params->clk_table.num_entries = j + 1;
 
-	for (i = 0; i < bw_params->clk_table.num_entries; i++) {
-		volt = clock_table->DcfClocks[i].Vol;
-
-		bw_params->clk_table.entries[i].voltage = volt;
-		bw_params->clk_table.entries[i].dcfclk_mhz =
-			clock_table->DcfClocks[i].Freq;
-		bw_params->clk_table.entries[i].fclk_mhz =
-			find_max_fclk_for_voltage(clock_table, volt);
-		bw_params->clk_table.entries[i].memclk_mhz =
-			find_max_memclk_for_voltage(clock_table, volt);
-		bw_params->clk_table.entries[i].socclk_mhz =
-			find_max_socclk_for_voltage(clock_table, volt);
+	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+		bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
+		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
+		bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
+		bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
+		bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table,
+									bw_params->clk_table.entries[i].voltage);
 	}
 
 	bw_params->vram_type = bios_info->memory_type;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
new file mode 100644
index 000000000000..7b7d884d58be
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -0,0 +1,673 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+
+#include "dccg.h"
+#include "clk_mgr_internal.h"
+
+// For dce12_get_dp_ref_freq_khz
+#include "dce100/dce_clk_mgr.h"
+
+// For dcn20_update_clocks_update_dpp_dto
+#include "dcn20/dcn20_clk_mgr.h"
+
+
+
+#include "dcn31_clk_mgr.h"
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn31_smu.h"
+#include "dm_helpers.h"
+
+/* TODO: remove this include once we ported over remaining clk mgr functions*/
+#include "dcn30/dcn30_clk_mgr.h"
+
+#include "dc_dmub_srv.h"
+
+#define TO_CLK_MGR_DCN31(clk_mgr)\
+	container_of(clk_mgr, struct clk_mgr_dcn31, base)
+
+int dcn31_get_active_display_cnt_wa(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	int i, display_count;
+	bool tmds_present = false;
+
+	display_count = 0;
+	for (i = 0; i < context->stream_count; i++) {
+		const struct dc_stream_state *stream = context->streams[i];
+
+		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
+				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
+			tmds_present = true;
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		const struct dc_link *link = dc->links[i];
+
+		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
+		if (link->link_enc->funcs->is_dig_enabled &&
+				link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			display_count++;
+	}
+
+	/* WA for hang on HDMI after display off back back on*/
+	if (display_count == 0 && tmds_present)
+		display_count = 1;
+
+	return display_count;
+}
+
+static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
+{
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+		if (pipe->top_pipe || pipe->prev_odm_pipe)
+			continue;
+		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
+			if (disable)
+				pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
+			else
+				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
+		}
+	}
+}
+
+static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
+			struct dc_state *context,
+			bool safe_to_lower)
+{
+	union dmub_rb_cmd cmd;
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
+	struct dc *dc = clk_mgr_base->ctx->dc;
+	int display_count;
+	bool update_dppclk = false;
+	bool update_dispclk = false;
+	bool dpp_clock_lowered = false;
+
+	if (dc->work_arounds.skip_clock_update)
+		return;
+
+	/*
+	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
+	 * also if safe to lower is false, we just go in the higher state
+	 */
+	if (safe_to_lower) {
+		if (new_clocks->z9_support == DCN_Z9_SUPPORT_ALLOW &&
+				new_clocks->z9_support != clk_mgr_base->clks.z9_support) {
+			dcn31_smu_set_Z9_support(clk_mgr, true);
+			clk_mgr_base->clks.z9_support = new_clocks->z9_support;
+		}
+
+		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
+			dcn31_smu_set_dtbclk(clk_mgr, false);
+			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
+		}
+		/* check that we're not already in lower */
+		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+			display_count = dcn31_get_active_display_cnt_wa(dc, context);
+			/* if we can go lower, go lower */
+			if (display_count == 0) {
+				union display_idle_optimization_u idle_info = { 0 };
+				idle_info.idle_info.df_request_disabled = 1;
+				idle_info.idle_info.phy_ref_clk_off = 1;
+				dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+				/* update power state */
+				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+			}
+		}
+	} else {
+		if (new_clocks->z9_support == DCN_Z9_SUPPORT_DISALLOW &&
+				new_clocks->z9_support != clk_mgr_base->clks.z9_support) {
+			dcn31_smu_set_Z9_support(clk_mgr, false);
+			clk_mgr_base->clks.z9_support = new_clocks->z9_support;
+		}
+
+		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
+			dcn31_smu_set_dtbclk(clk_mgr, true);
+			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
+		}
+
+		/* check that we're not already in D0 */
+		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
+			union display_idle_optimization_u idle_info = { 0 };
+			dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+			/* update power state */
+			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
+		}
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
+		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
+		dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
+	}
+
+	if (should_set_clock(safe_to_lower,
+			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
+		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
+		dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
+	}
+
+	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
+	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+		if (new_clocks->dppclk_khz < 100000)
+			new_clocks->dppclk_khz = 100000;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
+		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
+			dpp_clock_lowered = true;
+		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
+		update_dppclk = true;
+	}
+
+	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
+		dcn31_disable_otg_wa(clk_mgr_base, true);
+
+		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
+		dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
+		dcn31_disable_otg_wa(clk_mgr_base, false);
+
+		update_dispclk = true;
+	}
+
+	/* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
+	if (dpp_clock_lowered) {
+		// increase per DPP DTO before lowering global dppclk
+		dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+	} else {
+		// increase global DPPCLK before lowering per DPP DTO
+		if (update_dppclk || update_dispclk)
+			dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+	}
+
+	// notify DMCUB of latest clocks
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
+	cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
+	cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
+	cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
+		clk_mgr_base->clks.dcfclk_deep_sleep_khz;
+	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
+	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+}
+
+static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
+{
+	return 0;
+}
+
+static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+
+	dcn31_smu_enable_pme_wa(clk_mgr);
+}
+
+static void dcn31_init_clocks(struct clk_mgr *clk_mgr)
+{
+	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
+	// Assumption is that boot state always supports pstate
+	clk_mgr->clks.p_state_change_support = true;
+	clk_mgr->clks.prev_p_state_change_support = true;
+	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
+	clk_mgr->clks.z9_support = DCN_Z9_SUPPORT_UNKNOWN;
+}
+
+static bool dcn31_are_clock_states_equal(struct dc_clocks *a,
+		struct dc_clocks *b)
+{
+	if (a->dispclk_khz != b->dispclk_khz)
+		return false;
+	else if (a->dppclk_khz != b->dppclk_khz)
+		return false;
+	else if (a->dcfclk_khz != b->dcfclk_khz)
+		return false;
+	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
+		return false;
+	else if (a->z9_support != b->z9_support)
+		return false;
+	else if (a->dtbclk_en != b->dtbclk_en)
+		return false;
+
+	return true;
+}
+
+static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
+		struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
+{
+	return;
+}
+
+static struct clk_bw_params dcn31_bw_params = {
+	.vram_type = Ddr4MemType,
+	.num_channels = 1,
+	.clk_table = {
+		.num_entries = 4,
+	},
+
+};
+
+static struct wm_table ddr4_wm_table = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 6.09,
+			.sr_enter_plus_exit_time_us = 7.14,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.72,
+			.sr_exit_time_us = 10.12,
+			.sr_enter_plus_exit_time_us = 11.48,
+			.valid = true,
+		},
+	}
+};
+
+static struct wm_table lpddr5_wm_table = {
+	.entries = {
+		{
+			.wm_inst = WM_A,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 5.32,
+			.sr_enter_plus_exit_time_us = 6.38,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_B,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.82,
+			.sr_enter_plus_exit_time_us = 11.196,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_C,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.89,
+			.sr_enter_plus_exit_time_us = 11.24,
+			.valid = true,
+		},
+		{
+			.wm_inst = WM_D,
+			.wm_type = WM_TYPE_PSTATE_CHG,
+			.pstate_latency_us = 11.65333,
+			.sr_exit_time_us = 9.748,
+			.sr_enter_plus_exit_time_us = 11.102,
+			.valid = true,
+		},
+	}
+};
+
+static DpmClocks_t dummy_clocks;
+
+static struct dcn31_watermarks dummy_wms = { 0 };
+
+static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
+{
+	int i, num_valid_sets;
+
+	num_valid_sets = 0;
+
+	for (i = 0; i < WM_SET_COUNT; i++) {
+		/* skip empty entries, the smu array has no holes*/
+		if (!bw_params->wm_table.entries[i].valid)
+			continue;
+
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		/* We will not select WM based on fclk, so leave it as unconstrained */
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
+			if (i == 0)
+				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
+			else {
+				/* add 1 to make it non-overlapping with next lvl */
+				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
+						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+			}
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
+					bw_params->clk_table.entries[i].dcfclk_mhz;
+
+		} else {
+			/* unconstrained for memory retraining */
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
+
+			/* Modify previous watermark range to cover up to max */
+			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+		}
+		num_valid_sets++;
+	}
+
+	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
+
+	/* modify the min and max to make sure we cover the whole range*/
+	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
+	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
+	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
+	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
+
+	/* This is for writeback only, does not matter currently as no writeback support*/
+	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
+	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
+	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
+	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
+	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
+}
+
+static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
+	struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
+
+	if (!clk_mgr->smu_ver)
+		return;
+
+	if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
+
+	dcn31_smu_set_dram_addr_high(clk_mgr,
+			clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
+	dcn31_smu_set_dram_addr_low(clk_mgr,
+			clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
+	dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
+}
+
+static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
+		struct dcn31_smu_dpm_clks *smu_dpm_clks)
+{
+	DpmClocks_t *table = smu_dpm_clks->dpm_clks;
+
+	if (!clk_mgr->smu_ver)
+		return;
+
+	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
+		return;
+
+	memset(table, 0, sizeof(*table));
+
+	dcn31_smu_set_dram_addr_high(clk_mgr,
+			smu_dpm_clks->mc_address.high_part);
+	dcn31_smu_set_dram_addr_low(clk_mgr,
+			smu_dpm_clks->mc_address.low_part);
+	dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
+}
+
+static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
+{
+	uint32_t max = 0;
+	int i;
+
+	for (i = 0; i < num_clocks; ++i) {
+		if (clocks[i] > max)
+			max = clocks[i];
+	}
+
+	return max;
+}
+
+static unsigned int find_clk_for_voltage(
+		const DpmClocks_t *clock_table,
+		const uint32_t clocks[],
+		unsigned int voltage)
+{
+	int i;
+
+	for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
+		if (clock_table->SocVoltage[i] == voltage)
+			return clocks[i];
+	}
+
+	ASSERT(0);
+	return 0;
+}
+
+void dcn31_clk_mgr_helper_populate_bw_params(
+		struct clk_mgr_internal *clk_mgr,
+		struct integrated_info *bios_info,
+		const DpmClocks_t *clock_table)
+{
+	int i, j;
+	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
+	uint32_t max_dispclk = 0, max_dppclk = 0;
+
+	j = -1;
+
+	ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
+
+	/* Find lowest DPM, FCLK is filled in reverse order*/
+
+	for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
+		if (clock_table->DfPstateTable[i].FClk != 0) {
+			j = i;
+			break;
+		}
+	}
+
+	if (j == -1) {
+		/* clock table is all 0s, just use our own hardcode */
+		ASSERT(0);
+		return;
+	}
+
+	bw_params->clk_table.num_entries = j + 1;
+
+	/* dispclk and dppclk can be max at any voltage, same number of levels for both */
+	if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
+	    clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
+		max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
+		max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
+	} else {
+		ASSERT(0);
+	}
+
+	for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
+		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
+		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
+		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
+		switch (clock_table->DfPstateTable[j].WckRatio) {
+		case WCK_RATIO_1_2:
+			bw_params->clk_table.entries[i].wck_ratio = 2;
+			break;
+		case WCK_RATIO_1_4:
+			bw_params->clk_table.entries[i].wck_ratio = 4;
+			break;
+		default:
+			bw_params->clk_table.entries[i].wck_ratio = 1;
+		}
+		bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
+		bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
+		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
+		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
+	}
+
+	bw_params->vram_type = bios_info->memory_type;
+	bw_params->num_channels = bios_info->ma_channel_number;
+
+	for (i = 0; i < WM_SET_COUNT; i++) {
+		bw_params->wm_table.entries[i].wm_inst = i;
+
+		if (i >= bw_params->clk_table.num_entries) {
+			bw_params->wm_table.entries[i].valid = false;
+			continue;
+		}
+
+		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
+		bw_params->wm_table.entries[i].valid = true;
+	}
+}
+
+static struct clk_mgr_funcs dcn31_funcs = {
+	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
+	.update_clocks = dcn31_update_clocks,
+	.init_clocks = dcn31_init_clocks,
+	.enable_pme_wa = dcn31_enable_pme_wa,
+	.are_clock_states_equal = dcn31_are_clock_states_equal,
+	.notify_wm_ranges = dcn31_notify_wm_ranges
+};
+extern struct clk_mgr_funcs dcn3_fpga_funcs;
+
+void dcn31_clk_mgr_construct(
+		struct dc_context *ctx,
+		struct clk_mgr_dcn31 *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg)
+{
+	struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
+
+	clk_mgr->base.base.ctx = ctx;
+	clk_mgr->base.base.funcs = &dcn31_funcs;
+
+	clk_mgr->base.pp_smu = pp_smu;
+
+	clk_mgr->base.dccg = dccg;
+	clk_mgr->base.dfs_bypass_disp_clk = 0;
+
+	clk_mgr->base.dprefclk_ss_percentage = 0;
+	clk_mgr->base.dprefclk_ss_divider = 1000;
+	clk_mgr->base.ss_on_dprefclk = false;
+
+	clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
+				clk_mgr->base.base.ctx,
+				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				sizeof(struct dcn31_watermarks),
+				&clk_mgr->smu_wm_set.mc_address.quad_part);
+
+	if (clk_mgr->smu_wm_set.wm_set == 0) {
+		clk_mgr->smu_wm_set.wm_set = &dummy_wms;
+		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
+	}
+	ASSERT(clk_mgr->smu_wm_set.wm_set);
+
+	smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
+				clk_mgr->base.base.ctx,
+				DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				sizeof(DpmClocks_t),
+				&smu_dpm_clks.mc_address.quad_part);
+
+	if (smu_dpm_clks.dpm_clks == NULL) {
+		smu_dpm_clks.dpm_clks = &dummy_clocks;
+		smu_dpm_clks.mc_address.quad_part = 0;
+	}
+
+	ASSERT(smu_dpm_clks.dpm_clks);
+
+	if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+		clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
+	} else {
+		struct clk_log_info log_info = {0};
+
+		clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
+
+		if (clk_mgr->base.smu_ver)
+			clk_mgr->base.smu_present = true;
+
+		/* TODO: Check we get what we expect during bringup */
+		clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
+
+		if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
+			dcn31_bw_params.wm_table = lpddr5_wm_table;
+		} else {
+			dcn31_bw_params.wm_table = ddr4_wm_table;
+		}
+		/* Saved clocks configured at boot for debug purposes */
+		 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
+
+	}
+
+	clk_mgr->base.base.dprefclk_khz = 600000;
+	clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
+	dce_clock_read_ss_info(&clk_mgr->base);
+
+	clk_mgr->base.base.bw_params = &dcn31_bw_params;
+
+	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
+		dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
+
+		if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
+			dcn31_clk_mgr_helper_populate_bw_params(
+					&clk_mgr->base,
+					ctx->dc_bios->integrated_info,
+					smu_dpm_clks.dpm_clks);
+		}
+	}
+
+	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
+		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				smu_dpm_clks.dpm_clks);
+}
+
+void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
+{
+	struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
+
+	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
+		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
+				clk_mgr->smu_wm_set.wm_set);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
new file mode 100644
index 000000000000..cc21cf75eafd
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN31_CLK_MGR_H__
+#define __DCN31_CLK_MGR_H__
+#include "clk_mgr_internal.h"
+
+//CLK1_CLK_PLL_REQ
+#ifndef CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int__SHIFT                                                                   0x0
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                                  0xc
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT                                                                  0x10
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_int_MASK                                                                     0x000001FFL
+#define CLK11_CLK1_CLK_PLL_REQ__PllSpineDiv_MASK                                                                    0x0000F000L
+#define CLK11_CLK1_CLK_PLL_REQ__FbMult_frac_MASK                                                                    0xFFFF0000L
+//CLK1_CLK0_DFS_CNTL
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER__SHIFT                                                               0x0
+#define CLK11_CLK1_CLK0_DFS_CNTL__CLK0_DIVIDER_MASK                                                                 0x0000007FL
+/*DPREF clock related*/
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK0_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK1_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK2_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER__SHIFT                                                               0x0
+#define CLK3_CLK3_DFS_CNTL__CLK3_DIVIDER_MASK                                                                 0x0000007FL
+
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT                                                            0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT                                                           0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT                                                           0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK                                                              0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK                                                             0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK                                                             0xFFFF0000L
+
+#define mmCLK0_CLK3_DFS_CNTL                            0x16C60
+#define mmCLK00_CLK0_CLK3_DFS_CNTL                      0x16C60
+#define mmCLK01_CLK0_CLK3_DFS_CNTL                      0x16E60
+#define mmCLK02_CLK0_CLK3_DFS_CNTL                      0x17060
+#define mmCLK03_CLK0_CLK3_DFS_CNTL                      0x17260
+
+#define mmCLK0_CLK_PLL_REQ                              0x16C10
+#define mmCLK00_CLK0_CLK_PLL_REQ                        0x16C10
+#define mmCLK01_CLK0_CLK_PLL_REQ                        0x16E10
+#define mmCLK02_CLK0_CLK_PLL_REQ                        0x17010
+#define mmCLK03_CLK0_CLK_PLL_REQ                        0x17210
+
+#define mmCLK1_CLK_PLL_REQ                              0x1B00D
+#define mmCLK10_CLK1_CLK_PLL_REQ                        0x1B00D
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+#define mmCLK12_CLK1_CLK_PLL_REQ                        0x1B40D
+#define mmCLK13_CLK1_CLK_PLL_REQ                        0x1B60D
+
+#define mmCLK2_CLK_PLL_REQ                              0x17E0D
+
+/*AMCLK*/
+#define mmCLK11_CLK1_CLK0_DFS_CNTL                      0x1B23F
+#define mmCLK11_CLK1_CLK_PLL_REQ                        0x1B20D
+#endif
+
+struct dcn31_watermarks;
+
+struct dcn31_smu_watermark_set {
+	struct dcn31_watermarks *wm_set;
+	union large_integer mc_address;
+};
+
+struct clk_mgr_dcn31 {
+	struct clk_mgr_internal base;
+	struct dcn31_smu_watermark_set smu_wm_set;
+};
+
+void dcn31_clk_mgr_construct(struct dc_context *ctx,
+		struct clk_mgr_dcn31 *clk_mgr,
+		struct pp_smu_funcs *pp_smu,
+		struct dccg *dccg);
+
+void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
+
+#endif //__DCN31_CLK_MGR_H__
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
new file mode 100644
index 000000000000..66db5e988bc1
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2012-16 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include <linux/delay.h>
+#include "core_types.h"
+#include "clk_mgr_internal.h"
+#include "reg_helper.h"
+#include "dm_helpers.h"
+#include "dcn31_smu.h"
+
+#include "yellow_carp_offset.h"
+#include "mp/mp_13_0_1_offset.h"
+#include "mp/mp_13_0_1_sh_mask.h"
+
+#define REG(reg_name) \
+	(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
+
+#define FN(reg_name, field) \
+	FD(reg_name##__##field)
+
+#define VBIOSSMC_MSG_TestMessage                  0x1
+#define VBIOSSMC_MSG_GetSmuVersion                0x2
+#define VBIOSSMC_MSG_PowerUpGfx                   0x3
+#define VBIOSSMC_MSG_SetDispclkFreq               0x4
+#define VBIOSSMC_MSG_SetDprefclkFreq              0x5   //Not used. DPRef is constant
+#define VBIOSSMC_MSG_SetDppclkFreq                0x6
+#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq       0x7
+#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk        0x8
+#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq       0x9	//Keep it in case VMIN dees not support phy clk
+#define VBIOSSMC_MSG_GetFclkFrequency             0xA
+#define VBIOSSMC_MSG_SetDisplayCount              0xB   //Not used anymore
+#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC   //Not used anymore
+#define VBIOSSMC_MSG_UpdatePmeRestore             0xD
+#define VBIOSSMC_MSG_SetVbiosDramAddrHigh         0xE   //Used for WM table txfr
+#define VBIOSSMC_MSG_SetVbiosDramAddrLow          0xF
+#define VBIOSSMC_MSG_TransferTableSmu2Dram        0x10
+#define VBIOSSMC_MSG_TransferTableDram2Smu        0x11
+#define VBIOSSMC_MSG_SetDisplayIdleOptimizations  0x12
+#define VBIOSSMC_MSG_GetDprefclkFreq              0x13
+#define VBIOSSMC_MSG_GetDtbclkFreq                0x14
+#define VBIOSSMC_MSG_AllowZstatesEntry            0x15
+#define VBIOSSMC_MSG_DisallowZstatesEntry     	  0x16
+#define VBIOSSMC_MSG_SetDtbClk                    0x17
+#define VBIOSSMC_Message_Count                    0x18
+
+#define VBIOSSMC_Status_BUSY                      0x0
+#define VBIOSSMC_Result_OK                        0x1
+#define VBIOSSMC_Result_Failed                    0xFF
+#define VBIOSSMC_Result_UnknownCmd                0xFE
+#define VBIOSSMC_Result_CmdRejectedPrereq         0xFD
+#define VBIOSSMC_Result_CmdRejectedBusy           0xFC
+
+/*
+ * Function to be used instead of REG_WAIT macro because the wait ends when
+ * the register is NOT EQUAL to zero, and because the translation in msg_if.h
+ * won't work with REG_WAIT.
+ */
+static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
+{
+	uint32_t res_val = VBIOSSMC_Status_BUSY;
+
+	do {
+		res_val = REG_READ(MP1_SMN_C2PMSG_91);
+		if (res_val != VBIOSSMC_Status_BUSY)
+			break;
+
+		if (delay_us >= 1000)
+			msleep(delay_us/1000);
+		else if (delay_us > 0)
+			udelay(delay_us);
+	} while (max_retries--);
+
+	return res_val;
+}
+
+int dcn31_smu_send_msg_with_param(
+		struct clk_mgr_internal *clk_mgr,
+		unsigned int msg_id, unsigned int param)
+{
+	uint32_t result;
+
+	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
+	ASSERT(result == VBIOSSMC_Result_OK);
+
+	if (result == VBIOSSMC_Status_BUSY) {
+		return -1;
+	}
+
+	/* First clear response register */
+	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
+
+	/* Set the parameter register for the SMU message, unit is Mhz */
+	REG_WRITE(MP1_SMN_C2PMSG_83, param);
+
+	/* Trigger the message transaction by writing the message ID */
+	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
+
+	result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
+
+	if (IS_SMU_TIMEOUT(result)) {
+		ASSERT(0);
+		dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
+	}
+
+	return REG_READ(MP1_SMN_C2PMSG_83);
+}
+
+int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
+{
+	return dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_GetSmuVersion,
+			0);
+}
+
+
+int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
+{
+	int actual_dispclk_set_mhz = -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_dispclk_khz;
+
+	/*  Unit of SMU msg parameter is Mhz */
+	actual_dispclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDispclkFreq,
+			(requested_dispclk_khz + 999) / 1000);
+
+	return actual_dispclk_set_mhz * 1000;
+}
+
+int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
+{
+	int actual_dprefclk_set_mhz = -1;
+
+	if (!clk_mgr->smu_present)
+		return clk_mgr->base.dprefclk_khz;
+
+	actual_dprefclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDprefclkFreq,
+			(clk_mgr->base.dprefclk_khz + 999) / 1000);
+
+	/* TODO: add code for programing DP DTO, currently this is down by command table */
+
+	return actual_dprefclk_set_mhz * 1000;
+}
+
+int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
+{
+	int actual_dcfclk_set_mhz = -1;
+
+	if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
+		return -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_dcfclk_khz;
+
+	actual_dcfclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
+			(requested_dcfclk_khz + 999) / 1000);
+
+	return actual_dcfclk_set_mhz * 1000;
+}
+
+int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
+{
+	int actual_min_ds_dcfclk_mhz = -1;
+
+	if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
+		return -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_min_ds_dcfclk_khz;
+
+	actual_min_ds_dcfclk_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
+			(requested_min_ds_dcfclk_khz + 999) / 1000);
+
+	return actual_min_ds_dcfclk_mhz * 1000;
+}
+
+int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
+{
+	int actual_dppclk_set_mhz = -1;
+
+	if (!clk_mgr->smu_present)
+		return requested_dpp_khz;
+
+	actual_dppclk_set_mhz = dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDppclkFreq,
+			(requested_dpp_khz + 999) / 1000);
+
+	return actual_dppclk_set_mhz * 1000;
+}
+
+void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
+{
+	if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
+		return;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	//TODO: Work with smu team to define optimization options.
+	dcn31_smu_send_msg_with_param(
+		clk_mgr,
+		VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+		idle_info);
+}
+
+void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	union display_idle_optimization_u idle_info = { 0 };
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (enable) {
+		idle_info.idle_info.df_request_disabled = 1;
+		idle_info.idle_info.phy_ref_clk_off = 1;
+	}
+
+	dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDisplayIdleOptimizations,
+			idle_info.data);
+}
+
+void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_UpdatePmeRestore,
+			0);
+}
+
+void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
+}
+
+void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
+}
+
+void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
+}
+
+void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(clk_mgr,
+			VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
+}
+
+void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support)
+{
+	//TODO: Work with smu team to define optimization options.
+	unsigned int msg_id;
+
+	if (!clk_mgr->smu_present)
+		return;
+
+	if (support)
+		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
+	else
+		msg_id = VBIOSSMC_MSG_DisallowZstatesEntry;
+
+	dcn31_smu_send_msg_with_param(
+		clk_mgr,
+		msg_id,
+		0);
+
+}
+
+/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
+void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
+{
+	if (!clk_mgr->smu_present)
+		return;
+
+	dcn31_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_SetDtbClk,
+			enable);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h
new file mode 100644
index 000000000000..cd0b7e1e685f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DAL_DC_31_SMU_H_
+#define DAL_DC_31_SMU_H_
+
+#ifndef PMFW_DRIVER_IF_H
+#define PMFW_DRIVER_IF_H
+#define PMFW_DRIVER_IF_VERSION 4
+
+typedef struct {
+  int32_t value;
+  uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+  DSPCLK_DCFCLK = 0,
+  DSPCLK_DISPCLK,
+  DSPCLK_PIXCLK,
+  DSPCLK_PHYCLK,
+  DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+  uint16_t Freq; // in MHz
+  uint16_t Vid;  // min voltage in SVI3 VID
+} DisplayClockTable_t;
+
+typedef struct {
+  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MinMclk;
+  uint16_t MaxMclk;
+
+  uint8_t  WmSetting;
+  uint8_t  WmType;  // Used for normal pstate change or memory retraining
+  uint8_t  Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+  WM_SOCCLK = 0,
+  WM_DCFCLK,
+  WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+  CUSTOM_DPM_SETTING_GFXCLK,
+  CUSTOM_DPM_SETTING_CCLK,
+  CUSTOM_DPM_SETTING_FCLK_CCX,
+  CUSTOM_DPM_SETTING_FCLK_GFX,
+  CUSTOM_DPM_SETTING_FCLK_STALLS,
+  CUSTOM_DPM_SETTING_LCLK,
+  CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+  uint8_t             ActiveHystLimit;
+  uint8_t             IdleHystLimit;
+  uint8_t             FPS;
+  uint8_t             MinActiveFreqType;
+  FloatInIntFormat_t  MinActiveFreq;
+  FloatInIntFormat_t  PD_Data_limit;
+  FloatInIntFormat_t  PD_Data_time_constant;
+  FloatInIntFormat_t  PD_Data_error_coeff;
+  FloatInIntFormat_t  PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS   8
+#define NUM_DISPCLK_DPM_LEVELS  8
+#define NUM_DPPCLK_DPM_LEVELS   8
+#define NUM_SOCCLK_DPM_LEVELS   8
+#define NUM_VCN_DPM_LEVELS      8
+#define NUM_SOC_VOLTAGE_LEVELS  8
+#define NUM_DF_PSTATE_LEVELS    4
+
+typedef enum{
+  WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;
+  WCK_RATIO_1_2,
+  WCK_RATIO_1_4,
+  WCK_RATIO_MAX
+} WCK_RATIO_e;
+
+typedef struct {
+  uint32_t FClk;
+  uint32_t MemClk;
+  uint32_t Voltage;
+  uint8_t  WckRatio;
+  uint8_t  Spare[3];
+} DfPstateTable_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+typedef struct {
+  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+  uint32_t VClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t DClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+  DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
+
+  uint8_t  NumDcfClkLevelsEnabled;
+  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
+  uint8_t  NumSocClkLevelsEnabled;
+  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
+  uint8_t  NumDfPstatesEnabled;
+  uint8_t  spare[3];
+
+  uint32_t MinGfxClk;
+  uint32_t MaxGfxClk;
+} DpmClocks_t;
+
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL            0
+#define THROTTLER_STATUS_BIT_FPPT           1
+#define THROTTLER_STATUS_BIT_SPPT           2
+#define THROTTLER_STATUS_BIT_SPPT_APU       3
+#define THROTTLER_STATUS_BIT_THM_CORE       4
+#define THROTTLER_STATUS_BIT_THM_GFX        5
+#define THROTTLER_STATUS_BIT_THM_SOC        6
+#define THROTTLER_STATUS_BIT_TDC_VDD        7
+#define THROTTLER_STATUS_BIT_TDC_SOC        8
+#define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
+#define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
+#define THROTTLER_STATUS_BIT_EDC_CPU       11
+#define THROTTLER_STATUS_BIT_EDC_GFX       12
+
+typedef struct {
+  uint16_t GfxclkFrequency;             //[MHz]
+  uint16_t SocclkFrequency;             //[MHz]
+  uint16_t VclkFrequency;               //[MHz]
+  uint16_t DclkFrequency;               //[MHz]
+  uint16_t MemclkFrequency;             //[MHz]
+  uint16_t spare;
+
+  uint16_t GfxActivity;                 //[centi]
+  uint16_t UvdActivity;                 //[centi]
+
+  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
+
+  //3rd party tools in Windows need this info in the case of APUs
+  uint16_t CoreFrequency[8];            //[MHz]
+  uint16_t CorePower[8];                //[mW]
+  uint16_t CoreTemperature[8];          //[centi-Celsius]
+  uint16_t L3Frequency;                 //[MHz]
+  uint16_t L3Temperature;               //[centi-Celsius]
+
+  uint16_t GfxTemperature;              //[centi-Celsius]
+  uint16_t SocTemperature;              //[centi-Celsius]
+  uint16_t ThrottlerStatus;
+
+  uint16_t CurrentSocketPower;          //[mW]
+  uint16_t StapmOriginalLimit;          //[W]
+  uint16_t StapmCurrentLimit;           //[W]
+  uint16_t ApuPower;                    //[W]
+  uint16_t dGpuPower;                   //[W]
+
+  uint16_t VddTdcValue;                 //[mA]
+  uint16_t SocTdcValue;                 //[mA]
+  uint16_t VddEdcValue;                 //[mA]
+  uint16_t SocEdcValue;                 //[mA]
+
+  uint16_t InfrastructureCpuMaxFreq;    //[MHz]
+  uint16_t InfrastructureGfxMaxFreq;    //[MHz]
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT          2
+#define WORKLOAD_PPLIB_VR_BIT             3
+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
+#define WORKLOAD_PPLIB_COUNT              6
+
+#define TABLE_BIOS_IF            0 // Called by BIOS
+#define TABLE_WATERMARKS         1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM         2 // Called by Driver
+#define TABLE_SPARE1             3
+#define TABLE_DPMCLOCKS          4 // Called by Driver
+#define TABLE_MOMENTARY_PM       5 // Called by Tools
+#define TABLE_MODERN_STDBY       6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS        7 // Called by Driver
+#define TABLE_COUNT              8
+
+#endif
+
+struct dcn31_watermarks {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t MmHubPadding[7]; // SMU internal use
+};
+
+struct dcn31_smu_dpm_clks {
+	DpmClocks_t *dpm_clks;
+	union large_integer mc_address;
+};
+
+/* TODO: taken from vgh, may not be correct */
+struct display_idle_optimization {
+	unsigned int df_request_disabled : 1;
+	unsigned int phy_ref_clk_off     : 1;
+	unsigned int s0i2_rdy            : 1;
+	unsigned int reserved            : 29;
+};
+
+union display_idle_optimization_u {
+	struct display_idle_optimization idle_info;
+	uint32_t data;
+};
+
+int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
+int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
+int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
+int dcn31_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
+int dcn31_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
+int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
+void dcn31_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
+void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
+void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
+void dcn31_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
+void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
+void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
+void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
+
+void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support);
+void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
+
+#endif /* DAL_DC_31_SMU_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f03889b3654b..be1dbd3136ec 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -325,6 +325,48 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 	return ret;
 }
 
+/**
+ *****************************************************************************
+ *  Function: dc_stream_get_last_vrr_vtotal
+ *
+ *  @brief
+ *     Looks up the pipe context of dc_stream_state and gets the
+ *     last VTOTAL used by DRR (Dynamic Refresh Rate)
+ *
+ *  @param [in] dc: dc reference
+ *  @param [in] stream: Initial dc stream state
+ *  @param [in] adjust: Updated parameters for vertical_total_min and
+ *  vertical_total_max
+ *****************************************************************************
+ */
+bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
+		struct dc_stream_state *stream,
+		uint32_t *refresh_rate)
+{
+	bool status = false;
+
+	int i = 0;
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
+
+		if (pipe->stream == stream && pipe->stream_res.tg) {
+			/* Only execute if a function pointer has been defined for
+			 * the DC version in question
+			 */
+			if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) {
+				pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate);
+
+				status = true;
+
+				break;
+			}
+		}
+	}
+
+	return status;
+}
+
 bool dc_stream_get_crtc_position(struct dc *dc,
 		struct dc_stream_state **streams, int num_streams,
 		unsigned int *v_pos, unsigned int *nom_v_pos)
@@ -1482,6 +1524,13 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
 	return stream_mask;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+void dc_z10_restore(struct dc *dc)
+{
+	if (dc->hwss.z10_restore)
+		dc->hwss.z10_restore(dc);
+}
+#endif
 /*
  * Applies given context to HW and copy it into current context.
  * It's up to the user to release the src context afterwards.
@@ -1495,6 +1544,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
 	struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	dc_z10_restore(dc);
+#endif
 	dc_allow_idle_optimizations(dc, false);
 #endif
 
@@ -1917,8 +1969,13 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
 	if (u->plane_info->dcc.enable != u->surface->dcc.enable
 			|| u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
 			|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
+		/* During DCC on/off, stutter period is calculated before
+		 * DCC has fully transitioned. This results in incorrect
+		 * stutter period calculation. Triggering a full update will
+		 * recalculate stutter period.
+		 */
 		update_flags->bits.dcc_change = 1;
-		elevate_update_type(&update_type, UPDATE_TYPE_MED);
+		elevate_update_type(&update_type, UPDATE_TYPE_FULL);
 	}
 
 	if (resource_pixel_format_to_bpp(u->plane_info->format) !=
@@ -2569,6 +2626,10 @@ static void commit_planes_for_stream(struct dc *dc,
 	int i, j;
 	struct pipe_ctx *top_pipe_to_program = NULL;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	dc_z10_restore(dc);
+#endif
+
 	if (get_seamless_boot_stream_count(context) > 0 && surface_count > 0) {
 		/* Optimize seamless boot flag keeps clocks and watermarks high until
 		 * first flip. After first flip, optimization is required to lower
@@ -3024,6 +3085,9 @@ void dc_set_power_state(
 	case DC_ACPI_CM_POWER_STATE_D0:
 		dc_resource_state_construct(dc, dc->current_state);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		dc_z10_restore(dc);
+#endif
 		if (dc->ctx->dmub_srv)
 			dc_dmub_srv_wait_phy_init(dc->ctx->dmub_srv);
 
@@ -3256,10 +3320,13 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable)
 			continue;
 
 		if (link->psr_settings.psr_feature_enabled) {
-			if (enable && !link->psr_settings.psr_allow_active)
-				return dc_link_set_psr_allow_active(link, true, false, false);
-			else if (!enable && link->psr_settings.psr_allow_active)
-				return dc_link_set_psr_allow_active(link, false, true, false);
+			if (enable && !link->psr_settings.psr_allow_active) {
+				if (!dc_link_set_psr_allow_active(link, true, false, false))
+					return false;
+			} else if (!enable && link->psr_settings.psr_allow_active) {
+				if (!dc_link_set_psr_allow_active(link, false, true, false))
+					return false;
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 2a9080400bdd..15f987a63025 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -291,3 +291,136 @@ bool hwss_wait_for_blank_complete(
 
 	return true;
 }
+
+void get_mpctree_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	const struct tg_color pipe_colors[6] = {
+			{MAX_TG_COLOR_VALUE, 0, 0}, /* red */
+			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, /* orange */
+			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, /* yellow */
+			{0, MAX_TG_COLOR_VALUE, 0}, /* green */
+			{0, 0, MAX_TG_COLOR_VALUE}, /* blue */
+			{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, /* purple */
+	};
+
+	struct pipe_ctx *top_pipe = pipe_ctx;
+
+	while (top_pipe->top_pipe)
+		top_pipe = top_pipe->top_pipe;
+
+	*color = pipe_colors[top_pipe->pipe_idx];
+}
+
+void get_surface_visual_confirm_color(
+		const struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	uint32_t color_value = MAX_TG_COLOR_VALUE;
+
+	switch (pipe_ctx->plane_res.scl_data.format) {
+	case PIXEL_FORMAT_ARGB8888:
+		/* set border color to red */
+		color->color_r_cr = color_value;
+		if (pipe_ctx->plane_state->layer_index > 0) {
+			/* set border color to pink */
+			color->color_b_cb = color_value;
+			color->color_g_y = color_value * 0.5;
+		}
+		break;
+
+	case PIXEL_FORMAT_ARGB2101010:
+		/* set border color to blue */
+		color->color_b_cb = color_value;
+		if (pipe_ctx->plane_state->layer_index > 0) {
+			/* set border color to cyan */
+			color->color_g_y = color_value;
+		}
+		break;
+	case PIXEL_FORMAT_420BPP8:
+		/* set border color to green */
+		color->color_g_y = color_value;
+		break;
+	case PIXEL_FORMAT_420BPP10:
+		/* set border color to yellow */
+		color->color_g_y = color_value;
+		color->color_r_cr = color_value;
+		break;
+	case PIXEL_FORMAT_FP16:
+		/* set border color to white */
+		color->color_r_cr = color_value;
+		color->color_b_cb = color_value;
+		color->color_g_y = color_value;
+		if (pipe_ctx->plane_state->layer_index > 0) {
+			/* set border color to orange */
+			color->color_g_y = 0.22 * color_value;
+			color->color_b_cb = 0;
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void get_hdr_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	uint32_t color_value = MAX_TG_COLOR_VALUE;
+
+	/* Determine the overscan color based on the top-most (desktop) plane's context */
+	struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
+
+	while (top_pipe_ctx->top_pipe != NULL)
+		top_pipe_ctx = top_pipe_ctx->top_pipe;
+
+	switch (top_pipe_ctx->plane_res.scl_data.format) {
+	case PIXEL_FORMAT_ARGB2101010:
+		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
+			/* HDR10, ARGB2101010 - set border color to red */
+			color->color_r_cr = color_value;
+		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
+			/* FreeSync 2 ARGB2101010 - set border color to pink */
+			color->color_r_cr = color_value;
+			color->color_b_cb = color_value;
+		}
+		break;
+	case PIXEL_FORMAT_FP16:
+		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
+			/* HDR10, FP16 - set border color to blue */
+			color->color_b_cb = color_value;
+		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
+			/* FreeSync 2 HDR - set border color to green */
+			color->color_g_y = color_value;
+		}
+		break;
+	default:
+		/* SDR - set border color to Gray */
+		color->color_r_cr = color_value/2;
+		color->color_b_cb = color_value/2;
+		color->color_g_y = color_value/2;
+		break;
+	}
+}
+
+void get_surface_tile_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color)
+{
+	uint32_t color_value = MAX_TG_COLOR_VALUE;
+	/* Determine the overscan color based on the top-most (desktop) plane's context */
+	struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
+
+	while (top_pipe_ctx->top_pipe != NULL)
+		top_pipe_ctx = top_pipe_ctx->top_pipe;
+
+	switch (top_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
+	case DC_SW_LINEAR:
+		/* LINEAR Surface - set border color to red */
+		color->color_r_cr = color_value;
+		break;
+	default:
+		break;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c07b45c021d5..0f91280883a6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1099,24 +1099,6 @@ static bool dc_link_detect_helper(struct dc_link *link,
 			    dc_is_dvi_signal(link->connector_signal)) {
 				if (prev_sink)
 					dc_sink_release(prev_sink);
-				link_disconnect_sink(link);
-
-				return false;
-			}
-			/*
-			 * Abort detection for DP connectors if we have
-			 * no EDID and connector is active converter
-			 * as there are no display downstream
-			 *
-			 */
-			if (dc_is_dp_sst_signal(link->connector_signal) &&
-				(link->dpcd_caps.dongle_type ==
-						DISPLAY_DONGLE_DP_VGA_CONVERTER ||
-				link->dpcd_caps.dongle_type ==
-						DISPLAY_DONGLE_DP_DVI_CONVERTER)) {
-				if (prev_sink)
-					dc_sink_release(prev_sink);
-				link_disconnect_sink(link);
 
 				return false;
 			}
@@ -2701,16 +2683,24 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dmub_psr *psr = dc->res_pool->psr;
+	unsigned int panel_inst;
 
 	if (psr == NULL && force_static)
 		return false;
 
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return false;
+
 	link->psr_settings.psr_allow_active = allow_active;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (!allow_active)
+		dc_z10_restore(dc);
+#endif
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled) {
 		if (force_static && psr->funcs->psr_force_static)
-			psr->funcs->psr_force_static(psr);
-		psr->funcs->psr_enable(psr, allow_active, wait);
+			psr->funcs->psr_force_static(psr, panel_inst);
+		psr->funcs->psr_enable(psr, allow_active, wait, panel_inst);
 	} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
 		dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
 	else
@@ -2724,9 +2714,13 @@ bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
 	struct dc  *dc = link->ctx->dc;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dmub_psr *psr = dc->res_pool->psr;
+	unsigned int panel_inst;
+
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return false;
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_get_state(psr, state);
+		psr->funcs->psr_get_state(psr, state, panel_inst);
 	else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
 		dmcu->funcs->get_psr_state(dmcu, state);
 
@@ -2776,6 +2770,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 	struct dmcu *dmcu;
 	struct dmub_psr *psr;
 	int i;
+	unsigned int panel_inst;
 	/* updateSinkPsrDpcdConfig*/
 	union dpcd_psr_configuration psr_configuration;
 
@@ -2791,6 +2786,9 @@ bool dc_link_setup_psr(struct dc_link *link,
 	if (!dmcu && !psr)
 		return false;
 
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return false;
+
 
 	memset(&psr_configuration, 0, sizeof(psr_configuration));
 
@@ -2875,8 +2873,16 @@ bool dc_link_setup_psr(struct dc_link *link,
 	psr_context->psr_level.u32all = 0;
 
 	/*skip power down the single pipe since it blocks the cstate*/
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
+		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
+		if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
+			psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
+	}
+#else
 	if (link->ctx->asic_id.chip_family >= FAMILY_RV)
 		psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
+#endif
 
 	/* SMU will perform additional powerdown sequence.
 	 * For unsupported ASICs, set psr_level flag to skip PSR
@@ -2897,7 +2903,8 @@ bool dc_link_setup_psr(struct dc_link *link,
 	psr_context->frame_delay = 0;
 
 	if (psr)
-		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
+		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
+			link, psr_context, panel_inst);
 	else
 		link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
 
@@ -2915,10 +2922,14 @@ void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
 {
 	struct dc  *dc = link->ctx->dc;
 	struct dmub_psr *psr = dc->res_pool->psr;
+	unsigned int panel_inst;
 
-	// PSR residency measurements only supported on DMCUB
+	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
+		return;
+
+	/* PSR residency measurements only supported on DMCUB */
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_get_residency(psr, residency);
+		psr->funcs->psr_get_residency(psr, residency, panel_inst);
 	else
 		*residency = 0;
 }
@@ -3208,8 +3219,14 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
 				dp_get_panel_mode(pipe_ctx->stream->link);
 
 		config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
+		/*stream_enc_inst*/
 		config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
 		config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
+		config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+		config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+#endif
 		config.dpms_off = dpms_off;
 		config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
 		config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5a70f55e075c..919c94de2a20 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -435,7 +435,7 @@ bool dp_is_cr_done(enum dc_lane_count ln_count,
 	return true;
 }
 
-static bool is_ch_eq_done(enum dc_lane_count ln_count,
+bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
 		union lane_status *dpcd_lane_status)
 {
 	bool done = true;
@@ -446,7 +446,7 @@ static bool is_ch_eq_done(enum dc_lane_count ln_count,
 	return done;
 }
 
-static bool is_symbol_locked(enum dc_lane_count ln_count,
+bool dp_is_symbol_locked(enum dc_lane_count ln_count,
 		union lane_status *dpcd_lane_status)
 {
 	bool locked = true;
@@ -457,7 +457,7 @@ static bool is_symbol_locked(enum dc_lane_count ln_count,
 	return locked;
 }
 
-static inline bool is_interlane_aligned(union lane_align_status_updated align_status)
+bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
 {
 	return align_status.bits.INTERLANE_ALIGN_DONE == 1;
 }
@@ -865,9 +865,9 @@ static bool perform_post_lt_adj_req_sequence(
 			if (!dp_is_cr_done(lane_count, dpcd_lane_status))
 				return false;
 
-			if (!is_ch_eq_done(lane_count, dpcd_lane_status) ||
-					!is_symbol_locked(lane_count, dpcd_lane_status) ||
-					!is_interlane_aligned(dpcd_lane_status_updated))
+			if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
+					!dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
+					!dp_is_interlane_aligned(dpcd_lane_status_updated))
 				return false;
 
 			for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
@@ -913,7 +913,7 @@ static bool perform_post_lt_adj_req_sequence(
 }
 
 /* Only used for channel equalization */
-static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
+uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 {
 	unsigned int aux_rd_interval_us = 400;
 
@@ -998,7 +998,7 @@ static enum link_training_result perform_channel_equalization_sequence(
 
 		if (is_repeater(link, offset))
 			wait_time_microsec =
-					translate_training_aux_read_interval(
+					dp_translate_training_aux_read_interval(
 						link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 
 		dp_wait_for_training_aux_rd_interval(
@@ -1021,9 +1021,9 @@ static enum link_training_result perform_channel_equalization_sequence(
 			return LINK_TRAINING_EQ_FAIL_CR;
 
 		/* 6. check CHEQ done*/
-		if (is_ch_eq_done(lane_count, dpcd_lane_status) &&
-				is_symbol_locked(lane_count, dpcd_lane_status) &&
-				is_interlane_aligned(dpcd_lane_status_updated))
+		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
+				dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
+				dp_is_interlane_aligned(dpcd_lane_status_updated))
 			return LINK_TRAINING_SUCCESS;
 
 		/* 7. update VS/PE/PC2 in lt_settings*/
@@ -1917,6 +1917,8 @@ static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
 		link->type = dc_connection_single;
 		link->local_sink = link->remote_sinks[0];
 		link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
+		dc_sink_retain(link->local_sink);
+		dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 	} else if (mst_enable == true &&
 			link->type == dc_connection_single &&
 			link->remote_sinks[0] != NULL) {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 13c5c4a34a58..f7dfc8fefdfa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -332,7 +332,16 @@ void dp_set_hw_test_pattern(
 	uint32_t custom_pattern_size)
 {
 	struct encoder_set_dp_phy_pattern_param pattern_param = {0};
-	struct link_encoder *encoder = link->link_enc;
+	struct link_encoder *encoder;
+
+	/* Access link encoder based on whether it is statically
+	 * or dynamically assigned to a link.
+	 */
+	if (link->is_dig_mapping_flexible &&
+			link->dc->res_pool->funcs->link_encs_assign)
+		encoder = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
+	else
+		encoder = link->link_enc;
 
 	pattern_param.dp_phy_pattern = test_pattern;
 	pattern_param.custom_pattern = custom_pattern;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index cd864cc83539..5fe4c5f80b54 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -58,6 +58,9 @@
 #include "dcn301/dcn301_resource.h"
 #include "dcn302/dcn302_resource.h"
 #include "dcn303/dcn303_resource.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#include "../dcn31/dcn31_resource.h"
+#endif
 #endif
 
 #define DC_LOGGER_INIT(logger)
@@ -139,6 +142,14 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
 		dc_version = DCN_VERSION_3_01;
 		break;
 #endif
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case FAMILY_YELLOW_CARP:
+		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
+			dc_version = DCN_VERSION_3_1;
+		break;
+#endif
+
 	default:
 		dc_version = DCE_VERSION_UNKNOWN;
 		break;
@@ -222,6 +233,11 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 	case DCN_VERSION_3_03:
 		res_pool = dcn303_create_resource_pool(init_data, dc);
 		break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case DCN_VERSION_3_1:
+		res_pool = dcn31_create_resource_pool(init_data, dc);
+		break;
+#endif
 #endif
 	default:
 		break;
@@ -783,6 +799,11 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx)
 			if (split_idx == split_count) {
 				/* rightmost pipe is the remainder recout */
 				data->recout.width -= data->h_active * split_count - data->recout.x;
+
+				/* ODM combine cases with MPO we can get negative widths */
+				if (data->recout.width < 0)
+					data->recout.width = 0;
+
 				data->recout.x = 0;
 			} else
 				data->recout.width = data->h_active - data->recout.x;
@@ -1042,9 +1063,16 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
 	 * on certain displays, such as the Sharp 4k. 36bpp is needed
 	 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
 	 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
-	 * precision on at least DCN display engines.
+	 * precision on at least DCN display engines. However, at least
+	 * Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
+	 * so use only 30 bpp on DCE_VERSION_11_0. Testing with DCE 11.2 and 8.3
+	 * did not show such problems, so this seems to be the exception.
 	 */
-	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
+	if (plane_state->ctx->dce_version != DCE_VERSION_11_0)
+		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
+	else
+		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
+
 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
 
 	if (pipe_ctx->plane_res.xfm != NULL)
@@ -2114,6 +2142,16 @@ enum dc_status dc_validate_global_state(
 
 	if (!new_ctx)
 		return DC_ERROR_UNEXPECTED;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+
+	/*
+	 * Update link encoder to stream assignment.
+	 * TODO: Split out reason allocation from validation.
+	 */
+	if (dc->res_pool->funcs->link_encs_assign)
+		dc->res_pool->funcs->link_encs_assign(
+			dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
+#endif
 
 	if (dc->res_pool->funcs->validate_global) {
 		result = dc->res_pool->funcs->validate_global(dc, new_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 25fa712a7847..5420fda47bb7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -294,6 +294,9 @@ bool dc_stream_set_cursor_attributes(
 	stream->cursor_attributes = *attributes;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	dc_z10_restore(dc);
+#endif
 	/* disable idle optimizations while updating cursor */
 	if (dc->idle_optimizations_allowed) {
 		dc_allow_idle_optimizations(dc, false);
@@ -355,6 +358,9 @@ bool dc_stream_set_cursor_position(
 	dc = stream->ctx->dc;
 	res_ctx = &dc->current_state->res_ctx;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	dc_z10_restore(dc);
+#endif
 
 	/* disable idle optimizations if enabling cursor */
 	if (dc->idle_optimizations_allowed && !stream->cursor_position.enable && position->enable) {
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c0fbcbd4cbfc..a70697898025 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -45,7 +45,7 @@
 /* forward declaration */
 struct aux_payload;
 
-#define DC_VER "3.2.137"
+#define DC_VER "3.2.139"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
@@ -318,6 +318,7 @@ enum visual_confirm {
 	VISUAL_CONFIRM_HDR = 2,
 	VISUAL_CONFIRM_MPCTREE = 4,
 	VISUAL_CONFIRM_PSR = 5,
+	VISUAL_CONFIRM_SWIZZLE = 9,
 };
 
 enum dcc_option {
@@ -350,6 +351,13 @@ enum dcn_pwr_state {
 	DCN_PWR_STATE_LOW_POWER = 3,
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+enum dcn_z9_support_state {
+	DCN_Z9_SUPPORT_UNKNOWN,
+	DCN_Z9_SUPPORT_ALLOW,
+	DCN_Z9_SUPPORT_DISALLOW,
+};
+#endif
 /*
  * For any clocks that may differ per pipe
  * only the max is stored in this structure
@@ -367,6 +375,10 @@ struct dc_clocks {
 	int phyclk_khz;
 	int dramclk_khz;
 	bool p_state_change_support;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	enum dcn_z9_support_state z9_support;
+	bool dtbclk_en;
+#endif
 	enum dcn_pwr_state pwr_state;
 	/*
 	 * Elements below are not compared for the purposes of
@@ -433,6 +445,7 @@ struct dc_bw_validation_profile {
 
 union mem_low_power_enable_options {
 	struct {
+		bool vga: 1;
 		bool i2c: 1;
 		bool dmcu: 1;
 		bool dscl: 1;
@@ -487,6 +500,9 @@ struct dc_debug_options {
 	bool disable_pplib_clock_request;
 	bool disable_clock_gate;
 	bool disable_mem_low_power;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	bool pstate_enabled;
+#endif
 	bool disable_dmcu;
 	bool disable_psr;
 	bool force_abm_enable;
@@ -506,6 +522,9 @@ struct dc_debug_options {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
 #endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	bool disable_z9_mpc;
+#endif
 	unsigned int force_fclk_khz;
 	bool enable_tri_buf;
 	bool dmub_offload_enabled;
@@ -547,6 +566,10 @@ struct dc_debug_options {
 	bool force_enable_edp_fec;
 	/* FEC/PSR1 sequence enable delay in 100us */
 	uint8_t fec_enable_delay_in100us;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	bool disable_z10;
+	bool enable_sw_cntl_psr;
+#endif
 };
 
 struct dc_debug_data {
@@ -571,6 +594,9 @@ struct dc_phy_addr_space_config {
 		uint64_t page_table_start_addr;
 		uint64_t page_table_end_addr;
 		uint64_t page_table_base_addr;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		bool base_addr_is_mc_addr;
+#endif
 	} gart_config;
 
 	bool valid;
@@ -1308,6 +1334,9 @@ void dc_hardware_release(struct dc *dc);
 #endif
 
 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+void dc_z10_restore(struct dc *dc);
+#endif
 
 bool dc_enable_dmub_notifications(struct dc *dc);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 4b2854d1d981..48ca23e1e599 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -180,6 +180,29 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 		       dmub, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
 		       stream_mask, timeout) == DMUB_STATUS_OK;
 }
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
+{
+	struct dmub_srv *dmub;
+	struct dc_context *dc_ctx;
+	union dmub_fw_boot_status boot_status;
+	enum dmub_status status;
+
+	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
+		return false;
+
+	dmub = dc_dmub_srv->dmub;
+	dc_ctx = dc_dmub_srv->ctx;
+
+	status = dmub_srv_get_fw_boot_status(dmub, &boot_status);
+	if (status != DMUB_STATUS_OK) {
+		DC_ERROR("Error querying DMUB boot status: error=%d\n", status);
+		return false;
+	}
+
+	return boot_status.bits.restore_required;
+}
+#endif
 
 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
index f615e3a76d01..f5489c7aa770 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
@@ -62,6 +62,9 @@ bool dc_dmub_srv_cmd_with_reply_data(struct dc_dmub_srv *dc_dmub_srv, union dmub
 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 				    unsigned int stream_mask);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv);
+#endif
 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry);
 
 void dc_dmub_trace_event_control(struct dc *dc, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 0ab1a33dae84..b8ebc1f09538 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -465,6 +465,10 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
 				struct dc_stream_state *stream,
 				struct dc_crtc_timing_adjust *adjust);
 
+bool dc_stream_get_last_used_drr_vtotal(struct dc *dc,
+		struct dc_stream_state *stream,
+		uint32_t *refresh_rate);
+
 bool dc_stream_get_crtc_position(struct dc *dc,
 				 struct dc_stream_state **stream,
 				 int num_streams,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 0db1bad7a93c..8817a834383a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -635,6 +635,7 @@ struct dce_hwseq_registers {
 	uint32_t HPO_TOP_CLOCK_CONTROL;
 	uint32_t ODM_MEM_PWR_CTRL3;
 	uint32_t DMU_MEM_PWR_CNTL;
+	uint32_t MMHUBBUB_MEM_PWR_CNTL;
 };
  /* set field name */
 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\
@@ -875,7 +876,8 @@ struct dce_hwseq_registers {
 	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
-	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh)
+	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
 
 #define HWSEQ_DCN301_MASK_SH_LIST(mask_sh)\
 	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
@@ -1092,7 +1094,8 @@ struct dce_hwseq_registers {
 	type AZALIA_AUDIO_DTO_MODULE; \
 	type ODM_MEM_UNASSIGNED_PWR_MODE; \
 	type ODM_MEM_VBLANK_PWR_MODE; \
-	type DMCU_ERAM_MEM_PWR_FORCE;
+	type DMCU_ERAM_MEM_PWR_FORCE; \
+	type VGA_MEM_PWR_FORCE;
 
 #define HWSEQ_DCN3_REG_FIELD_LIST(type) \
 	type HPO_HDMISTREAMCLK_GATE_DIS;
@@ -1103,11 +1106,22 @@ struct dce_hwseq_registers {
 	type PANEL_DIGON_OVRD;\
 	type PANEL_PWRSEQ_TARGET_STATE_R;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define HWSEQ_DCN31_REG_FIELD_LIST(type) \
+	type DOMAIN_POWER_FORCEON;\
+	type DOMAIN_POWER_GATE;\
+	type DOMAIN_PGFSM_PWR_STATUS;\
+	type HPO_HDMISTREAMCLK_G_GATE_DIS;
+
+#endif
 struct dce_hwseq_shift {
 	HWSEQ_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN3_REG_FIELD_LIST(uint8_t)
 	HWSEQ_DCN301_REG_FIELD_LIST(uint8_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	HWSEQ_DCN31_REG_FIELD_LIST(uint8_t)
+#endif
 };
 
 struct dce_hwseq_mask {
@@ -1115,6 +1129,9 @@ struct dce_hwseq_mask {
 	HWSEQ_DCN_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN3_REG_FIELD_LIST(uint32_t)
 	HWSEQ_DCN301_REG_FIELD_LIST(uint32_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	HWSEQ_DCN31_REG_FIELD_LIST(uint32_t)
+#endif
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
index 08a4c8d029d9..f98400efdd9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
@@ -297,6 +297,7 @@ struct dce_mem_input_registers {
 	MI_DCP_PTE_MASK_SH_LIST(mask_sh, )
 
 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\
+	SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\
 	SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index 5e99553fcdd4..10d42ae0cffe 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -77,7 +77,7 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
 /*
  * Get PSR state from firmware.
  */
-static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
+static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state, uint8_t panel_inst)
 {
 	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
 	uint32_t raw_state = 0;
@@ -86,7 +86,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
 
 	do {
 		// Send gpint command and wait for ack
-		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30);
+		status = dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, panel_inst, 30);
 
 		if (status == DMUB_STATUS_OK) {
 			// GPINT was executed, get response
@@ -105,7 +105,7 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, enum dc_psr_state *state)
 /*
  * Set PSR version.
  */
-static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream)
+static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *stream, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
@@ -125,6 +125,8 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 		cmd.psr_set_version.psr_set_version_data.version = PSR_VERSION_UNSUPPORTED;
 		break;
 	}
+	cmd.psr_set_version.psr_set_version_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	cmd.psr_set_version.psr_set_version_data.panel_inst = panel_inst;
 	cmd.psr_set_version.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_version_data);
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
@@ -137,7 +139,7 @@ static bool dmub_psr_set_version(struct dmub_psr *dmub, struct dc_stream_state *
 /*
  * Enable/Disable PSR.
  */
-static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
+static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
@@ -147,6 +149,9 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.psr_enable.header.type = DMUB_CMD__PSR;
 
+	cmd.psr_enable.data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+	cmd.psr_enable.data.panel_inst = panel_inst;
+
 	if (enable)
 		cmd.psr_enable.header.sub_type = DMUB_CMD__PSR_ENABLE;
 	else
@@ -164,7 +169,7 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 	 */
 	if (wait) {
 		for (retry_count = 0; retry_count <= 1000; retry_count++) {
-			dmub_psr_get_state(dmub, &state);
+			dmub_psr_get_state(dmub, &state, panel_inst);
 
 			if (enable) {
 				if (state != PSR_STATE0)
@@ -186,13 +191,13 @@ static void dmub_psr_enable(struct dmub_psr *dmub, bool enable, bool wait)
 /*
  * Set PSR level.
  */
-static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
+static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	enum dc_psr_state state = PSR_STATE0;
 	struct dc_context *dc = dmub->ctx;
 
-	dmub_psr_get_state(dmub, &state);
+	dmub_psr_get_state(dmub, &state, panel_inst);
 
 	if (state == PSR_STATE0)
 		return;
@@ -202,7 +207,8 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
 	cmd.psr_set_level.header.sub_type = DMUB_CMD__PSR_SET_LEVEL;
 	cmd.psr_set_level.header.payload_bytes = sizeof(struct dmub_cmd_psr_set_level_data);
 	cmd.psr_set_level.psr_set_level_data.psr_level = psr_level;
-
+	cmd.psr_set_level.psr_set_level_data.cmd_version = PSR_VERSION_1;
+	cmd.psr_set_level.psr_set_level_data.panel_inst = panel_inst;
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 	dc_dmub_srv_cmd_execute(dc->dmub_srv);
 	dc_dmub_srv_wait_idle(dc->dmub_srv);
@@ -213,7 +219,8 @@ static void dmub_psr_set_level(struct dmub_psr *dmub, uint16_t psr_level)
  */
 static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 		struct dc_link *link,
-		struct psr_context *psr_context)
+		struct psr_context *psr_context,
+		uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
@@ -237,7 +244,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 		return false;
 
 	// First, set the psr version
-	if (!dmub_psr_set_version(dmub, pipe_ctx->stream))
+	if (!dmub_psr_set_version(dmub, pipe_ctx->stream, panel_inst))
 		return false;
 
 	// Program DP DPHY fast training registers
@@ -286,6 +293,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
 	copy_settings_data->fec_enable_status = (link->fec_state == dc_link_fec_enabled);
 	copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us;
+	copy_settings_data->cmd_version =  PSR_VERSION_1;
+	copy_settings_data->panel_inst = panel_inst;
 
 	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);
 	dc_dmub_srv_cmd_execute(dc->dmub_srv);
@@ -297,12 +306,15 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 /*
  * Send command to PSR to force static ENTER and ignore all state changes until exit
  */
-static void dmub_psr_force_static(struct dmub_psr *dmub)
+static void dmub_psr_force_static(struct dmub_psr *dmub, uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
 
 	memset(&cmd, 0, sizeof(cmd));
+
+	cmd.psr_force_static.psr_force_static_data.panel_inst = panel_inst;
+	cmd.psr_force_static.psr_force_static_data.cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
 	cmd.psr_force_static.header.type = DMUB_CMD__PSR;
 	cmd.psr_force_static.header.sub_type = DMUB_CMD__PSR_FORCE_STATIC;
 	cmd.psr_enable.header.payload_bytes = 0;
@@ -315,12 +327,13 @@ static void dmub_psr_force_static(struct dmub_psr *dmub)
 /*
  * Get PSR residency from firmware.
  */
-static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency)
+static void dmub_psr_get_residency(struct dmub_psr *dmub, uint32_t *residency, uint8_t panel_inst)
 {
 	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
+	uint16_t param = (uint16_t)(panel_inst << 8);
 
-	// Send gpint command and wait for ack
-	dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, 0, 30);
+	/* Send gpint command and wait for ack */
+	dmub_srv_send_gpint_command(srv, DMUB_GPINT__PSR_RESIDENCY, param, 30);
 
 	dmub_srv_get_gpint_response(srv, residency);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
index fe747c20a0d2..9675c269e649 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h
@@ -35,12 +35,17 @@ struct dmub_psr {
 };
 
 struct dmub_psr_funcs {
-	bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link, struct psr_context *psr_context);
-	void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait);
-	void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state);
-	void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level);
-	void (*psr_force_static)(struct dmub_psr *dmub);
-	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency);
+	bool (*psr_copy_settings)(struct dmub_psr *dmub, struct dc_link *link,
+	struct psr_context *psr_context, uint8_t panel_inst);
+	void (*psr_enable)(struct dmub_psr *dmub, bool enable, bool wait,
+	uint8_t panel_inst);
+	void (*psr_get_state)(struct dmub_psr *dmub, enum dc_psr_state *dc_psr_state,
+	uint8_t panel_inst);
+	void (*psr_set_level)(struct dmub_psr *dmub, uint16_t psr_level,
+	uint8_t panel_inst);
+	void (*psr_force_static)(struct dmub_psr *dmub, uint8_t panel_inst);
+	void (*psr_get_residency)(struct dmub_psr *dmub, uint32_t *residency,
+	uint8_t panel_inst);
 };
 
 struct dmub_psr *dmub_psr_create(struct dc_context *ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index e73198738fd8..53dd305fa6b0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -32,7 +32,6 @@
 #include "core_status.h"
 #include "resource.h"
 #include "dm_helpers.h"
-#include "dce110_hw_sequencer.h"
 #include "dce110_timing_generator.h"
 #include "dce/dce_hwseq.h"
 #include "gpio_service_interface.h"
@@ -49,6 +48,9 @@
 #include "link_encoder.h"
 #include "link_hwss.h"
 #include "dc_link_dp.h"
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#include "dccg.h"
+#endif
 #include "clock_source.h"
 #include "clk_mgr.h"
 #include "abm.h"
@@ -1310,41 +1312,6 @@ static void build_audio_output(
 			pipe_ctx->pll_settings.ss_percentage;
 }
 
-static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
-{
-	uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
-
-	switch (pipe_ctx->plane_res.scl_data.format) {
-	case PIXEL_FORMAT_ARGB8888:
-		/* set boarder color to red */
-		color->color_r_cr = color_value;
-		break;
-
-	case PIXEL_FORMAT_ARGB2101010:
-		/* set boarder color to blue */
-		color->color_b_cb = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP8:
-		/* set boarder color to green */
-		color->color_g_y = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP10:
-		/* set boarder color to yellow */
-		color->color_g_y = color_value;
-		color->color_r_cr = color_value;
-		break;
-	case PIXEL_FORMAT_FP16:
-		/* set boarder color to white */
-		color->color_r_cr = color_value;
-		color->color_b_cb = color_value;
-		color->color_g_y = color_value;
-		break;
-	default:
-		break;
-	}
-}
-
 static void program_scaler(const struct dc *dc,
 		const struct pipe_ctx *pipe_ctx)
 {
@@ -2124,11 +2091,31 @@ static void dce110_setup_audio_dto(
 
 			build_audio_output(context, pipe_ctx, &audio_output);
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+			/* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */
+			if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) {
+				/* disable audio DTBCLK DTO */
+				dc->res_pool->dccg->funcs->set_audio_dtbclk_dto(
+					dc->res_pool->dccg, 0);
+
+				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
+						pipe_ctx->stream_res.audio,
+						pipe_ctx->stream->signal,
+						&audio_output.crtc_info,
+						&audio_output.pll_info);
+			} else
+				pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
+					pipe_ctx->stream_res.audio,
+					pipe_ctx->stream->signal,
+					&audio_output.crtc_info,
+					&audio_output.pll_info);
+#else
 			pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
 				pipe_ctx->stream_res.audio,
 				pipe_ctx->stream->signal,
 				&audio_output.crtc_info,
 				&audio_output.pll_info);
+#endif
 			break;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
index d88a74559edd..27cbb5b42c7e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
@@ -2231,6 +2231,7 @@ static const struct timing_generator_funcs dce110_tg_funcs = {
 				dce110_timing_generator_enable_advanced_request,
 		.set_drr =
 				dce110_timing_generator_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control =
 			dce110_timing_generator_set_static_screen_control,
 		.set_test_pattern = dce110_timing_generator_set_test_pattern,
diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
index b57c466124e7..4af0c70098c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
@@ -1190,6 +1190,7 @@ static const struct timing_generator_funcs dce120_tg_funcs = {
 		.tear_down_global_swap_lock = dce120_timing_generator_tear_down_global_swap_lock,
 		.enable_advanced_request = dce120_timing_generator_enable_advanced_request,
 		.set_drr = dce120_timing_generator_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control = dce120_timing_generator_set_static_screen_control,
 		.set_test_pattern = dce120_timing_generator_set_test_pattern,
 		.arm_vert_intr = dce120_arm_vert_intr,
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 397e7f94e1e8..b8fd43dc010b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -209,6 +209,7 @@ static const struct timing_generator_funcs dce80_tg_funcs = {
 		.tear_down_global_swap_lock =
 				dce110_timing_generator_tear_down_global_swap_lock,
 		.set_drr = dce110_timing_generator_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control =
 			dce110_timing_generator_set_static_screen_control,
 		.set_test_pattern = dce110_timing_generator_set_test_pattern,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index 343a537172c7..83c3f944e9ab 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -139,6 +139,23 @@ struct dcn_hubbub_registers {
 	uint32_t DCHVM_CLK_CTRL;
 	uint32_t DCHVM_RIOMMU_CTRL0;
 	uint32_t DCHVM_RIOMMU_STAT0;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	uint32_t DCHUBBUB_DET0_CTRL;
+	uint32_t DCHUBBUB_DET1_CTRL;
+	uint32_t DCHUBBUB_DET2_CTRL;
+	uint32_t DCHUBBUB_DET3_CTRL;
+	uint32_t DCHUBBUB_COMPBUF_CTRL;
+	uint32_t COMPBUF_RESERVED_SPACE;
+	uint32_t DCHUBBUB_DEBUG_CTRL_0;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;
+	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D;
+#endif
 };
 
 /* set field name */
@@ -275,17 +292,48 @@ struct dcn_hubbub_registers {
 		type HOSTVM_POWERSTATUS; \
 		type RIOMMU_ACTIVE; \
 		type HOSTVM_PREFETCH_DONE
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define HUBBUB_RET_REG_FIELD_LIST(type) \
+		type DET_DEPTH;\
+		type DET0_SIZE;\
+		type DET1_SIZE;\
+		type DET2_SIZE;\
+		type DET3_SIZE;\
+		type DET0_SIZE_CURRENT;\
+		type DET1_SIZE_CURRENT;\
+		type DET2_SIZE_CURRENT;\
+		type DET3_SIZE_CURRENT;\
+		type COMPBUF_SIZE;\
+		type COMPBUF_SIZE_CURRENT;\
+		type COMPBUF_RESERVED_SPACE_64B;\
+		type COMPBUF_RESERVED_SPACE_ZS;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C;\
+		type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D;\
+		type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D
+#endif
+
 
 struct dcn_hubbub_shift {
 	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint8_t);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	HUBBUB_RET_REG_FIELD_LIST(uint8_t);
+#endif
 };
 
 struct dcn_hubbub_mask {
 	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
 	HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t);
 	HUBBUB_HVM_REG_FIELD_LIST(uint32_t);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	HUBBUB_RET_REG_FIELD_LIST(uint32_t);
+#endif
 };
 
 struct dc;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ef37d3abaa56..3b175af97388 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2407,83 +2407,6 @@ void dcn10_program_output_csc(struct dc *dc,
 	}
 }
 
-void dcn10_get_surface_visual_confirm_color(
-		const struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
-{
-	uint32_t color_value = MAX_TG_COLOR_VALUE;
-
-	switch (pipe_ctx->plane_res.scl_data.format) {
-	case PIXEL_FORMAT_ARGB8888:
-		/* set border color to red */
-		color->color_r_cr = color_value;
-		break;
-
-	case PIXEL_FORMAT_ARGB2101010:
-		/* set border color to blue */
-		color->color_b_cb = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP8:
-		/* set border color to green */
-		color->color_g_y = color_value;
-		break;
-	case PIXEL_FORMAT_420BPP10:
-		/* set border color to yellow */
-		color->color_g_y = color_value;
-		color->color_r_cr = color_value;
-		break;
-	case PIXEL_FORMAT_FP16:
-		/* set border color to white */
-		color->color_r_cr = color_value;
-		color->color_b_cb = color_value;
-		color->color_g_y = color_value;
-		break;
-	default:
-		break;
-	}
-}
-
-void dcn10_get_hdr_visual_confirm_color(
-		struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
-{
-	uint32_t color_value = MAX_TG_COLOR_VALUE;
-
-	// Determine the overscan color based on the top-most (desktop) plane's context
-	struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
-
-	while (top_pipe_ctx->top_pipe != NULL)
-		top_pipe_ctx = top_pipe_ctx->top_pipe;
-
-	switch (top_pipe_ctx->plane_res.scl_data.format) {
-	case PIXEL_FORMAT_ARGB2101010:
-		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
-			/* HDR10, ARGB2101010 - set border color to red */
-			color->color_r_cr = color_value;
-		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
-			/* FreeSync 2 ARGB2101010 - set border color to pink */
-			color->color_r_cr = color_value;
-			color->color_b_cb = color_value;
-		}
-		break;
-	case PIXEL_FORMAT_FP16:
-		if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
-			/* HDR10, FP16 - set border color to blue */
-			color->color_b_cb = color_value;
-		} else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
-			/* FreeSync 2 HDR - set border color to green */
-			color->color_g_y = color_value;
-		}
-		break;
-	default:
-		/* SDR - set border color to Gray */
-		color->color_r_cr = color_value/2;
-		color->color_b_cb = color_value/2;
-		color->color_g_y = color_value/2;
-		break;
-	}
-}
-
 static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
 {
 	struct dc_bias_and_scale bns_params = {0};
@@ -2502,9 +2425,26 @@ static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state
 		dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
 }
 
+void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
+{
+	struct mpc *mpc = dc->res_pool->mpc;
+
+	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
+		get_hdr_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
+		get_surface_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+		get_surface_tile_visual_confirm_color(pipe_ctx, color);
+	else
+		color_space_to_black_color(
+				dc, pipe_ctx->stream->output_color_space, color);
+
+	if (mpc->funcs->set_bg_color)
+		mpc->funcs->set_bg_color(mpc, color, mpcc_id);
+}
+
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct mpcc_blnd_cfg blnd_cfg = {{0}};
 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
@@ -2513,18 +2453,6 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	struct mpc *mpc = dc->res_pool->mpc;
 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
 
-	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
-		hws->funcs.get_hdr_visual_confirm_color(
-				pipe_ctx, &blnd_cfg.black_color);
-	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
-		hws->funcs.get_surface_visual_confirm_color(
-				pipe_ctx, &blnd_cfg.black_color);
-	} else {
-		color_space_to_black_color(
-				dc, pipe_ctx->stream->output_color_space,
-				&blnd_cfg.black_color);
-	}
-
 	if (per_pixel_alpha)
 		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
 	else
@@ -2559,6 +2487,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	/* If there is no full update, don't need to touch MPC tree*/
 	if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
 		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
+		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 		return;
 	}
 
@@ -2580,6 +2509,7 @@ void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 			NULL,
 			hubp->inst,
 			mpcc_id);
+	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index c9bdffe5989b..9ae07c77fdc0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -189,12 +189,6 @@ void dcn10_bios_golden_init(struct dc *dc);
 void dcn10_plane_atomic_power_down(struct dc *dc,
 		struct dpp *dpp,
 		struct hubp *hubp);
-void dcn10_get_surface_visual_confirm_color(
-		const struct pipe_ctx *pipe_ctx,
-		struct tg_color *color);
-void dcn10_get_hdr_visual_confirm_color(
-		struct pipe_ctx *pipe_ctx,
-		struct tg_color *color);
 bool dcn10_disconnect_pipes(
 		struct dc *dc,
 		struct dc_state *context);
@@ -206,4 +200,10 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc);
 
 void dcn10_get_dcc_en_bits(struct dc *dc, int *dcc_en_bits);
 
+void dcn10_update_visual_confirm_color(
+		struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color,
+		int mpcc_id);
+
 #endif /* __DC_HWSS_DCN10_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
index 680ca53455a2..34001a30d449 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_init.c
@@ -82,6 +82,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.set_abm_immediate_disable = dce110_set_abm_immediate_disable,
 	.set_pipe = dce110_set_pipe,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn10_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn10_private_funcs = {
@@ -111,8 +112,6 @@ static const struct hwseq_private_funcs dcn10_private_funcs = {
 	.dpp_pg_control = dcn10_dpp_pg_control,
 	.hubp_pg_control = dcn10_hubp_pg_control,
 	.dsc_pg_control = NULL,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 };
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 3e1a582e4b88..ba47553081a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -160,6 +160,14 @@ struct dcn10_link_enc_registers {
 	uint32_t PHYA_LINK_CNTL2;
 	uint32_t PHYB_LINK_CNTL2;
 	uint32_t PHYC_LINK_CNTL2;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	uint32_t DIO_LINKA_CNTL;
+	uint32_t DIO_LINKB_CNTL;
+	uint32_t DIO_LINKC_CNTL;
+	uint32_t DIO_LINKD_CNTL;
+	uint32_t DIO_LINKE_CNTL;
+	uint32_t DIO_LINKF_CNTL;
+#endif
 };
 
 #define LE_SF(reg_name, field_name, post_fix)\
@@ -459,17 +467,29 @@ struct dcn10_link_enc_registers {
 	type DPCS_TX_DATA_SWAP_10_BIT;\
 	type DPCS_TX_DATA_ORDER_INVERT_18_BIT;\
 	type RDPCS_TX_CLK_EN
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define DCN31_LINK_ENCODER_REG_FIELD_LIST(type) \
+	type ENC_TYPE_SEL;\
+	type HPO_DP_ENC_SEL;\
+	type HPO_HDMI_ENC_SEL
+#endif
 
 struct dcn10_link_enc_shift {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+#endif
 };
 
 struct dcn10_link_enc_mask {
 	DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
 	DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+#endif
 };
 
 struct dcn10_link_encoder {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index b096011acb49..11019c2c62cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -45,6 +45,8 @@ void mpc1_set_bg_color(struct mpc *mpc,
 	struct mpcc *bottommost_mpcc = mpc1_get_mpcc(mpc, mpcc_id);
 	uint32_t bg_r_cr, bg_g_y, bg_b_cb;
 
+	bottommost_mpcc->blnd_cfg.black_color = *bg_color;
+
 	/* find bottommost mpcc. */
 	while (bottommost_mpcc->mpcc_bot) {
 		bottommost_mpcc = bottommost_mpcc->mpcc_bot;
@@ -81,7 +83,6 @@ static void mpc1_update_blending(
 			MPCC_GLOBAL_ALPHA,		blnd_cfg->global_alpha,
 			MPCC_GLOBAL_GAIN,		blnd_cfg->global_gain);
 
-	mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
 	mpcc->blnd_cfg = *blnd_cfg;
 }
 
@@ -495,6 +496,7 @@ static const struct mpc_funcs dcn10_mpc_funcs = {
 	.set_output_csc = NULL,
 	.set_output_gamma = NULL,
 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
+	.set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn10_mpc_construct(struct dcn10_mpc *mpc10,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 677663cc7bff..3696faf12d86 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -968,6 +968,17 @@ void optc1_set_drr(
 	}
 }
 
+void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_SET(OTG_V_TOTAL_MAX, 0,
+		OTG_V_TOTAL_MAX, vtotal_max);
+
+	REG_SET(OTG_V_TOTAL_MIN, 0,
+		OTG_V_TOTAL_MIN, vtotal_min);
+}
+
 static void optc1_set_test_pattern(
 	struct timing_generator *optc,
 	/* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
@@ -1543,6 +1554,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = {
 		.unlock = optc1_unlock,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = NULL,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.set_test_pattern = optc1_set_test_pattern,
 		.program_stereo = optc1_program_stereo,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index cabfe83fd634..29d6fbe0093a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -171,6 +171,7 @@ struct dcn_optc_registers {
 	uint32_t OPTC_DATA_FORMAT_CONTROL;
 	uint32_t OPTC_BYTES_PER_PIXEL;
 	uint32_t OPTC_WIDTH_CONTROL;
+	uint32_t OTG_DRR_CONTROL;
 	uint32_t OTG_BLANK_DATA_COLOR;
 	uint32_t OTG_BLANK_DATA_COLOR_EXT;
 	uint32_t OTG_DRR_TRIGGER_WINDOW;
@@ -517,7 +518,8 @@ struct dcn_optc_registers {
 	type OTG_CRC_DSC_MODE;\
 	type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
 	type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
-	type OTG_CRC_DATA_FORMAT;
+	type OTG_CRC_DATA_FORMAT;\
+	type OTG_V_TOTAL_LAST_USED_BY_DRR;
 
 
 struct dcn_optc_shift {
@@ -666,6 +668,8 @@ void optc1_set_drr(
 	struct timing_generator *optc,
 	const struct drr_params *params);
 
+void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
+
 void optc1_set_static_screen_control(
 	struct timing_generator *optc,
 	uint32_t event_triggers,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index f962b905e79e..7daadb6a5233 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -1266,8 +1266,6 @@ static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *cont
 
 static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state)
 {
-	enum dc_status result = DC_OK;
-
 	enum surface_pixel_format surf_pix_format = plane_state->format;
 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
 
@@ -1279,7 +1277,7 @@ static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *pla
 		swizzle = DC_SW_64KB_S;
 
 	plane_state->tiling_info.gfx9.swizzle = swizzle;
-	return result;
+	return DC_OK;
 }
 
 struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
index 8774406120fc..5999b2da3a01 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
@@ -96,6 +96,39 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
 	return;
 }
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+		bool en)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL,
+			DCCG_FIFO_ERRDET_OVR_EN, en ? 1 : 0);
+}
+
+void dccg2_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 0,
+			OTG_DROP_PIXEL[otg_inst], 0);
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 1);
+}
+
+void dccg2_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_ADD_PIXEL[otg_inst], 0,
+			OTG_DROP_PIXEL[otg_inst], 0);
+	REG_UPDATE(OTG_PIXEL_RATE_CNTL[otg_inst],
+			OTG_DROP_PIXEL[otg_inst], 1);
+}
+
 void dccg2_init(struct dccg *dccg)
 {
 }
@@ -103,6 +136,9 @@ void dccg2_init(struct dccg *dccg)
 static const struct dccg_funcs dccg2_funcs = {
 	.update_dpp_dto = dccg2_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index d407f33308b9..62904d7ca100 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -34,12 +34,19 @@
 	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
-	SR(REFCLK_CNTL)
+	SR(REFCLK_CNTL),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SR(DISPCLK_FREQ_CHANGE_CNTL)
 
 #define DCCG_REG_LIST_DCN2() \
 	DCCG_COMMON_REG_LIST_DCN_BASE(),\
 	DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
-	DCCG_SRII(DTO_PARAM, DPPCLK, 5)
+	DCCG_SRII(DTO_PARAM, DPPCLK, 5),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5)
 
 #define DCCG_SF(reg_name, field_name, post_fix)\
 	.field_name = reg_name ## __ ## field_name ## post_fix
@@ -47,6 +54,9 @@
 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
 	.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
 
+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
+
 #define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
@@ -59,14 +69,49 @@
 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
 	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
 	DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
-	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
+	DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\
+	DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
+
+
+
 
 #define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
 	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
 	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
-	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh)
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 4, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 5, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 4, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 5, mask_sh)
+
+#define DCCG_MASK_SH_LIST_DCN2_1(mask_sh) \
+	DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 3, mask_sh)
+
 
 #define DCCG_REG_FIELD_LIST(type) \
 	type DPPCLK0_DTO_PHASE;\
@@ -74,7 +119,18 @@
 	type DPPCLK_DTO_ENABLE[6];\
 	type DPPCLK_DTO_DB_EN[6];\
 	type REFCLK_CLOCK_EN;\
-	type REFCLK_SRC_SEL;
+	type REFCLK_SRC_SEL;\
+	type DISPCLK_STEP_DELAY;\
+	type DISPCLK_STEP_SIZE;\
+	type DISPCLK_FREQ_RAMP_DONE;\
+	type DISPCLK_MAX_ERRDET_CYCLES;\
+	type DCCG_FIFO_ERRDET_RESET;\
+	type DCCG_FIFO_ERRDET_STATE;\
+	type DCCG_FIFO_ERRDET_OVR_EN;\
+	type DISPCLK_CHG_FWD_CORR_DISABLE;\
+	type DISPCLK_FREQ_CHANGE_CNTL;\
+	type OTG_ADD_PIXEL[MAX_PIPES];\
+	type OTG_DROP_PIXEL[MAX_PIPES];
 
 #define DCCG3_REG_FIELD_LIST(type) \
 	type PHYASYMCLK_FORCE_EN;\
@@ -84,24 +140,79 @@
 	type PHYCSYMCLK_FORCE_EN;\
 	type PHYCSYMCLK_FORCE_SRC_SEL;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define DCCG31_REG_FIELD_LIST(type) \
+	type PHYDSYMCLK_FORCE_EN;\
+	type PHYDSYMCLK_FORCE_SRC_SEL;\
+	type PHYESYMCLK_FORCE_EN;\
+	type PHYESYMCLK_FORCE_SRC_SEL;\
+	type DPSTREAMCLK_PIPE0_EN;\
+	type DPSTREAMCLK_PIPE1_EN;\
+	type DPSTREAMCLK_PIPE2_EN;\
+	type DPSTREAMCLK_PIPE3_EN;\
+	type HDMISTREAMCLK0_SRC_SEL;\
+	type HDMISTREAMCLK0_DTO_FORCE_DIS;\
+	type SYMCLK32_SE0_SRC_SEL;\
+	type SYMCLK32_SE1_SRC_SEL;\
+	type SYMCLK32_SE2_SRC_SEL;\
+	type SYMCLK32_SE3_SRC_SEL;\
+	type SYMCLK32_SE0_EN;\
+	type SYMCLK32_SE1_EN;\
+	type SYMCLK32_SE2_EN;\
+	type SYMCLK32_SE3_EN;\
+	type SYMCLK32_LE0_SRC_SEL;\
+	type SYMCLK32_LE1_SRC_SEL;\
+	type SYMCLK32_LE0_EN;\
+	type SYMCLK32_LE1_EN;\
+	type DTBCLK_DTO_ENABLE[MAX_PIPES];\
+	type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
+	type PIPE_DTO_SRC_SEL[MAX_PIPES];\
+	type DTBCLK_DTO_DIV[MAX_PIPES];\
+	type DCCG_AUDIO_DTO_SEL;\
+	type DCCG_AUDIO_DTO0_SOURCE_SEL;\
+	type DENTIST_DISPCLK_CHG_MODE;
+#endif
+
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
 	DCCG3_REG_FIELD_LIST(uint8_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCCG31_REG_FIELD_LIST(uint8_t)
+#endif
 };
 
 struct dccg_mask {
 	DCCG_REG_FIELD_LIST(uint32_t)
 	DCCG3_REG_FIELD_LIST(uint32_t)
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCCG31_REG_FIELD_LIST(uint32_t)
+#endif
 };
 
 struct dccg_registers {
 	uint32_t DPPCLK_DTO_CTRL;
 	uint32_t DPPCLK_DTO_PARAM[6];
 	uint32_t REFCLK_CNTL;
+	uint32_t DISPCLK_FREQ_CHANGE_CNTL;
+	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
 	uint32_t HDMICHARCLK_CLOCK_CNTL[6];
 	uint32_t PHYASYMCLK_CLOCK_CNTL;
 	uint32_t PHYBSYMCLK_CLOCK_CNTL;
 	uint32_t PHYCSYMCLK_CLOCK_CNTL;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	uint32_t PHYDSYMCLK_CLOCK_CNTL;
+	uint32_t PHYESYMCLK_CLOCK_CNTL;
+	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
+	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
+	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
+	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE;
+	uint32_t DCCG_AUDIO_DTO_SOURCE;
+	uint32_t DPSTREAMCLK_CNTL;
+	uint32_t HDMISTREAMCLK_CNTL;
+	uint32_t SYMCLK32_SE_CNTL;
+	uint32_t SYMCLK32_LE_CNTL;
+	uint32_t DENTIST_DISPCLK_CNTL;
+#endif
 };
 
 struct dcn_dccg {
@@ -117,6 +228,14 @@ void dccg2_get_dccg_ref_freq(struct dccg *dccg,
 		unsigned int xtalin_freq_inKhz,
 		unsigned int *dccg_ref_freq_inKhz);
 
+void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
+		bool en);
+void dccg2_otg_add_pixel(struct dccg *dccg,
+		uint32_t otg_inst);
+void dccg2_otg_drop_pixel(struct dccg *dccg,
+		uint32_t otg_inst);
+
+
 void dccg2_init(struct dccg *dccg);
 
 struct dccg *dccg2_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
index c478213ba7ad..a4fc70fa0957 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h
@@ -83,6 +83,15 @@ struct dcn20_hubbub {
 	int num_vmid;
 	struct dcn20_vmid vmid[16];
 	unsigned int detile_buf_size;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	unsigned int crb_size_segs;
+	unsigned int compbuf_size_segments;
+	unsigned int pixel_chunk_size;
+	unsigned int det0_size;
+	unsigned int det1_size;
+	unsigned int det2_size;
+	unsigned int det3_size;
+#endif
 };
 
 void hubbub2_construct(struct dcn20_hubbub *hubbub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
index f501c02c244b..2652d6abe9e3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h
@@ -216,16 +216,32 @@
 	type ROW_TTU_MODE; \
 	type NUM_PKRS
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+#define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \
+	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\
+	type HUBP_UNBOUNDED_REQ_MODE;\
+	type CURSOR_REQ_MODE;\
+	type HUBP_SOFT_RESET
+#endif
+
 struct dcn_hubp2_registers {
 	DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
 };
 
 struct dcn_hubp2_shift {
+#if   defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
+#else
 	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
+#endif
 };
 
 struct dcn_hubp2_mask {
+#if   defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCN31_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
+#else
 	DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
+#endif
 };
 
 struct dcn20_hubp {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 14e322761645..d0d6a94e4992 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -51,6 +51,7 @@
 #include "dccg.h"
 #include "dc_dmub_srv.h"
 #include "dce/dmub_hw_lock_mgr.h"
+#include "hw_sequencer.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -243,7 +244,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws)
 	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 
 	/* This value is dependent on the hardware pipeline delay so set once per SOC */
-	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
+	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
 }
 
 void dcn20_disable_vga(
@@ -1269,6 +1270,9 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx
 		new_pipe->update_flags.bits.gamut_remap = 1;
 		new_pipe->update_flags.bits.scaler = 1;
 		new_pipe->update_flags.bits.viewport = 1;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		new_pipe->update_flags.bits.det_size = 1;
+#endif
 		if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
 			new_pipe->update_flags.bits.odm = 1;
 			new_pipe->update_flags.bits.global_sync = 1;
@@ -1303,6 +1307,10 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx
 			new_pipe->update_flags.bits.global_sync = 1;
 	}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (old_pipe->det_buffer_size_kb != new_pipe->det_buffer_size_kb)
+		new_pipe->update_flags.bits.det_size = 1;
+#endif
 	/*
 	 * Detect opp / tg change, only set on change, not on enable
 	 * Assume mpcc inst = pipe index, if not this code needs to be updated
@@ -1418,6 +1426,10 @@ static void dcn20_update_dchubp_dpp(
 			&pipe_ctx->ttu_regs,
 			&pipe_ctx->rq_regs,
 			&pipe_ctx->pipe_dlg_param);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		if (hubp->funcs->set_unbounded_requesting)
+			hubp->funcs->set_unbounded_requesting(hubp, pipe_ctx->unbounded_req);
+#endif
 	}
 	if (pipe_ctx->update_flags.bits.hubp_interdependent)
 		hubp->funcs->hubp_setup_interdependent(
@@ -1597,6 +1609,12 @@ static void dcn20_program_pipe(
 			dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
 	}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (dc->res_pool->hubbub->funcs->program_det_size && pipe_ctx->update_flags.bits.det_size)
+		dc->res_pool->hubbub->funcs->program_det_size(
+			dc->res_pool->hubbub, pipe_ctx->plane_res.hubp->inst, pipe_ctx->det_buffer_size_kb);
+#endif
+
 	if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
 		dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
 
@@ -1687,6 +1705,12 @@ void dcn20_program_front_end_for_ctx(
 	for (i = 0; i < dc->res_pool->pipe_count; i++)
 		if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
 				|| context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
+		#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+			struct hubbub *hubbub = dc->res_pool->hubbub;
+
+			if (hubbub->funcs->program_det_size && context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
+				hubbub->funcs->program_det_size(hubbub, dc->current_state->res_ctx.pipe_ctx[i].plane_res.hubp->inst, 0);
+		#endif
 			hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
 			DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
 		}
@@ -1804,6 +1828,11 @@ void dcn20_prepare_bandwidth(
 					&context->bw_ctx.bw.dcn.watermarks,
 					dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
 					false);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	/* decrease compbuf size */
+	if (hubbub->funcs->program_compbuf_size)
+		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, false);
+#endif
 }
 
 void dcn20_optimize_bandwidth(
@@ -1822,6 +1851,11 @@ void dcn20_optimize_bandwidth(
 			dc->clk_mgr,
 			context,
 			true);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	/* increase compbuf size */
+	if (hubbub->funcs->program_compbuf_size)
+		hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
+#endif
 }
 
 bool dcn20_update_bandwidth(
@@ -2245,31 +2279,26 @@ void dcn20_reset_hw_ctx_wrap(
 	}
 }
 
-void dcn20_get_mpctree_visual_confirm_color(
-		struct pipe_ctx *pipe_ctx,
-		struct tg_color *color)
+void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx, struct tg_color *color, int mpcc_id)
 {
-	const struct tg_color pipe_colors[6] = {
-			{MAX_TG_COLOR_VALUE, 0, 0}, // red
-			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE / 4, 0}, // orange
-			{MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE, 0}, // yellow
-			{0, MAX_TG_COLOR_VALUE, 0}, // green
-			{0, 0, MAX_TG_COLOR_VALUE}, // blue
-			{MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
-	};
-
-	struct pipe_ctx *top_pipe = pipe_ctx;
-
-	while (top_pipe->top_pipe) {
-		top_pipe = top_pipe->top_pipe;
-	}
+	struct mpc *mpc = dc->res_pool->mpc;
 
-	*color = pipe_colors[top_pipe->pipe_idx];
+	// input to MPCC is always RGB, by default leave black_color at 0
+	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR)
+		get_hdr_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
+		get_surface_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE)
+		get_mpctree_visual_confirm_color(pipe_ctx, color);
+	else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE)
+		get_surface_tile_visual_confirm_color(pipe_ctx, color);
+
+	if (mpc->funcs->set_bg_color)
+		mpc->funcs->set_bg_color(mpc, color, mpcc_id);
 }
 
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
-	struct dce_hwseq *hws = dc->hwseq;
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
 	struct mpcc_blnd_cfg blnd_cfg = { {0} };
 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
@@ -2278,15 +2307,6 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	struct mpc *mpc = dc->res_pool->mpc;
 	struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
 
-	// input to MPCC is always RGB, by default leave black_color at 0
-	if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
-		hws->funcs.get_hdr_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
-	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
-		hws->funcs.get_surface_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
-	} else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
-		dcn20_get_mpctree_visual_confirm_color(pipe_ctx, &blnd_cfg.black_color);
-	}
-
 	if (per_pixel_alpha)
 		blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
 	else
@@ -2324,6 +2344,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 	if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
 		!pipe_ctx->update_flags.bits.mpcc) {
 		mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
+		dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 		return;
 	}
 
@@ -2345,6 +2366,7 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 			NULL,
 			hubp->inst,
 			mpcc_id);
+	dc->hwss.update_visual_confirm_color(dc, pipe_ctx, &blnd_cfg.black_color, mpcc_id);
 
 	ASSERT(new_mpcc != NULL);
 	hubp->opp_id = pipe_ctx->stream_res.opp->inst;
@@ -2539,6 +2561,10 @@ void dcn20_fpga_init_hw(struct dc *dc)
 
 		tg->funcs->tg_init(tg);
 	}
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+#endif
 }
 #ifndef TRIM_FSFT
 bool dcn20_optimize_timing_for_fsft(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index c69f766a40ce..6bba191cd33e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -146,5 +146,10 @@ void dcn20_set_disp_pattern_generator(const struct dc *dc,
 		const struct tg_color *solid_color,
 		int width, int height, int offset);
 
+void dcn20_update_visual_confirm_color(struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color,
+		int mpcc_id);
+
 #endif /* __DC_HWSS_DCN20_H__ */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
index b5bb613eed4d..5cfd4b0afea5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c
@@ -96,6 +96,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = {
 #endif
 	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color
 };
 
 static const struct hwseq_private_funcs dcn20_private_funcs = {
@@ -125,8 +126,6 @@ static const struct hwseq_private_funcs dcn20_private_funcs = {
 	.hubp_pg_control = dcn20_hubp_pg_control,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index 6a99fdd55e8c..947eb0df3f12 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -67,7 +67,6 @@ void mpc2_update_blending(
 	REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
 	REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
 
-	mpc1_set_bg_color(mpc, &blnd_cfg->black_color, mpcc_id);
 	mpcc->blnd_cfg = *blnd_cfg;
 }
 
@@ -557,6 +556,7 @@ const struct mpc_funcs dcn20_mpc_funcs = {
 	.set_output_gamma = mpc2_set_output_gamma,
 	.power_on_mpc_mem_pwr = mpc20_power_on_ogam_lut,
 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
+	.set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn20_mpc_construct(struct dcn20_mpc *mpc20,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 3139d90017ee..7fa9fc656b0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -520,6 +520,14 @@ bool optc2_configure_crc(struct timing_generator *optc,
 	return optc1_configure_crc(optc, params);
 }
 
+
+void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *refresh_rate)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
+}
+
 static struct timing_generator_funcs dcn20_tg_funcs = {
 		.validate_timing = optc1_validate_timing,
 		.program_timing = optc1_program_timing,
@@ -553,6 +561,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
 		.lock_doublebuffer_disable = optc2_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
@@ -591,4 +600,3 @@ void dcn20_timing_generator_init(struct optc *optc1)
 	optc1->min_h_sync_width = 4;//	Minimum HSYNC = 8 pixels asked By HW in the first place for no actual reason. Oculus Rift S will not light up with 8 as it's hsyncWidth is 6. Changing it to 4 to fix that issue.
 	optc1->min_v_sync_width = 1;
 }
-
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 3dee2ec2a1bb..be19a6885fbf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -42,7 +42,8 @@
 	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
 	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
 	SR(DWB_SOURCE_SELECT),\
-	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
+	SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \
+	SRI(OTG_DRR_CONTROL, OTG, inst)
 
 #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
 	TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
@@ -75,10 +76,14 @@
 	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
 	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
 	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
-	SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh)
+	SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh), \
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 void dcn20_timing_generator_init(struct optc *optc);
 
+void optc2_get_last_used_drr_vtotal(struct timing_generator *optc,
+		uint32_t *refresh_rate);
+
 bool optc2_enable_crtc(struct timing_generator *optc);
 
 void optc2_set_gsl(struct timing_generator *optc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 0d06307456a2..1b670c5de1aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1065,7 +1065,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
@@ -2789,7 +2789,6 @@ int dcn20_validate_apply_pipe_split_flags(
 				split[i] = 0;
 			} else if (get_num_odm_splits(pipe)) {
 				/* ODM -> MPC transition */
-				ASSERT(0); /* NOT expected yet */
 				if (pipe->prev_odm_pipe) {
 					split[i] = 0;
 					merge[i] = true;
@@ -3070,6 +3069,18 @@ static void dcn20_calculate_wm(
 	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
+{
+	int i;
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+	}
+	return false;
+}
+#endif
+
 void dcn20_calculate_dlg_params(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
@@ -3077,6 +3088,9 @@ void dcn20_calculate_dlg_params(
 		int vlevel)
 {
 	int i, pipe_idx;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	int plane_count;
+#endif
 
 	/* Writeback MCIF_WB arbitration parameters */
 	dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
@@ -3091,6 +3105,21 @@ void dcn20_calculate_dlg_params(
 		context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
 							!= dm_dram_clock_change_unsupported;
 	context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	context->bw_ctx.bw.dcn.clk.z9_support = (context->bw_ctx.dml.vba.StutterPeriod > 5000.0) ?
+			DCN_Z9_SUPPORT_ALLOW : DCN_Z9_SUPPORT_DISALLOW;
+
+	plane_count = 0;
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (context->res_ctx.pipe_ctx[i].plane_state)
+			plane_count++;
+	}
+
+	if (plane_count == 0)
+		context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
+
+	context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
+#endif
 
 	if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
 		context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
@@ -3102,6 +3131,10 @@ void dcn20_calculate_dlg_params(
 		pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
 		pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+			context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
+			context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
+#endif
 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
 			context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
@@ -3115,6 +3148,11 @@ void dcn20_calculate_dlg_params(
 	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
 	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
+						- context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
+#endif
+
 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 		bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
index 60cf3ff68cb0..33fc9aa8621b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_dccg.c
@@ -100,6 +100,9 @@ void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
 static const struct dccg_funcs dccg21_funcs = {
 	.update_dpp_dto = dccg21_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
index 4f20a85ff396..54c11ba550ae 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
@@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
 	.is_abm_supported = dcn21_is_abm_supported,
 	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn21_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn21_private_funcs = {
 	.hubp_pg_control = dcn20_hubp_pg_control,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 38a2aa87f5f5..f3d98e3ba624 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -448,11 +448,11 @@ static const struct dccg_registers dccg_regs = {
 };
 
 static const struct dccg_shift dccg_shift = {
-		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
+		DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
 };
 
 static const struct dccg_mask dccg_mask = {
-		DCCG_MASK_SH_LIST_DCN2(_MASK)
+		DCCG_MASK_SH_LIST_DCN2_1(_MASK)
 };
 
 #define opp_regs(id)\
@@ -1575,12 +1575,10 @@ static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_li
 	low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
 	low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
 
-	if (clk_table->num_entries < MAX_NUM_DPM_LVL) {
-		for (i = clk_table->num_entries; i > 1; i--)
-			clk_table->entries[i] = clk_table->entries[i-1];
-		clk_table->entries[1] = clk_table->entries[0];
-		clk_table->num_entries++;
-	}
+	for (i = clk_table->num_entries; i > 1; i--)
+		clk_table->entries[i] = clk_table->entries[i-1];
+	clk_table->entries[1] = clk_table->entries[0];
+	clk_table->num_entries++;
 
 	return low_pstate_lvl;
 }
@@ -1612,6 +1610,10 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 			}
 		}
 
+		/* clk_table[1] is reserved for min DF PState.  skip here to fill in later. */
+		if (i == 1)
+			k++;
+
 		clock_limits[k].state = k;
 		clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
 		clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
@@ -1628,25 +1630,14 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
 
 		k++;
 	}
-
-	if (clk_table->num_entries >= MAX_NUM_DPM_LVL) {
-		for (i = 0; i < clk_table->num_entries + 1; i++)
-			dcn2_1_soc.clock_limits[i] = clock_limits[i];
-	} else {
-		dcn2_1_soc.clock_limits[0] = clock_limits[0];
-		for (i = 2; i < clk_table->num_entries + 1; i++) {
-			dcn2_1_soc.clock_limits[i] = clock_limits[i - 1];
-			dcn2_1_soc.clock_limits[i].state = i;
-		}
-	}
-
+	for (i = 0; i < clk_table->num_entries + 1; i++)
+		dcn2_1_soc.clock_limits[i] = clock_limits[i];
 	if (clk_table->num_entries) {
+		dcn2_1_soc.num_states = clk_table->num_entries + 1;
 		/* fill in min DF PState */
 		dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
-		dcn2_1_soc.num_states = clk_table->num_entries;
 		/* duplicate last level */
-		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] =
-			dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
+		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
 		dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
index b822a13e40ce..d445dfefc047 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.c
@@ -46,6 +46,9 @@
 static const struct dccg_funcs dccg3_funcs = {
 	.update_dpp_dto = dccg2_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
index 029dda13a464..35a613bb08bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h
@@ -38,10 +38,25 @@
 
 #define DCCG_REG_LIST_DCN30() \
 	DCCG_REG_LIST_DCN2(),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\
 	SR(PHYASYMCLK_CLOCK_CNTL),\
 	SR(PHYBSYMCLK_CLOCK_CNTL),\
 	SR(PHYCSYMCLK_CLOCK_CNTL)
 
+#define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \
+	DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\
+	DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
+
 #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \
 	DCCG_MASK_SH_LIST_DCN2(mask_sh),\
 	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
@@ -49,7 +64,7 @@
 	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
 	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
 	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
-	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh)
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
 
 struct dccg *dccg3_create(
 	struct dc_context *ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 83685310a391..ef5d0b778a72 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -651,6 +651,11 @@ void dcn30_init_hw(struct dc *dc)
 	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
 		dc->res_pool->hubbub->funcs->force_pstate_change_control(
 				dc->res_pool->hubbub, false, false);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+#endif
+
 }
 
 void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
index bf7fa98b39eb..3a5b53dd2f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c
@@ -99,6 +99,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = {
 	.set_pipe = dcn21_set_pipe,
 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn30_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn30_private_funcs = {
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
index 950c9bfd53de..a82319f4d081 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mpc.c
@@ -1431,7 +1431,7 @@ const struct mpc_funcs dcn30_mpc_funcs = {
 	.release_rmu = mpcc3_release_rmu,
 	.power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut,
 	.get_mpc_out_mux = mpc1_get_mpc_out_mux,
-
+	.set_bg_color = mpc1_set_bg_color,
 };
 
 void dcn30_mpc_construct(struct dcn30_mpc *mpc30,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index ac478bdcfb2a..f37e8254df21 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -315,6 +315,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = {
 		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
 		.enable_optc_clock = optc1_enable_optc_clock,
 		.set_drr = optc1_set_drr,
+		.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
 		.set_static_screen_control = optc1_set_static_screen_control,
 		.program_stereo = optc1_program_stereo,
 		.is_stereo_left_eye = optc1_is_stereo_left_eye,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
index 379616831636..736e63bc80c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
@@ -87,7 +87,8 @@
 	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
 	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
 	SR(GSL_SOURCE_SELECT),\
-	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI(OTG_DRR_CONTROL, OTG, inst)
 
 
 #define OPTC_COMMON_REG_LIST_DCN3_0(inst) \
@@ -233,7 +234,8 @@
 	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
 	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
 	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh)
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+	SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
 
 #define OPTC_COMMON_MASK_SH_LIST_DCN3_0(mask_sh)\
 	OPTC_COMMON_MASK_SH_LIST_DCN3_BASE(mask_sh),\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
index 39920422409d..596c97dce67e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c
@@ -840,7 +840,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.timing_trace = false,
 	.clock_trace = true,
 	.disable_pplib_clock_request = true,
-	.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+	.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 	.force_single_disp_pipe_split = false,
 	.disable_dcc = DCC_ENABLE,
 	.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
index 420da414929c..97e9be87afd9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_dccg.c
@@ -45,6 +45,9 @@
 static const struct dccg_funcs dccg301_funcs = {
 	.update_dpp_dto = dccg2_update_dpp_dto,
 	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
+	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
+	.otg_add_pixel = dccg2_otg_add_pixel,
+	.otg_drop_pixel = dccg2_otg_drop_pixel,
 	.dccg_init = dccg2_init
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
index 70b053d9ba40..e85b695f2351 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
@@ -101,6 +101,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
 	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
 	.optimize_pwr_state = dcn21_optimize_pwr_state,
 	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn301_private_funcs = {
@@ -131,8 +132,6 @@ static const struct hwseq_private_funcs dcn301_private_funcs = {
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn20_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
index e8580cccbebf..0a6d58dd8f6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_hwseq.c
@@ -86,17 +86,12 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool po
 				1, 1000);
 		break;
 	case 4: /* DPP4 */
-		/*
-		 * Do not power gate DPP4, should be left at HW default, power on permanently.
-		 * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
-		 * reset.
-		 * REG_UPDATE(DOMAIN9_PG_CONFIG,
-		 *		DOMAIN9_POWER_GATE, power_gate);
-		 *
-		 * REG_WAIT(DOMAIN9_PG_STATUS,
-		 *		DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
-		 *		1, 1000);
-		 */
+		REG_UPDATE(DOMAIN9_PG_CONFIG,
+				DOMAIN9_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN9_PG_STATUS,
+				DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
@@ -148,17 +143,12 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
 				1, 1000);
 		break;
 	case 4: /* DCHUBP4 */
-		/*
-		 * Do not power gate DCHUB4, should be left at HW default, power on permanently.
-		 * PG on Pipe4 is De-featured, attempting to put it to PG state may result in hard
-		 * reset.
-		 * REG_UPDATE(DOMAIN8_PG_CONFIG,
-		 *		DOMAIN8_POWER_GATE, power_gate);
-		 *
-		 * REG_WAIT(DOMAIN8_PG_STATUS,
-		 *		DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
-		 *		1, 1000);
-		 */
+		REG_UPDATE(DOMAIN8_PG_CONFIG,
+				DOMAIN8_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN8_PG_STATUS,
+				DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 00cb6d11ed0d..b16d19a25d88 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -211,7 +211,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
index aff0230c9193..758f89ba0192 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
@@ -193,7 +193,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.timing_trace = false,
 		.clock_trace = true,
 		.disable_pplib_clock_request = true,
-		.pipe_split_policy = MPC_SPLIT_DYNAMIC,
+		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 		.force_single_disp_pipe_split = false,
 		.disable_dcc = DCC_ENABLE,
 		.vsr_support = true,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/Makefile b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile
new file mode 100644
index 000000000000..5dcdc5a858fe
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/Makefile
@@ -0,0 +1,42 @@
+#
+# (c) Copyright 2020 Advanced Micro Devices, Inc. All the rights reserved
+#
+#  All rights reserved.  This notice is intended as a precaution against
+#  inadvertent publication and does not imply publication or any waiver
+#  of confidentiality.  The year included in the foregoing notice is the
+#  year of creation of the work.
+#
+#  Authors: AMD
+#
+# Makefile for dcn31.
+
+DCN31 = dcn31_resource.o dcn31_hubbub.o dcn31_hwseq.o dcn31_init.o dcn31_hubp.o \
+	dcn31_dccg.o dcn31_optc.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o
+
+ifdef CONFIG_X86
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -msse
+endif
+
+ifdef CONFIG_PPC64
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -mhard-float -maltivec
+endif
+
+ifdef CONFIG_CC_IS_GCC
+ifeq ($(call cc-ifversion, -lt, 0701, y), y)
+IS_OLD_GCC = 1
+endif
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -mhard-float
+endif
+
+ifdef IS_OLD_GCC
+# Stack alignment mismatch, proceed with caution.
+# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
+# (8B stack alignment).
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -mpreferred-stack-boundary=4
+else
+CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o += -msse2
+endif
+
+AMD_DAL_DCN31 = $(addprefix $(AMDDALPATH)/dc/dcn31/,$(DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DCN31)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
new file mode 100644
index 000000000000..696c9307715d
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dcn31_dccg.h"
+
+#define TO_DCN_DCCG(dccg)\
+	container_of(dccg, struct dcn_dccg, base)
+
+#define REG(reg) \
+	(dccg_dcn->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
+
+#define CTX \
+	dccg_dcn->base.ctx
+#define DC_LOGGER \
+	dccg->ctx->logger
+
+void dccg31_set_physymclk(
+		struct dccg *dccg,
+		int phy_inst,
+		enum physymclk_clock_source clk_src,
+		bool force_enable)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	/* Force PHYSYMCLK on and Select phyd32clk as the source of clock which is output to PHY through DCIO */
+	switch (phy_inst) {
+	case 0:
+		if (force_enable)
+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
+					PHYASYMCLK_FORCE_EN, 1,
+					PHYASYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
+					PHYASYMCLK_FORCE_EN, 0,
+					PHYASYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 1:
+		if (force_enable)
+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
+					PHYBSYMCLK_FORCE_EN, 1,
+					PHYBSYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
+					PHYBSYMCLK_FORCE_EN, 0,
+					PHYBSYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 2:
+		if (force_enable)
+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
+					PHYCSYMCLK_FORCE_EN, 1,
+					PHYCSYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
+					PHYCSYMCLK_FORCE_EN, 0,
+					PHYCSYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 3:
+		if (force_enable)
+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
+					PHYDSYMCLK_FORCE_EN, 1,
+					PHYDSYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
+					PHYDSYMCLK_FORCE_EN, 0,
+					PHYDSYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	case 4:
+		if (force_enable)
+			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
+					PHYESYMCLK_FORCE_EN, 1,
+					PHYESYMCLK_FORCE_SRC_SEL, clk_src);
+		else
+			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
+					PHYESYMCLK_FORCE_EN, 0,
+					PHYESYMCLK_FORCE_SRC_SEL, 0);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+/* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
+void dccg31_set_dtbclk_dto(
+		struct dccg *dccg,
+		int dtbclk_inst,
+		int req_dtbclk_khz,
+		int num_odm_segments,
+		const struct dc_crtc_timing *timing)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+	uint32_t dtbdto_div;
+
+	/* Mode	                DTBDTO Rate       DTBCLK_DTO<x>_DIV Register
+	 * ODM 4:1 combine      pixel rate/4      2
+	 * ODM 2:1 combine      pixel rate/2      4
+	 * non-DSC 4:2:0 mode   pixel rate/2      4
+	 * DSC native 4:2:0     pixel rate/2      4
+	 * DSC native 4:2:2     pixel rate/2      4
+	 * Other modes          pixel rate        8
+	 */
+	if (num_odm_segments == 4) {
+		dtbdto_div = 2;
+		req_dtbclk_khz = req_dtbclk_khz / 4;
+	} else if ((num_odm_segments == 2) ||
+			(timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) ||
+			(timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
+					&& !timing->dsc_cfg.ycbcr422_simple)) {
+		dtbdto_div = 4;
+		req_dtbclk_khz = req_dtbclk_khz / 2;
+	} else
+		dtbdto_div = 8;
+
+	if (dccg->ref_dtbclk_khz && req_dtbclk_khz) {
+		uint32_t modulo, phase;
+
+		// phase / modulo = dtbclk / dtbclk ref
+		modulo = dccg->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
+			dccg->ref_dtbclk_khz);
+
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLK_DTO_DIV[dtbclk_inst], dtbdto_div);
+
+		REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], modulo);
+		REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], phase);
+
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLK_DTO_ENABLE[dtbclk_inst], 1);
+
+		REG_WAIT(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLKDTO_ENABLE_STATUS[dtbclk_inst], 1,
+				1, 100);
+
+		/* The recommended programming sequence to enable DTBCLK DTO to generate
+		 * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should
+		 * be set only after DTO is enabled
+		 */
+		REG_UPDATE(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				PIPE_DTO_SRC_SEL[dtbclk_inst], 1);
+
+		dccg->dtbclk_khz[dtbclk_inst] = req_dtbclk_khz;
+	} else {
+		REG_UPDATE_3(OTG_PIXEL_RATE_CNTL[dtbclk_inst],
+				DTBCLK_DTO_ENABLE[dtbclk_inst], 0,
+				PIPE_DTO_SRC_SEL[dtbclk_inst], 0,
+				DTBCLK_DTO_DIV[dtbclk_inst], dtbdto_div);
+
+		REG_WRITE(DTBCLK_DTO_MODULO[dtbclk_inst], 0);
+		REG_WRITE(DTBCLK_DTO_PHASE[dtbclk_inst], 0);
+
+		dccg->dtbclk_khz[dtbclk_inst] = 0;
+	}
+}
+
+void dccg31_set_audio_dtbclk_dto(
+		struct dccg *dccg,
+		uint32_t req_audio_dtbclk_khz)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (dccg->ref_dtbclk_khz && req_audio_dtbclk_khz) {
+		uint32_t modulo, phase;
+
+		// phase / modulo = dtbclk / dtbclk ref
+		modulo = dccg->ref_dtbclk_khz * 1000;
+		phase = div_u64((((unsigned long long)modulo * req_audio_dtbclk_khz) + dccg->ref_dtbclk_khz - 1),
+			dccg->ref_dtbclk_khz);
+
+
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, modulo);
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, phase);
+
+		//REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+		//		DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO, 1);
+
+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+				DCCG_AUDIO_DTO_SEL, 4);  //  04 - DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK
+
+		dccg->audio_dtbclk_khz = req_audio_dtbclk_khz;
+	} else {
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_PHASE, 0);
+		REG_WRITE(DCCG_AUDIO_DTBCLK_DTO_MODULO, 0);
+
+		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
+				DCCG_AUDIO_DTO_SEL, 3);  //  03 - DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO
+
+		dccg->audio_dtbclk_khz = 0;
+	}
+}
+
+static void dccg31_get_dccg_ref_freq(struct dccg *dccg,
+		unsigned int xtalin_freq_inKhz,
+		unsigned int *dccg_ref_freq_inKhz)
+{
+	/*
+	 * Assume refclk is sourced from xtalin
+	 * expect 24MHz
+	 */
+	*dccg_ref_freq_inKhz = xtalin_freq_inKhz;
+	return;
+}
+
+static void dccg31_set_dispclk_change_mode(
+	struct dccg *dccg,
+	enum dentist_dispclk_change_mode change_mode)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE,
+		   change_mode == DISPCLK_CHANGE_MODE_RAMPING ? 2 : 0);
+}
+
+void dccg31_init(struct dccg *dccg)
+{
+}
+
+static const struct dccg_funcs dccg31_funcs = {
+	.update_dpp_dto = dccg2_update_dpp_dto,
+	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
+	.dccg_init = dccg31_init,
+	.set_physymclk = dccg31_set_physymclk,
+	.set_dtbclk_dto = dccg31_set_dtbclk_dto,
+	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
+	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
+};
+
+struct dccg *dccg31_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask)
+{
+	struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
+	struct dccg *base;
+
+	if (dccg_dcn == NULL) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	base = &dccg_dcn->base;
+	base->ctx = ctx;
+	base->funcs = &dccg31_funcs;
+
+	dccg_dcn->regs = regs;
+	dccg_dcn->dccg_shift = dccg_shift;
+	dccg_dcn->dccg_mask = dccg_mask;
+
+	return &dccg_dcn->base;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
new file mode 100644
index 000000000000..706ad80ba873
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DCN31_DCCG_H__
+#define __DCN31_DCCG_H__
+
+#include "dcn30/dcn30_dccg.h"
+
+#define DCCG_SFII(block, reg_name, field_prefix, field_name, inst, post_fix)\
+	.field_prefix ## _ ## field_name[inst] = block ## inst ## _ ## reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
+
+
+#define DCCG_REG_LIST_DCN31() \
+	SR(DPPCLK_DTO_CTRL),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
+	DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
+	SR(PHYASYMCLK_CLOCK_CNTL),\
+	SR(PHYBSYMCLK_CLOCK_CNTL),\
+	SR(PHYCSYMCLK_CLOCK_CNTL),\
+	SR(PHYDSYMCLK_CLOCK_CNTL),\
+	SR(PHYESYMCLK_CLOCK_CNTL),\
+	SR(DPSTREAMCLK_CNTL),\
+	SR(SYMCLK32_SE_CNTL),\
+	SR(SYMCLK32_LE_CNTL),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
+	DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 0),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 1),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 2),\
+	DCCG_SRII(PHASE, DTBCLK_DTO, 3),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
+	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
+	SR(DCCG_AUDIO_DTO_SOURCE),\
+	SR(DENTIST_DISPCLK_CNTL)
+
+
+#define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
+	DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_EN, mask_sh),\
+	DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_FORCE_SRC_SEL, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE0_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE1_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE2_EN, mask_sh),\
+	DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK_PIPE3_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\
+	DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLKDTO, ENABLE_STATUS, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 0, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 1, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 2, mask_sh),\
+	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
+	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
+	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh)
+
+
+struct dccg *dccg31_create(
+	struct dc_context *ctx,
+	const struct dccg_registers *regs,
+	const struct dccg_shift *dccg_shift,
+	const struct dccg_mask *dccg_mask);
+
+void dccg31_init(struct dccg *dccg);
+
+void dccg31_set_physymclk(
+		struct dccg *dccg,
+		int phy_inst,
+		enum physymclk_clock_source clk_src,
+		bool force_enable);
+
+void dccg31_set_audio_dtbclk_dto(
+		struct dccg *dccg,
+		uint32_t req_audio_dtbclk_khz);
+
+void dccg31_set_hdmistreamclk(
+		struct dccg *dccg,
+		enum hdmistreamclk_source src);
+
+#endif //__DCN31_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
new file mode 100644
index 000000000000..90127c1f9e35
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+
+#include "core_types.h"
+#include "link_encoder.h"
+#include "dcn31_dio_link_encoder.h"
+#include "stream_encoder.h"
+#include "i2caux_interface.h"
+#include "dc_bios_types.h"
+
+#include "gpio_service_interface.h"
+
+#include "link_enc_cfg.h"
+#include "dc_dmub_srv.h"
+
+#define CTX \
+	enc10->base.ctx
+#define DC_LOGGER \
+	enc10->base.ctx->logger
+
+#define REG(reg)\
+	(enc10->link_regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+	enc10->link_shift->field_name, enc10->link_mask->field_name
+
+#define IND_REG(index) \
+	(enc10->link_regs->index)
+
+#define AUX_REG(reg)\
+	(enc10->aux_regs->reg)
+
+#define AUX_REG_READ(reg_name) \
+		dm_read_reg(CTX, AUX_REG(reg_name))
+
+#define AUX_REG_WRITE(reg_name, val) \
+			dm_write_reg(CTX, AUX_REG(reg_name), val)
+
+void dcn31_link_encoder_set_dio_phy_mux(
+	struct link_encoder *enc,
+	enum encoder_type_select sel,
+	uint32_t hpo_inst)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+	switch (enc->transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKA_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKA_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKA_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_B:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKB_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKB_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKB_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_C:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKC_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKC_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKC_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_D:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKD_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKD_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKD_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_E:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKE_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKE_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKE_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	case TRANSMITTER_UNIPHY_F:
+		if (sel == ENCODER_TYPE_HDMI_FRL)
+			REG_UPDATE(DIO_LINKF_CNTL,
+					HPO_HDMI_ENC_SEL, hpo_inst);
+		else if (sel == ENCODER_TYPE_DP_128B132B)
+			REG_UPDATE(DIO_LINKF_CNTL,
+					HPO_DP_ENC_SEL, hpo_inst);
+		REG_UPDATE(DIO_LINKF_CNTL,
+				ENC_TYPE_SEL, sel);
+		break;
+	default:
+		/* Do nothing */
+		break;
+	}
+}
+
+void enc31_hw_init(struct link_encoder *enc)
+{
+	struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+/*
+	00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
+	01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
+	02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
+	03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
+	04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
+	05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
+	06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
+	07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
+*/
+
+/*
+	AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
+	AUX_RX_START_WINDOW = 1 [6:4]
+	AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
+	AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
+	AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
+	AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
+	AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
+	AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
+	AUX_RX_DETECTION_THRESHOLD [30:28] = 1
+*/
+	AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
+
+	AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
+
+	//AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
+	// Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
+	// 27MHz -> 0xd
+	// 100MHz -> 0x32
+	// 48MHz -> 0x18
+
+#ifdef CLEANUP_FIXME
+	/*from display_init*/
+	REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
+#endif
+
+	// Set TMDS_CTL0 to 1.  This is a legacy setting.
+	REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
+
+	/*HW default is 5*/
+	REG_UPDATE(RDPCSTX_CNTL,
+			RDPCS_TX_FIFO_RD_START_DELAY, 4);
+
+	dcn10_aux_initialize(enc10);
+}
+
+static const struct link_encoder_funcs dcn31_link_enc_funcs = {
+	.read_state = link_enc2_read_state,
+	.validate_output_with_stream =
+			dcn30_link_encoder_validate_output_with_stream,
+	.hw_init = enc31_hw_init,
+	.setup = dcn10_link_encoder_setup,
+	.enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
+	.enable_dp_output = dcn31_link_encoder_enable_dp_output,
+	.enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
+	.disable_output = dcn31_link_encoder_disable_output,
+	.dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
+	.dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
+	.update_mst_stream_allocation_table =
+		dcn10_link_encoder_update_mst_stream_allocation_table,
+	.psr_program_dp_dphy_fast_training =
+			dcn10_psr_program_dp_dphy_fast_training,
+	.psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
+	.connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
+	.enable_hpd = dcn10_link_encoder_enable_hpd,
+	.disable_hpd = dcn10_link_encoder_disable_hpd,
+	.is_dig_enabled = dcn10_is_dig_enabled,
+	.destroy = dcn10_link_encoder_destroy,
+	.fec_set_enable = enc2_fec_set_enable,
+	.fec_set_ready = enc2_fec_set_ready,
+	.fec_is_active = enc2_fec_is_active,
+	.get_dig_frontend = dcn10_get_dig_frontend,
+	.get_dig_mode = dcn10_get_dig_mode,
+	.is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode,
+	.get_max_link_cap = dcn20_link_encoder_get_max_link_cap,
+	.set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
+};
+
+void dcn31_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask)
+{
+	struct bp_encoder_cap_info bp_cap_info = {0};
+	const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
+	enum bp_result result = BP_RESULT_OK;
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn31_link_enc_funcs;
+	enc10->base.ctx = init_data->ctx;
+	enc10->base.id = init_data->encoder;
+
+	enc10->base.hpd_source = init_data->hpd_source;
+	enc10->base.connector = init_data->connector;
+
+	enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+
+	enc10->base.features = *enc_features;
+
+	enc10->base.transmitter = init_data->transmitter;
+
+	/* set the flag to indicate whether driver poll the I2C data pin
+	 * while doing the DP sink detect
+	 */
+
+/*	if (dal_adapter_service_is_feature_supported(as,
+		FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
+		enc10->base.features.flags.bits.
+			DP_SINK_DETECT_POLL_DATA_PIN = true;*/
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DVI_SINGLE_LINK |
+		SIGNAL_TYPE_DVI_DUAL_LINK |
+		SIGNAL_TYPE_LVDS |
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP |
+		SIGNAL_TYPE_HDMI_TYPE_A;
+
+	/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
+	 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
+	 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
+	 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
+	 * Prefer DIG assignment is decided by board design.
+	 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
+	 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
+	 * By this, adding DIGG should not hurt DCE 8.0.
+	 * This will let DCE 8.1 share DCE 8.0 as much as possible
+	 */
+
+	enc10->link_regs = link_regs;
+	enc10->aux_regs = aux_regs;
+	enc10->hpd_regs = hpd_regs;
+	enc10->link_shift = link_shift;
+	enc10->link_mask = link_mask;
+
+	switch (enc10->base.transmitter) {
+	case TRANSMITTER_UNIPHY_A:
+		enc10->base.preferred_engine = ENGINE_ID_DIGA;
+	break;
+	case TRANSMITTER_UNIPHY_B:
+		enc10->base.preferred_engine = ENGINE_ID_DIGB;
+	break;
+	case TRANSMITTER_UNIPHY_C:
+		enc10->base.preferred_engine = ENGINE_ID_DIGC;
+	break;
+	case TRANSMITTER_UNIPHY_D:
+		enc10->base.preferred_engine = ENGINE_ID_DIGD;
+	break;
+	case TRANSMITTER_UNIPHY_E:
+		enc10->base.preferred_engine = ENGINE_ID_DIGE;
+	break;
+	case TRANSMITTER_UNIPHY_F:
+		enc10->base.preferred_engine = ENGINE_ID_DIGF;
+	break;
+	default:
+		ASSERT_CRITICAL(false);
+		enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
+	}
+
+	/* default to one to mirror Windows behavior */
+	enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
+
+	result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
+						enc10->base.id, &bp_cap_info);
+
+	/* Override features with DCE-specific values */
+	if (result == BP_RESULT_OK) {
+		enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
+				bp_cap_info.DP_HBR2_EN;
+		enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
+				bp_cap_info.DP_HBR3_EN;
+		enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
+		enc10->base.features.flags.bits.DP_IS_USB_C =
+				bp_cap_info.DP_IS_USB_C;
+	} else {
+		DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
+				__func__,
+				result);
+	}
+	if (enc10->base.ctx->dc->debug.hdmi20_disable) {
+		enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
+	}
+}
+
+void dcn31_link_encoder_construct_minimal(
+	struct dcn20_link_encoder *enc20,
+	struct dc_context *ctx,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	enum engine_id eng_id)
+{
+	struct dcn10_link_encoder *enc10 = &enc20->enc10;
+
+	enc10->base.funcs = &dcn31_link_enc_funcs;
+	enc10->base.ctx = ctx;
+	enc10->base.id.type = OBJECT_TYPE_ENCODER;
+	enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
+	enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
+	enc10->base.preferred_engine = eng_id;
+	enc10->base.features = *enc_features;
+	enc10->base.transmitter = TRANSMITTER_UNKNOWN;
+	enc10->link_regs = link_regs;
+
+	enc10->base.output_signals =
+		SIGNAL_TYPE_DISPLAY_PORT |
+		SIGNAL_TYPE_DISPLAY_PORT_MST |
+		SIGNAL_TYPE_EDP;
+}
+
+void dcn31_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source)
+{
+	/* Enable transmitter and encoder. */
+	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
+
+		dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
+
+	} else {
+
+		/** @todo Handle transmitter with programmable mapping to link encoder. */
+	}
+}
+
+void dcn31_link_encoder_enable_dp_mst_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source)
+{
+	/* Enable transmitter and encoder. */
+	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
+
+		dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
+
+	} else {
+
+		/** @todo Handle transmitter with programmable mapping to link encoder. */
+	}
+}
+
+void dcn31_link_encoder_disable_output(
+	struct link_encoder *enc,
+	enum signal_type signal)
+{
+	/* Disable transmitter and encoder. */
+	if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
+
+		dcn10_link_encoder_disable_output(enc, signal);
+
+	} else {
+
+		/** @todo Handle transmitter with programmable mapping to link encoder. */
+	}
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
new file mode 100644
index 000000000000..32d146312838
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_LINK_ENCODER__DCN31_H__
+#define __DC_LINK_ENCODER__DCN31_H__
+
+#include "dcn30/dcn30_dio_link_encoder.h"
+
+
+#define LE_DCN31_REG_LIST(id)\
+	LE_DCN3_REG_LIST(id),\
+	SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
+	SR(DIO_LINKA_CNTL), \
+	SR(DIO_LINKB_CNTL), \
+	SR(DIO_LINKC_CNTL), \
+	SR(DIO_LINKD_CNTL), \
+	SR(DIO_LINKE_CNTL), \
+	SR(DIO_LINKF_CNTL)
+
+#define LINK_ENCODER_MASK_SH_LIST_DCN31(mask_sh) \
+	LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh),\
+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\
+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\
+	LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\
+	LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \
+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\
+	LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\
+	LE_SF(DIO_LINKA_CNTL, ENC_TYPE_SEL, mask_sh),\
+	LE_SF(DIO_LINKA_CNTL, HPO_DP_ENC_SEL, mask_sh),\
+	LE_SF(DIO_LINKA_CNTL, HPO_HDMI_ENC_SEL, mask_sh)
+
+#define DPCS_DCN31_REG_LIST(id) \
+	SRI(TMDS_CTL_BITS, DIG, id), \
+	SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL10, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL11, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL12, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL13, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL14, RDPCSTX, id), \
+	SRI(RDPCSTX_CNTL, RDPCSTX, id), \
+	SRI(RDPCSTX_CLOCK_CNTL, RDPCSTX, id), \
+	SRI(RDPCSTX_INTERRUPT_CONTROL, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL0, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_CNTL2, RDPCSTX, id), \
+	SRI(RDPCS_TX_CR_ADDR, RDPCSTX, id), \
+	SRI(RDPCS_TX_CR_DATA, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE0, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE1, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE2, RDPCSTX, id), \
+	SRI(RDPCSTX_PHY_FUSE3, RDPCSTX, id), \
+	SR(RDPCSTX0_RDPCSTX_SCRATCH), \
+	SRI(RDPCSTX_PHY_RX_LD_VAL, RDPCSTX, id),\
+	SRI(RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG, RDPCSTX, id)
+
+#define DPCS_DCN31_MASK_SH_LIST(mask_sh)\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_CLK_RDY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DATA_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX0_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX1_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX2_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL4, RDPCS_PHY_DP_TX3_TERM_CTRL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_MPLLB_MULTIPLIER, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_WIDTH, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX0_RATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_WIDTH, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL5, RDPCS_PHY_DP_TX1_RATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_PSTATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_PSTATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX2_MPLL_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_TX3_MPLL_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_QUOT, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL7, RDPCS_PHY_DP_MPLLB_FRACN_DEN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL8, RDPCS_PHY_DP_MPLLB_SSC_PEAK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL9, RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL10, RDPCS_PHY_DP_MPLLB_FRACN_REM, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_DP_REF_CLK_MPLLB_DIV, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL11, RDPCS_PHY_HDMI_MPLLB_HDMI_DIV, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_SSC_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_TX_CLK_DIV, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL12, RDPCS_PHY_DP_MPLLB_STATE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_CLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL13, RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_FRACN_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL14, RDPCS_PHY_DP_MPLLB_PMIX_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE0_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE1_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE2_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_LANE3_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CNTL, RDPCS_TX_FIFO_RD_START_DELAY, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_EXT_REFCLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_BYPASS, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SRAMCLK_CLOCK_ON, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_CLOCK_ON, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_GATE_DIS, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_SYMCLK_DIV2_EN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_DISABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_REQ, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_ACK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX0_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX1_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX2_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL3, RDPCS_PHY_DP_TX3_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_RESET, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_CR_MUX_SEL, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_REF_RANGE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_BYPASS, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_EXT_LD_DONE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_HDMIMODE_ENABLE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_SRAM_INIT_DONE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL2, RDPCS_PHY_DP4_POR, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_REG_FIFO_ERROR_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_TX_FIFO_ERROR_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_DISABLE_TOGGLE_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL, RDPCS_DPALT_4LANE_TOGGLE_MASK, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCS_TX_CR_ADDR, RDPCS_TX_CR_ADDR, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCS_TX_CR_DATA, RDPCS_TX_CR_DATA, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_V2I, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_TX0_EQ_POST, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE0, RDPCS_PHY_DP_MPLLB_FREQ_VCO, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_INT, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_MPLLB_CP_PROP, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE1, RDPCS_PHY_DP_TX1_EQ_POST, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE2, RDPCS_PHY_DP_TX2_EQ_POST, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_MAIN, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_FINETUNE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DCO_RANGE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_PRE, mask_sh),\
+	LE_SF(RDPCSTX0_RDPCSTX_PHY_FUSE3, RDPCS_PHY_DP_TX3_EQ_POST, mask_sh)
+
+void dcn31_link_encoder_construct(
+	struct dcn20_link_encoder *enc20,
+	const struct encoder_init_data *init_data,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	const struct dcn10_link_enc_aux_registers *aux_regs,
+	const struct dcn10_link_enc_hpd_registers *hpd_regs,
+	const struct dcn10_link_enc_shift *link_shift,
+	const struct dcn10_link_enc_mask *link_mask);
+
+/*
+ * Create a minimal link encoder object with no dc_link object associated with it.
+ */
+void dcn31_link_encoder_construct_minimal(
+	struct dcn20_link_encoder *enc20,
+	struct dc_context *ctx,
+	const struct encoder_feature_support *enc_features,
+	const struct dcn10_link_enc_registers *link_regs,
+	enum engine_id eng_id);
+
+void dcn31_link_encoder_set_dio_phy_mux(
+	struct link_encoder *enc,
+	enum encoder_type_select sel,
+	uint32_t hpo_inst);
+
+/*
+ * Enable DP transmitter and its encoder.
+ */
+void dcn31_link_encoder_enable_dp_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source);
+
+/*
+ * Enable DP transmitter and its encoder in MST mode.
+ */
+void dcn31_link_encoder_enable_dp_mst_output(
+	struct link_encoder *enc,
+	const struct dc_link_settings *link_settings,
+	enum clock_source_id clock_source);
+
+/*
+ * Disable transmitter and its encoder.
+ */
+void dcn31_link_encoder_disable_output(
+	struct link_encoder *enc,
+	enum signal_type signal);
+
+#endif /* __DC_LINK_ENCODER__DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
new file mode 100644
index 000000000000..bb9648488900
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.c
@@ -0,0 +1,956 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31_hubbub.h"
+#include "dm_services.h"
+#include "reg_helper.h"
+
+
+#define CTX \
+	hubbub2->base.ctx
+#define DC_LOGGER \
+	hubbub2->base.ctx->logger
+#define REG(reg)\
+	hubbub2->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubbub2->shifts->field_name, hubbub2->masks->field_name
+
+#ifdef NUM_VMID
+#undef NUM_VMID
+#endif
+#define NUM_VMID 16
+
+#define DCN31_CRB_SEGMENT_SIZE_KB 64
+
+static void dcn31_init_crb(struct hubbub *hubbub)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	REG_GET(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT,
+		&hubbub2->det0_size);
+
+	REG_GET(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT,
+		&hubbub2->det1_size);
+
+	REG_GET(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT,
+		&hubbub2->det2_size);
+
+	REG_GET(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT,
+		&hubbub2->det3_size);
+
+	REG_GET(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT,
+		&hubbub2->compbuf_size_segments);
+
+	REG_SET_2(COMPBUF_RESERVED_SPACE, 0,
+			COMPBUF_RESERVED_SPACE_64B, hubbub2->pixel_chunk_size / 32,
+			COMPBUF_RESERVED_SPACE_ZS, hubbub2->pixel_chunk_size / 128);
+	REG_UPDATE(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, 0x17F);
+}
+
+static void dcn31_program_det_size(struct hubbub *hubbub, int hubp_inst, unsigned int det_buffer_size_in_kbyte)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+
+	unsigned int det_size_segments = (det_buffer_size_in_kbyte + DCN31_CRB_SEGMENT_SIZE_KB - 1) / DCN31_CRB_SEGMENT_SIZE_KB;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_UPDATE(DCHUBBUB_DET0_CTRL,
+					DET0_SIZE, det_size_segments);
+		hubbub2->det0_size = det_size_segments;
+		break;
+	case 1:
+		REG_UPDATE(DCHUBBUB_DET1_CTRL,
+					DET1_SIZE, det_size_segments);
+		hubbub2->det1_size = det_size_segments;
+		break;
+	case 2:
+		REG_UPDATE(DCHUBBUB_DET2_CTRL,
+					DET2_SIZE, det_size_segments);
+		hubbub2->det2_size = det_size_segments;
+		break;
+	case 3:
+		REG_UPDATE(DCHUBBUB_DET3_CTRL,
+					DET3_SIZE, det_size_segments);
+		hubbub2->det3_size = det_size_segments;
+		break;
+	default:
+		break;
+	}
+	/* Should never be hit, if it is we have an erroneous hw config*/
+	ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+			+ hubbub2->det3_size + hubbub2->compbuf_size_segments <= hubbub2->crb_size_segs);
+}
+
+static void dcn31_program_compbuf_size(struct hubbub *hubbub, unsigned int compbuf_size_kb, bool safe_to_increase)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	unsigned int compbuf_size_segments = (compbuf_size_kb + DCN31_CRB_SEGMENT_SIZE_KB - 1) / DCN31_CRB_SEGMENT_SIZE_KB;
+
+	if (safe_to_increase || compbuf_size_segments <= hubbub2->compbuf_size_segments) {
+		if (compbuf_size_segments > hubbub2->compbuf_size_segments) {
+			REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, hubbub2->det1_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, hubbub2->det2_size, 1, 100);
+			REG_WAIT(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, hubbub2->det3_size, 1, 100);
+		}
+		/* Should never be hit, if it is we have an erroneous hw config*/
+		ASSERT(hubbub2->det0_size + hubbub2->det1_size + hubbub2->det2_size
+				+ hubbub2->det3_size + compbuf_size_segments <= hubbub2->crb_size_segs);
+		REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_segments);
+		REG_WAIT(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, compbuf_size_segments, 1, 100);
+		hubbub2->compbuf_size_segments = compbuf_size_segments;
+	}
+}
+
+static uint32_t convert_and_clamp(
+	uint32_t wm_ns,
+	uint32_t refclk_mhz,
+	uint32_t clamp_value)
+{
+	uint32_t ret_val = 0;
+	ret_val = wm_ns * refclk_mhz;
+	ret_val /= 1000;
+
+	if (ret_val > clamp_value)
+		ret_val = clamp_value;
+
+	return ret_val;
+}
+
+static bool hubbub31_program_urgent_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* Repeat for water mark set A, B, C and D. */
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.urgent_ns > hubbub2->watermarks.a.urgent_ns) {
+		hubbub2->watermarks.a.urgent_ns = watermarks->a.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.urgent_ns, prog_wm_value);
+	} else if (watermarks->a.urgent_ns < hubbub2->watermarks.a.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->a.frac_urg_bw_flip
+			> hubbub2->watermarks.a.frac_urg_bw_flip) {
+		hubbub2->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip);
+	} else if (watermarks->a.frac_urg_bw_flip
+			< hubbub2->watermarks.a.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.frac_urg_bw_nom
+			> hubbub2->watermarks.a.frac_urg_bw_nom) {
+		hubbub2->watermarks.a.frac_urg_bw_nom = watermarks->a.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->a.frac_urg_bw_nom);
+	} else if (watermarks->a.frac_urg_bw_nom
+			< hubbub2->watermarks.a.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.urgent_latency_ns > hubbub2->watermarks.a.urgent_latency_ns) {
+		hubbub2->watermarks.a.urgent_latency_ns = watermarks->a.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->a.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, prog_wm_value);
+	} else if (watermarks->a.urgent_latency_ns < hubbub2->watermarks.a.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.urgent_ns > hubbub2->watermarks.b.urgent_ns) {
+		hubbub2->watermarks.b.urgent_ns = watermarks->b.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.urgent_ns, prog_wm_value);
+	} else if (watermarks->b.urgent_ns < hubbub2->watermarks.b.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->b.frac_urg_bw_flip
+			> hubbub2->watermarks.b.frac_urg_bw_flip) {
+		hubbub2->watermarks.b.frac_urg_bw_flip = watermarks->b.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->b.frac_urg_bw_flip);
+	} else if (watermarks->b.frac_urg_bw_flip
+			< hubbub2->watermarks.b.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.frac_urg_bw_nom
+			> hubbub2->watermarks.b.frac_urg_bw_nom) {
+		hubbub2->watermarks.b.frac_urg_bw_nom = watermarks->b.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->b.frac_urg_bw_nom);
+	} else if (watermarks->b.frac_urg_bw_nom
+			< hubbub2->watermarks.b.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.urgent_latency_ns > hubbub2->watermarks.b.urgent_latency_ns) {
+		hubbub2->watermarks.b.urgent_latency_ns = watermarks->b.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->b.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, prog_wm_value);
+	} else if (watermarks->b.urgent_latency_ns < hubbub2->watermarks.b.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.urgent_ns > hubbub2->watermarks.c.urgent_ns) {
+		hubbub2->watermarks.c.urgent_ns = watermarks->c.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.urgent_ns, prog_wm_value);
+	} else if (watermarks->c.urgent_ns < hubbub2->watermarks.c.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->c.frac_urg_bw_flip
+			> hubbub2->watermarks.c.frac_urg_bw_flip) {
+		hubbub2->watermarks.c.frac_urg_bw_flip = watermarks->c.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->c.frac_urg_bw_flip);
+	} else if (watermarks->c.frac_urg_bw_flip
+			< hubbub2->watermarks.c.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.frac_urg_bw_nom
+			> hubbub2->watermarks.c.frac_urg_bw_nom) {
+		hubbub2->watermarks.c.frac_urg_bw_nom = watermarks->c.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->c.frac_urg_bw_nom);
+	} else if (watermarks->c.frac_urg_bw_nom
+			< hubbub2->watermarks.c.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.urgent_latency_ns > hubbub2->watermarks.c.urgent_latency_ns) {
+		hubbub2->watermarks.c.urgent_latency_ns = watermarks->c.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->c.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, prog_wm_value);
+	} else if (watermarks->c.urgent_latency_ns < hubbub2->watermarks.c.urgent_latency_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.urgent_ns > hubbub2->watermarks.d.urgent_ns) {
+		hubbub2->watermarks.d.urgent_ns = watermarks->d.urgent_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
+				DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);
+
+		DC_LOG_BANDWIDTH_CALCS("URGENCY_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.urgent_ns, prog_wm_value);
+	} else if (watermarks->d.urgent_ns < hubbub2->watermarks.d.urgent_ns)
+		wm_pending = true;
+
+	/* determine the transfer time for a quantity of data for a particular requestor.*/
+	if (safe_to_lower || watermarks->d.frac_urg_bw_flip
+			> hubbub2->watermarks.d.frac_urg_bw_flip) {
+		hubbub2->watermarks.d.frac_urg_bw_flip = watermarks->d.frac_urg_bw_flip;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->d.frac_urg_bw_flip);
+	} else if (watermarks->d.frac_urg_bw_flip
+			< hubbub2->watermarks.d.frac_urg_bw_flip)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.frac_urg_bw_nom
+			> hubbub2->watermarks.d.frac_urg_bw_nom) {
+		hubbub2->watermarks.d.frac_urg_bw_nom = watermarks->d.frac_urg_bw_nom;
+
+		REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0,
+				DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->d.frac_urg_bw_nom);
+	} else if (watermarks->d.frac_urg_bw_nom
+			< hubbub2->watermarks.d.frac_urg_bw_nom)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.urgent_latency_ns > hubbub2->watermarks.d.urgent_latency_ns) {
+		hubbub2->watermarks.d.urgent_latency_ns = watermarks->d.urgent_latency_ns;
+		prog_wm_value = convert_and_clamp(watermarks->d.urgent_latency_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0,
+				DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, prog_wm_value);
+	} else if (watermarks->d.urgent_latency_ns < hubbub2->watermarks.d.urgent_latency_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub31_program_stutter_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns =
+				watermarks->a.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->a.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->a.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_A calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->a.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.a.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns =
+				watermarks->b.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->b.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->b.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_B calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->b.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.b.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns =
+				watermarks->c.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->c.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->c.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_C calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->c.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.c.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns =
+				watermarks->d.cstate_pstate.cstate_exit_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_exit_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_exit_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_exit_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns =
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_ENTER_WATERMARK_Z8_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_enter_plus_exit_z8_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns)
+		wm_pending = true;
+
+	if (safe_to_lower || watermarks->d.cstate_pstate.cstate_exit_z8_ns
+			> hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns) {
+		hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns =
+				watermarks->d.cstate_pstate.cstate_exit_z8_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.cstate_exit_z8_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0,
+				DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("SR_EXIT_WATERMARK_Z8_D calculated =%d\n"
+			"HW register value = 0x%x\n",
+			watermarks->d.cstate_pstate.cstate_exit_z8_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.cstate_exit_z8_ns
+			< hubbub2->watermarks.d.cstate_pstate.cstate_exit_z8_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub31_program_pstate_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t prog_wm_value;
+
+	bool wm_pending = false;
+
+	/* clock state A */
+	if (safe_to_lower || watermarks->a.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.a.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.a.cstate_pstate.pstate_change_ns =
+				watermarks->a.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->a.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->a.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.a.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state B */
+	if (safe_to_lower || watermarks->b.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.b.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.b.cstate_pstate.pstate_change_ns =
+				watermarks->b.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->b.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->b.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.b.cstate_pstate.pstate_change_ns)
+		wm_pending = false;
+
+	/* clock state C */
+	if (safe_to_lower || watermarks->c.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.c.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.c.cstate_pstate.pstate_change_ns =
+				watermarks->c.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->c.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->c.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.c.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	/* clock state D */
+	if (safe_to_lower || watermarks->d.cstate_pstate.pstate_change_ns
+			> hubbub2->watermarks.d.cstate_pstate.pstate_change_ns) {
+		hubbub2->watermarks.d.cstate_pstate.pstate_change_ns =
+				watermarks->d.cstate_pstate.pstate_change_ns;
+		prog_wm_value = convert_and_clamp(
+				watermarks->d.cstate_pstate.pstate_change_ns,
+				refclk_mhz, 0x1fffff);
+		REG_SET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 0,
+				DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);
+		DC_LOG_BANDWIDTH_CALCS("DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"
+			"HW register value = 0x%x\n\n",
+			watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
+	} else if (watermarks->d.cstate_pstate.pstate_change_ns
+			< hubbub2->watermarks.d.cstate_pstate.pstate_change_ns)
+		wm_pending = true;
+
+	return wm_pending;
+}
+
+static bool hubbub31_program_watermarks(
+		struct hubbub *hubbub,
+		struct dcn_watermark_set *watermarks,
+		unsigned int refclk_mhz,
+		bool safe_to_lower)
+{
+	bool wm_pending = false;
+
+	if (hubbub31_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub31_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	if (hubbub31_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower))
+		wm_pending = true;
+
+	/*
+	 * The DCHub arbiter has a mechanism to dynamically rate limit the DCHub request stream to the fabric.
+	 * If the memory controller is fully utilized and the DCHub requestors are
+	 * well ahead of their amortized schedule, then it is safe to prevent the next winner
+	 * from being committed and sent to the fabric.
+	 * The utilization of the memory controller is approximated by ensuring that
+	 * the number of outstanding requests is greater than a threshold specified
+	 * by the ARB_MIN_REQ_OUTSTANDING. To determine that the DCHub requestors are well ahead of the amortized schedule,
+	 * the slack of the next winner is compared with the ARB_SAT_LEVEL in DLG RefClk cycles.
+	 *
+	 * TODO: Revisit request limit after figure out right number. request limit for RM isn't decided yet, set maximum value (0x1FF)
+	 * to turn off it for now.
+	 */
+	/*REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
+			DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
+	REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
+			DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0x1FF);*/
+
+	hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
+	return wm_pending;
+}
+
+static void hubbub3_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
+		unsigned int bytes_per_element)
+{
+	/* copied from DML.  might want to refactor DML to leverage from DML */
+	/* DML : get_blk256_size */
+	if (bytes_per_element == 1) {
+		*blk256_width = 16;
+		*blk256_height = 16;
+	} else if (bytes_per_element == 2) {
+		*blk256_width = 16;
+		*blk256_height = 8;
+	} else if (bytes_per_element == 4) {
+		*blk256_width = 8;
+		*blk256_height = 8;
+	} else if (bytes_per_element == 8) {
+		*blk256_width = 8;
+		*blk256_height = 4;
+	}
+}
+
+static void hubbub31_det_request_size(
+		unsigned int detile_buf_size,
+		unsigned int height,
+		unsigned int width,
+		unsigned int bpe,
+		bool *req128_horz_wc,
+		bool *req128_vert_wc)
+{
+	unsigned int blk256_height = 0;
+	unsigned int blk256_width = 0;
+	unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
+
+	hubbub3_get_blk256_size(&blk256_width, &blk256_height, bpe);
+
+	swath_bytes_horz_wc = width * blk256_height * bpe;
+	swath_bytes_vert_wc = height * blk256_width * bpe;
+
+	*req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
+			false : /* full 256B request */
+			true; /* half 128b request */
+
+	*req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
+			false : /* full 256B request */
+			true; /* half 128b request */
+}
+
+static bool hubbub31_get_dcc_compression_cap(struct hubbub *hubbub,
+		const struct dc_dcc_surface_param *input,
+		struct dc_surface_dcc_cap *output)
+{
+	struct dc *dc = hubbub->ctx->dc;
+	enum dcc_control dcc_control;
+	unsigned int bpe;
+	enum segment_order segment_order_horz, segment_order_vert;
+	bool req128_horz_wc, req128_vert_wc;
+
+	memset(output, 0, sizeof(*output));
+
+	if (dc->debug.disable_dcc == DCC_DISABLE)
+		return false;
+
+	if (!hubbub->funcs->dcc_support_pixel_format(input->format,
+			&bpe))
+		return false;
+
+	if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
+			&segment_order_horz, &segment_order_vert))
+		return false;
+
+	hubbub31_det_request_size(TO_DCN20_HUBBUB(hubbub)->detile_buf_size,
+			input->surface_size.height,  input->surface_size.width,
+			bpe, &req128_horz_wc, &req128_vert_wc);
+
+	if (!req128_horz_wc && !req128_vert_wc) {
+		dcc_control = dcc_control__256_256_xxx;
+	} else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
+		if (!req128_horz_wc)
+			dcc_control = dcc_control__256_256_xxx;
+		else if (segment_order_horz == segment_order__contiguous)
+			dcc_control = dcc_control__128_128_xxx;
+		else
+			dcc_control = dcc_control__256_64_64;
+	} else if (input->scan == SCAN_DIRECTION_VERTICAL) {
+		if (!req128_vert_wc)
+			dcc_control = dcc_control__256_256_xxx;
+		else if (segment_order_vert == segment_order__contiguous)
+			dcc_control = dcc_control__128_128_xxx;
+		else
+			dcc_control = dcc_control__256_64_64;
+	} else {
+		if ((req128_horz_wc &&
+			segment_order_horz == segment_order__non_contiguous) ||
+			(req128_vert_wc &&
+			segment_order_vert == segment_order__non_contiguous))
+			/* access_dir not known, must use most constraining */
+			dcc_control = dcc_control__256_64_64;
+		else
+			/* reg128 is true for either horz and vert
+			 * but segment_order is contiguous
+			 */
+			dcc_control = dcc_control__128_128_xxx;
+	}
+
+	/* Exception for 64KB_R_X */
+	if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
+		dcc_control = dcc_control__128_128_xxx;
+
+	if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
+		dcc_control != dcc_control__256_256_xxx)
+		return false;
+
+	switch (dcc_control) {
+	case dcc_control__256_256_xxx:
+		output->grph.rgb.max_uncompressed_blk_size = 256;
+		output->grph.rgb.max_compressed_blk_size = 256;
+		output->grph.rgb.independent_64b_blks = false;
+		output->grph.rgb.dcc_controls.dcc_256_256_unconstrained = 1;
+		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
+		break;
+	case dcc_control__128_128_xxx:
+		output->grph.rgb.max_uncompressed_blk_size = 128;
+		output->grph.rgb.max_compressed_blk_size = 128;
+		output->grph.rgb.independent_64b_blks = false;
+		output->grph.rgb.dcc_controls.dcc_128_128_uncontrained = 1;
+		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
+		break;
+	case dcc_control__256_64_64:
+		output->grph.rgb.max_uncompressed_blk_size = 256;
+		output->grph.rgb.max_compressed_blk_size = 64;
+		output->grph.rgb.independent_64b_blks = true;
+		output->grph.rgb.dcc_controls.dcc_256_64_64 = 1;
+		break;
+	case dcc_control__256_128_128:
+		output->grph.rgb.max_uncompressed_blk_size = 256;
+		output->grph.rgb.max_compressed_blk_size = 128;
+		output->grph.rgb.independent_64b_blks = false;
+		output->grph.rgb.dcc_controls.dcc_256_128_128 = 1;
+		break;
+	}
+	output->capable = true;
+	output->const_color_support = true;
+
+	return true;
+}
+
+static int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,
+		struct dcn_hubbub_phys_addr_config *pa_config)
+{
+	hubbub3_init_dchub_sys_ctx(hubbub, pa_config);
+
+	dcn21_dchvm_init(hubbub);
+
+	return NUM_VMID;
+}
+
+static void hubbub31_get_dchub_ref_freq(struct hubbub *hubbub,
+		unsigned int dccg_ref_freq_inKhz,
+		unsigned int *dchub_ref_freq_inKhz)
+{
+	struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+	uint32_t ref_div = 0;
+	uint32_t ref_en = 0;
+	unsigned int dc_refclk_khz = 24000;
+
+	REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
+			DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
+
+	if (ref_en) {
+		if (ref_div == 2)
+			*dchub_ref_freq_inKhz = dc_refclk_khz / 2;
+		else
+			*dchub_ref_freq_inKhz = dc_refclk_khz;
+
+		/*
+		 * The external Reference Clock may change based on the board or
+		 * platform requirements and the programmable integer divide must
+		 * be programmed to provide a suitable DLG RefClk frequency between
+		 * a minimum of 20MHz and maximum of 50MHz
+		 */
+		if (*dchub_ref_freq_inKhz < 20000 || *dchub_ref_freq_inKhz > 50000)
+			ASSERT_CRITICAL(false);
+
+		return;
+	} else {
+		*dchub_ref_freq_inKhz = dc_refclk_khz;
+
+		// HUBBUB global timer must be enabled.
+		ASSERT_CRITICAL(false);
+		return;
+	}
+}
+
+static const struct hubbub_funcs hubbub31_funcs = {
+	.update_dchub = hubbub2_update_dchub,
+	.init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx,
+	.init_vm_ctx = hubbub2_init_vm_ctx,
+	.dcc_support_swizzle = hubbub3_dcc_support_swizzle,
+	.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
+	.get_dcc_compression_cap = hubbub31_get_dcc_compression_cap,
+	.wm_read_state = hubbub21_wm_read_state,
+	.get_dchub_ref_freq = hubbub31_get_dchub_ref_freq,
+	.program_watermarks = hubbub31_program_watermarks,
+	.allow_self_refresh_control = hubbub1_allow_self_refresh_control,
+	.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
+	.program_det_size = dcn31_program_det_size,
+	.program_compbuf_size = dcn31_program_compbuf_size,
+	.init_crb = dcn31_init_crb
+};
+
+void hubbub31_construct(struct dcn20_hubbub *hubbub31,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb)
+{
+
+	hubbub3_construct(hubbub31, ctx, hubbub_regs, hubbub_shift, hubbub_mask);
+	hubbub31->base.funcs = &hubbub31_funcs;
+	hubbub31->detile_buf_size = det_size_kb * 1024;
+	hubbub31->pixel_chunk_size = pixel_chunk_size_kb * 1024;
+	hubbub31->crb_size_segs = config_return_buffer_size_kb / DCN31_CRB_SEGMENT_SIZE_KB;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
new file mode 100644
index 000000000000..8ec98cbcbd47
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubbub.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBBUB_DCN31_H__
+#define __DC_HUBBUB_DCN31_H__
+
+#include "dcn21/dcn21_hubbub.h"
+
+#define HUBBUB_REG_LIST_DCN31(id)\
+	HUBBUB_REG_LIST_DCN30(id),\
+	SR(DCHVM_CTRL0),\
+	SR(DCHVM_MEM_CTRL),\
+	SR(DCHVM_CLK_CTRL),\
+	SR(DCHVM_RIOMMU_CTRL0),\
+	SR(DCHVM_RIOMMU_STAT0),\
+	SR(DCHUBBUB_DET0_CTRL),\
+	SR(DCHUBBUB_DET1_CTRL),\
+	SR(DCHUBBUB_DET2_CTRL),\
+	SR(DCHUBBUB_DET3_CTRL),\
+	SR(DCHUBBUB_COMPBUF_CTRL),\
+	SR(COMPBUF_RESERVED_SPACE),\
+	SR(DCHUBBUB_DEBUG_CTRL_0),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\
+	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D)
+
+#define HUBBUB_MASK_SH_LIST_DCN31(mask_sh)\
+	HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
+	HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
+	HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \
+	HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \
+	HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\
+	HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\
+	HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\
+	HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\
+	HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \
+	HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh)
+
+
+void hubbub31_construct(struct dcn20_hubbub *hubbub3,
+	struct dc_context *ctx,
+	const struct dcn_hubbub_registers *hubbub_regs,
+	const struct dcn_hubbub_shift *hubbub_shift,
+	const struct dcn_hubbub_mask *hubbub_mask,
+	int det_size_kb,
+	int pixel_chunk_size_kb,
+	int config_return_buffer_size_kb);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
new file mode 100644
index 000000000000..53b792b997b7
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dce_calcs.h"
+#include "reg_helper.h"
+#include "basics/conversion.h"
+#include "dcn31_hubp.h"
+
+#define REG(reg)\
+	hubp2->hubp_regs->reg
+
+#define CTX \
+	hubp2->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
+
+void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	REG_UPDATE(DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, enable);
+	REG_UPDATE(CURSOR_CONTROL, CURSOR_REQ_MODE, enable);
+}
+
+void hubp31_soft_reset(struct hubp *hubp, bool reset)
+{
+	struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+	REG_UPDATE(DCHUBP_CNTL, HUBP_SOFT_RESET, reset);
+}
+
+static struct hubp_funcs dcn31_hubp_funcs = {
+	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
+	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
+	.hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr,
+	.hubp_program_surface_config = hubp3_program_surface_config,
+	.hubp_is_flip_pending = hubp2_is_flip_pending,
+	.hubp_setup = hubp3_setup,
+	.hubp_setup_interdependent = hubp2_setup_interdependent,
+	.hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
+	.set_blank = hubp2_set_blank,
+	.dcc_control = hubp3_dcc_control,
+	.mem_program_viewport = min_set_viewport,
+	.set_cursor_attributes	= hubp2_cursor_set_attributes,
+	.set_cursor_position	= hubp2_cursor_set_position,
+	.hubp_clk_cntl = hubp2_clk_cntl,
+	.hubp_vtg_sel = hubp2_vtg_sel,
+	.dmdata_set_attributes = hubp3_dmdata_set_attributes,
+	.dmdata_load = hubp2_dmdata_load,
+	.dmdata_status_done = hubp2_dmdata_status_done,
+	.hubp_read_state = hubp3_read_state,
+	.hubp_clear_underflow = hubp2_clear_underflow,
+	.hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
+	.hubp_init = hubp3_init,
+	.set_unbounded_requesting = hubp31_set_unbounded_requesting,
+	.hubp_soft_reset = hubp31_soft_reset,
+	.hubp_in_blank = hubp1_in_blank,
+};
+
+bool hubp31_construct(
+	struct dcn20_hubp *hubp2,
+	struct dc_context *ctx,
+	uint32_t inst,
+	const struct dcn_hubp2_registers *hubp_regs,
+	const struct dcn_hubp2_shift *hubp_shift,
+	const struct dcn_hubp2_mask *hubp_mask)
+{
+	hubp2->base.funcs = &dcn31_hubp_funcs;
+	hubp2->base.ctx = ctx;
+	hubp2->hubp_regs = hubp_regs;
+	hubp2->hubp_shift = hubp_shift;
+	hubp2->hubp_mask = hubp_mask;
+	hubp2->base.inst = inst;
+	hubp2->base.opp_id = OPP_ID_INVALID;
+	hubp2->base.mpcc_id = 0xf;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
new file mode 100644
index 000000000000..c31a7b8f81ee
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hubp.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright 2012-20 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HUBP_DCN31_H__
+#define __DC_HUBP_DCN31_H__
+
+#include "dcn20/dcn20_hubp.h"
+#include "dcn21/dcn21_hubp.h"
+#include "dcn30/dcn30_hubp.h"
+
+#define HUBP_MASK_SH_LIST_DCN31(mask_sh)\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, REFCYC_PER_VM_DMDATA, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_FAULT_STATUS_CLEAR, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_LATE_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_UNDERFLOW_STATUS_CLEAR, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_DMDATA_VM_CNTL, DMDATA_VM_DONE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNBOUNDED_REQ_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_IN_BLANK, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_SOFT_RESET, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, MAX_COMPRESSED_FRAGS, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PKRS, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, SW_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, META_LINEAR, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, PIPE_ALIGNED, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH, META_PITCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, PITCH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_PITCH_C, META_PITCH_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_TYPE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_FLIP_PENDING, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_X_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START, PRI_VIEWPORT_Y_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_WIDTH, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION, SEC_VIEWPORT_HEIGHT, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_X_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START, SEC_VIEWPORT_Y_START, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_WIDTH_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C, PRI_VIEWPORT_HEIGHT_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_X_START_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_PRI_VIEWPORT_START_C, PRI_VIEWPORT_Y_START_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_WIDTH_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C, SEC_VIEWPORT_HEIGHT_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_X_START_C, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SEC_VIEWPORT_START_C, SEC_VIEWPORT_Y_START_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS, PRIMARY_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS, SECONDARY_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, PRIMARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS, PRIMARY_META_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, SECONDARY_META_SURFACE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS, SECONDARY_META_SURFACE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, PRIMARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, SECONDARY_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C, SECONDARY_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, SECONDARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, SECONDARY_META_SURFACE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_META_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_META_SURFACE_TMZ_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, SECONDARY_SURFACE_DCC_IND_BLK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CB_B, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_CR_R, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_Y_G, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, CROSSBAR_SRC_ALPHA, mask_sh),\
+	HUBP_SF(HUBPRET0_HUBPRET_CONTROL, PACK_3TO2_ELEMENT_DISABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, DRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, PRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, MRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_EXPANSION_MODE, CRQ_EXPANSION_MODE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, META_CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MIN_META_CHUNK_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, DPTE_GROUP_SIZE, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, SWATH_HEIGHT, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, PTE_ROW_HEIGHT_LINEAR, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, META_CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MIN_META_CHUNK_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, DPTE_GROUP_SIZE_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, SWATH_HEIGHT_C, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, PTE_ROW_HEIGHT_LINEAR_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, REFCYC_H_BLANK_END, mask_sh),\
+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_0, DLG_V_BLANK_END, mask_sh),\
+	HUBP_SF(HUBPREQ0_BLANK_OFFSET_1, MIN_DST_Y_NEXT_START, mask_sh),\
+	HUBP_SF(HUBPREQ0_DST_DIMENSIONS, REFCYC_PER_HTOTAL, mask_sh),\
+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, REFCYC_X_AFTER_SCALER, mask_sh),\
+	HUBP_SF(HUBPREQ0_DST_AFTER_SCALER, DST_Y_AFTER_SCALER, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_VM_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_0, DST_Y_PER_ROW_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_REF_FREQ_TO_PIX_FREQ, REF_FREQ_TO_PIX_FREQ, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_1, REFCYC_PER_PTE_GROUP_VBLANK_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_3, REFCYC_PER_META_CHUNK_VBLANK_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_4, DST_Y_PER_META_ROW_NOM_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_5, REFCYC_PER_META_CHUNK_NOM_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY_PRE, REFCYC_PER_LINE_DELIVERY_PRE_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_PER_LINE_DELIVERY, REFCYC_PER_LINE_DELIVERY_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_2, REFCYC_PER_PTE_GROUP_VBLANK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_4, REFCYC_PER_META_CHUNK_VBLANK_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_6, DST_Y_PER_META_ROW_NOM_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_NOM_PARAMETERS_7, REFCYC_PER_META_CHUNK_NOM_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_LOW_WM, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_TTU_QOS_WM, QoS_LEVEL_HIGH_WM, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, MIN_TTU_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, QoS_LEVEL_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_GLOBAL_TTU_CNTL, ROW_TTU_MODE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, REFCYC_PER_REQ_DELIVERY, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_LEVEL_FIXED, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\
+	HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh),\
+	HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\
+	HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ALPHA_PLANE_EN, mask_sh),\
+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\
+	HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\
+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+	HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_REQ_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+	HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \
+	HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\
+	HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_5, REFCYC_PER_PTE_GROUP_FLIP_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_6, REFCYC_PER_META_CHUNK_FLIP_C, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, mask_sh),\
+	HUBP_SF(HUBPREQ0_VBLANK_PARAMETERS_6, REFCYC_PER_VM_REQ_VBLANK, mask_sh),\
+	HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, VM_GROUP_SIZE, mask_sh)
+
+
+bool hubp31_construct(
+		struct dcn20_hubp *hubp2,
+		struct dc_context *ctx,
+		uint32_t inst,
+		const struct dcn_hubp2_registers *hubp_regs,
+		const struct dcn_hubp2_shift *hubp_shift,
+		const struct dcn_hubp2_mask *hubp_mask);
+
+void hubp31_soft_reset(struct hubp *hubp, bool reset);
+
+void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
+
+#endif /* __DC_HUBP_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
new file mode 100644
index 000000000000..c0e544d7556f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dm_helpers.h"
+#include "core_types.h"
+#include "resource.h"
+#include "dccg.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "reg_helper.h"
+#include "abm.h"
+#include "clk_mgr.h"
+#include "hubp.h"
+#include "dchubbub.h"
+#include "timing_generator.h"
+#include "opp.h"
+#include "ipp.h"
+#include "mpc.h"
+#include "mcif_wb.h"
+#include "dc_dmub_srv.h"
+#include "dcn31_hwseq.h"
+#include "link_hwss.h"
+#include "dpcd_defs.h"
+#include "dce/dmub_outbox.h"
+#include "dc_link_dp.h"
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+	hws->ctx
+#define REG(reg)\
+	hws->regs->reg
+#define DC_LOGGER \
+		dc->ctx->logger
+
+
+#undef FN
+#define FN(reg_name, field_name) \
+	hws->shifts->field_name, hws->masks->field_name
+
+void dcn31_init_hw(struct dc *dc)
+{
+	struct abm **abms = dc->res_pool->multiple_abms;
+	struct dce_hwseq *hws = dc->hwseq;
+	struct dc_bios *dcb = dc->ctx->dc_bios;
+	struct resource_pool *res_pool = dc->res_pool;
+	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
+	int i, j;
+	int edp_num;
+
+	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
+		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
+
+	// Initialize the dccg
+	if (res_pool->dccg->funcs->dccg_init)
+		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
+
+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+
+		REG_WRITE(REFCLK_CNTL, 0);
+		REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
+		REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+		if (!dc->debug.disable_clock_gate) {
+			/* enable all DCN clock gating */
+			REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+			REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+			REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+		}
+
+		//Enable ability to power gate / don't force power on permanently
+		if (hws->funcs.enable_power_gating_plane)
+			hws->funcs.enable_power_gating_plane(hws, true);
+
+		return;
+	}
+
+	if (!dcb->funcs->is_accelerated_mode(dcb)) {
+		hws->funcs.bios_golden_init(dc);
+		hws->funcs.disable_vga(dc->hwseq);
+	}
+
+	if (dc->debug.enable_mem_low_power.bits.dmcu) {
+		// Force ERAM to shutdown if DMCU is not enabled
+		if (dc->debug.disable_dmcu || dc->config.disable_dmcu) {
+			REG_UPDATE(DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, 3);
+		}
+	}
+
+	// Set default OPTC memory power states
+	if (dc->debug.enable_mem_low_power.bits.optc) {
+		// Shutdown when unassigned and light sleep in VBLANK
+		REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1);
+	}
+
+	if (dc->debug.enable_mem_low_power.bits.vga) {
+		// Power down VGA memory
+		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
+	}
+
+	if (dc->ctx->dc_bios->fw_info_valid) {
+		res_pool->ref_clocks.xtalin_clock_inKhz =
+				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
+
+		if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+			if (res_pool->dccg && res_pool->hubbub) {
+
+				(res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg,
+						dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency,
+						&res_pool->ref_clocks.dccg_ref_clock_inKhz);
+
+				(res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub,
+						res_pool->ref_clocks.dccg_ref_clock_inKhz,
+						&res_pool->ref_clocks.dchub_ref_clock_inKhz);
+			} else {
+				// Not all ASICs have DCCG sw component
+				res_pool->ref_clocks.dccg_ref_clock_inKhz =
+						res_pool->ref_clocks.xtalin_clock_inKhz;
+				res_pool->ref_clocks.dchub_ref_clock_inKhz =
+						res_pool->ref_clocks.xtalin_clock_inKhz;
+			}
+		}
+	} else
+		ASSERT_CRITICAL(false);
+
+	for (i = 0; i < dc->link_count; i++) {
+		/* Power up AND update implementation according to the
+		 * required signal (which may be different from the
+		 * default signal on connector).
+		 */
+		struct dc_link *link = dc->links[i];
+
+		link->link_enc->funcs->hw_init(link->link_enc);
+
+		/* Check for enabled DIG to identify enabled display */
+		if (link->link_enc->funcs->is_dig_enabled &&
+			link->link_enc->funcs->is_dig_enabled(link->link_enc))
+			link->link_status.link_active = true;
+	}
+
+	/* Power gate DSCs */
+	for (i = 0; i < res_pool->res_cap->num_dsc; i++)
+		if (hws->funcs.dsc_pg_control != NULL)
+			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
+
+	/* we want to turn off all dp displays before doing detection */
+	if (dc->config.power_down_display_on_boot) {
+		uint8_t dpcd_power_state = '\0';
+		enum dc_status status = DC_ERROR_UNEXPECTED;
+
+		for (i = 0; i < dc->link_count; i++) {
+			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
+				continue;
+
+			/* if any of the displays are lit up turn them off */
+			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+						     &dpcd_power_state, sizeof(dpcd_power_state));
+			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
+				/* blank dp stream before power off receiver*/
+				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
+					unsigned int fe;
+
+					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
+										dc->links[i]->link_enc);
+					if (fe == ENGINE_ID_UNKNOWN)
+						continue;
+
+					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+						if (fe == dc->res_pool->stream_enc[j]->id) {
+							dc->res_pool->stream_enc[j]->funcs->dp_blank(
+										dc->res_pool->stream_enc[j]);
+							break;
+						}
+					}
+				}
+				dp_receiver_power_ctrl(dc->links[i], false);
+			}
+		}
+	}
+
+	/* If taking control over from VBIOS, we may want to optimize our first
+	 * mode set, so we need to skip powering down pipes until we know which
+	 * pipes we want to use.
+	 * Otherwise, if taking control is not possible, we need to power
+	 * everything down.
+	 */
+	if (dcb->funcs->is_accelerated_mode(dcb) || dc->config.power_down_display_on_boot) {
+		hws->funcs.init_pipes(dc, dc->current_state);
+		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
+			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
+					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
+	}
+
+	/* In headless boot cases, DIG may be turned
+	 * on which causes HW/SW discrepancies.
+	 * To avoid this, power down hardware on boot
+	 * if DIG is turned on and seamless boot not enabled
+	 */
+	if (dc->config.power_down_display_on_boot) {
+		struct dc_link *edp_links[MAX_NUM_EDP];
+		struct dc_link *edp_link;
+
+		get_edp_links(dc, edp_links, &edp_num);
+		if (edp_num) {
+			for (i = 0; i < edp_num; i++) {
+				edp_link = edp_links[i];
+				if (edp_link->link_enc->funcs->is_dig_enabled &&
+						edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
+						dc->hwss.edp_backlight_control &&
+						dc->hwss.power_down &&
+						dc->hwss.edp_power_control) {
+					dc->hwss.edp_backlight_control(edp_link, false);
+					dc->hwss.power_down(dc);
+					dc->hwss.edp_power_control(edp_link, false);
+				}
+			}
+		} else {
+			for (i = 0; i < dc->link_count; i++) {
+				struct dc_link *link = dc->links[i];
+
+				if (link->link_enc->funcs->is_dig_enabled &&
+						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
+						dc->hwss.power_down) {
+					dc->hwss.power_down(dc);
+					break;
+				}
+
+			}
+		}
+	}
+
+	for (i = 0; i < res_pool->audio_count; i++) {
+		struct audio *audio = res_pool->audios[i];
+
+		audio->funcs->hw_init(audio);
+	}
+
+	for (i = 0; i < dc->link_count; i++) {
+		struct dc_link *link = dc->links[i];
+
+		if (link->panel_cntl)
+			backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
+	}
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		if (abms[i] != NULL)
+			abms[i]->funcs->abm_init(abms[i], backlight);
+	}
+
+	/* power AFMT HDMI memory TODO: may move to dis/en output save power*/
+	REG_WRITE(DIO_MEM_PWR_CTRL, 0);
+
+	if (!dc->debug.disable_clock_gate) {
+		/* enable all DCN clock gating */
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+
+		REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+
+		REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
+	}
+	if (hws->funcs.enable_power_gating_plane)
+		hws->funcs.enable_power_gating_plane(dc->hwseq, true);
+
+	if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
+		dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
+
+	if (dc->clk_mgr->funcs->notify_wm_ranges)
+		dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
+
+	if (dc->clk_mgr->funcs->set_hard_max_memclk)
+		dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
+
+	if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
+		dc->res_pool->hubbub->funcs->force_pstate_change_control(
+				dc->res_pool->hubbub, false, false);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	if (dc->res_pool->hubbub->funcs->init_crb)
+		dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
+#endif
+}
+
+void dcn31_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+	uint32_t org_ip_request_cntl = 0;
+
+	if (hws->ctx->dc->debug.disable_dsc_power_gate)
+		return;
+
+	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
+
+	switch (dsc_inst) {
+	case 0: /* DSC0 */
+		REG_UPDATE(DOMAIN16_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN16_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 1: /* DSC1 */
+		REG_UPDATE(DOMAIN17_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN17_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	case 2: /* DSC2 */
+		REG_UPDATE(DOMAIN18_PG_CONFIG,
+				DOMAIN_POWER_GATE, power_gate);
+
+		REG_WAIT(DOMAIN18_PG_STATUS,
+				DOMAIN_PGFSM_PWR_STATUS, pwr_status,
+				1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+
+	if (org_ip_request_cntl == 0)
+		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+}
+
+
+void dcn31_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable)
+{
+	bool force_on = true; /* disable power gating */
+
+	if (enable)
+		force_on = false;
+
+	/* DCHUBP0/1/2/3/4/5 */
+	REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+
+	/* DPP0/1/2/3/4/5 */
+	REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+
+	/* DCS0/1/2/3/4/5 */
+	REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+	REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on);
+}
+
+void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx)
+{
+	bool is_hdmi_tmds;
+	bool is_dp;
+
+	ASSERT(pipe_ctx->stream);
+
+	if (pipe_ctx->stream_res.stream_enc == NULL)
+		return;  /* this is not root pipe */
+
+	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
+	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
+
+	if (!is_hdmi_tmds)
+		return;
+
+	if (is_hdmi_tmds)
+		pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
+			pipe_ctx->stream_res.stream_enc,
+			&pipe_ctx->stream_res.encoder_info_frame);
+	else {
+		pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
+			pipe_ctx->stream_res.stream_enc,
+			&pipe_ctx->stream_res.encoder_info_frame);
+	}
+}
+
+void dcn31_z10_restore(struct dc *dc)
+{
+	union dmub_rb_cmd cmd;
+
+	/*
+	 * DMUB notifies whether restore is required.
+	 * Optimization to avoid sending commands when not required.
+	 */
+	if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))
+		return;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.dcn_restore.header.type = DMUB_CMD__IDLE_OPT;
+	cmd.dcn_restore.header.sub_type = DMUB_CMD__IDLE_OPT_DCN_RESTORE;
+
+	dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+	dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+	dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+}
+
+void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+{
+	uint32_t power_gate = power_on ? 0 : 1;
+	uint32_t pwr_status = power_on ? 0 : 2;
+
+	if (hws->ctx->dc->debug.disable_hubp_power_gate)
+		return;
+
+	if (REG(DOMAIN0_PG_CONFIG) == 0)
+		return;
+
+	switch (hubp_inst) {
+	case 0:
+		REG_SET(DOMAIN0_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 1:
+		REG_SET(DOMAIN1_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 2:
+		REG_SET(DOMAIN2_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	case 3:
+		REG_SET(DOMAIN3_PG_CONFIG, 0, DOMAIN_POWER_GATE, power_gate);
+		REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		break;
+	}
+}
+
+int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
+{
+	struct dcn_hubbub_phys_addr_config config;
+
+	config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
+	config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
+	config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
+	config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
+	config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
+	config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
+	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
+	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
+
+	if (pa_config->gart_config.base_addr_is_mc_addr) {
+		/* Convert from MC address to offset into FB */
+		config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr -
+				pa_config->system_aperture.fb_base +
+				pa_config->system_aperture.fb_offset;
+	} else
+		config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
+
+	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
+}
+
+static void dcn31_reset_back_end_for_pipe(
+		struct dc *dc,
+		struct pipe_ctx *pipe_ctx,
+		struct dc_state *context)
+{
+	struct dc_link *link;
+
+	DC_LOGGER_INIT(dc->ctx->logger);
+	if (pipe_ctx->stream_res.stream_enc == NULL) {
+		pipe_ctx->stream = NULL;
+		return;
+	}
+	ASSERT(!pipe_ctx->top_pipe);
+
+	dc->hwss.set_abm_immediate_disable(pipe_ctx);
+
+	pipe_ctx->stream_res.tg->funcs->set_dsc_config(
+			pipe_ctx->stream_res.tg,
+			OPTC_DSC_DISABLED, 0, 0);
+	pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
+
+	pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
+	if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
+		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
+				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+
+	if (pipe_ctx->stream_res.tg->funcs->set_drr)
+		pipe_ctx->stream_res.tg->funcs->set_drr(
+				pipe_ctx->stream_res.tg, NULL);
+
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		link = pipe_ctx->stream->link;
+		/* DPMS may already disable or */
+		/* dpms_off status is incorrect due to fastboot
+		 * feature. When system resume from S4 with second
+		 * screen only, the dpms_off would be true but
+		 * VBIOS lit up eDP, so check link status too.
+		 */
+		if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
+			core_link_disable_stream(pipe_ctx);
+		else if (pipe_ctx->stream_res.audio)
+			dc->hwss.disable_audio_stream(pipe_ctx);
+
+		/* free acquired resources */
+		if (pipe_ctx->stream_res.audio) {
+			/*disable az_endpoint*/
+			pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+
+			/*free audio*/
+			if (dc->caps.dynamic_audio == true) {
+				/*we have to dynamic arbitrate the audio endpoints*/
+				/*we free the resource, need reset is_audio_acquired*/
+				update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
+						pipe_ctx->stream_res.audio, false);
+				pipe_ctx->stream_res.audio = NULL;
+			}
+		}
+	} else if (pipe_ctx->stream_res.dsc) {
+			dp_set_dsc_enable(pipe_ctx, false);
+	}
+
+	pipe_ctx->stream = NULL;
+	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
+					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
+}
+
+void dcn31_reset_hw_ctx_wrap(
+		struct dc *dc,
+		struct dc_state *context)
+{
+	int i;
+	struct dce_hwseq *hws = dc->hwseq;
+
+	/* Reset Back End*/
+	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
+		struct pipe_ctx *pipe_ctx_old =
+			&dc->current_state->res_ctx.pipe_ctx[i];
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (!pipe_ctx_old->stream)
+			continue;
+
+		if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
+			continue;
+
+		if (!pipe_ctx->stream ||
+				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
+			struct clock_source *old_clk = pipe_ctx_old->clock_source;
+
+			dcn31_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
+			if (hws->funcs.enable_stream_gating)
+				hws->funcs.enable_stream_gating(dc, pipe_ctx);
+			if (old_clk)
+				old_clk->funcs->cs_power_down(old_clk);
+		}
+	}
+}
+
+bool dcn31_is_abm_supported(struct dc *dc,
+		struct dc_state *context, struct dc_stream_state *stream)
+{
+	int i;
+
+	for (i = 0; i < dc->res_pool->pipe_count; i++) {
+		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
+
+		if (pipe_ctx->stream == stream &&
+				(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
+			return true;
+	}
+	return false;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
new file mode 100644
index 000000000000..ff72f0fdd5be
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.h
@@ -0,0 +1,56 @@
+/*
+* Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_HWSS_DCN31_H__
+#define __DC_HWSS_DCN31_H__
+
+#include "hw_sequencer_private.h"
+
+struct dc;
+
+void dcn31_init_hw(struct dc *dc);
+
+void dcn31_dsc_pg_control(
+		struct dce_hwseq *hws,
+		unsigned int dsc_inst,
+		bool power_on);
+
+void dcn31_enable_power_gating_plane(
+	struct dce_hwseq *hws,
+	bool enable);
+
+void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);
+
+void dcn31_z10_restore(struct dc *dc);
+
+void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+void dcn31_reset_hw_ctx_wrap(
+		struct dc *dc,
+		struct dc_state *context);
+bool dcn31_is_abm_supported(struct dc *dc,
+		struct dc_state *context, struct dc_stream_state *stream);
+
+#endif /* __DC_HWSS_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
new file mode 100644
index 000000000000..e3048f8827d2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn10/dcn10_hw_sequencer.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn21/dcn21_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dcn301/dcn301_hwseq.h"
+#include "dcn31/dcn31_hwseq.h"
+
+static const struct hw_sequencer_funcs dcn31_funcs = {
+	.program_gamut_remap = dcn10_program_gamut_remap,
+	.init_hw = dcn31_init_hw,
+	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
+	.apply_ctx_for_surface = NULL,
+	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
+	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
+	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.update_dchub = dcn10_update_dchub,
+	.update_pending_status = dcn10_update_pending_status,
+	.program_output_csc = dcn20_program_output_csc,
+	.enable_accelerated_mode = dce110_enable_accelerated_mode,
+	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
+	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
+	.update_info_frame = dcn31_update_info_frame,
+	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
+	.enable_stream = dcn20_enable_stream,
+	.disable_stream = dce110_disable_stream,
+	.unblank_stream = dcn20_unblank_stream,
+	.blank_stream = dce110_blank_stream,
+	.enable_audio_stream = dce110_enable_audio_stream,
+	.disable_audio_stream = dce110_disable_audio_stream,
+	.disable_plane = dcn20_disable_plane,
+	.pipe_control_lock = dcn20_pipe_control_lock,
+	.interdependent_update_lock = dcn10_lock_all_pipes,
+	.cursor_lock = dcn10_cursor_lock,
+	.prepare_bandwidth = dcn20_prepare_bandwidth,
+	.optimize_bandwidth = dcn20_optimize_bandwidth,
+	.update_bandwidth = dcn20_update_bandwidth,
+	.set_drr = dcn10_set_drr,
+	.get_position = dcn10_get_position,
+	.set_static_screen_control = dcn10_set_static_screen_control,
+	.setup_stereo = dcn10_setup_stereo,
+	.set_avmute = dcn30_set_avmute,
+	.log_hw_state = dcn10_log_hw_state,
+	.get_hw_state = dcn10_get_hw_state,
+	.clear_status_bits = dcn10_clear_status_bits,
+	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.edp_power_control = dce110_edp_power_control,
+	.edp_wait_for_T12 = dce110_edp_wait_for_T12,
+	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
+	.set_cursor_position = dcn10_set_cursor_position,
+	.set_cursor_attribute = dcn10_set_cursor_attribute,
+	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
+	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
+	.set_clock = dcn10_set_clock,
+	.get_clock = dcn10_get_clock,
+	.program_triplebuffer = dcn20_program_triple_buffer,
+	.enable_writeback = dcn30_enable_writeback,
+	.disable_writeback = dcn30_disable_writeback,
+	.update_writeback = dcn30_update_writeback,
+	.mmhubbub_warmup = dcn30_mmhubbub_warmup,
+	.dmdata_status_done = dcn20_dmdata_status_done,
+	.program_dmdata_engine = dcn30_program_dmdata_engine,
+	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
+	.init_sys_ctx = dcn31_init_sys_ctx,
+	.init_vm_ctx = dcn20_init_vm_ctx,
+	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
+	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
+	.calc_vupdate_position = dcn10_calc_vupdate_position,
+	.apply_idle_power_optimizations = dcn30_apply_idle_power_optimizations,
+	.set_backlight_level = dcn21_set_backlight_level,
+	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
+	.set_pipe = dcn21_set_pipe,
+	.z10_restore = dcn31_z10_restore,
+	.is_abm_supported = dcn31_is_abm_supported,
+	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
+};
+
+static const struct hwseq_private_funcs dcn31_private_funcs = {
+	.init_pipes = dcn10_init_pipes,
+	.update_plane_addr = dcn20_update_plane_addr,
+	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
+	.update_mpcc = dcn20_update_mpcc,
+	.set_input_transfer_func = dcn30_set_input_transfer_func,
+	.set_output_transfer_func = dcn30_set_output_transfer_func,
+	.power_down = dce110_power_down,
+	.enable_display_power_gating = dcn10_dummy_display_power_gating,
+	.blank_pixel_data = dcn20_blank_pixel_data,
+	.reset_hw_ctx_wrap = dcn31_reset_hw_ctx_wrap,
+	.enable_stream_timing = dcn20_enable_stream_timing,
+	.edp_backlight_control = dce110_edp_backlight_control,
+	.disable_stream_gating = dcn20_disable_stream_gating,
+	.enable_stream_gating = dcn20_enable_stream_gating,
+	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
+	.did_underflow_occur = dcn10_did_underflow_occur,
+	.init_blank = dcn20_init_blank,
+	.disable_vga = dcn20_disable_vga,
+	.bios_golden_init = dcn10_bios_golden_init,
+	.plane_atomic_disable = dcn20_plane_atomic_disable,
+	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
+	.enable_power_gating_plane = dcn31_enable_power_gating_plane,
+	.hubp_pg_control = dcn31_hubp_pg_control,
+	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+	.update_odm = dcn20_update_odm,
+	.dsc_pg_control = dcn31_dsc_pg_control,
+	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
+	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
+	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
+	.dccg_init = dcn20_dccg_init,
+	.set_blend_lut = dcn30_set_blend_lut,
+	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
+};
+
+void dcn31_hw_sequencer_construct(struct dc *dc)
+{
+	dc->hwss = dcn31_funcs;
+	dc->hwseq->funcs = dcn31_private_funcs;
+
+	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+		dc->hwss.init_hw = dcn20_fpga_init_hw;
+		dc->hwseq->funcs.init_pipes = NULL;
+	}
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h
new file mode 100644
index 000000000000..a3db08c8bd35
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_DCN31_INIT_H__
+#define __DC_DCN31_INIT_H__
+
+struct dc;
+
+void dcn31_hw_sequencer_construct(struct dc *dc);
+
+#endif /* __DC_DCN31_INIT_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
new file mode 100644
index 000000000000..a4b1d98f0007
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn31_optc.h"
+
+#include "dcn30/dcn30_optc.h"
+#include "reg_helper.h"
+#include "dc.h"
+#include "dcn_calc_math.h"
+
+#define REG(reg)\
+	optc1->tg_regs->reg
+
+#define CTX \
+	optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+	optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
+		struct dc_crtc_timing *timing)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+	int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
+			/ opp_cnt;
+	uint32_t memory_mask = 0;
+	int mem_count_per_opp = (mpcc_hactive + 2559) / 2560;
+
+	/* Assume less than 6 pipes */
+	if (opp_cnt == 4) {
+		if (mem_count_per_opp == 1)
+			memory_mask = 0xf;
+		else {
+			ASSERT(mem_count_per_opp == 2);
+			memory_mask = 0xff;
+		}
+	} else if (mem_count_per_opp == 1)
+		memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2);
+	else if (mem_count_per_opp == 2)
+		memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
+	else if (mem_count_per_opp == 3)
+		memory_mask = 0x77;
+	else if (mem_count_per_opp == 4)
+		memory_mask = 0xff;
+
+	if (REG(OPTC_MEMORY_CONFIG))
+		REG_SET(OPTC_MEMORY_CONFIG, 0,
+			OPTC_MEM_SEL, memory_mask);
+
+	if (opp_cnt == 2) {
+		REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 1,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1]);
+	} else if (opp_cnt == 4) {
+		REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
+				OPTC_NUM_OF_INPUT_SEGMENT, 3,
+				OPTC_SEG0_SRC_SEL, opp_id[0],
+				OPTC_SEG1_SRC_SEL, opp_id[1],
+				OPTC_SEG2_SRC_SEL, opp_id[2],
+				OPTC_SEG3_SRC_SEL, opp_id[3]);
+	}
+
+	REG_UPDATE(OPTC_WIDTH_CONTROL,
+			OPTC_SEGMENT_WIDTH, mpcc_hactive);
+
+	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
+	optc1->opp_count = opp_cnt;
+}
+
+/**
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+static bool optc31_enable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* opp instance for OTG, 1 to 1 mapping and odm will adjust */
+	REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
+			OPTC_SEG0_SRC_SEL, optc->inst);
+
+	/* VTG enable first is for HW workaround */
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 1);
+
+	REG_SEQ_START();
+
+	/* Enable CRTC */
+	REG_UPDATE_2(OTG_CONTROL,
+			OTG_DISABLE_POINT_CNTL, 2,
+			OTG_MASTER_EN, 1);
+
+	REG_SEQ_SUBMIT();
+	REG_SEQ_WAIT_DONE();
+
+	return true;
+}
+
+/* disable_crtc - call ASIC Control Object to disable Timing generator. */
+static bool optc31_disable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	/* disable otg request until end of the first line
+	 * in the vertical blank region
+	 */
+	REG_UPDATE(OTG_CONTROL,
+			OTG_MASTER_EN, 0);
+
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL,
+			OTG_BUSY, 0,
+			1, 100000);
+
+	return true;
+}
+
+static bool optc31_immediate_disable_crtc(struct timing_generator *optc)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	REG_UPDATE_2(OTG_CONTROL,
+			OTG_DISABLE_POINT_CNTL, 0,
+			OTG_MASTER_EN, 0);
+
+	REG_UPDATE(CONTROL,
+			VTG0_ENABLE, 0);
+
+	/* CRTC disabled, so disable  clock. */
+	REG_WAIT(OTG_CLOCK_CONTROL,
+			OTG_BUSY, 0,
+			1, 100000);
+
+	return true;
+}
+
+static void optc31_set_drr(
+	struct timing_generator *optc,
+	const struct drr_params *params)
+{
+	struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+	if (params != NULL &&
+		params->vertical_total_max > 0 &&
+		params->vertical_total_min > 0) {
+
+		if (params->vertical_total_mid != 0) {
+
+			REG_SET(OTG_V_TOTAL_MID, 0,
+				OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
+
+			REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
+					OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
+					OTG_VTOTAL_MID_FRAME_NUM,
+					(uint8_t)params->vertical_total_mid_frame_num);
+
+		}
+
+		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
+
+		/*
+		 * MIN_MASK_EN is gone and MASK is now always enabled.
+		 *
+		 * To get it to it work with manual trigger we need to make sure
+		 * we program the correct bit.
+		 */
+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+				OTG_V_TOTAL_MIN_SEL, 1,
+				OTG_V_TOTAL_MAX_SEL, 1,
+				OTG_FORCE_LOCK_ON_EVENT, 0,
+				OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
+
+		// Setup manual flow control for EOF via TRIG_A
+		optc->funcs->setup_manual_trigger(optc);
+
+	} else {
+		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
+				OTG_SET_V_TOTAL_MIN_MASK, 0,
+				OTG_V_TOTAL_MIN_SEL, 0,
+				OTG_V_TOTAL_MAX_SEL, 0,
+				OTG_FORCE_LOCK_ON_EVENT, 0);
+
+		optc->funcs->set_vtotal_min_max(optc, 0, 0);
+	}
+}
+
+static struct timing_generator_funcs dcn31_tg_funcs = {
+		.validate_timing = optc1_validate_timing,
+		.program_timing = optc1_program_timing,
+		.setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
+		.setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
+		.setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
+		.program_global_sync = optc1_program_global_sync,
+		.enable_crtc = optc31_enable_crtc,
+		.disable_crtc = optc31_disable_crtc,
+		.immediate_disable_crtc = optc31_immediate_disable_crtc,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.is_counter_moving = optc1_is_counter_moving,
+		.get_position = optc1_get_position,
+		.get_frame_count = optc1_get_vblank_counter,
+		.get_scanoutpos = optc1_get_crtc_scanoutpos,
+		.get_otg_active_size = optc1_get_otg_active_size,
+		.set_early_control = optc1_set_early_control,
+		/* used by enable_timing_synchronization. Not need for FPGA */
+		.wait_for_state = optc1_wait_for_state,
+		.set_blank_color = optc3_program_blank_color,
+		.did_triggered_reset_occur = optc1_did_triggered_reset_occur,
+		.triplebuffer_lock = optc3_triplebuffer_lock,
+		.triplebuffer_unlock = optc2_triplebuffer_unlock,
+		.enable_reset_trigger = optc1_enable_reset_trigger,
+		.enable_crtc_reset = optc1_enable_crtc_reset,
+		.disable_reset_trigger = optc1_disable_reset_trigger,
+		.lock = optc3_lock,
+		.is_locked = optc1_is_locked,
+		.unlock = optc1_unlock,
+		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
+		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
+		.enable_optc_clock = optc1_enable_optc_clock,
+		.set_drr = optc31_set_drr,
+		.set_vtotal_min_max = optc1_set_vtotal_min_max,
+		.set_static_screen_control = optc1_set_static_screen_control,
+		.program_stereo = optc1_program_stereo,
+		.is_stereo_left_eye = optc1_is_stereo_left_eye,
+		.tg_init = optc3_tg_init,
+		.is_tg_enabled = optc1_is_tg_enabled,
+		.is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
+		.clear_optc_underflow = optc1_clear_optc_underflow,
+		.setup_global_swap_lock = NULL,
+		.get_crc = optc1_get_crc,
+		.configure_crc = optc2_configure_crc,
+		.set_dsc_config = optc3_set_dsc_config,
+		.set_dwb_source = NULL,
+		.set_odm_bypass = optc3_set_odm_bypass,
+		.set_odm_combine = optc31_set_odm_combine,
+		.get_optc_source = optc2_get_optc_source,
+		.set_out_mux = optc3_set_out_mux,
+		.set_drr_trigger_window = optc3_set_drr_trigger_window,
+		.set_vtotal_change_limit = optc3_set_vtotal_change_limit,
+		.set_gsl = optc2_set_gsl,
+		.set_gsl_source_select = optc2_set_gsl_source_select,
+		.set_vtg_params = optc1_set_vtg_params,
+		.program_manual_trigger = optc2_program_manual_trigger,
+		.setup_manual_trigger = optc2_setup_manual_trigger,
+		.get_hw_timing = optc1_get_hw_timing,
+};
+
+void dcn31_timing_generator_init(struct optc *optc1)
+{
+	optc1->base.funcs = &dcn31_tg_funcs;
+
+	optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
+	optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
+
+	optc1->min_h_blank = 32;
+	optc1->min_v_blank = 3;
+	optc1->min_v_blank_interlace = 5;
+	optc1->min_h_sync_width = 4;
+	optc1->min_v_sync_width = 1;
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
new file mode 100644
index 000000000000..d8ef2f0d0c95
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_optc.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_OPTC_DCN31_H__
+#define __DC_OPTC_DCN31_H__
+
+#include "dcn10/dcn10_optc.h"
+
+#define OPTC_COMMON_REG_LIST_DCN3_1(inst) \
+	SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
+	SRI(OTG_VUPDATE_PARAM, OTG, inst),\
+	SRI(OTG_VREADY_PARAM, OTG, inst),\
+	SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
+	SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
+	SRI(OTG_H_TOTAL, OTG, inst),\
+	SRI(OTG_H_BLANK_START_END, OTG, inst),\
+	SRI(OTG_H_SYNC_A, OTG, inst),\
+	SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_H_TIMING_CNTL, OTG, inst),\
+	SRI(OTG_V_TOTAL, OTG, inst),\
+	SRI(OTG_V_BLANK_START_END, OTG, inst),\
+	SRI(OTG_V_SYNC_A, OTG, inst),\
+	SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\
+	SRI(OTG_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_CONTROL, OTG, inst),\
+	SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\
+	SRI(OTG_STEREO_STATUS, OTG, inst),\
+	SRI(OTG_V_TOTAL_MAX, OTG, inst),\
+	SRI(OTG_V_TOTAL_MIN, OTG, inst),\
+	SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\
+	SRI(OTG_TRIGA_CNTL, OTG, inst),\
+	SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\
+	SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\
+	SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\
+	SRI(OTG_STATUS, OTG, inst),\
+	SRI(OTG_STATUS_POSITION, OTG, inst),\
+	SRI(OTG_NOM_VERT_POSITION, OTG, inst),\
+	SRI(OTG_M_CONST_DTO0, OTG, inst),\
+	SRI(OTG_M_CONST_DTO1, OTG, inst),\
+	SRI(OTG_CLOCK_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\
+	SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\
+	SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\
+	SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\
+	SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\
+	SRI(CONTROL, VTG, inst),\
+	SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\
+	SRI(OTG_GSL_CONTROL, OTG, inst),\
+	SRI(OTG_CRC_CNTL, OTG, inst),\
+	SRI(OTG_CRC0_DATA_RG, OTG, inst),\
+	SRI(OTG_CRC0_DATA_B, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\
+	SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\
+	SR(GSL_SOURCE_SELECT),\
+	SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
+	SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_X, OTG, inst),\
+	SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
+	SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
+	SRI(OTG_DSC_START_POSITION, OTG, inst),\
+	SRI(OTG_DRR_TRIGGER_WINDOW, OTG, inst),\
+	SRI(OTG_DRR_V_TOTAL_CHANGE, OTG, inst),\
+	SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
+	SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
+	SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
+	SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
+	SRI(OTG_CRC_CNTL2, OTG, inst),\
+	SR(DWB_SOURCE_SELECT)
+
+#define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\
+	SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\
+	SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\
+	SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\
+	SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\
+	SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\
+	SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\
+	SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\
+	SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\
+	SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\
+	SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\
+	SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\
+	SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\
+	SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\
+	SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\
+	SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\
+	SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\
+	SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\
+	SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\
+	SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\
+	SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\
+	SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\
+	SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\
+	SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\
+	SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\
+	SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\
+	SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
+	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
+	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\
+	SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \
+	SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \
+	SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_X, mask_sh), \
+	SF(OTG0_OTG_DSC_START_POSITION, OTG_DSC_START_POSITION_LINE_NUM, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\
+	SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\
+	SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\
+	SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
+	SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
+	SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\
+	SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\
+	SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\
+	SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\
+	SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DSC_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\
+	SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh)
+
+void dcn31_timing_generator_init(struct optc *optc1);
+
+#endif /* __DC_OPTC_DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
new file mode 100644
index 000000000000..7db268da6976
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "core_types.h"
+#include "dc_dmub_srv.h"
+#include "dcn31_panel_cntl.h"
+#include "atom.h"
+
+#define TO_DCN31_PANEL_CNTL(panel_cntl)\
+	container_of(panel_cntl, struct dcn31_panel_cntl, base)
+
+#define CTX \
+	dcn31_panel_cntl->base.ctx
+
+#define DC_LOGGER \
+	dcn31_panel_cntl->base.ctx->logger
+
+static bool dcn31_query_backlight_info(struct panel_cntl *panel_cntl, union dmub_rb_cmd *cmd)
+{
+	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);
+	struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;
+
+	if (!dc_dmub_srv)
+		return false;
+
+	memset(cmd, 0, sizeof(*cmd));
+	cmd->panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;
+	cmd->panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO;
+	cmd->panel_cntl.header.payload_bytes = sizeof(cmd->panel_cntl.data);
+	cmd->panel_cntl.data.inst = dcn31_panel_cntl->base.inst;
+
+	return dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, cmd);
+}
+
+static uint32_t dcn31_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return 0;
+
+	return cmd.panel_cntl.data.current_backlight;
+}
+
+uint32_t dcn31_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
+{
+	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(panel_cntl);
+	struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;
+	union dmub_rb_cmd cmd;
+
+	if (!dc_dmub_srv)
+		return 0;
+
+	memset(&cmd, 0, sizeof(cmd));
+	cmd.panel_cntl.header.type = DMUB_CMD__PANEL_CNTL;
+	cmd.panel_cntl.header.sub_type = DMUB_CMD__PANEL_CNTL_HW_INIT;
+	cmd.panel_cntl.header.payload_bytes = sizeof(cmd.panel_cntl.data);
+	cmd.panel_cntl.data.inst = dcn31_panel_cntl->base.inst;
+	cmd.panel_cntl.data.bl_pwm_cntl = panel_cntl->stored_backlight_registers.BL_PWM_CNTL;
+	cmd.panel_cntl.data.bl_pwm_period_cntl = panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL;
+	cmd.panel_cntl.data.bl_pwm_ref_div1 =
+		panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
+
+	if (!dc_dmub_srv_cmd_with_reply_data(dc_dmub_srv, &cmd))
+		return 0;
+
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl;
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 0; /* unused */
+	panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = cmd.panel_cntl.data.bl_pwm_period_cntl;
+	panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV =
+		cmd.panel_cntl.data.bl_pwm_ref_div1;
+
+	return cmd.panel_cntl.data.current_backlight;
+}
+
+void dcn31_panel_cntl_destroy(struct panel_cntl **panel_cntl)
+{
+	struct dcn31_panel_cntl *dcn31_panel_cntl = TO_DCN31_PANEL_CNTL(*panel_cntl);
+
+	kfree(dcn31_panel_cntl);
+	*panel_cntl = NULL;
+}
+
+bool dcn31_is_panel_backlight_on(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return 0;
+
+	return cmd.panel_cntl.data.is_backlight_on;
+}
+
+bool dcn31_is_panel_powered_on(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return 0;
+
+	return cmd.panel_cntl.data.is_powered_on;
+}
+
+void dcn31_store_backlight_level(struct panel_cntl *panel_cntl)
+{
+	union dmub_rb_cmd cmd;
+
+	if (!dcn31_query_backlight_info(panel_cntl, &cmd))
+		return;
+
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL = cmd.panel_cntl.data.bl_pwm_cntl;
+	panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 = 0; /* unused */
+	panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL = cmd.panel_cntl.data.bl_pwm_period_cntl;
+	panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV =
+		cmd.panel_cntl.data.bl_pwm_ref_div1;
+}
+
+static const struct panel_cntl_funcs dcn31_link_panel_cntl_funcs = {
+	.destroy = dcn31_panel_cntl_destroy,
+	.hw_init = dcn31_panel_cntl_hw_init,
+	.is_panel_backlight_on = dcn31_is_panel_backlight_on,
+	.is_panel_powered_on = dcn31_is_panel_powered_on,
+	.store_backlight_level = dcn31_store_backlight_level,
+	.get_current_backlight = dcn31_get_16_bit_backlight_from_pwm,
+};
+
+void dcn31_panel_cntl_construct(
+	struct dcn31_panel_cntl *dcn31_panel_cntl,
+	const struct panel_cntl_init_data *init_data)
+{
+	dcn31_panel_cntl->base.funcs = &dcn31_link_panel_cntl_funcs;
+	dcn31_panel_cntl->base.ctx = init_data->ctx;
+	dcn31_panel_cntl->base.inst = init_data->inst;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h
new file mode 100644
index 000000000000..d33ccd6ef8c3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DC_PANEL_CNTL__DCN31_H__
+#define __DC_PANEL_CNTL__DCN31_H__
+
+#include "panel_cntl.h"
+#include "dce/dce_panel_cntl.h"
+
+struct dcn31_panel_cntl {
+	struct panel_cntl base;
+};
+
+void dcn31_panel_cntl_construct(
+	struct dcn31_panel_cntl *dcn31_panel_cntl,
+	const struct panel_cntl_init_data *init_data);
+
+#endif /* __DC_PANEL_CNTL__DCN31_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
new file mode 100644
index 000000000000..0d6cb6caad81
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -0,0 +1,2196 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "dm_services.h"
+#include "dc.h"
+
+#include "dcn31/dcn31_init.h"
+
+#include "resource.h"
+#include "include/irq_service_interface.h"
+#include "dcn31_resource.h"
+
+#include "dcn20/dcn20_resource.h"
+#include "dcn30/dcn30_resource.h"
+
+#include "dcn10/dcn10_ipp.h"
+#include "dcn30/dcn30_hubbub.h"
+#include "dcn31/dcn31_hubbub.h"
+#include "dcn30/dcn30_mpc.h"
+#include "dcn31/dcn31_hubp.h"
+#include "irq/dcn31/irq_service_dcn31.h"
+#include "dcn30/dcn30_dpp.h"
+#include "dcn31/dcn31_optc.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "dcn30/dcn30_hwseq.h"
+#include "dce110/dce110_hw_sequencer.h"
+#include "dcn30/dcn30_opp.h"
+#include "dcn20/dcn20_dsc.h"
+#include "dcn30/dcn30_vpg.h"
+#include "dcn30/dcn30_afmt.h"
+#include "dcn30/dcn30_dio_stream_encoder.h"
+#include "dcn31/dcn31_dio_link_encoder.h"
+#include "dce/dce_clock_source.h"
+#include "dce/dce_audio.h"
+#include "dce/dce_hwseq.h"
+#include "clk_mgr.h"
+#include "virtual/virtual_stream_encoder.h"
+#include "dce110/dce110_resource.h"
+#include "dml/display_mode_vba.h"
+#include "dcn31/dcn31_dccg.h"
+#include "dcn10/dcn10_resource.h"
+#include "dcn31_panel_cntl.h"
+
+#include "dcn30/dcn30_dwb.h"
+#include "dcn30/dcn30_mmhubbub.h"
+
+// TODO: change include headers /amd/include/asic_reg after upstream
+#include "yellow_carp_offset.h"
+#include "dcn/dcn_3_1_2_offset.h"
+#include "dcn/dcn_3_1_2_sh_mask.h"
+#include "nbio/nbio_7_2_0_offset.h"
+#include "dpcs/dpcs_4_2_0_offset.h"
+#include "dpcs/dpcs_4_2_0_sh_mask.h"
+#include "mmhub/mmhub_2_3_0_offset.h"
+#include "mmhub/mmhub_2_3_0_sh_mask.h"
+
+
+#define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
+#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
+#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
+
+#include "reg_helper.h"
+#include "dce/dmub_abm.h"
+#include "dce/dmub_psr.h"
+#include "dce/dce_aux.h"
+#include "dce/dce_i2c.h"
+
+#include "dml/dcn30/display_mode_vba_30.h"
+#include "vm_helper.h"
+#include "dcn20/dcn20_vmid.h"
+
+#include "link_enc_cfg.h"
+
+#define DC_LOGGER_INIT(logger)
+#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
+#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
+
+#define DCN3_1_DEFAULT_DET_SIZE 384
+
+struct _vcs_dpi_ip_params_st dcn3_1_ip = {
+	.gpuvm_enable = 1,
+	.gpuvm_max_page_table_levels = 1,
+	.hostvm_enable = 1,
+	.hostvm_max_page_table_levels = 2,
+	.rob_buffer_size_kbytes = 64,
+	.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
+	.config_return_buffer_size_in_kbytes = 1792,
+	.compressed_buffer_segment_size_in_kbytes = 64,
+	.meta_fifo_size_in_kentries = 32,
+	.zero_size_buffer_entries = 512,
+	.compbuf_reserved_space_64b = 256,
+	.compbuf_reserved_space_zs = 64,
+	.dpp_output_buffer_pixels = 2560,
+	.opp_output_buffer_lines = 1,
+	.pixel_chunk_size_kbytes = 8,
+	.meta_chunk_size_kbytes = 2,
+	.min_meta_chunk_size_bytes = 256,
+	.writeback_chunk_size_kbytes = 8,
+	.ptoi_supported = false,
+	.num_dsc = 3,
+	.maximum_dsc_bits_per_component = 10,
+	.dsc422_native_support = false,
+	.is_line_buffer_bpp_fixed = true,
+	.line_buffer_fixed_bpp = 48,
+	.line_buffer_size_bits = 789504,
+	.max_line_buffer_lines = 12,
+	.writeback_interface_buffer_size_kbytes = 90,
+	.max_num_dpp = 4,
+	.max_num_otg = 4,
+	.max_num_hdmi_frl_outputs = 1,
+	.max_num_wb = 1,
+	.max_dchub_pscl_bw_pix_per_clk = 4,
+	.max_pscl_lb_bw_pix_per_clk = 2,
+	.max_lb_vscl_bw_pix_per_clk = 4,
+	.max_vscl_hscl_bw_pix_per_clk = 4,
+	.max_hscl_ratio = 6,
+	.max_vscl_ratio = 6,
+	.max_hscl_taps = 8,
+	.max_vscl_taps = 8,
+	.dpte_buffer_size_in_pte_reqs_luma = 64,
+	.dpte_buffer_size_in_pte_reqs_chroma = 34,
+	.dispclk_ramp_margin_percent = 1,
+	.max_inter_dcn_tile_repeaters = 8,
+	.cursor_buffer_size = 16,
+	.cursor_chunk_size = 2,
+	.writeback_line_buffer_buffer_size = 0,
+	.writeback_min_hscl_ratio = 1,
+	.writeback_min_vscl_ratio = 1,
+	.writeback_max_hscl_ratio = 1,
+	.writeback_max_vscl_ratio = 1,
+	.writeback_max_hscl_taps = 1,
+	.writeback_max_vscl_taps = 1,
+	.dppclk_delay_subtotal = 46,
+	.dppclk_delay_scl = 50,
+	.dppclk_delay_scl_lb_only = 16,
+	.dppclk_delay_cnvc_formatter = 27,
+	.dppclk_delay_cnvc_cursor = 6,
+	.dispclk_delay_subtotal = 119,
+	.dynamic_metadata_vm_enabled = false,
+	.odm_combine_4to1_supported = false,
+	.dcc_supported = true,
+};
+
+struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
+		/*TODO: correct dispclk/dppclk voltage level determination*/
+	.clock_limits = {
+		{
+			.state = 0,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 600.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 186.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 1,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 209.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 2,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 209.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 3,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 371.0,
+			.dtbclk_mhz = 625.0,
+		},
+		{
+			.state = 4,
+			.dispclk_mhz = 1200.0,
+			.dppclk_mhz = 1200.0,
+			.phyclk_mhz = 810.0,
+			.phyclk_d18_mhz = 667.0,
+			.dscclk_mhz = 417.0,
+			.dtbclk_mhz = 625.0,
+		},
+	},
+	.num_states = 5,
+	.sr_exit_time_us = 9.0,
+	.sr_enter_plus_exit_time_us = 11.0,
+	.sr_exit_z8_time_us = 402.0,
+	.sr_enter_plus_exit_z8_time_us = 520.0,
+	.writeback_latency_us = 12.0,
+	.round_trip_ping_latency_dcfclk_cycles = 106,
+	.urgent_latency_pixel_data_only_us = 4.0,
+	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
+	.urgent_latency_vm_data_only_us = 4.0,
+	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
+	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
+	.pct_ideal_sdp_bw_after_urgent = 80.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
+	.pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
+	.max_avg_sdp_bw_use_normal_percent = 60.0,
+	.max_avg_dram_bw_use_normal_percent = 60.0,
+	.fabric_datapath_to_dcn_data_return_bytes = 32,
+	.return_bus_width_bytes = 64,
+	.downspread_percent = 0.38,
+	.dcn_downspread_percent = 0.5,
+	.gpuvm_min_page_size_bytes = 4096,
+	.hostvm_min_page_size_bytes = 4096,
+	.do_urgent_latency_adjustment = false,
+	.urgent_latency_adjustment_fabric_clock_component_us = 0,
+	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
+};
+
+enum dcn31_clk_src_array_id {
+	DCN31_CLK_SRC_PLL0,
+	DCN31_CLK_SRC_PLL1,
+	DCN31_CLK_SRC_PLL2,
+	DCN31_CLK_SRC_PLL3,
+	DCN31_CLK_SRC_PLL4,
+	DCN30_CLK_SRC_TOTAL
+};
+
+/* begin *********************
+ * macros to expend register list macro defined in HW object header file
+ */
+
+/* DCN */
+/* TODO awful hack. fixup dcn20_dwb.h */
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+#define SR(reg_name)\
+		.reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
+					reg ## reg_name
+
+#define SRI(reg_name, block, id)\
+	.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRI2(reg_name, block, id)\
+	.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
+					reg ## reg_name
+
+#define SRIR(var_name, reg_name, block, id)\
+	.var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_MPC_RMU(reg_name, block, id)\
+	.RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define SRII_DWB(reg_name, temp_name, block, id)\
+	.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## temp_name
+
+#define DCCG_SRII(reg_name, block, id)\
+	.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## id ## _ ## reg_name
+
+#define VUPDATE_SRII(reg_name, block, id)\
+	.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
+					reg ## reg_name ## _ ## block ## id
+
+/* NBIO */
+#define NBIO_BASE_INNER(seg) \
+	NBIO_BASE__INST0_SEG ## seg
+
+#define NBIO_BASE(seg) \
+	NBIO_BASE_INNER(seg)
+
+#define NBIO_SR(reg_name)\
+		.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
+					regBIF_BX1_ ## reg_name
+
+/* MMHUB */
+#define MMHUB_BASE_INNER(seg) \
+	MMHUB_BASE__INST0_SEG ## seg
+
+#define MMHUB_BASE(seg) \
+	MMHUB_BASE_INNER(seg)
+
+#define MMHUB_SR(reg_name)\
+		.reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
+					mm ## reg_name
+
+/* CLOCK */
+#define CLK_BASE_INNER(seg) \
+	CLK_BASE__INST0_SEG ## seg
+
+#define CLK_BASE(seg) \
+	CLK_BASE_INNER(seg)
+
+#define CLK_SRI(reg_name, block, inst)\
+	.reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
+					reg ## block ## _ ## inst ## _ ## reg_name
+
+
+static const struct bios_registers bios_regs = {
+		NBIO_SR(BIOS_SCRATCH_3),
+		NBIO_SR(BIOS_SCRATCH_6)
+};
+
+#define clk_src_regs(index, pllid)\
+[index] = {\
+	CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
+}
+
+static const struct dce110_clk_src_regs clk_src_regs[] = {
+	clk_src_regs(0, A),
+	clk_src_regs(1, B),
+	clk_src_regs(2, C),
+	clk_src_regs(3, D),
+	clk_src_regs(4, E)
+};
+
+static const struct dce110_clk_src_shift cs_shift = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dce110_clk_src_mask cs_mask = {
+		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+#define abm_regs(id)\
+[id] = {\
+		ABM_DCN301_REG_LIST(id)\
+}
+
+static const struct dce_abm_registers abm_regs[] = {
+		abm_regs(0),
+		abm_regs(1),
+		abm_regs(2),
+		abm_regs(3),
+};
+
+static const struct dce_abm_shift abm_shift = {
+		ABM_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_abm_mask abm_mask = {
+		ABM_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define audio_regs(id)\
+[id] = {\
+		AUD_COMMON_REG_LIST(id)\
+}
+
+static const struct dce_audio_registers audio_regs[] = {
+	audio_regs(0),
+	audio_regs(1),
+	audio_regs(2),
+	audio_regs(3),
+	audio_regs(4),
+	audio_regs(5),
+	audio_regs(6)
+};
+
+#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
+		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
+		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
+
+static const struct dce_audio_shift audio_shift = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_audio_mask audio_mask = {
+		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
+};
+
+#define vpg_regs(id)\
+[id] = {\
+	VPG_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_vpg_registers vpg_regs[] = {
+	vpg_regs(0),
+	vpg_regs(1),
+	vpg_regs(2),
+	vpg_regs(3),
+	vpg_regs(4),
+	vpg_regs(5),
+	vpg_regs(6),
+	vpg_regs(7),
+	vpg_regs(8),
+	vpg_regs(9),
+};
+
+static const struct dcn30_vpg_shift vpg_shift = {
+	DCN3_VPG_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_vpg_mask vpg_mask = {
+	DCN3_VPG_MASK_SH_LIST(_MASK)
+};
+
+#define afmt_regs(id)\
+[id] = {\
+	AFMT_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn30_afmt_registers afmt_regs[] = {
+	afmt_regs(0),
+	afmt_regs(1),
+	afmt_regs(2),
+	afmt_regs(3),
+	afmt_regs(4),
+	afmt_regs(5)
+};
+
+static const struct dcn30_afmt_shift afmt_shift = {
+	DCN3_AFMT_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn30_afmt_mask afmt_mask = {
+	DCN3_AFMT_MASK_SH_LIST(_MASK)
+};
+
+#define stream_enc_regs(id)\
+[id] = {\
+	SE_DCN3_REG_LIST(id)\
+}
+
+static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
+	stream_enc_regs(0),
+	stream_enc_regs(1),
+	stream_enc_regs(2),
+	stream_enc_regs(3),
+	stream_enc_regs(4)
+};
+
+static const struct dcn10_stream_encoder_shift se_shift = {
+		SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn10_stream_encoder_mask se_mask = {
+		SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+
+#define aux_regs(id)\
+[id] = {\
+	DCN2_AUX_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
+		aux_regs(0),
+		aux_regs(1),
+		aux_regs(2),
+		aux_regs(3),
+		aux_regs(4)
+};
+
+#define hpd_regs(id)\
+[id] = {\
+	HPD_REG_LIST(id)\
+}
+
+static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
+		hpd_regs(0),
+		hpd_regs(1),
+		hpd_regs(2),
+		hpd_regs(3),
+		hpd_regs(4)
+};
+
+#define link_regs(id, phyid)\
+[id] = {\
+	LE_DCN31_REG_LIST(id), \
+	UNIPHY_DCN2_REG_LIST(phyid), \
+	DPCS_DCN31_REG_LIST(id), \
+}
+
+static const struct dce110_aux_registers_shift aux_shift = {
+	DCN_AUX_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce110_aux_registers_mask aux_mask = {
+	DCN_AUX_MASK_SH_LIST(_MASK)
+};
+
+static const struct dcn10_link_enc_registers link_enc_regs[] = {
+	link_regs(0, A),
+	link_regs(1, B),
+	link_regs(2, C),
+	link_regs(3, D),
+	link_regs(4, E)
+};
+
+static const struct dcn10_link_enc_shift le_shift = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
+	DPCS_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn10_link_enc_mask le_mask = {
+	LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
+	DPCS_DCN31_MASK_SH_LIST(_MASK)
+};
+
+#define dpp_regs(id)\
+[id] = {\
+	DPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn3_dpp_registers dpp_regs[] = {
+	dpp_regs(0),
+	dpp_regs(1),
+	dpp_regs(2),
+	dpp_regs(3)
+};
+
+static const struct dcn3_dpp_shift tf_shift = {
+		DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
+};
+
+static const struct dcn3_dpp_mask tf_mask = {
+		DPP_REG_LIST_SH_MASK_DCN30(_MASK)
+};
+
+#define opp_regs(id)\
+[id] = {\
+	OPP_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn20_opp_registers opp_regs[] = {
+	opp_regs(0),
+	opp_regs(1),
+	opp_regs(2),
+	opp_regs(3)
+};
+
+static const struct dcn20_opp_shift opp_shift = {
+	OPP_MASK_SH_LIST_DCN20(__SHIFT)
+};
+
+static const struct dcn20_opp_mask opp_mask = {
+	OPP_MASK_SH_LIST_DCN20(_MASK)
+};
+
+#define aux_engine_regs(id)\
+[id] = {\
+	AUX_COMMON_REG_LIST0(id), \
+	.AUXN_IMPCAL = 0, \
+	.AUXP_IMPCAL = 0, \
+	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
+}
+
+static const struct dce110_aux_registers aux_engine_regs[] = {
+		aux_engine_regs(0),
+		aux_engine_regs(1),
+		aux_engine_regs(2),
+		aux_engine_regs(3),
+		aux_engine_regs(4)
+};
+
+#define dwbc_regs_dcn3(id)\
+[id] = {\
+	DWBC_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_dwbc_registers dwbc30_regs[] = {
+	dwbc_regs_dcn3(0),
+};
+
+static const struct dcn30_dwbc_shift dwbc30_shift = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_dwbc_mask dwbc30_mask = {
+	DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define mcif_wb_regs_dcn3(id)\
+[id] = {\
+	MCIF_WB_COMMON_REG_LIST_DCN30(id),\
+}
+
+static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
+	mcif_wb_regs_dcn3(0)
+};
+
+static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
+	MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define dsc_regsDCN20(id)\
+[id] = {\
+	DSC_REG_LIST_DCN20(id)\
+}
+
+static const struct dcn20_dsc_registers dsc_regs[] = {
+	dsc_regsDCN20(0),
+	dsc_regsDCN20(1),
+	dsc_regsDCN20(2)
+};
+
+static const struct dcn20_dsc_shift dsc_shift = {
+	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
+};
+
+static const struct dcn20_dsc_mask dsc_mask = {
+	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
+};
+
+static const struct dcn30_mpc_registers mpc_regs = {
+		MPC_REG_LIST_DCN3_0(0),
+		MPC_REG_LIST_DCN3_0(1),
+		MPC_REG_LIST_DCN3_0(2),
+		MPC_REG_LIST_DCN3_0(3),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(0),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(1),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(2),
+		MPC_OUT_MUX_REG_LIST_DCN3_0(3),
+		MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
+		MPC_RMU_REG_LIST_DCN3AG(0),
+		MPC_RMU_REG_LIST_DCN3AG(1),
+		//MPC_RMU_REG_LIST_DCN3AG(2),
+		MPC_DWB_MUX_REG_LIST_DCN3_0(0),
+};
+
+static const struct dcn30_mpc_shift mpc_shift = {
+	MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dcn30_mpc_mask mpc_mask = {
+	MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+#define optc_regs(id)\
+[id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
+
+static const struct dcn_optc_registers optc_regs[] = {
+	optc_regs(0),
+	optc_regs(1),
+	optc_regs(2),
+	optc_regs(3)
+};
+
+static const struct dcn_optc_shift optc_shift = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
+};
+
+static const struct dcn_optc_mask optc_mask = {
+	OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
+};
+
+#define hubp_regs(id)\
+[id] = {\
+	HUBP_REG_LIST_DCN30(id)\
+}
+
+static const struct dcn_hubp2_registers hubp_regs[] = {
+		hubp_regs(0),
+		hubp_regs(1),
+		hubp_regs(2),
+		hubp_regs(3)
+};
+
+
+static const struct dcn_hubp2_shift hubp_shift = {
+		HUBP_MASK_SH_LIST_DCN31(__SHIFT)
+};
+
+static const struct dcn_hubp2_mask hubp_mask = {
+		HUBP_MASK_SH_LIST_DCN31(_MASK)
+};
+static const struct dcn_hubbub_registers hubbub_reg = {
+		HUBBUB_REG_LIST_DCN31(0)
+};
+
+static const struct dcn_hubbub_shift hubbub_shift = {
+		HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
+};
+
+static const struct dcn_hubbub_mask hubbub_mask = {
+		HUBBUB_MASK_SH_LIST_DCN31(_MASK)
+};
+
+static const struct dccg_registers dccg_regs = {
+		DCCG_REG_LIST_DCN31()
+};
+
+static const struct dccg_shift dccg_shift = {
+		DCCG_MASK_SH_LIST_DCN31(__SHIFT)
+};
+
+static const struct dccg_mask dccg_mask = {
+		DCCG_MASK_SH_LIST_DCN31(_MASK)
+};
+
+
+#define SRII2(reg_name_pre, reg_name_post, id)\
+	.reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
+			## id ## _ ## reg_name_post ## _BASE_IDX) + \
+			reg ## reg_name_pre ## id ## _ ## reg_name_post
+
+
+#define HWSEQ_DCN31_REG_LIST()\
+	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
+	SR(DIO_MEM_PWR_CTRL), \
+	SR(ODM_MEM_PWR_CTRL3), \
+	SR(DMU_MEM_PWR_CNTL), \
+	SR(MMHUBBUB_MEM_PWR_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL), \
+	SR(DCCG_GATE_DISABLE_CNTL2), \
+	SR(DCFCLK_CNTL),\
+	SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
+	SRII(PIXEL_RATE_CNTL, OTG, 0), \
+	SRII(PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PIXEL_RATE_CNTL, OTG, 3),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
+	SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
+	SR(MICROSECOND_TIME_BASE_DIV), \
+	SR(MILLISECOND_TIME_BASE_DIV), \
+	SR(DISPCLK_FREQ_CHANGE_CNTL), \
+	SR(RBBMIF_TIMEOUT_DIS), \
+	SR(RBBMIF_TIMEOUT_DIS_2), \
+	SR(DCHUBBUB_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_CTRL), \
+	SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+	SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+	SR(MPC_CRC_CTRL), \
+	SR(MPC_CRC_RESULT_GB), \
+	SR(MPC_CRC_RESULT_C), \
+	SR(MPC_CRC_RESULT_AR), \
+	SR(DOMAIN0_PG_CONFIG), \
+	SR(DOMAIN1_PG_CONFIG), \
+	SR(DOMAIN2_PG_CONFIG), \
+	SR(DOMAIN3_PG_CONFIG), \
+	SR(DOMAIN16_PG_CONFIG), \
+	SR(DOMAIN17_PG_CONFIG), \
+	SR(DOMAIN18_PG_CONFIG), \
+	SR(DOMAIN0_PG_STATUS), \
+	SR(DOMAIN1_PG_STATUS), \
+	SR(DOMAIN2_PG_STATUS), \
+	SR(DOMAIN3_PG_STATUS), \
+	SR(DOMAIN16_PG_STATUS), \
+	SR(DOMAIN17_PG_STATUS), \
+	SR(DOMAIN18_PG_STATUS), \
+	SR(D1VGA_CONTROL), \
+	SR(D2VGA_CONTROL), \
+	SR(D3VGA_CONTROL), \
+	SR(D4VGA_CONTROL), \
+	SR(D5VGA_CONTROL), \
+	SR(D6VGA_CONTROL), \
+	SR(DC_IP_REQUEST_CNTL), \
+	SR(AZALIA_AUDIO_DTO), \
+	SR(AZALIA_CONTROLLER_CLOCK_GATING)
+
+static const struct dce_hwseq_registers hwseq_reg = {
+		HWSEQ_DCN31_REG_LIST()
+};
+
+#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
+	HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+	HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
+	HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
+	HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+	HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
+	HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
+	HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
+	HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
+	HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+
+static const struct dce_hwseq_shift hwseq_shift = {
+		HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dce_hwseq_mask hwseq_mask = {
+		HWSEQ_DCN31_MASK_SH_LIST(_MASK)
+};
+#define vmid_regs(id)\
+[id] = {\
+		DCN20_VMID_REG_LIST(id)\
+}
+
+static const struct dcn_vmid_registers vmid_regs[] = {
+	vmid_regs(0),
+	vmid_regs(1),
+	vmid_regs(2),
+	vmid_regs(3),
+	vmid_regs(4),
+	vmid_regs(5),
+	vmid_regs(6),
+	vmid_regs(7),
+	vmid_regs(8),
+	vmid_regs(9),
+	vmid_regs(10),
+	vmid_regs(11),
+	vmid_regs(12),
+	vmid_regs(13),
+	vmid_regs(14),
+	vmid_regs(15)
+};
+
+static const struct dcn20_vmid_shift vmid_shifts = {
+		DCN20_VMID_MASK_SH_LIST(__SHIFT)
+};
+
+static const struct dcn20_vmid_mask vmid_masks = {
+		DCN20_VMID_MASK_SH_LIST(_MASK)
+};
+
+static const struct resource_caps res_cap_dcn31 = {
+	.num_timing_generator = 4,
+	.num_opp = 4,
+	.num_video_plane = 4,
+	.num_audio = 5,
+	.num_stream_encoder = 5,
+	.num_dig_link_enc = 5,
+	.num_pll = 5,
+	.num_dwb = 1,
+	.num_ddc = 5,
+	.num_vmid = 16,
+	.num_mpc_3dlut = 2,
+	.num_dsc = 3,
+};
+
+static const struct dc_plane_cap plane_cap = {
+	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
+	.blends_with_above = true,
+	.blends_with_below = true,
+	.per_pixel_alpha = true,
+
+	.pixel_format_support = {
+			.argb8888 = true,
+			.nv12 = true,
+			.fp16 = true,
+			.p010 = false,
+			.ayuv = false,
+	},
+
+	.max_upscale_factor = {
+			.argb8888 = 16000,
+			.nv12 = 16000,
+			.fp16 = 16000
+	},
+
+	// 6:1 downscaling ratio: 1000/6 = 166.666
+	.max_downscale_factor = {
+			.argb8888 = 167,
+			.nv12 = 167,
+			.fp16 = 167
+	},
+	64,
+	64
+};
+
+static const struct dc_debug_options debug_defaults_drv = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = false,
+	.clock_trace = true,
+	.disable_pplib_clock_request = false,
+	.pipe_split_policy = MPC_SPLIT_AVOID,
+	.force_single_disp_pipe_split = false,
+	.disable_dcc = DCC_ENABLE,
+	.vsr_support = true,
+	.performance_trace = false,
+	.max_downscale_src_width = 7680,/*upto 8K*/
+	.disable_pplib_wm_range = false,
+	.scl_reset_length10 = true,
+	.sanity_checks = false,
+	.underflow_assert_delay_us = 0xFFFFFFFF,
+	.dwb_fi_phase = -1, // -1 = disable,
+	.dmub_command_table = true,
+	.pstate_enabled = true,
+	.use_max_lb = true,
+	.pstate_enabled = true,
+	.enable_mem_low_power = {
+		.bits = {
+			.vga = false,
+			.i2c = false,
+			.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
+			.dscl = false,
+			.cm = false,
+			.mpc = false,
+			.optc = false,
+		}
+	},
+	.optimize_edp_link_rate = true,
+	.enable_sw_cntl_psr = true,
+};
+
+static const struct dc_debug_options debug_defaults_diags = {
+	.disable_dmcu = true,
+	.force_abm_enable = false,
+	.timing_trace = true,
+	.clock_trace = true,
+	.disable_dpp_power_gate = true,
+	.disable_hubp_power_gate = true,
+	.disable_clock_gate = true,
+	.disable_pplib_clock_request = true,
+	.disable_pplib_wm_range = true,
+	.disable_stutter = false,
+	.scl_reset_length10 = true,
+	.dwb_fi_phase = -1, // -1 = disable
+	.dmub_command_table = true,
+	.enable_tri_buf = true,
+	.use_max_lb = true
+};
+
+static void dcn31_dpp_destroy(struct dpp **dpp)
+{
+	kfree(TO_DCN20_DPP(*dpp));
+	*dpp = NULL;
+}
+
+static struct dpp *dcn31_dpp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn3_dpp *dpp =
+		kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
+
+	if (!dpp)
+		return NULL;
+
+	if (dpp3_construct(dpp, ctx, inst,
+			&dpp_regs[inst], &tf_shift, &tf_mask))
+		return &dpp->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(dpp);
+	return NULL;
+}
+
+static struct output_pixel_processor *dcn31_opp_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_opp *opp =
+		kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
+
+	if (!opp) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dcn20_opp_construct(opp, ctx, inst,
+			&opp_regs[inst], &opp_shift, &opp_mask);
+	return &opp->base;
+}
+
+static struct dce_aux *dcn31_aux_engine_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct aux_engine_dce110 *aux_engine =
+		kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
+
+	if (!aux_engine)
+		return NULL;
+
+	dce110_aux_engine_construct(aux_engine, ctx, inst,
+				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
+				    &aux_engine_regs[inst],
+					&aux_mask,
+					&aux_shift,
+					ctx->dc->caps.extended_aux_timeout_support);
+
+	return &aux_engine->base;
+}
+#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
+
+static const struct dce_i2c_registers i2c_hw_regs[] = {
+		i2c_inst_regs(1),
+		i2c_inst_regs(2),
+		i2c_inst_regs(3),
+		i2c_inst_regs(4),
+		i2c_inst_regs(5),
+};
+
+static const struct dce_i2c_shift i2c_shifts = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
+};
+
+static const struct dce_i2c_mask i2c_masks = {
+		I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
+};
+
+static struct dce_i2c_hw *dcn31_i2c_hw_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dce_i2c_hw *dce_i2c_hw =
+		kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
+
+	if (!dce_i2c_hw)
+		return NULL;
+
+	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
+				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
+
+	return dce_i2c_hw;
+}
+static struct mpc *dcn31_mpc_create(
+		struct dc_context *ctx,
+		int num_mpcc,
+		int num_rmu)
+{
+	struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
+					  GFP_KERNEL);
+
+	if (!mpc30)
+		return NULL;
+
+	dcn30_mpc_construct(mpc30, ctx,
+			&mpc_regs,
+			&mpc_shift,
+			&mpc_mask,
+			num_mpcc,
+			num_rmu);
+
+	return &mpc30->base;
+}
+
+static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
+{
+	int i;
+
+	struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
+					  GFP_KERNEL);
+
+	if (!hubbub3)
+		return NULL;
+
+	hubbub31_construct(hubbub3, ctx,
+			&hubbub_reg,
+			&hubbub_shift,
+			&hubbub_mask,
+			dcn3_1_ip.det_buffer_size_kbytes,
+			dcn3_1_ip.pixel_chunk_size_kbytes,
+			dcn3_1_ip.config_return_buffer_size_in_kbytes);
+
+
+	for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
+		struct dcn20_vmid *vmid = &hubbub3->vmid[i];
+
+		vmid->ctx = ctx;
+
+		vmid->regs = &vmid_regs[i];
+		vmid->shifts = &vmid_shifts;
+		vmid->masks = &vmid_masks;
+	}
+
+	return &hubbub3->base;
+}
+
+static struct timing_generator *dcn31_timing_generator_create(
+		struct dc_context *ctx,
+		uint32_t instance)
+{
+	struct optc *tgn10 =
+		kzalloc(sizeof(struct optc), GFP_KERNEL);
+
+	if (!tgn10)
+		return NULL;
+
+	tgn10->base.inst = instance;
+	tgn10->base.ctx = ctx;
+
+	tgn10->tg_regs = &optc_regs[instance];
+	tgn10->tg_shift = &optc_shift;
+	tgn10->tg_mask = &optc_mask;
+
+	dcn31_timing_generator_init(tgn10);
+
+	return &tgn10->base;
+}
+
+static const struct encoder_feature_support link_enc_feature = {
+		.max_hdmi_deep_color = COLOR_DEPTH_121212,
+		.max_hdmi_pixel_clock = 600000,
+		.hdmi_ycbcr420_supported = true,
+		.dp_ycbcr420_supported = true,
+		.fec_supported = true,
+		.flags.bits.IS_HBR2_CAPABLE = true,
+		.flags.bits.IS_HBR3_CAPABLE = true,
+		.flags.bits.IS_TPS3_CAPABLE = true,
+		.flags.bits.IS_TPS4_CAPABLE = true
+};
+
+static struct link_encoder *dcn31_link_encoder_create(
+	const struct encoder_init_data *enc_init_data)
+{
+	struct dcn20_link_encoder *enc20 =
+		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+
+	if (!enc20)
+		return NULL;
+
+	dcn31_link_encoder_construct(enc20,
+			enc_init_data,
+			&link_enc_feature,
+			&link_enc_regs[enc_init_data->transmitter],
+			&link_enc_aux_regs[enc_init_data->channel - 1],
+			&link_enc_hpd_regs[enc_init_data->hpd_source],
+			&le_shift,
+			&le_mask);
+
+	return &enc20->enc10.base;
+}
+
+/* Create a minimal link encoder object not associated with a particular
+ * physical connector.
+ * resource_funcs.link_enc_create_minimal
+ */
+static struct link_encoder *dcn31_link_enc_create_minimal(
+		struct dc_context *ctx, enum engine_id eng_id)
+{
+	struct dcn20_link_encoder *enc20;
+
+	if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
+		return NULL;
+
+	enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
+	if (!enc20)
+		return NULL;
+
+	dcn31_link_encoder_construct_minimal(
+			enc20,
+			ctx,
+			&link_enc_feature,
+			&link_enc_regs[eng_id - ENGINE_ID_DIGA],
+			eng_id);
+
+	return &enc20->enc10.base;
+}
+
+struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
+{
+	struct dcn31_panel_cntl *panel_cntl =
+		kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
+
+	if (!panel_cntl)
+		return NULL;
+
+	dcn31_panel_cntl_construct(panel_cntl, init_data);
+
+	return &panel_cntl->base;
+}
+
+static void read_dce_straps(
+	struct dc_context *ctx,
+	struct resource_straps *straps)
+{
+	generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
+		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
+
+}
+
+static struct audio *dcn31_create_audio(
+		struct dc_context *ctx, unsigned int inst)
+{
+	return dce_audio_create(ctx, inst,
+			&audio_regs[inst], &audio_shift, &audio_mask);
+}
+
+static struct vpg *dcn31_vpg_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
+
+	if (!vpg3)
+		return NULL;
+
+	vpg3_construct(vpg3, ctx, inst,
+			&vpg_regs[inst],
+			&vpg_shift,
+			&vpg_mask);
+
+	return &vpg3->base;
+}
+
+static struct afmt *dcn31_afmt_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
+
+	if (!afmt3)
+		return NULL;
+
+	afmt3_construct(afmt3, ctx, inst,
+			&afmt_regs[inst],
+			&afmt_shift,
+			&afmt_mask);
+
+	return &afmt3->base;
+}
+
+static struct stream_encoder *dcn31_stream_encoder_create(
+	enum engine_id eng_id,
+	struct dc_context *ctx)
+{
+	struct dcn10_stream_encoder *enc1;
+	struct vpg *vpg;
+	struct afmt *afmt;
+	int vpg_inst;
+	int afmt_inst;
+
+	/* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
+	if (eng_id <= ENGINE_ID_DIGF) {
+		vpg_inst = eng_id;
+		afmt_inst = eng_id;
+	} else
+		return NULL;
+
+	enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
+	vpg = dcn31_vpg_create(ctx, vpg_inst);
+	afmt = dcn31_afmt_create(ctx, afmt_inst);
+
+	if (!enc1 || !vpg || !afmt)
+		return NULL;
+
+	dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
+					eng_id, vpg, afmt,
+					&stream_enc_regs[eng_id],
+					&se_shift, &se_mask);
+
+	return &enc1->base;
+}
+
+static struct dce_hwseq *dcn31_hwseq_create(
+	struct dc_context *ctx)
+{
+	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
+
+	if (hws) {
+		hws->ctx = ctx;
+		hws->regs = &hwseq_reg;
+		hws->shifts = &hwseq_shift;
+		hws->masks = &hwseq_mask;
+	}
+	return hws;
+}
+static const struct resource_create_funcs res_create_funcs = {
+	.read_dce_straps = read_dce_straps,
+	.create_audio = dcn31_create_audio,
+	.create_stream_encoder = dcn31_stream_encoder_create,
+	.create_hwseq = dcn31_hwseq_create,
+};
+
+static const struct resource_create_funcs res_create_maximus_funcs = {
+	.read_dce_straps = NULL,
+	.create_audio = NULL,
+	.create_stream_encoder = NULL,
+	.create_hwseq = dcn31_hwseq_create,
+};
+
+static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
+{
+	unsigned int i;
+
+	for (i = 0; i < pool->base.stream_enc_count; i++) {
+		if (pool->base.stream_enc[i] != NULL) {
+			if (pool->base.stream_enc[i]->vpg != NULL) {
+				kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
+				pool->base.stream_enc[i]->vpg = NULL;
+			}
+			if (pool->base.stream_enc[i]->afmt != NULL) {
+				kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
+				pool->base.stream_enc[i]->afmt = NULL;
+			}
+			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
+			pool->base.stream_enc[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		if (pool->base.dscs[i] != NULL)
+			dcn20_dsc_destroy(&pool->base.dscs[i]);
+	}
+
+	if (pool->base.mpc != NULL) {
+		kfree(TO_DCN20_MPC(pool->base.mpc));
+		pool->base.mpc = NULL;
+	}
+	if (pool->base.hubbub != NULL) {
+		kfree(pool->base.hubbub);
+		pool->base.hubbub = NULL;
+	}
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		if (pool->base.dpps[i] != NULL)
+			dcn31_dpp_destroy(&pool->base.dpps[i]);
+
+		if (pool->base.ipps[i] != NULL)
+			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
+
+		if (pool->base.hubps[i] != NULL) {
+			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
+			pool->base.hubps[i] = NULL;
+		}
+
+		if (pool->base.irqs != NULL) {
+			dal_irq_service_destroy(&pool->base.irqs);
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		if (pool->base.engines[i] != NULL)
+			dce110_engine_destroy(&pool->base.engines[i]);
+		if (pool->base.hw_i2cs[i] != NULL) {
+			kfree(pool->base.hw_i2cs[i]);
+			pool->base.hw_i2cs[i] = NULL;
+		}
+		if (pool->base.sw_i2cs[i] != NULL) {
+			kfree(pool->base.sw_i2cs[i]);
+			pool->base.sw_i2cs[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		if (pool->base.opps[i] != NULL)
+			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.timing_generators[i] != NULL)	{
+			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
+			pool->base.timing_generators[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+		if (pool->base.dwbc[i] != NULL) {
+			kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
+			pool->base.dwbc[i] = NULL;
+		}
+		if (pool->base.mcif_wb[i] != NULL) {
+			kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
+			pool->base.mcif_wb[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.audio_count; i++) {
+		if (pool->base.audios[i])
+			dce_aud_destroy(&pool->base.audios[i]);
+	}
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] != NULL) {
+			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
+			pool->base.clock_sources[i] = NULL;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
+		if (pool->base.mpc_lut[i] != NULL) {
+			dc_3dlut_func_release(pool->base.mpc_lut[i]);
+			pool->base.mpc_lut[i] = NULL;
+		}
+		if (pool->base.mpc_shaper[i] != NULL) {
+			dc_transfer_func_release(pool->base.mpc_shaper[i]);
+			pool->base.mpc_shaper[i] = NULL;
+		}
+	}
+
+	if (pool->base.dp_clock_source != NULL) {
+		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
+		pool->base.dp_clock_source = NULL;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		if (pool->base.multiple_abms[i] != NULL)
+			dce_abm_destroy(&pool->base.multiple_abms[i]);
+	}
+
+	if (pool->base.psr != NULL)
+		dmub_psr_destroy(&pool->base.psr);
+
+	if (pool->base.dccg != NULL)
+		dcn_dccg_destroy(&pool->base.dccg);
+}
+
+static struct hubp *dcn31_hubp_create(
+	struct dc_context *ctx,
+	uint32_t inst)
+{
+	struct dcn20_hubp *hubp2 =
+		kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
+
+	if (!hubp2)
+		return NULL;
+
+	if (hubp31_construct(hubp2, ctx, inst,
+			&hubp_regs[inst], &hubp_shift, &hubp_mask))
+		return &hubp2->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(hubp2);
+	return NULL;
+}
+
+static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
+						    GFP_KERNEL);
+
+		if (!dwbc30) {
+			dm_error("DC: failed to create dwbc30!\n");
+			return false;
+		}
+
+		dcn30_dwbc_construct(dwbc30, ctx,
+				&dwbc30_regs[i],
+				&dwbc30_shift,
+				&dwbc30_mask,
+				i);
+
+		pool->dwbc[i] = &dwbc30->base;
+	}
+	return true;
+}
+
+static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+	int i;
+	uint32_t pipe_count = pool->res_cap->num_dwb;
+
+	for (i = 0; i < pipe_count; i++) {
+		struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
+						    GFP_KERNEL);
+
+		if (!mcif_wb30) {
+			dm_error("DC: failed to create mcif_wb30!\n");
+			return false;
+		}
+
+		dcn30_mmhubbub_construct(mcif_wb30, ctx,
+				&mcif_wb30_regs[i],
+				&mcif_wb30_shift,
+				&mcif_wb30_mask,
+				i);
+
+		pool->mcif_wb[i] = &mcif_wb30->base;
+	}
+	return true;
+}
+
+static struct display_stream_compressor *dcn31_dsc_create(
+	struct dc_context *ctx, uint32_t inst)
+{
+	struct dcn20_dsc *dsc =
+		kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
+
+	if (!dsc) {
+		BREAK_TO_DEBUGGER();
+		return NULL;
+	}
+
+	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
+	return &dsc->base;
+}
+
+static void dcn31_destroy_resource_pool(struct resource_pool **pool)
+{
+	struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
+
+	dcn31_resource_destruct(dcn31_pool);
+	kfree(dcn31_pool);
+	*pool = NULL;
+}
+
+static struct clock_source *dcn31_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static bool is_dual_plane(enum surface_pixel_format format)
+{
+	return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
+}
+
+static int dcn31_populate_dml_pipes_from_context(
+	struct dc *dc, struct dc_state *context,
+	display_e2e_pipe_params_st *pipes,
+	bool fast_validate)
+{
+	int i, pipe_cnt;
+	struct resource_context *res_ctx = &context->res_ctx;
+	struct pipe_ctx *pipe;
+
+	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
+
+	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
+		struct dc_crtc_timing *timing;
+
+		if (!res_ctx->pipe_ctx[i].stream)
+			continue;
+		pipe = &res_ctx->pipe_ctx[i];
+		timing = &pipe->stream->timing;
+
+		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
+		pipes[pipe_cnt].pipe.src.gpuvm = true;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
+		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
+		pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
+		pipes[pipe_cnt].pipe.src.dcc_rate = 3;
+		pipes[pipe_cnt].dout.dsc_input_bpc = 0;
+
+		if (pipes[pipe_cnt].dout.dsc_enable) {
+			switch (timing->display_color_depth) {
+			case COLOR_DEPTH_888:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 8;
+				break;
+			case COLOR_DEPTH_101010:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 10;
+				break;
+			case COLOR_DEPTH_121212:
+				pipes[pipe_cnt].dout.dsc_input_bpc = 12;
+				break;
+			default:
+				ASSERT(0);
+				break;
+			}
+		}
+
+		pipe_cnt++;
+	}
+	context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
+	dc->config.enable_4to1MPC = false;
+	if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
+		if (is_dual_plane(pipe->plane_state->format)
+				&& pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
+			dc->config.enable_4to1MPC = true;
+		} else if (!is_dual_plane(pipe->plane_state->format)) {
+			context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
+			pipes[0].pipe.src.unbounded_req_mode = true;
+		}
+	}
+
+	return pipe_cnt;
+}
+
+static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+{
+	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
+	}
+}
+
+static void dcn31_calculate_wm_and_dlg_fp(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	int i, pipe_idx;
+	double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
+
+	if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
+		dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
+
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
+#if 0 // TODO
+	/* Set B:
+	 * TODO
+	 */
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
+		if (vlevel == 0) {
+			pipes[0].clks_cfg.voltage = 1;
+			pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
+		}
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	pipes[0].clks_cfg.voltage = vlevel;
+	pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
+
+	/* Set C:
+	 * TODO
+	 */
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+
+	/* Set D:
+	 * TODO
+	 */
+	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
+	}
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+#endif
+
+	/* Set A:
+	 * All clocks min required
+	 *
+	 * Set A calculated last so that following calculations are based on Set A
+	 */
+	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
+	context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
+	/* TODO: remove: */
+	context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
+	context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
+	context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
+	/* end remove*/
+
+	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
+		if (!context->res_ctx.pipe_ctx[i].stream)
+			continue;
+
+		pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
+		pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
+
+		if (dc->config.forced_clocks) {
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
+		}
+		if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
+		if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
+			pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
+
+		pipe_idx++;
+	}
+
+	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
+}
+
+static void dcn31_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	DC_FP_START();
+	dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
+	DC_FP_END();
+}
+
+static struct dc_cap_funcs cap_funcs = {
+	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
+};
+
+static void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
+{
+	struct clk_limit_table *clk_table = &bw_params->clk_table;
+	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
+	unsigned int i, closest_clk_lvl;
+	int j;
+
+	// Default clock levels are used for diags, which may lead to overclocking.
+	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
+		int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
+
+		dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
+		dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
+		dcn3_1_soc.num_chans = bw_params->num_channels;
+
+		ASSERT(clk_table->num_entries);
+
+		/* Prepass to find max clocks independent of voltage level. */
+		for (i = 0; i < clk_table->num_entries; ++i) {
+			if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
+				max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
+			if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
+				max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
+		}
+
+		for (i = 0; i < clk_table->num_entries; i++) {
+			/* loop backwards*/
+			for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
+				if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
+					closest_clk_lvl = j;
+					break;
+				}
+			}
+
+			clock_limits[i].state = i;
+
+			/* Clocks dependent on voltage level. */
+			clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+			clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+			clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+			clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+
+			/* Clocks independent of voltage level. */
+			clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+				dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+
+			clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+				dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+
+			clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+			clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+			clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+			clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+			clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+		}
+		for (i = 0; i < clk_table->num_entries; i++)
+			dcn3_1_soc.clock_limits[i] = clock_limits[i];
+		if (clk_table->num_entries) {
+			dcn3_1_soc.num_states = clk_table->num_entries;
+		}
+	}
+
+	dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
+
+	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+		dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
+	else
+		dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
+}
+
+static struct resource_funcs dcn31_res_pool_funcs = {
+	.destroy = dcn31_destroy_resource_pool,
+	.link_enc_create = dcn31_link_encoder_create,
+	.link_enc_create_minimal = dcn31_link_enc_create_minimal,
+	.link_encs_assign = link_enc_cfg_link_encs_assign,
+	.link_enc_unassign = link_enc_cfg_link_enc_unassign,
+	.panel_cntl_create = dcn31_panel_cntl_create,
+	.validate_bandwidth = dcn30_validate_bandwidth,
+	.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
+	.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
+	.populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
+	.acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
+	.add_stream_to_ctx = dcn30_add_stream_to_ctx,
+	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
+	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
+	.populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
+	.set_mcif_arb_params = dcn30_set_mcif_arb_params,
+	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
+	.acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
+	.release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
+	.update_bw_bounding_box = dcn31_update_bw_bounding_box,
+	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
+};
+
+static struct clock_source *dcn30_clock_source_create(
+		struct dc_context *ctx,
+		struct dc_bios *bios,
+		enum clock_source_id id,
+		const struct dce110_clk_src_regs *regs,
+		bool dp_clk_src)
+{
+	struct dce110_clk_src *clk_src =
+		kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
+
+	if (!clk_src)
+		return NULL;
+
+	if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+			regs, &cs_shift, &cs_mask)) {
+		clk_src->base.dp_clk_src = dp_clk_src;
+		return &clk_src->base;
+	}
+
+	BREAK_TO_DEBUGGER();
+	return NULL;
+}
+
+static bool dcn31_resource_construct(
+	uint8_t num_virtual_links,
+	struct dc *dc,
+	struct dcn31_resource_pool *pool)
+{
+	int i;
+	struct dc_context *ctx = dc->ctx;
+	struct irq_service_init_data init_data;
+
+	DC_FP_START();
+
+	ctx->dc_bios->regs = &bios_regs;
+
+	pool->base.res_cap = &res_cap_dcn31;
+
+	pool->base.funcs = &dcn31_res_pool_funcs;
+
+	/*************************************************
+	 *  Resource + asic cap harcoding                *
+	 *************************************************/
+	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
+	dc->caps.max_downscale_ratio = 600;
+	dc->caps.i2c_speed_in_khz = 100;
+	dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
+	dc->caps.max_cursor_size = 256;
+	dc->caps.min_horizontal_blanking_period = 80;
+	dc->caps.dmdata_alloc_size = 2048;
+
+	dc->caps.max_slave_planes = 1;
+	dc->caps.max_slave_yuv_planes = 1;
+	dc->caps.max_slave_rgb_planes = 1;
+	dc->caps.post_blend_color_processing = true;
+	dc->caps.force_dp_tps4_for_cp2520 = true;
+	dc->caps.extended_aux_timeout_support = true;
+	dc->caps.dmcub_support = true;
+	dc->caps.is_apu = true;
+
+	/* Color pipeline capabilities */
+	dc->caps.color.dpp.dcn_arch = 1;
+	dc->caps.color.dpp.input_lut_shared = 0;
+	dc->caps.color.dpp.icsc = 1;
+	dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
+	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
+	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
+	dc->caps.color.dpp.dgam_rom_caps.pq = 1;
+	dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
+	dc->caps.color.dpp.post_csc = 1;
+	dc->caps.color.dpp.gamma_corr = 1;
+	dc->caps.color.dpp.dgam_rom_for_yuv = 0;
+
+	dc->caps.color.dpp.hw_3d_lut = 1;
+	dc->caps.color.dpp.ogam_ram = 1;
+	// no OGAM ROM on DCN301
+	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
+	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
+	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
+	dc->caps.color.dpp.ocsc = 0;
+
+	dc->caps.color.mpc.gamut_remap = 1;
+	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.ogam_ram = 1;
+	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
+	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
+	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
+	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
+	dc->caps.color.mpc.ocsc = 1;
+
+	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
+		dc->debug = debug_defaults_drv;
+	else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
+		dc->debug = debug_defaults_diags;
+	} else
+		dc->debug = debug_defaults_diags;
+	// Init the vm_helper
+	if (dc->vm_helper)
+		vm_helper_init(dc->vm_helper, 16);
+
+	/*************************************************
+	 *  Create resources                             *
+	 *************************************************/
+
+	/* Clock Sources for Pixel Clock*/
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL0,
+				&clk_src_regs[0], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL1,
+				&clk_src_regs[1], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL2,
+				&clk_src_regs[2], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL3,
+				&clk_src_regs[3], false);
+	pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
+			dcn30_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_COMBO_PHY_PLL4,
+				&clk_src_regs[4], false);
+
+	pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
+
+	/* todo: not reuse phy_pll registers */
+	pool->base.dp_clock_source =
+			dcn31_clock_source_create(ctx, ctx->dc_bios,
+				CLOCK_SOURCE_ID_DP_DTO,
+				&clk_src_regs[0], true);
+
+	for (i = 0; i < pool->base.clk_src_count; i++) {
+		if (pool->base.clock_sources[i] == NULL) {
+			dm_error("DC: failed to create clock sources!\n");
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* TODO: DCCG */
+	pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
+	if (pool->base.dccg == NULL) {
+		dm_error("DC: failed to create dccg!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* TODO: IRQ */
+	init_data.ctx = dc->ctx;
+	pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
+	if (!pool->base.irqs)
+		goto create_fail;
+
+	/* HUBBUB */
+	pool->base.hubbub = dcn31_hubbub_create(ctx);
+	if (pool->base.hubbub == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create hubbub!\n");
+		goto create_fail;
+	}
+
+	/* HUBPs, DPPs, OPPs and TGs */
+	for (i = 0; i < pool->base.pipe_count; i++) {
+		pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
+		if (pool->base.hubps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create hubps!\n");
+			goto create_fail;
+		}
+
+		pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
+		if (pool->base.dpps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create dpps!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
+		pool->base.opps[i] = dcn31_opp_create(ctx, i);
+		if (pool->base.opps[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC: failed to create output pixel processor!\n");
+			goto create_fail;
+		}
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		pool->base.timing_generators[i] = dcn31_timing_generator_create(
+				ctx, i);
+		if (pool->base.timing_generators[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create tg!\n");
+			goto create_fail;
+		}
+	}
+	pool->base.timing_generator_count = i;
+
+	/* PSR */
+	pool->base.psr = dmub_psr_create(ctx);
+	if (pool->base.psr == NULL) {
+		dm_error("DC: failed to create psr obj!\n");
+		BREAK_TO_DEBUGGER();
+		goto create_fail;
+	}
+
+	/* ABM */
+	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
+		pool->base.multiple_abms[i] = dmub_abm_create(ctx,
+				&abm_regs[i],
+				&abm_shift,
+				&abm_mask);
+		if (pool->base.multiple_abms[i] == NULL) {
+			dm_error("DC: failed to create abm for pipe %d!\n", i);
+			BREAK_TO_DEBUGGER();
+			goto create_fail;
+		}
+	}
+
+	/* MPC and DSC */
+	pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
+	if (pool->base.mpc == NULL) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mpc!\n");
+		goto create_fail;
+	}
+
+	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
+		pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
+		if (pool->base.dscs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error("DC: failed to create display stream compressor %d!\n", i);
+			goto create_fail;
+		}
+	}
+
+	/* DWB and MMHUBBUB */
+	if (!dcn31_dwbc_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create dwbc!\n");
+		goto create_fail;
+	}
+
+	if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
+		BREAK_TO_DEBUGGER();
+		dm_error("DC: failed to create mcif_wb!\n");
+		goto create_fail;
+	}
+
+	/* AUX and I2C */
+	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
+		pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
+		if (pool->base.engines[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create aux engine!!\n");
+			goto create_fail;
+		}
+		pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
+		if (pool->base.hw_i2cs[i] == NULL) {
+			BREAK_TO_DEBUGGER();
+			dm_error(
+				"DC:failed to create hw i2c!!\n");
+			goto create_fail;
+		}
+		pool->base.sw_i2cs[i] = NULL;
+	}
+
+	/* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
+	if (!resource_construct(num_virtual_links, dc, &pool->base,
+			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
+			&res_create_funcs : &res_create_maximus_funcs)))
+			goto create_fail;
+
+	/* HW Sequencer and Plane caps */
+	dcn31_hw_sequencer_construct(dc);
+
+	dc->caps.max_planes =  pool->base.pipe_count;
+
+	for (i = 0; i < dc->caps.max_planes; ++i)
+		dc->caps.planes[i] = plane_cap;
+
+	dc->cap_funcs = cap_funcs;
+
+	DC_FP_END();
+
+	return true;
+
+create_fail:
+
+	DC_FP_END();
+	dcn31_resource_destruct(pool);
+
+	return false;
+}
+
+struct resource_pool *dcn31_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc)
+{
+	struct dcn31_resource_pool *pool =
+		kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
+
+	if (!pool)
+		return NULL;
+
+	if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
+		return &pool->base;
+
+	BREAK_TO_DEBUGGER();
+	kfree(pool);
+	return NULL;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
new file mode 100644
index 000000000000..93571c976996
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DCN31_RESOURCE_H_
+#define _DCN31_RESOURCE_H_
+
+#include "core_types.h"
+
+#define TO_DCN31_RES_POOL(pool)\
+	container_of(pool, struct dcn31_resource_pool, base)
+
+struct dcn31_resource_pool {
+	struct resource_pool base;
+};
+
+struct resource_pool *dcn31_create_resource_pool(
+		const struct dc_init_data *init_data,
+		struct dc *dc);
+
+#endif /* _DCN31_RESOURCE_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
index cac0b2c0d31b..8381c8f9ddb7 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_cp_psp.h
@@ -32,6 +32,11 @@ struct cp_psp_stream_config {
 	uint8_t otg_inst;
 	uint8_t dig_be;
 	uint8_t dig_fe;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	uint8_t link_enc_idx;
+	uint8_t stream_enc_idx;
+	uint8_t phy_idx;
+#endif
 	uint8_t assr_enabled;
 	uint8_t mst_enabled;
 	void *dm_stream_ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
index 304d50d16d01..9ab854293ace 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h
@@ -162,6 +162,12 @@ void dm_set_dcn_clocks(
 
 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable);
 
+void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us);
+
+// 0x1 = Result_OK, 0xFE = Result_UnkmownCmd
+#define IS_SMU_TIMEOUT(result) \
+	(!(result == 0x1 || result == 0xFE))
+
 int dm_helper_dmub_aux_transfer_sync(
 		struct dc_context *ctx,
 		const struct dc_link *link,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 6bb7f2905821..11ab03abc0fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -62,6 +62,10 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
 CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) -Wframe-larger-than=2048
+CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
+endif
 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_rcflags)
@@ -72,6 +76,10 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
+CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
+endif
 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
 endif
 CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
@@ -86,6 +94,9 @@ DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_
 DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
 DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
 DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
+endif
 endif
 
 AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index ec56210b6180..9d2016d8fafe 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -64,6 +64,7 @@ typedef struct {
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0xffffffff
 #define DCN30_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN30_MAX_FMT_420_BUFFER_WIDTH 4096
 
 static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
 static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -2052,7 +2053,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			v->DISPCLKWithoutRamping,
 			v->DISPCLKDPPCLKVCOSpeed);
 	v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
-			v->soc.clock_limits[mode_lib->soc.num_states].dispclk_mhz,
+			v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz,
 			v->DISPCLKDPPCLKVCOSpeed);
 	if (v->DISPCLKWithoutRampingRoundedToDFSGranularity
 			> v->MaxDispclkRoundedToDFSGranularity) {
@@ -3957,20 +3958,20 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
 				v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
 						* (1.0 + v->DISPCLKRampingMargin / 100.0);
-				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]
-						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {
+				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
 					v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 				}
 				v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
 						* (1 + v->DISPCLKRampingMargin / 100.0);
-				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]
-						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {
+				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
 					v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 				}
 				v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
 						* (1 + v->DISPCLKRampingMargin / 100.0);
-				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states]
-						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states])) {
+				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) {
 					v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
 				}
 
@@ -3987,19 +3988,30 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 				} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
 					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
 					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
-				} else if (v->DSCEnabled[k] && (v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH)) {
-					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
-					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
 				} else {
 					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
 					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
-					/*420 format workaround*/
-					if (v->HActive[k] > 4096 && v->OutputFormat[k] == dm_420) {
+				}
+				if (v->DSCEnabled[k] && v->HActive[k] > DCN30_MAX_DSC_IMAGE_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN30_MAX_DSC_IMAGE_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN30_MAX_FMT_420_BUFFER_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN30_MAX_FMT_420_BUFFER_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
 						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
 						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
 					}
 				}
-
 				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
 					v->MPCCombine[i][j][k] = false;
 					v->NoOfDPP[i][j][k] = 4;
@@ -4281,42 +4293,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		}
 	}
 
-	for (i = 0; i < v->soc.num_states; i++) {
-		v->DSCCLKRequiredMoreThanSupported[i] = false;
-		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-			if (v->BlendingAndTiming[k] == k) {
-				if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
-					if (v->OutputFormat[k] == dm_420) {
-						v->DSCFormatFactor = 2;
-					} else if (v->OutputFormat[k] == dm_444) {
-						v->DSCFormatFactor = 1;
-					} else if (v->OutputFormat[k] == dm_n422) {
-						v->DSCFormatFactor = 2;
-					} else {
-						v->DSCFormatFactor = 1;
-					}
-					if (v->RequiresDSC[i][k] == true) {
-						if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
-							if (v->PixelClockBackEnd[k] / 12.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
-							if (v->PixelClockBackEnd[k] / 6.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						} else {
-							if (v->PixelClockBackEnd[k] / 3.0 / v->DSCFormatFactor
-									> (1.0 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) * v->MaxDSCCLK[i]) {
-								v->DSCCLKRequiredMoreThanSupported[i] = true;
-							}
-						}
-					}
-				}
-			}
-		}
-	}
+	/* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
+
 	for (i = 0; i < v->soc.num_states; i++) {
 		v->NotEnoughDSCUnits[i] = false;
 		v->TotalDSCUnitsRequired = 0.0;
@@ -5319,7 +5297,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		for (j = 0; j < 2; j++) {
 			if (v->ScaleRatioAndTapsSupport == 1 && v->SourceFormatPixelAndScanSupport == 1 && v->ViewportSizeSupport[i][j] == 1
 					&& v->DIOSupport[i] == 1 && v->ODMCombine4To1SupportCheckOK[i] == 1
-					&& v->NotEnoughDSCUnits[i] == 0 && v->DSCCLKRequiredMoreThanSupported[i] == 0
+					&& v->NotEnoughDSCUnits[i] == 0
 					&& v->DTBCLKRequiredMoreThanSupported[i] == 0
 					&& v->ROBSupport[i][j] == 1 && v->DISPCLK_DPPCLK_Support[i][j] == 1 && v->TotalAvailablePipesSupport[i][j] == 1
 					&& EnoughWritebackUnits == 1 && WritebackModeSupport == 1
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
new file mode 100644
index 000000000000..d655655baaba
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -0,0 +1,7508 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+#include "dc.h"
+#include "dc_link.h"
+#include "../display_mode_lib.h"
+#include "display_mode_vba_31.h"
+#include "../dml_inline_defs.h"
+
+/*
+ * NOTE:
+ *   This file is gcc-parsable HW gospel, coming straight from HW engineers.
+ *
+ * It doesn't adhere to Linux kernel style and sometimes will do things in odd
+ * ways. Unless there is something clearly wrong with it the code should
+ * remain as-is as it provides us with a guarantee from HW that it is correct.
+ */
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
+#define DCN31_MAX_DSC_IMAGE_WIDTH 5184
+#define DCN31_MAX_FMT_420_BUFFER_WIDTH 4096
+
+// For DML-C changes that hasn't been propagated to VBA yet
+//#define __DML_VBA_ALLOW_DELTA__
+
+// Move these to ip paramaters/constant
+
+// At which vstartup the DML start to try if the mode can be supported
+#define __DML_VBA_MIN_VSTARTUP__    9
+
+// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
+#define __DML_ARB_TO_RET_DELAY__    (7 + 95)
+
+// fudge factor for min dcfclk calclation
+#define __DML_MIN_DCFCLK_FACTOR__   1.15
+
+typedef struct {
+	double DPPCLK;
+	double DISPCLK;
+	double PixelClock;
+	double DCFCLKDeepSleep;
+	unsigned int DPPPerPlane;
+	bool ScalerEnabled;
+	enum scan_direction_class SourceScan;
+	unsigned int BlockWidth256BytesY;
+	unsigned int BlockHeight256BytesY;
+	unsigned int BlockWidth256BytesC;
+	unsigned int BlockHeight256BytesC;
+	unsigned int InterlaceEnable;
+	unsigned int NumberOfCursors;
+	unsigned int VBlank;
+	unsigned int HTotal;
+	unsigned int DCCEnable;
+	bool ODMCombineIsEnabled;
+	enum source_format_class SourcePixelFormat;
+	int BytePerPixelY;
+	int BytePerPixelC;
+	bool ProgressiveToInterlaceUnitInOPP;
+} Pipe;
+
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0xffffffff
+
+static bool CalculateBytePerPixelAnd256BBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double *BytePerPixelDETY,
+		double *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC);
+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib);
+static unsigned int dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output);
+static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output);
+static bool CalculatePrefetchSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		Pipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		double VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		double VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		double *DSTXAfterScaler,
+		double *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix);
+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
+static void CalculateDCCConfiguration(
+		bool DCCEnabled,
+		bool DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceWidthLuma,
+		unsigned int SurfaceWidthChroma,
+		unsigned int SurfaceHeightLuma,
+		unsigned int SurfaceHeightChroma,
+		double DETBufferSize,
+		unsigned int RequestHeight256ByteLuma,
+		unsigned int RequestHeight256ByteChroma,
+		enum dm_swizzle_mode TilingFormat,
+		unsigned int BytePerPixelY,
+		unsigned int BytePerPixelC,
+		double BytePerPixelDETY,
+		double BytePerPixelDETC,
+		enum scan_direction_class ScanOrientation,
+		unsigned int *MaxUncompressedBlockLuma,
+		unsigned int *MaxUncompressedBlockChroma,
+		unsigned int *MaxCompressedBlockLuma,
+		unsigned int *MaxCompressedBlockChroma,
+		unsigned int *IndependentBlockLuma,
+		unsigned int *IndependentBlockChroma);
+static double CalculatePrefetchSourceLines(
+		struct display_mode_lib *mode_lib,
+		double VRatio,
+		double vtaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		unsigned int ViewportYStart,
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath);
+static unsigned int CalculateVMAndRowBytes(
+		struct display_mode_lib *mode_lib,
+		bool DCCEnable,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum scan_direction_class ScanDirection,
+		unsigned int SwathWidth,
+		unsigned int ViewportHeight,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMinPageSize,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int *MacroTileWidth,
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		bool *PTEBufferSizeNotExceeded,
+		int *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		int *vm_group_bytes,
+		unsigned int *dpte_group_bytes,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		int *DPDE0BytesFrame,
+		int *MetaPTEBytesFrame);
+static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime);
+static void CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		double *meta_row_bw,
+		double *dpte_row_bw);
+
+static void CalculateFlipSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe);
+static double CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		int WritebackDestinationWidth,
+		int WritebackDestinationHeight,
+		int WritebackSourceHeight,
+		unsigned int HTotal);
+
+static void CalculateVupdateAndDynamicMetadataParameters(
+		int MaxInterDCNTileRepeaters,
+		double DPPCLK,
+		double DISPCLK,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		int HTotal,
+		int VBlank,
+		int DynamicMetadataTransmittedBytes,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix);
+
+static void CalculateWatermarksAndDRAMSpeedChangeSupport(
+		struct display_mode_lib *mode_lib,
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActivePlanes,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizedVBlank,
+		unsigned int dpte_group_bytes[],
+		unsigned int MetaChunkSize,
+		double UrgentLatency,
+		double ExtraLatency,
+		double WritebackLatency,
+		double WritebackChunkSize,
+		double SOCCLK,
+		double DRAMClockChangeLatency,
+		double SRExitTime,
+		double SREnterPlusExitTime,
+		double SRExitZ8Time,
+		double SREnterPlusExitZ8Time,
+		double DCFCLKDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int vtaps[],
+		unsigned int VTAPsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerPlane[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		int unsigned CompressedBufferSizeInkByte,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double *UrgentWatermark,
+		double *WritebackUrgentWatermark,
+		double *DRAMClockChangeWatermark,
+		double *WritebackDRAMClockChangeWatermark,
+		double *StutterExitWatermark,
+		double *StutterEnterPlusExitWatermark,
+		double *Z8StutterExitWatermark,
+		double *Z8StutterEnterPlusExitWatermark,
+		double *MinActiveDRAMClockChangeLatencySupported);
+
+static void CalculateDCFCLKDeepSleep(
+		struct display_mode_lib *mode_lib,
+		unsigned int NumberOfActivePlanes,
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		int ReturnBusWidth,
+		double *DCFCLKDeepSleep);
+
+static void CalculateUrgentBurstFactor(
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double LineTime,
+		double UrgentLatency,
+		double CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double VRatio,
+		double VRatioC,
+		double BytePerPixelInDETY,
+		double BytePerPixelInDETC,
+		double DETBufferSizeY,
+		double DETBufferSizeC,
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool *NotEnoughUrgentLatencyHiding);
+
+static void UseMinimumDCFCLK(
+		struct display_mode_lib *mode_lib,
+		int MaxInterDCNTileRepeaters,
+		int MaxPrefetchMode,
+		double FinalDRAMClockChangeLatency,
+		double SREnterPlusExitTime,
+		int ReturnBusWidth,
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		int PixelChunkSizeInKByte,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		enum immediate_flip_requirement ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+		int VTotal[],
+		int VActive[],
+		int DynamicMetadataTransmittedBytes[],
+		int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFCLKDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		double TotalVActivePixelBandwidth[][2],
+		double TotalVActiveCursorBandwidth[][2],
+		double TotalMetaRowBandwidth[][2],
+		double TotalDPTERowBandwidth[][2],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
+		double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		double DCFCLKState[][2]);
+
+static void CalculatePixelDeliveryTimes(
+		unsigned int NumberOfActivePlanes,
+		double VRatio[],
+		double VRatioChroma[],
+		double VRatioPrefetchY[],
+		double VRatioPrefetchC[],
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		unsigned int NumberOfCursors[],
+		unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int BlockWidth256BytesY[],
+		unsigned int BlockHeight256BytesY[],
+		unsigned int BlockWidth256BytesC[],
+		unsigned int BlockHeight256BytesC[],
+		double DisplayPipeLineDeliveryTimeLuma[],
+		double DisplayPipeLineDeliveryTimeChroma[],
+		double DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeLuma[],
+		double DisplayPipeRequestDeliveryTimeChroma[],
+		double DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double CursorRequestDeliveryTime[],
+		double CursorRequestDeliveryTimePrefetch[]);
+
+static void CalculateMetaAndPTETimes(
+		int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		int MetaChunkSize,
+		int MinMetaChunkSizeBytes,
+		int HTotal[],
+		double VRatio[],
+		double VRatioChroma[],
+		double DestinationLinesToRequestRowInVBlank[],
+		double DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		int dpte_row_height[],
+		int dpte_row_height_chroma[],
+		int meta_row_width[],
+		int meta_row_width_chroma[],
+		int meta_row_height[],
+		int meta_row_height_chroma[],
+		int meta_req_width[],
+		int meta_req_width_chroma[],
+		int meta_req_height[],
+		int meta_req_height_chroma[],
+		int dpte_group_bytes[],
+		int PTERequestSizeY[],
+		int PTERequestSizeC[],
+		int PixelPTEReqWidthY[],
+		int PixelPTEReqHeightY[],
+		int PixelPTEReqWidthC[],
+		int PixelPTEReqHeightC[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[]);
+
+static void CalculateVMGroupAndRequestTimes(
+		unsigned int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int HTotal[],
+		int BytePerPixelC[],
+		double DestinationLinesToRequestVMInVBlank[],
+		double DestinationLinesToRequestVMInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		int vm_group_bytes[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		int meta_pte_bytes_per_frame_ub_l[],
+		int meta_pte_bytes_per_frame_ub_c[],
+		double TimePerVMGroupVBlank[],
+		double TimePerVMGroupFlip[],
+		double TimePerVMRequestVBlank[],
+		double TimePerVMRequestFlip[]);
+
+static void CalculateStutterEfficiency(
+		struct display_mode_lib *mode_lib,
+		int CompressedBufferSizeInkByte,
+		bool UnboundedRequestEnabled,
+		int ConfigReturnBufferSizeInKByte,
+		int MetaFIFOSizeInKEntries,
+		int ZeroSizeBufferEntries,
+		int NumberOfActivePlanes,
+		int ROBBufferSizeInKByte,
+		double TotalDataReadBandwidth,
+		double DCFCLK,
+		double ReturnBW,
+		double COMPBUF_RESERVED_SPACE_64B,
+		double COMPBUF_RESERVED_SPACE_ZS,
+		double SRExitTime,
+		double SRExitZ8Time,
+		bool SynchronizedVBlank,
+		double Z8StutterEnterPlusExitWatermark,
+		double StutterEnterPlusExitWatermark,
+		bool ProgressiveToInterlaceUnitInOPP,
+		bool Interlace[],
+		double MinTTUVBlank[],
+		int DPPPerPlane[],
+		unsigned int DETBufferSizeY[],
+		int BytePerPixelY[],
+		double BytePerPixelDETY[],
+		double SwathWidthY[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		double NetDCCRateLuma[],
+		double NetDCCRateChroma[],
+		double DCCFractionOfZeroSizeRequestsLuma[],
+		double DCCFractionOfZeroSizeRequestsChroma[],
+		int HTotal[],
+		int VTotal[],
+		double PixelClock[],
+		double VRatio[],
+		enum scan_direction_class SourceScan[],
+		int BlockHeight256BytesY[],
+		int BlockWidth256BytesY[],
+		int BlockHeight256BytesC[],
+		int BlockWidth256BytesC[],
+		int DCCYMaxUncompressedBlock[],
+		int DCCCMaxUncompressedBlock[],
+		int VActive[],
+		bool DCCEnable[],
+		bool WritebackEnable[],
+		double ReadBandwidthPlaneLuma[],
+		double ReadBandwidthPlaneChroma[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double *StutterEfficiencyNotIncludingVBlank,
+		double *StutterEfficiency,
+		int *NumberOfStutterBurstsPerFrame,
+		double *Z8StutterEfficiencyNotIncludingVBlank,
+		double *Z8StutterEfficiency,
+		int *Z8NumberOfStutterBurstsPerFrame,
+		double *StutterPeriod);
+
+static void CalculateSwathAndDETConfiguration(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		unsigned int DETBufferSizeInKByte,
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum scan_direction_class SourceScan[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BlendingAndTiming[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		int DPPPerPlane[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool ViewportSizeSupportPerPlane[],
+		bool *ViewportSizeSupport);
+static void CalculateSwathWidth(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		enum source_format_class SourcePixelFormat[],
+		enum scan_direction_class SourceScan[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		int BlendingAndTiming[],
+		int HActive[],
+		double HRatio[],
+		int DPPPerPlane[],
+		double SwathWidthSingleDPPY[],
+		double SwathWidthSingleDPPC[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		int MaximumSwathHeightY[],
+		int MaximumSwathHeightC[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[]);
+
+static double CalculateExtraLatency(
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		double DCFCLK,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels);
+
+static double CalculateExtraLatencyBytes(
+		int ReorderingBytes,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels);
+
+static double CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClockSingle);
+
+static void CalculateUnboundedRequestAndCompressedBufferSize(
+		unsigned int DETBufferSizeInKByte,
+		int ConfigReturnBufferSizeInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		int TotalActiveDPP,
+		bool NoChromaPlanes,
+		int MaxNumDPP,
+		int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class *Output,
+		bool *UnboundedRequestEnabled,
+		int *CompressedBufferSizeInkByte);
+
+static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output);
+
+void dml31_recalculate(struct display_mode_lib *mode_lib)
+{
+	ModeSupportAndSystemConfiguration(mode_lib);
+	PixelClockAdjustmentForProgressiveToInterlaceUnit(mode_lib);
+	DisplayPipeConfiguration(mode_lib);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Calling DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation\n", __func__);
+#endif
+	DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(mode_lib);
+}
+
+static unsigned int dscceComputeDelay(
+		unsigned int bpc,
+		double BPP,
+		unsigned int sliceWidth,
+		unsigned int numSlices,
+		enum output_format_class pixelFormat,
+		enum output_encoder_class Output)
+{
+	// valid bpc         = source bits per component in the set of {8, 10, 12}
+	// valid bpp         = increments of 1/16 of a bit
+	//                    min = 6/7/8 in N420/N422/444, respectively
+	//                    max = such that compression is 1:1
+	//valid sliceWidth  = number of pixels per slice line, must be less than or equal to 5184/numSlices (or 4096/numSlices in 420 mode)
+	//valid numSlices   = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4}
+	//valid pixelFormat = pixel/color format in the set of {:N444_RGB, :S422, :N422, :N420}
+
+	// fixed value
+	unsigned int rcModelSize = 8192;
+
+	// N422/N420 operate at 2 pixels per clock
+	unsigned int pixelsPerClock = 0, lstall, D, initalXmitDelay, w, s, ix, wx, P, l0, a, ax, L, Delay, pixels;
+
+	if (pixelFormat == dm_420)
+		pixelsPerClock = 2;
+	else if (pixelFormat == dm_444)
+		pixelsPerClock = 1;
+	else if (pixelFormat == dm_n422)
+		pixelsPerClock = 2;
+	// #all other modes operate at 1 pixel per clock
+	else
+		pixelsPerClock = 1;
+
+	//initial transmit delay as per PPS
+	initalXmitDelay = dml_round(rcModelSize / 2.0 / BPP / pixelsPerClock);
+
+	//compute ssm delay
+	if (bpc == 8)
+		D = 81;
+	else if (bpc == 10)
+		D = 89;
+	else
+		D = 113;
+
+	//divide by pixel per cycle to compute slice width as seen by DSC
+	w = sliceWidth / pixelsPerClock;
+
+	//422 mode has an additional cycle of delay
+	if (pixelFormat == dm_420 || pixelFormat == dm_444 || pixelFormat == dm_n422)
+		s = 0;
+	else
+		s = 1;
+
+	//main calculation for the dscce
+	ix = initalXmitDelay + 45;
+	wx = (w + 2) / 3;
+	P = 3 * wx - w;
+	l0 = ix / w;
+	a = ix + P * l0;
+	ax = (a + 2) / 3 + D + 6 + 1;
+	L = (ax + wx - 1) / wx;
+	if ((ix % w) == 0 && P != 0)
+		lstall = 1;
+	else
+		lstall = 0;
+	Delay = L * wx * (numSlices - 1) + ax + s + lstall + 22;
+
+	//dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels
+	pixels = Delay * 3 * pixelsPerClock;
+	return pixels;
+}
+
+static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum output_encoder_class Output)
+{
+	unsigned int Delay = 0;
+
+	if (pixelFormat == dm_420) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 2;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 13;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc gets pixels every other cycle
+		Delay = Delay + 3;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else if (pixelFormat == dm_n422) {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 1;
+		//   dscc - input deserializer
+		Delay = Delay + 5;
+		//  dscc - input cdc fifo
+		Delay = Delay + 25;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 10;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   sft
+		Delay = Delay + 1;
+	} else {
+		//   sfr
+		Delay = Delay + 2;
+		//   dsccif
+		Delay = Delay + 0;
+		//   dscc - input deserializer
+		Delay = Delay + 3;
+		//   dscc - input cdc fifo
+		Delay = Delay + 12;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   dscc - output cdc fifo
+		Delay = Delay + 7;
+		//   dscc - output serializer
+		Delay = Delay + 1;
+		//   dscc - cdc uncertainty
+		Delay = Delay + 2;
+		//   sft
+		Delay = Delay + 1;
+	}
+
+	return Delay;
+}
+
+static bool CalculatePrefetchSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		Pipe *myPipe,
+		unsigned int DSCDelay,
+		double DPPCLKDelaySubtotalPlusCNVCFormater,
+		double DPPCLKDelaySCL,
+		double DPPCLKDelaySCLLBOnly,
+		double DPPCLKDelayCNVCCursor,
+		double DISPCLKDelaySubtotal,
+		unsigned int DPP_RECOUT_WIDTH,
+		enum output_format_class OutputFormat,
+		unsigned int MaxInterDCNTileRepeaters,
+		unsigned int VStartup,
+		unsigned int MaxVStartup,
+		unsigned int GPUVMPageTableLevels,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		double HostVMMinPageSize,
+		bool DynamicMetadataEnable,
+		bool DynamicMetadataVMEnabled,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		unsigned int DynamicMetadataTransmittedBytes,
+		double UrgentLatency,
+		double UrgentExtraLatency,
+		double TCalc,
+		unsigned int PDEAndMetaPTEBytesFrame,
+		unsigned int MetaRowByte,
+		unsigned int PixelPTEBytesPerRow,
+		double PrefetchSourceLinesY,
+		unsigned int SwathWidthY,
+		double VInitPreFillY,
+		unsigned int MaxNumSwathY,
+		double PrefetchSourceLinesC,
+		unsigned int SwathWidthC,
+		double VInitPreFillC,
+		unsigned int MaxNumSwathC,
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double TWait,
+		double *DSTXAfterScaler,
+		double *DSTYAfterScaler,
+		double *DestinationLinesForPrefetch,
+		double *PrefetchBandwidth,
+		double *DestinationLinesToRequestVMInVBlank,
+		double *DestinationLinesToRequestRowInVBlank,
+		double *VRatioPrefetchY,
+		double *VRatioPrefetchC,
+		double *RequiredPrefetchPixDataBWLuma,
+		double *RequiredPrefetchPixDataBWChroma,
+		bool *NotEnoughTimeForDynamicMetadata,
+		double *Tno_bw,
+		double *prefetch_vmrow_bw,
+		double *Tdmdl_vm,
+		double *Tdmdl,
+		double *TSetup,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix)
+{
+	bool MyError = false;
+	unsigned int DPPCycles, DISPCLKCycles;
+	double DSTTotalPixelsAfterScaler;
+	double LineTime;
+	double dst_y_prefetch_equ;
+	double Tsw_oto;
+	double prefetch_bw_oto;
+	double Tvm_oto;
+	double Tr0_oto;
+	double Tvm_oto_lines;
+	double Tr0_oto_lines;
+	double dst_y_prefetch_oto;
+	double TimeForFetchingMetaPTE = 0;
+	double TimeForFetchingRowInVBlank = 0;
+	double LinesToRequestPrefetchPixelData = 0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double trip_to_mem;
+	double Tvm_trips;
+	double Tr0_trips;
+	double Tvm_trips_rounded;
+	double Tr0_trips_rounded;
+	double Lsw_oto;
+	double Tpre_rounded;
+	double prefetch_bw_equ;
+	double Tvm_equ;
+	double Tr0_equ;
+	double Tdmbf;
+	double Tdmec;
+	double Tdmsks;
+	double prefetch_sw_bytes;
+	double bytes_pp;
+	double dep_bytes;
+	int max_vratio_pre = 4;
+	double min_Lsw;
+	double Tsw_est1 = 0;
+	double Tsw_est3 = 0;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	} else {
+		HostVMDynamicLevelsTrips = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: GPUVMEnable=%d HostVMEnable=%d HostVMInefficiencyFactor=%f\n", __func__, GPUVMEnable, HostVMEnable, HostVMInefficiencyFactor);
+#endif
+	CalculateVupdateAndDynamicMetadataParameters(
+			MaxInterDCNTileRepeaters,
+			myPipe->DPPCLK,
+			myPipe->DISPCLK,
+			myPipe->DCFCLKDeepSleep,
+			myPipe->PixelClock,
+			myPipe->HTotal,
+			myPipe->VBlank,
+			DynamicMetadataTransmittedBytes,
+			DynamicMetadataLinesBeforeActiveRequired,
+			myPipe->InterlaceEnable,
+			myPipe->ProgressiveToInterlaceUnitInOPP,
+			TSetup,
+			&Tdmbf,
+			&Tdmec,
+			&Tdmsks,
+			VUpdateOffsetPix,
+			VUpdateWidthPix,
+			VReadyOffsetPix);
+
+	LineTime = myPipe->HTotal / myPipe->PixelClock;
+	trip_to_mem = UrgentLatency;
+	Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) {
+#else
+	if (DynamicMetadataVMEnabled == true) {
+#endif
+		*Tdmdl = TWait + Tvm_trips + trip_to_mem;
+	} else {
+		*Tdmdl = TWait + UrgentExtraLatency;
+	}
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (DynamicMetadataEnable == false) {
+		*Tdmdl = 0.0;
+	}
+#endif
+
+	if (DynamicMetadataEnable == true) {
+		if (VStartup * LineTime < *TSetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) {
+			*NotEnoughTimeForDynamicMetadata = true;
+			dml_print("DML::%s: Not Enough Time for Dynamic Meta!\n", __func__);
+			dml_print("DML::%s: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", __func__, Tdmbf);
+			dml_print("DML::%s: Tdmec: %fus - time dio takes to transfer dmd\n", __func__, Tdmec);
+			dml_print("DML::%s: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", __func__, Tdmsks);
+			dml_print("DML::%s: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", __func__, *Tdmdl);
+		} else {
+			*NotEnoughTimeForDynamicMetadata = false;
+		}
+	} else {
+		*NotEnoughTimeForDynamicMetadata = false;
+	}
+
+	*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0);
+
+	if (myPipe->ScalerEnabled)
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL;
+	else
+		DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly;
+
+	DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor;
+
+	DISPCLKCycles = DISPCLKDelaySubtotal;
+
+	if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
+		return true;
+
+	*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK + DSCDelay;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DPPCycles: %d\n", __func__, DPPCycles);
+	dml_print("DML::%s: PixelClock: %f\n", __func__, myPipe->PixelClock);
+	dml_print("DML::%s: DPPCLK: %f\n", __func__, myPipe->DPPCLK);
+	dml_print("DML::%s: DISPCLKCycles: %d\n", __func__, DISPCLKCycles);
+	dml_print("DML::%s: DISPCLK: %f\n", __func__, myPipe->DISPCLK);
+	dml_print("DML::%s: DSCDelay: %d\n", __func__, DSCDelay);
+	dml_print("DML::%s: DSTXAfterScaler: %d\n", __func__, *DSTXAfterScaler);
+	dml_print("DML::%s: ODMCombineIsEnabled: %d\n", __func__, myPipe->ODMCombineIsEnabled);
+#endif
+
+	*DSTXAfterScaler = *DSTXAfterScaler + ((myPipe->ODMCombineIsEnabled) ? 18 : 0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
+
+	if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && myPipe->ProgressiveToInterlaceUnitInOPP))
+		*DSTYAfterScaler = 1;
+	else
+		*DSTYAfterScaler = 0;
+
+	DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler;
+	*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
+	*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal));
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DSTXAfterScaler: %d (final)\n", __func__, *DSTXAfterScaler);
+#endif
+
+	MyError = false;
+
+	Tr0_trips = trip_to_mem * (HostVMDynamicLevelsTrips + 1);
+	Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
+	Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+	if (!myPipe->DCCEnable) {
+		Tr0_trips = 0.0;
+		Tr0_trips_rounded = 0.0;
+	}
+#endif
+
+	if (!GPUVMEnable) {
+		Tvm_trips = 0.0;
+		Tvm_trips_rounded = 0.0;
+	}
+
+	if (GPUVMEnable) {
+		if (GPUVMPageTableLevels >= 3) {
+			*Tno_bw = UrgentExtraLatency + trip_to_mem * ((GPUVMPageTableLevels - 2) - 1);
+		} else {
+			*Tno_bw = 0;
+		}
+	} else if (!myPipe->DCCEnable) {
+		*Tno_bw = LineTime;
+	} else {
+		*Tno_bw = LineTime / 4;
+	}
+
+	if (myPipe->SourcePixelFormat == dm_420_8 || myPipe->SourcePixelFormat == dm_420_10 || myPipe->SourcePixelFormat == dm_420_12)
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC / 4;
+	else
+		bytes_pp = myPipe->BytePerPixelY + myPipe->BytePerPixelC;
+
+	prefetch_sw_bytes = PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC;
+	prefetch_bw_oto = dml_max(bytes_pp * myPipe->PixelClock / myPipe->DPPPerPlane, prefetch_sw_bytes / (dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) * LineTime));
+
+	min_Lsw = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC) / max_vratio_pre;
+	Lsw_oto = dml_ceil(4 * dml_max(prefetch_sw_bytes / prefetch_bw_oto / LineTime, min_Lsw), 1) / 4;
+	Tsw_oto = Lsw_oto * LineTime;
+
+	prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * myPipe->BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * myPipe->BytePerPixelC) / Tsw_oto;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML: HTotal: %d\n", myPipe->HTotal);
+	dml_print("DML: prefetch_bw_oto: %f\n", prefetch_bw_oto);
+	dml_print("DML: PrefetchSourceLinesY: %f\n", PrefetchSourceLinesY);
+	dml_print("DML: swath_width_luma_ub: %d\n", swath_width_luma_ub);
+	dml_print("DML: BytePerPixelY: %d\n", myPipe->BytePerPixelY);
+	dml_print("DML: Tsw_oto: %f\n", Tsw_oto);
+#endif
+
+	if (GPUVMEnable == true)
+		Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, Tvm_trips, LineTime / 4.0);
+	else
+		Tvm_oto = LineTime / 4.0;
+
+	if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+		Tr0_oto = dml_max4((MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, Tr0_trips, // PREVIOUS_ERROR (missing this term)
+				LineTime - Tvm_oto,
+				LineTime / 4);
+	} else {
+		Tr0_oto = (LineTime - Tvm_oto) / 2.0;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Tvm_trips = %f\n", __func__, Tvm_trips);
+	dml_print("DML::%s: Tr0_trips = %f\n", __func__, Tr0_trips);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, MetaRowByte);
+	dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+	dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+	dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+	dml_print("DML::%s: prefetch_bw_oto = %f\n", __func__, prefetch_bw_oto);
+	dml_print("DML::%s: Tr0_oto = %f\n", __func__, Tr0_oto);
+	dml_print("DML::%s: Tvm_oto = %f\n", __func__, Tvm_oto);
+#endif
+
+	Tvm_oto_lines = dml_ceil(4.0 * Tvm_oto / LineTime, 1) / 4.0;
+	Tr0_oto_lines = dml_ceil(4.0 * Tr0_oto / LineTime, 1) / 4.0;
+	dst_y_prefetch_oto = Tvm_oto_lines + 2 * Tr0_oto_lines + Lsw_oto;
+	dst_y_prefetch_equ =  VStartup - (*TSetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime - (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal);
+	dst_y_prefetch_equ = dml_floor(4.0 * (dst_y_prefetch_equ + 0.125), 1) / 4.0;
+	Tpre_rounded = dst_y_prefetch_equ * LineTime;
+
+	dep_bytes = dml_max(PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor, MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor);
+
+	if (prefetch_sw_bytes < dep_bytes)
+		prefetch_sw_bytes = 2 * dep_bytes;
+
+	dml_print("DML: dst_y_prefetch_oto: %f\n", dst_y_prefetch_oto);
+	dml_print("DML: Tvm_oto_lines: %f\n", Tvm_oto_lines);
+	dml_print("DML: Tr0_oto_lines: %f\n", Tr0_oto_lines);
+	dml_print("DML: Lsw_oto: %f\n", Lsw_oto);
+	dml_print("DML: LineTime: %f\n", LineTime);
+	dml_print("DML: dst_y_prefetch_equ: %f (after round)\n", dst_y_prefetch_equ);
+
+	dml_print("DML: LineTime: %f\n", LineTime);
+	dml_print("DML: VStartup: %d\n", VStartup);
+	dml_print("DML: Tvstartup: %fus - time between vstartup and first pixel of active\n", VStartup * LineTime);
+	dml_print("DML: TSetup: %fus - time from vstartup to vready\n", *TSetup);
+	dml_print("DML: TCalc: %fus - time for calculations in dchub starting at vready\n", TCalc);
+	dml_print("DML: TWait: %fus - time for fabric to become ready max(pstate exit,cstate enter/exit, urgent latency) after TCalc\n", TWait);
+	dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf);
+	dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec);
+	dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks);
+	dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", *Tdmdl_vm);
+	dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl);
+	dml_print("DML: DSTXAfterScaler: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", *DSTXAfterScaler);
+	dml_print("DML: DSTYAfterScaler: %f lines - number of lines of pipeline and buffer delay after scaler \n", *DSTYAfterScaler);
+
+	*PrefetchBandwidth = 0;
+	*DestinationLinesToRequestVMInVBlank = 0;
+	*DestinationLinesToRequestRowInVBlank = 0;
+	*VRatioPrefetchY = 0;
+	*VRatioPrefetchC = 0;
+	*RequiredPrefetchPixDataBWLuma = 0;
+	if (dst_y_prefetch_equ > 1) {
+		double PrefetchBandwidth1;
+		double PrefetchBandwidth2;
+		double PrefetchBandwidth3;
+		double PrefetchBandwidth4;
+
+		if (Tpre_rounded - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw);
+			Tsw_est1 = prefetch_sw_bytes / PrefetchBandwidth1;
+		} else {
+			PrefetchBandwidth1 = 0;
+		}
+
+		if (VStartup == MaxVStartup && Tsw_est1 / LineTime < min_Lsw && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw > 0) {
+			PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - *Tno_bw);
+		}
+
+		if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0)
+			PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + prefetch_sw_bytes) / (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded);
+		else
+			PrefetchBandwidth2 = 0;
+
+		if (Tpre_rounded - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+					+ prefetch_sw_bytes) / (Tpre_rounded - Tvm_trips_rounded);
+			Tsw_est3 = prefetch_sw_bytes / PrefetchBandwidth3;
+		} else {
+			PrefetchBandwidth3 = 0;
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: Tpre_rounded: %f\n", __func__, Tpre_rounded);
+		dml_print("DML::%s: Tvm_trips_rounded: %f\n", __func__, Tvm_trips_rounded);
+		dml_print("DML::%s: PrefetchBandwidth3: %f\n", __func__, PrefetchBandwidth3);
+#endif
+		if (VStartup == MaxVStartup && Tsw_est3 / LineTime < min_Lsw && Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded > 0) {
+			PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor)
+					/ (Tpre_rounded - min_Lsw * LineTime - 0.75 * LineTime - Tvm_trips_rounded);
+		}
+
+		if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0)
+			PrefetchBandwidth4 = prefetch_sw_bytes / (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded);
+		else
+			PrefetchBandwidth4 = 0;
+
+		{
+			bool Case1OK;
+			bool Case2OK;
+			bool Case3OK;
+
+			if (PrefetchBandwidth1 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 >= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= Tr0_trips_rounded) {
+					Case1OK = true;
+				} else {
+					Case1OK = false;
+				}
+			} else {
+				Case1OK = false;
+			}
+
+			if (PrefetchBandwidth2 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 >= Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < Tr0_trips_rounded) {
+					Case2OK = true;
+				} else {
+					Case2OK = false;
+				}
+			} else {
+				Case2OK = false;
+			}
+
+			if (PrefetchBandwidth3 > 0) {
+				if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 < Tvm_trips_rounded
+						&& (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= Tr0_trips_rounded) {
+					Case3OK = true;
+				} else {
+					Case3OK = false;
+				}
+			} else {
+				Case3OK = false;
+			}
+
+			if (Case1OK) {
+				prefetch_bw_equ = PrefetchBandwidth1;
+			} else if (Case2OK) {
+				prefetch_bw_equ = PrefetchBandwidth2;
+			} else if (Case3OK) {
+				prefetch_bw_equ = PrefetchBandwidth3;
+			} else {
+				prefetch_bw_equ = PrefetchBandwidth4;
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: Case1OK: %d\n", __func__, Case1OK);
+			dml_print("DML::%s: Case2OK: %d\n", __func__, Case2OK);
+			dml_print("DML::%s: Case3OK: %d\n", __func__, Case3OK);
+			dml_print("DML::%s: prefetch_bw_equ: %f\n", __func__, prefetch_bw_equ);
+#endif
+
+			if (prefetch_bw_equ > 0) {
+				if (GPUVMEnable == true) {
+					Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
+				} else {
+					Tvm_equ = LineTime / 4;
+				}
+
+				if ((GPUVMEnable == true || myPipe->DCCEnable == true)) {
+					Tr0_equ = dml_max4(
+							(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_equ,
+							Tr0_trips,
+							(LineTime - Tvm_equ) / 2,
+							LineTime / 4);
+				} else {
+					Tr0_equ = (LineTime - Tvm_equ) / 2;
+				}
+			} else {
+				Tvm_equ = 0;
+				Tr0_equ = 0;
+				dml_print("DML: prefetch_bw_equ equals 0! %s:%d\n", __FILE__, __LINE__);
+			}
+		}
+
+		if (dst_y_prefetch_oto < dst_y_prefetch_equ) {
+			*DestinationLinesForPrefetch = dst_y_prefetch_oto;
+			TimeForFetchingMetaPTE = Tvm_oto;
+			TimeForFetchingRowInVBlank = Tr0_oto;
+			*PrefetchBandwidth = prefetch_bw_oto;
+		} else {
+			*DestinationLinesForPrefetch = dst_y_prefetch_equ;
+			TimeForFetchingMetaPTE = Tvm_equ;
+			TimeForFetchingRowInVBlank = Tr0_equ;
+			*PrefetchBandwidth = prefetch_bw_equ;
+		}
+
+		*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
+
+		*DestinationLinesToRequestRowInVBlank = dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
+
+#ifdef __DML_VBA_ALLOW_DELTA__
+		LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch
+		// See note above dated 5/30/2018
+		//                      - ((NumberOfCursors > 0 || GPUVMEnable || DCCEnable) ?
+				- ((GPUVMEnable || myPipe->DCCEnable) ? (*DestinationLinesToRequestVMInVBlank + 2 * *DestinationLinesToRequestRowInVBlank) : 0.0); // TODO: Did someone else add this??
+#else
+				LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch - *DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
+#endif
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: DestinationLinesForPrefetch = %f\n", __func__, *DestinationLinesForPrefetch);
+		dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", __func__, *DestinationLinesToRequestVMInVBlank);
+		dml_print("DML::%s: TimeForFetchingRowInVBlank = %f\n", __func__, TimeForFetchingRowInVBlank);
+		dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+		dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", __func__, *DestinationLinesToRequestRowInVBlank);
+		dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+		dml_print("DML::%s: LinesToRequestPrefetchPixelData = %f\n", __func__, LinesToRequestPrefetchPixelData);
+#endif
+
+		if (LinesToRequestPrefetchPixelData > 0 && prefetch_bw_equ > 0) {
+
+			*VRatioPrefetchY = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+			dml_print("DML::%s: SwathHeightY = %d\n", __func__, SwathHeightY);
+			dml_print("DML::%s: VInitPreFillY = %f\n", __func__, VInitPreFillY);
+#endif
+			if ((SwathHeightY > 4) && (VInitPreFillY > 3)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillY - 3.0) / 2.0) {
+					*VRatioPrefetchY = dml_max(
+							(double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData,
+							(double) MaxNumSwathY * SwathHeightY / (LinesToRequestPrefetchPixelData - (VInitPreFillY - 3.0) / 2.0));
+					*VRatioPrefetchY = dml_max(*VRatioPrefetchY, 1.0);
+				} else {
+					MyError = true;
+					dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+					*VRatioPrefetchY = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchY = %f\n", __func__, *VRatioPrefetchY);
+				dml_print("DML::%s: PrefetchSourceLinesY = %f\n", __func__, PrefetchSourceLinesY);
+				dml_print("DML::%s: MaxNumSwathY = %d\n", __func__, MaxNumSwathY);
+#endif
+			}
+
+			*VRatioPrefetchC = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData;
+			*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+			dml_print("DML::%s: SwathHeightC = %d\n", __func__, SwathHeightC);
+			dml_print("DML::%s: VInitPreFillC = %f\n", __func__, VInitPreFillC);
+#endif
+			if ((SwathHeightC > 4)) {
+				if (LinesToRequestPrefetchPixelData > (VInitPreFillC - 3.0) / 2.0) {
+					*VRatioPrefetchC = dml_max(
+							*VRatioPrefetchC,
+							(double) MaxNumSwathC * SwathHeightC / (LinesToRequestPrefetchPixelData - (VInitPreFillC - 3.0) / 2.0));
+					*VRatioPrefetchC = dml_max(*VRatioPrefetchC, 1.0);
+				} else {
+					MyError = true;
+					dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+					*VRatioPrefetchC = 0;
+				}
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: VRatioPrefetchC = %f\n", __func__, *VRatioPrefetchC);
+				dml_print("DML::%s: PrefetchSourceLinesC = %f\n", __func__, PrefetchSourceLinesC);
+				dml_print("DML::%s: MaxNumSwathC = %d\n", __func__, MaxNumSwathC);
+#endif
+			}
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: BytePerPixelY = %d\n", __func__, myPipe->BytePerPixelY);
+			dml_print("DML::%s: swath_width_luma_ub = %d\n", __func__, swath_width_luma_ub);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+#endif
+
+			*RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelY * swath_width_luma_ub / LineTime;
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: RequiredPrefetchPixDataBWLuma = %f\n", __func__, *RequiredPrefetchPixDataBWLuma);
+#endif
+
+			*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * myPipe->BytePerPixelC * swath_width_chroma_ub
+					/ LineTime;
+		} else {
+			MyError = true;
+			dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+			dml_print("DML: LinesToRequestPrefetchPixelData: %f, should be > 0\n", LinesToRequestPrefetchPixelData);
+			*VRatioPrefetchY = 0;
+			*VRatioPrefetchC = 0;
+			*RequiredPrefetchPixDataBWLuma = 0;
+			*RequiredPrefetchPixDataBWChroma = 0;
+		}
+
+		dml_print(
+				"DML: Tpre: %fus - sum of time to request meta pte, 2 x data pte + meta data, swaths\n",
+				(double) LinesToRequestPrefetchPixelData * LineTime + 2.0 * TimeForFetchingRowInVBlank + TimeForFetchingMetaPTE);
+		dml_print("DML:  Tvm: %fus - time to fetch page tables for meta surface\n", TimeForFetchingMetaPTE);
+		dml_print("DML:  Tr0: %fus - time to fetch first row of data pagetables and first row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank);
+		dml_print(
+				"DML:  Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n",
+				(double) LinesToRequestPrefetchPixelData * LineTime);
+		dml_print("DML: To: %fus - time for propagation from scaler to optc\n",
+			  (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) /
+			  (double) myPipe->HTotal)) * LineTime);
+		dml_print("DML: Tvstartup - TSetup - Tcalc - Twait - Tpre - To > 0\n");
+		dml_print("DML: Tslack(pre): %fus - time left over in schedule\n",
+				VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank
+						- (*DSTYAfterScaler + ((double) (*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - *TSetup);
+		dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
+
+	} else {
+		MyError = true;
+		dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+	}
+
+	{
+		double prefetch_vm_bw;
+		double prefetch_row_bw;
+
+		if (PDEAndMetaPTEBytesFrame == 0) {
+			prefetch_vm_bw = 0;
+		} else if (*DestinationLinesToRequestVMInVBlank > 0) {
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+			dml_print("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, HostVMInefficiencyFactor);
+			dml_print("DML::%s: DestinationLinesToRequestVMInVBlank = %f\n", __func__, *DestinationLinesToRequestVMInVBlank);
+			dml_print("DML::%s: LineTime = %f\n", __func__, LineTime);
+#endif
+			prefetch_vm_bw = PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInVBlank * LineTime);
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw);
+#endif
+		} else {
+			prefetch_vm_bw = 0;
+			MyError = true;
+			dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+		}
+
+		if (MetaRowByte + PixelPTEBytesPerRow == 0) {
+			prefetch_row_bw = 0;
+		} else if (*DestinationLinesToRequestRowInVBlank > 0) {
+			prefetch_row_bw = (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInVBlank * LineTime);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: MetaRowByte = %d\n", __func__, MetaRowByte);
+			dml_print("DML::%s: PixelPTEBytesPerRow = %d\n", __func__, PixelPTEBytesPerRow);
+			dml_print("DML::%s: DestinationLinesToRequestRowInVBlank = %f\n", __func__, *DestinationLinesToRequestRowInVBlank);
+			dml_print("DML::%s: prefetch_row_bw = %f\n", __func__, prefetch_row_bw);
+#endif
+		} else {
+			prefetch_row_bw = 0;
+			MyError = true;
+			dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
+		}
+
+		*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw);
+	}
+
+	if (MyError) {
+		*PrefetchBandwidth = 0;
+		TimeForFetchingMetaPTE = 0;
+		TimeForFetchingRowInVBlank = 0;
+		*DestinationLinesToRequestVMInVBlank = 0;
+		*DestinationLinesToRequestRowInVBlank = 0;
+		*DestinationLinesForPrefetch = 0;
+		LinesToRequestPrefetchPixelData = 0;
+		*VRatioPrefetchY = 0;
+		*VRatioPrefetchC = 0;
+		*RequiredPrefetchPixDataBWLuma = 0;
+		*RequiredPrefetchPixDataBWChroma = 0;
+	}
+
+	return MyError;
+}
+
+static double RoundToDFSGranularityUp(double Clock, double VCOSpeed)
+{
+	return VCOSpeed * 4 / dml_floor(VCOSpeed * 4 / Clock, 1);
+}
+
+static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
+{
+	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4.0 / Clock, 1);
+}
+
+static void CalculateDCCConfiguration(
+		bool DCCEnabled,
+		bool DCCProgrammingAssumesScanDirectionUnknown,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceWidthLuma,
+		unsigned int SurfaceWidthChroma,
+		unsigned int SurfaceHeightLuma,
+		unsigned int SurfaceHeightChroma,
+		double DETBufferSize,
+		unsigned int RequestHeight256ByteLuma,
+		unsigned int RequestHeight256ByteChroma,
+		enum dm_swizzle_mode TilingFormat,
+		unsigned int BytePerPixelY,
+		unsigned int BytePerPixelC,
+		double BytePerPixelDETY,
+		double BytePerPixelDETC,
+		enum scan_direction_class ScanOrientation,
+		unsigned int *MaxUncompressedBlockLuma,
+		unsigned int *MaxUncompressedBlockChroma,
+		unsigned int *MaxCompressedBlockLuma,
+		unsigned int *MaxCompressedBlockChroma,
+		unsigned int *IndependentBlockLuma,
+		unsigned int *IndependentBlockChroma)
+{
+	int yuv420;
+	int horz_div_l;
+	int horz_div_c;
+	int vert_div_l;
+	int vert_div_c;
+
+	int swath_buf_size;
+	double detile_buf_vp_horz_limit;
+	double detile_buf_vp_vert_limit;
+
+	int MAS_vp_horz_limit;
+	int MAS_vp_vert_limit;
+	int max_vp_horz_width;
+	int max_vp_vert_height;
+	int eff_surf_width_l;
+	int eff_surf_width_c;
+	int eff_surf_height_l;
+	int eff_surf_height_c;
+
+	int full_swath_bytes_horz_wc_l;
+	int full_swath_bytes_horz_wc_c;
+	int full_swath_bytes_vert_wc_l;
+	int full_swath_bytes_vert_wc_c;
+	int req128_horz_wc_l;
+	int req128_horz_wc_c;
+	int req128_vert_wc_l;
+	int req128_vert_wc_c;
+	int segment_order_horz_contiguous_luma;
+	int segment_order_horz_contiguous_chroma;
+	int segment_order_vert_contiguous_luma;
+	int segment_order_vert_contiguous_chroma;
+
+	typedef enum {
+		REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
+	} RequestType;
+	RequestType RequestLuma;
+	RequestType RequestChroma;
+
+	yuv420 = ((SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12) ? 1 : 0);
+	horz_div_l = 1;
+	horz_div_c = 1;
+	vert_div_l = 1;
+	vert_div_c = 1;
+
+	if (BytePerPixelY == 1)
+		vert_div_l = 0;
+	if (BytePerPixelC == 1)
+		vert_div_c = 0;
+	if (BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_s || TilingFormat == dm_sw_64kb_s_t || TilingFormat == dm_sw_64kb_s_x))
+		horz_div_l = 0;
+	if (BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_s || TilingFormat == dm_sw_64kb_s_t || TilingFormat == dm_sw_64kb_s_x))
+		horz_div_c = 0;
+
+	if (BytePerPixelC == 0) {
+		swath_buf_size = DETBufferSize / 2 - 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size / ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l));
+		detile_buf_vp_vert_limit = (double) swath_buf_size / (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l));
+	} else {
+		swath_buf_size = DETBufferSize / 2 - 2 * 2 * 256;
+		detile_buf_vp_horz_limit = (double) swath_buf_size
+				/ ((double) RequestHeight256ByteLuma * BytePerPixelY / (1 + horz_div_l)
+						+ (double) RequestHeight256ByteChroma * BytePerPixelC / (1 + horz_div_c) / (1 + yuv420));
+		detile_buf_vp_vert_limit = (double) swath_buf_size
+				/ (256.0 / RequestHeight256ByteLuma / (1 + vert_div_l) + 256.0 / RequestHeight256ByteChroma / (1 + vert_div_c) / (1 + yuv420));
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		detile_buf_vp_horz_limit = 1.5 * detile_buf_vp_horz_limit;
+		detile_buf_vp_vert_limit = 1.5 * detile_buf_vp_vert_limit;
+	}
+
+	detile_buf_vp_horz_limit = dml_floor(detile_buf_vp_horz_limit - 1, 16);
+	detile_buf_vp_vert_limit = dml_floor(detile_buf_vp_vert_limit - 1, 16);
+
+	MAS_vp_horz_limit = SourcePixelFormat == dm_rgbe_alpha ? 3840 : 5760;
+	MAS_vp_vert_limit = (BytePerPixelC > 0 ? 2880 : 5760);
+	max_vp_horz_width = dml_min((double) MAS_vp_horz_limit, detile_buf_vp_horz_limit);
+	max_vp_vert_height = dml_min((double) MAS_vp_vert_limit, detile_buf_vp_vert_limit);
+	eff_surf_width_l = (SurfaceWidthLuma > max_vp_horz_width ? max_vp_horz_width : SurfaceWidthLuma);
+	eff_surf_width_c = eff_surf_width_l / (1 + yuv420);
+	eff_surf_height_l = (SurfaceHeightLuma > max_vp_vert_height ? max_vp_vert_height : SurfaceHeightLuma);
+	eff_surf_height_c = eff_surf_height_l / (1 + yuv420);
+
+	full_swath_bytes_horz_wc_l = eff_surf_width_l * RequestHeight256ByteLuma * BytePerPixelY;
+	full_swath_bytes_vert_wc_l = eff_surf_height_l * 256 / RequestHeight256ByteLuma;
+	if (BytePerPixelC > 0) {
+		full_swath_bytes_horz_wc_c = eff_surf_width_c * RequestHeight256ByteChroma * BytePerPixelC;
+		full_swath_bytes_vert_wc_c = eff_surf_height_c * 256 / RequestHeight256ByteChroma;
+	} else {
+		full_swath_bytes_horz_wc_c = 0;
+		full_swath_bytes_vert_wc_c = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_10) {
+		full_swath_bytes_horz_wc_l = dml_ceil(full_swath_bytes_horz_wc_l * 2 / 3, 256);
+		full_swath_bytes_horz_wc_c = dml_ceil(full_swath_bytes_horz_wc_c * 2 / 3, 256);
+		full_swath_bytes_vert_wc_l = dml_ceil(full_swath_bytes_vert_wc_l * 2 / 3, 256);
+		full_swath_bytes_vert_wc_c = dml_ceil(full_swath_bytes_vert_wc_c * 2 / 3, 256);
+	}
+
+	if (2 * full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 0;
+	} else if (full_swath_bytes_horz_wc_l < 1.5 * full_swath_bytes_horz_wc_c && 2 * full_swath_bytes_horz_wc_l + full_swath_bytes_horz_wc_c <= DETBufferSize) {
+		req128_horz_wc_l = 0;
+		req128_horz_wc_c = 1;
+	} else if (full_swath_bytes_horz_wc_l >= 1.5 * full_swath_bytes_horz_wc_c && full_swath_bytes_horz_wc_l + 2 * full_swath_bytes_horz_wc_c <= DETBufferSize) {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 0;
+	} else {
+		req128_horz_wc_l = 1;
+		req128_horz_wc_c = 1;
+	}
+
+	if (2 * full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSize) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 0;
+	} else if (full_swath_bytes_vert_wc_l < 1.5 * full_swath_bytes_vert_wc_c && 2 * full_swath_bytes_vert_wc_l + full_swath_bytes_vert_wc_c <= DETBufferSize) {
+		req128_vert_wc_l = 0;
+		req128_vert_wc_c = 1;
+	} else if (full_swath_bytes_vert_wc_l >= 1.5 * full_swath_bytes_vert_wc_c && full_swath_bytes_vert_wc_l + 2 * full_swath_bytes_vert_wc_c <= DETBufferSize) {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 0;
+	} else {
+		req128_vert_wc_l = 1;
+		req128_vert_wc_c = 1;
+	}
+
+	if (BytePerPixelY == 2 || (BytePerPixelY == 4 && TilingFormat != dm_sw_64kb_r_x)) {
+		segment_order_horz_contiguous_luma = 0;
+	} else {
+		segment_order_horz_contiguous_luma = 1;
+	}
+	if ((BytePerPixelY == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))
+			|| (BytePerPixelY == 4 && TilingFormat == dm_sw_64kb_r_x)) {
+		segment_order_vert_contiguous_luma = 0;
+	} else {
+		segment_order_vert_contiguous_luma = 1;
+	}
+	if (BytePerPixelC == 2 || (BytePerPixelC == 4 && TilingFormat != dm_sw_64kb_r_x)) {
+		segment_order_horz_contiguous_chroma = 0;
+	} else {
+		segment_order_horz_contiguous_chroma = 1;
+	}
+	if ((BytePerPixelC == 8 && (TilingFormat == dm_sw_64kb_d || TilingFormat == dm_sw_64kb_d_x || TilingFormat == dm_sw_64kb_d_t || TilingFormat == dm_sw_64kb_r_x))
+			|| (BytePerPixelC == 4 && TilingFormat == dm_sw_64kb_r_x)) {
+		segment_order_vert_contiguous_chroma = 0;
+	} else {
+		segment_order_vert_contiguous_chroma = 1;
+	}
+
+	if (DCCProgrammingAssumesScanDirectionUnknown == true) {
+		if (req128_horz_wc_l == 0 && req128_vert_wc_l == 0) {
+			RequestLuma = REQ_256Bytes;
+		} else if ((req128_horz_wc_l == 1 && segment_order_horz_contiguous_luma == 0) || (req128_vert_wc_l == 1 && segment_order_vert_contiguous_luma == 0)) {
+			RequestLuma = REQ_128BytesNonContiguous;
+		} else {
+			RequestLuma = REQ_128BytesContiguous;
+		}
+		if (req128_horz_wc_c == 0 && req128_vert_wc_c == 0) {
+			RequestChroma = REQ_256Bytes;
+		} else if ((req128_horz_wc_c == 1 && segment_order_horz_contiguous_chroma == 0) || (req128_vert_wc_c == 1 && segment_order_vert_contiguous_chroma == 0)) {
+			RequestChroma = REQ_128BytesNonContiguous;
+		} else {
+			RequestChroma = REQ_128BytesContiguous;
+		}
+	} else if (ScanOrientation != dm_vert) {
+		if (req128_horz_wc_l == 0) {
+			RequestLuma = REQ_256Bytes;
+		} else if (segment_order_horz_contiguous_luma == 0) {
+			RequestLuma = REQ_128BytesNonContiguous;
+		} else {
+			RequestLuma = REQ_128BytesContiguous;
+		}
+		if (req128_horz_wc_c == 0) {
+			RequestChroma = REQ_256Bytes;
+		} else if (segment_order_horz_contiguous_chroma == 0) {
+			RequestChroma = REQ_128BytesNonContiguous;
+		} else {
+			RequestChroma = REQ_128BytesContiguous;
+		}
+	} else {
+		if (req128_vert_wc_l == 0) {
+			RequestLuma = REQ_256Bytes;
+		} else if (segment_order_vert_contiguous_luma == 0) {
+			RequestLuma = REQ_128BytesNonContiguous;
+		} else {
+			RequestLuma = REQ_128BytesContiguous;
+		}
+		if (req128_vert_wc_c == 0) {
+			RequestChroma = REQ_256Bytes;
+		} else if (segment_order_vert_contiguous_chroma == 0) {
+			RequestChroma = REQ_128BytesNonContiguous;
+		} else {
+			RequestChroma = REQ_128BytesContiguous;
+		}
+	}
+
+	if (RequestLuma == REQ_256Bytes) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 256;
+		*IndependentBlockLuma = 0;
+	} else if (RequestLuma == REQ_128BytesContiguous) {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 128;
+		*IndependentBlockLuma = 128;
+	} else {
+		*MaxUncompressedBlockLuma = 256;
+		*MaxCompressedBlockLuma = 64;
+		*IndependentBlockLuma = 64;
+	}
+
+	if (RequestChroma == REQ_256Bytes) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 256;
+		*IndependentBlockChroma = 0;
+	} else if (RequestChroma == REQ_128BytesContiguous) {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 128;
+		*IndependentBlockChroma = 128;
+	} else {
+		*MaxUncompressedBlockChroma = 256;
+		*MaxCompressedBlockChroma = 64;
+		*IndependentBlockChroma = 64;
+	}
+
+	if (DCCEnabled != true || BytePerPixelC == 0) {
+		*MaxUncompressedBlockChroma = 0;
+		*MaxCompressedBlockChroma = 0;
+		*IndependentBlockChroma = 0;
+	}
+
+	if (DCCEnabled != true) {
+		*MaxUncompressedBlockLuma = 0;
+		*MaxCompressedBlockLuma = 0;
+		*IndependentBlockLuma = 0;
+	}
+}
+
+static double CalculatePrefetchSourceLines(
+		struct display_mode_lib *mode_lib,
+		double VRatio,
+		double vtaps,
+		bool Interlace,
+		bool ProgressiveToInterlaceUnitInOPP,
+		unsigned int SwathHeight,
+		unsigned int ViewportYStart,
+		double *VInitPreFill,
+		unsigned int *MaxNumSwath)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int MaxPartialSwath;
+
+	if (ProgressiveToInterlaceUnitInOPP)
+		*VInitPreFill = dml_floor((VRatio + vtaps + 1) / 2.0, 1);
+	else
+		*VInitPreFill = dml_floor((VRatio + vtaps + 1 + Interlace * 0.5 * VRatio) / 2.0, 1);
+
+	if (!v->IgnoreViewportPositioning) {
+
+		*MaxNumSwath = dml_ceil((*VInitPreFill - 1.0) / SwathHeight, 1) + 1.0;
+
+		if (*VInitPreFill > 1.0)
+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 2) % SwathHeight;
+		else
+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 2) % SwathHeight;
+		MaxPartialSwath = dml_max(1U, MaxPartialSwath);
+
+	} else {
+
+		if (ViewportYStart != 0)
+			dml_print("WARNING DML: using viewport y position of 0 even though actual viewport y position is non-zero in prefetch source lines calculation\n");
+
+		*MaxNumSwath = dml_ceil(*VInitPreFill / SwathHeight, 1);
+
+		if (*VInitPreFill > 1.0)
+			MaxPartialSwath = (unsigned int) (*VInitPreFill - 1) % SwathHeight;
+		else
+			MaxPartialSwath = (unsigned int) (*VInitPreFill + SwathHeight - 1) % SwathHeight;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VRatio = %f\n", __func__, VRatio);
+	dml_print("DML::%s: vtaps = %f\n", __func__, vtaps);
+	dml_print("DML::%s: VInitPreFill = %f\n", __func__, *VInitPreFill);
+	dml_print("DML::%s: ProgressiveToInterlaceUnitInOPP = %d\n", __func__, ProgressiveToInterlaceUnitInOPP);
+	dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning);
+	dml_print("DML::%s: SwathHeight = %d\n", __func__, SwathHeight);
+	dml_print("DML::%s: MaxPartialSwath = %d\n", __func__, MaxPartialSwath);
+	dml_print("DML::%s: MaxNumSwath = %d\n", __func__, *MaxNumSwath);
+	dml_print("DML::%s: Prefetch source lines = %d\n", __func__, *MaxNumSwath * SwathHeight + MaxPartialSwath);
+#endif
+	return *MaxNumSwath * SwathHeight + MaxPartialSwath;
+}
+
+static unsigned int CalculateVMAndRowBytes(
+		struct display_mode_lib *mode_lib,
+		bool DCCEnable,
+		unsigned int BlockHeight256Bytes,
+		unsigned int BlockWidth256Bytes,
+		enum source_format_class SourcePixelFormat,
+		unsigned int SurfaceTiling,
+		unsigned int BytePerPixel,
+		enum scan_direction_class ScanDirection,
+		unsigned int SwathWidth,
+		unsigned int ViewportHeight,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		unsigned int GPUVMMinPageSize,
+		unsigned int HostVMMinPageSize,
+		unsigned int PTEBufferSizeInRequests,
+		unsigned int Pitch,
+		unsigned int DCCMetaPitch,
+		unsigned int *MacroTileWidth,
+		unsigned int *MetaRowByte,
+		unsigned int *PixelPTEBytesPerRow,
+		bool *PTEBufferSizeNotExceeded,
+		int *dpte_row_width_ub,
+		unsigned int *dpte_row_height,
+		unsigned int *MetaRequestWidth,
+		unsigned int *MetaRequestHeight,
+		unsigned int *meta_row_width,
+		unsigned int *meta_row_height,
+		int *vm_group_bytes,
+		unsigned int *dpte_group_bytes,
+		unsigned int *PixelPTEReqWidth,
+		unsigned int *PixelPTEReqHeight,
+		unsigned int *PTERequestSize,
+		int *DPDE0BytesFrame,
+		int *MetaPTEBytesFrame)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int MPDEBytesFrame;
+	unsigned int DCCMetaSurfaceBytes;
+	unsigned int MacroTileSizeBytes;
+	unsigned int MacroTileHeight;
+	unsigned int ExtraDPDEBytesFrame;
+	unsigned int PDEAndMetaPTEBytesFrame;
+	unsigned int PixelPTEReqHeightPTEs = 0;
+	unsigned int HostVMDynamicLevels = 0;
+	double FractionOfPTEReturnDrop;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048) {
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		} else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		} else {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+		}
+	}
+
+	*MetaRequestHeight = 8 * BlockHeight256Bytes;
+	*MetaRequestWidth = 8 * BlockWidth256Bytes;
+	if (ScanDirection != dm_vert) {
+		*meta_row_height = *MetaRequestHeight;
+		*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestWidth) + *MetaRequestWidth;
+		*MetaRowByte = *meta_row_width * *MetaRequestHeight * BytePerPixel / 256.0;
+	} else {
+		*meta_row_height = *MetaRequestWidth;
+		*meta_row_width = dml_ceil((double) SwathWidth - 1, *MetaRequestHeight) + *MetaRequestHeight;
+		*MetaRowByte = *meta_row_width * *MetaRequestWidth * BytePerPixel / 256.0;
+	}
+	DCCMetaSurfaceBytes = DCCMetaPitch * (dml_ceil(ViewportHeight - 1, 64 * BlockHeight256Bytes) + 64 * BlockHeight256Bytes) * BytePerPixel / 256;
+	if (GPUVMEnable == true) {
+		*MetaPTEBytesFrame = (dml_ceil((double) (DCCMetaSurfaceBytes - 4.0 * 1024.0) / (8 * 4.0 * 1024), 1) + 1) * 64;
+		MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1);
+	} else {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+	}
+
+	if (DCCEnable != true) {
+		*MetaPTEBytesFrame = 0;
+		MPDEBytesFrame = 0;
+		*MetaRowByte = 0;
+	}
+
+	if (SurfaceTiling == dm_sw_linear) {
+		MacroTileSizeBytes = 256;
+		MacroTileHeight = BlockHeight256Bytes;
+	} else {
+		MacroTileSizeBytes = 65536;
+		MacroTileHeight = 16 * BlockHeight256Bytes;
+	}
+	*MacroTileWidth = MacroTileSizeBytes / BytePerPixel / MacroTileHeight;
+
+	if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {
+		if (ScanDirection != dm_vert) {
+			*DPDE0BytesFrame = 64
+					* (dml_ceil(
+							((Pitch * (dml_ceil(ViewportHeight - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes)
+									/ (8 * 2097152),
+							1) + 1);
+		} else {
+			*DPDE0BytesFrame = 64
+					* (dml_ceil(
+							((Pitch * (dml_ceil((double) SwathWidth - 1, MacroTileHeight) + MacroTileHeight) * BytePerPixel) - MacroTileSizeBytes)
+									/ (8 * 2097152),
+							1) + 1);
+		}
+		ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2);
+	} else {
+		*DPDE0BytesFrame = 0;
+		ExtraDPDEBytesFrame = 0;
+	}
+
+	PDEAndMetaPTEBytesFrame = *MetaPTEBytesFrame + MPDEBytesFrame + *DPDE0BytesFrame + ExtraDPDEBytesFrame;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MetaPTEBytesFrame = %d\n", __func__, *MetaPTEBytesFrame);
+	dml_print("DML::%s: MPDEBytesFrame = %d\n", __func__, MPDEBytesFrame);
+	dml_print("DML::%s: DPDE0BytesFrame = %d\n", __func__, *DPDE0BytesFrame);
+	dml_print("DML::%s: ExtraDPDEBytesFrame= %d\n", __func__, ExtraDPDEBytesFrame);
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+#endif
+
+	if (HostVMEnable == true) {
+		PDEAndMetaPTEBytesFrame = PDEAndMetaPTEBytesFrame * (1 + 8 * HostVMDynamicLevels);
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: PDEAndMetaPTEBytesFrame = %d\n", __func__, PDEAndMetaPTEBytesFrame);
+#endif
+
+	if (SurfaceTiling == dm_sw_linear) {
+		PixelPTEReqHeightPTEs = 1;
+		*PixelPTEReqHeight = 1;
+		*PixelPTEReqWidth = 32768.0 / BytePerPixel;
+		*PTERequestSize = 64;
+		FractionOfPTEReturnDrop = 0;
+	} else if (MacroTileSizeBytes == 4096) {
+		PixelPTEReqHeightPTEs = 1;
+		*PixelPTEReqHeight = MacroTileHeight;
+		*PixelPTEReqWidth = 8 * *MacroTileWidth;
+		*PTERequestSize = 64;
+		if (ScanDirection != dm_vert)
+			FractionOfPTEReturnDrop = 0;
+		else
+			FractionOfPTEReturnDrop = 7 / 8;
+	} else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) {
+		PixelPTEReqHeightPTEs = 16;
+		*PixelPTEReqHeight = 16 * BlockHeight256Bytes;
+		*PixelPTEReqWidth = 16 * BlockWidth256Bytes;
+		*PTERequestSize = 128;
+		FractionOfPTEReturnDrop = 0;
+	} else {
+		PixelPTEReqHeightPTEs = 1;
+		*PixelPTEReqHeight = MacroTileHeight;
+		*PixelPTEReqWidth = 8 * *MacroTileWidth;
+		*PTERequestSize = 64;
+		FractionOfPTEReturnDrop = 0;
+	}
+
+	if (SurfaceTiling == dm_sw_linear) {
+		*dpte_row_height = dml_min(128, 1 << (unsigned int) dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1));
+		*dpte_row_width_ub = (dml_ceil((double)(Pitch * *dpte_row_height - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
+	} else if (ScanDirection != dm_vert) {
+		*dpte_row_height = *PixelPTEReqHeight;
+		*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqWidth, 1) + 1) * *PixelPTEReqWidth;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqWidth * *PTERequestSize;
+	} else {
+		*dpte_row_height = dml_min(*PixelPTEReqWidth, *MacroTileWidth);
+		*dpte_row_width_ub = (dml_ceil((double) (SwathWidth - 1) / *PixelPTEReqHeight, 1) + 1) * *PixelPTEReqHeight;
+		*PixelPTEBytesPerRow = *dpte_row_width_ub / *PixelPTEReqHeight * *PTERequestSize;
+	}
+
+	if (*PixelPTEBytesPerRow * (1 - FractionOfPTEReturnDrop) <= 64 * PTEBufferSizeInRequests) {
+		*PTEBufferSizeNotExceeded = true;
+	} else {
+		*PTEBufferSizeNotExceeded = false;
+	}
+
+	if (GPUVMEnable != true) {
+		*PixelPTEBytesPerRow = 0;
+		*PTEBufferSizeNotExceeded = true;
+	}
+
+	dml_print("DML: vm_bytes = meta_pte_bytes_per_frame (per_pipe) = MetaPTEBytesFrame = : %i\n", *MetaPTEBytesFrame);
+
+	if (HostVMEnable == true) {
+		*PixelPTEBytesPerRow = *PixelPTEBytesPerRow * (1 + 8 * HostVMDynamicLevels);
+	}
+
+	if (HostVMEnable == true) {
+		*vm_group_bytes = 512;
+		*dpte_group_bytes = 512;
+	} else if (GPUVMEnable == true) {
+		*vm_group_bytes = 2048;
+		if (SurfaceTiling != dm_sw_linear && PixelPTEReqHeightPTEs == 1 && ScanDirection == dm_vert) {
+			*dpte_group_bytes = 512;
+		} else {
+			*dpte_group_bytes = 2048;
+		}
+	} else {
+		*vm_group_bytes = 0;
+		*dpte_group_bytes = 0;
+	}
+	return PDEAndMetaPTEBytesFrame;
+}
+
+static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	unsigned int j, k;
+	double HostVMInefficiencyFactor = 1.0;
+	bool NoChromaPlanes = true;
+	int ReorderBytes;
+	double VMDataOnlyReturnBW;
+	double MaxTotalRDBandwidth = 0;
+	int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
+
+	v->WritebackDISPCLK = 0.0;
+	v->DISPCLKWithRamping = 0;
+	v->DISPCLKWithoutRamping = 0;
+	v->GlobalDPPCLK = 0.0;
+	/* DAL custom code: need to update ReturnBW in case min dcfclk is overriden */
+	{
+	double IdealFabricAndSDPPortBandwidthPerState = dml_min(
+			v->ReturnBusWidth * v->DCFCLKState[v->VoltageLevel][v->maxMpcComb],
+			v->FabricClockPerState[v->VoltageLevel] * v->FabricDatapathToDCNDataReturn);
+	double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth;
+	if (v->HostVMEnable != true) {
+		v->ReturnBW = dml_min(
+				IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+				IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
+	} else {
+		v->ReturnBW = dml_min(
+				IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+				IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
+	}
+	}
+	/* End DAL custom code */
+
+	// DISPCLK and DPPCLK Calculation
+	//
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->WritebackEnable[k]) {
+			v->WritebackDISPCLK = dml_max(
+					v->WritebackDISPCLK,
+					dml31_CalculateWriteBackDISPCLK(
+							v->WritebackPixelFormat[k],
+							v->PixelClock[k],
+							v->WritebackHRatio[k],
+							v->WritebackVRatio[k],
+							v->WritebackHTaps[k],
+							v->WritebackVTaps[k],
+							v->WritebackSourceWidth[k],
+							v->WritebackDestinationWidth[k],
+							v->HTotal[k],
+							v->WritebackLineBufferSize));
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->HRatio[k] > 1) {
+			v->PSCL_THROUGHPUT_LUMA[k] = dml_min(
+					v->MaxDCHUBToPSCLThroughput,
+					v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1));
+		} else {
+			v->PSCL_THROUGHPUT_LUMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+		}
+
+		v->DPPCLKUsingSingleDPPLuma = v->PixelClock[k]
+				* dml_max(
+						v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
+						dml_max(v->HRatio[k] * v->VRatio[k] / v->PSCL_THROUGHPUT_LUMA[k], 1.0));
+
+		if ((v->htaps[k] > 6 || v->vtaps[k] > 6) && v->DPPCLKUsingSingleDPPLuma < 2 * v->PixelClock[k]) {
+			v->DPPCLKUsingSingleDPPLuma = 2 * v->PixelClock[k];
+		}
+
+		if ((v->SourcePixelFormat[k] != dm_420_8 && v->SourcePixelFormat[k] != dm_420_10 && v->SourcePixelFormat[k] != dm_420_12
+				&& v->SourcePixelFormat[k] != dm_rgbe_alpha)) {
+			v->PSCL_THROUGHPUT_CHROMA[k] = 0.0;
+			v->DPPCLKUsingSingleDPP[k] = v->DPPCLKUsingSingleDPPLuma;
+		} else {
+			if (v->HRatioChroma[k] > 1) {
+				v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(
+						v->MaxDCHUBToPSCLThroughput,
+						v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
+			} else {
+				v->PSCL_THROUGHPUT_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+			}
+			v->DPPCLKUsingSingleDPPChroma = v->PixelClock[k]
+					* dml_max3(
+							v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
+							v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_THROUGHPUT_CHROMA[k],
+							1.0);
+
+			if ((v->HTAPsChroma[k] > 6 || v->VTAPsChroma[k] > 6) && v->DPPCLKUsingSingleDPPChroma < 2 * v->PixelClock[k]) {
+				v->DPPCLKUsingSingleDPPChroma = 2 * v->PixelClock[k];
+			}
+
+			v->DPPCLKUsingSingleDPP[k] = dml_max(v->DPPCLKUsingSingleDPPLuma, v->DPPCLKUsingSingleDPPChroma);
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] != k)
+			continue;
+		if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1) {
+			v->DISPCLKWithRamping = dml_max(
+					v->DISPCLKWithRamping,
+					v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
+							* (1 + v->DISPCLKRampingMargin / 100));
+			v->DISPCLKWithoutRamping = dml_max(
+					v->DISPCLKWithoutRamping,
+					v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
+		} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
+			v->DISPCLKWithRamping = dml_max(
+					v->DISPCLKWithRamping,
+					v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100)
+							* (1 + v->DISPCLKRampingMargin / 100));
+			v->DISPCLKWithoutRamping = dml_max(
+					v->DISPCLKWithoutRamping,
+					v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
+		} else {
+			v->DISPCLKWithRamping = dml_max(
+					v->DISPCLKWithRamping,
+					v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) * (1 + v->DISPCLKRampingMargin / 100));
+			v->DISPCLKWithoutRamping = dml_max(
+					v->DISPCLKWithoutRamping,
+					v->PixelClock[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100));
+		}
+	}
+
+	v->DISPCLKWithRamping = dml_max(v->DISPCLKWithRamping, v->WritebackDISPCLK);
+	v->DISPCLKWithoutRamping = dml_max(v->DISPCLKWithoutRamping, v->WritebackDISPCLK);
+
+	ASSERT(v->DISPCLKDPPCLKVCOSpeed != 0);
+	v->DISPCLKWithRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithRamping, v->DISPCLKDPPCLKVCOSpeed);
+	v->DISPCLKWithoutRampingRoundedToDFSGranularity = RoundToDFSGranularityUp(v->DISPCLKWithoutRamping, v->DISPCLKDPPCLKVCOSpeed);
+	v->MaxDispclkRoundedToDFSGranularity = RoundToDFSGranularityDown(
+			v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
+			v->DISPCLKDPPCLKVCOSpeed);
+	if (v->DISPCLKWithoutRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
+		v->DISPCLK_calculated = v->DISPCLKWithoutRampingRoundedToDFSGranularity;
+	} else if (v->DISPCLKWithRampingRoundedToDFSGranularity > v->MaxDispclkRoundedToDFSGranularity) {
+		v->DISPCLK_calculated = v->MaxDispclkRoundedToDFSGranularity;
+	} else {
+		v->DISPCLK_calculated = v->DISPCLKWithRampingRoundedToDFSGranularity;
+	}
+	v->DISPCLK = v->DISPCLK_calculated;
+	DTRACE("   dispclk_mhz (calculated) = %f", v->DISPCLK_calculated);
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->DPPCLK_calculated[k] = v->DPPCLKUsingSingleDPP[k] / v->DPPPerPlane[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		v->GlobalDPPCLK = dml_max(v->GlobalDPPCLK, v->DPPCLK_calculated[k]);
+	}
+	v->GlobalDPPCLK = RoundToDFSGranularityUp(v->GlobalDPPCLK, v->DISPCLKDPPCLKVCOSpeed);
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->DPPCLK_calculated[k] = v->GlobalDPPCLK / 255 * dml_ceil(v->DPPCLK_calculated[k] * 255.0 / v->GlobalDPPCLK, 1);
+		DTRACE("   dppclk_mhz[%i] (calculated) = %f", k, v->DPPCLK_calculated[k]);
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->DPPCLK[k] = v->DPPCLK_calculated[k];
+	}
+
+	// Urgent and B P-State/DRAM Clock Change Watermark
+	DTRACE("   dcfclk_mhz         = %f", v->DCFCLK);
+	DTRACE("   return_bus_bw      = %f", v->ReturnBW);
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		CalculateBytePerPixelAnd256BBlockSizes(
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				&v->BytePerPixelY[k],
+				&v->BytePerPixelC[k],
+				&v->BytePerPixelDETY[k],
+				&v->BytePerPixelDETC[k],
+				&v->BlockHeight256BytesY[k],
+				&v->BlockHeight256BytesC[k],
+				&v->BlockWidth256BytesY[k],
+				&v->BlockWidth256BytesC[k]);
+	}
+
+	CalculateSwathWidth(
+			false,
+			v->NumberOfActivePlanes,
+			v->SourcePixelFormat,
+			v->SourceScan,
+			v->ViewportWidth,
+			v->ViewportHeight,
+			v->SurfaceWidthY,
+			v->SurfaceWidthC,
+			v->SurfaceHeightY,
+			v->SurfaceHeightC,
+			v->ODMCombineEnabled,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->BlockHeight256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesY,
+			v->BlockWidth256BytesC,
+			v->BlendingAndTiming,
+			v->HActive,
+			v->HRatio,
+			v->DPPPerPlane,
+			v->SwathWidthSingleDPPY,
+			v->SwathWidthSingleDPPC,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			v->dummyinteger3,
+			v->dummyinteger4,
+			v->swath_width_luma_ub,
+			v->swath_width_chroma_ub);
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->ReadBandwidthPlaneLuma[k] = v->SwathWidthSingleDPPY[k] * v->BytePerPixelY[k] / (v->HTotal[k] / v->PixelClock[k])
+				* v->VRatio[k];
+		v->ReadBandwidthPlaneChroma[k] = v->SwathWidthSingleDPPC[k] * v->BytePerPixelC[k] / (v->HTotal[k] / v->PixelClock[k])
+				* v->VRatioChroma[k];
+		DTRACE("   read_bw[%i] = %fBps", k, v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k]);
+	}
+
+	// DCFCLK Deep Sleep
+	CalculateDCFCLKDeepSleep(
+			mode_lib,
+			v->NumberOfActivePlanes,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->VRatio,
+			v->VRatioChroma,
+			v->SwathWidthY,
+			v->SwathWidthC,
+			v->DPPPerPlane,
+			v->HRatio,
+			v->HRatioChroma,
+			v->PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			v->DPPCLK,
+			v->ReadBandwidthPlaneLuma,
+			v->ReadBandwidthPlaneChroma,
+			v->ReturnBusWidth,
+			&v->DCFCLKDeepSleep);
+
+	// DSCCLK
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
+			v->DSCCLK_calculated[k] = 0.0;
+		} else {
+			if (v->OutputFormat[k] == dm_420)
+				v->DSCFormatFactor = 2;
+			else if (v->OutputFormat[k] == dm_444)
+				v->DSCFormatFactor = 1;
+			else if (v->OutputFormat[k] == dm_n422)
+				v->DSCFormatFactor = 2;
+			else
+				v->DSCFormatFactor = 1;
+			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
+				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
+						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
+				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
+						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+			else
+				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
+						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
+		}
+	}
+
+	// DSC Delay
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		double BPP = v->OutputBpp[k];
+
+		if (v->DSCEnabled[k] && BPP != 0) {
+			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_disabled) {
+				v->DSCDelay[k] = dscceComputeDelay(
+						v->DSCInputBitPerComponent[k],
+						BPP,
+						dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
+						v->NumberOfDSCSlices[k],
+						v->OutputFormat[k],
+						v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
+			} else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1) {
+				v->DSCDelay[k] = 2
+						* (dscceComputeDelay(
+								v->DSCInputBitPerComponent[k],
+								BPP,
+								dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
+								v->NumberOfDSCSlices[k] / 2.0,
+								v->OutputFormat[k],
+								v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+			} else {
+				v->DSCDelay[k] = 4
+						* (dscceComputeDelay(
+								v->DSCInputBitPerComponent[k],
+								BPP,
+								dml_ceil((double) v->HActive[k] / v->NumberOfDSCSlices[k], 1),
+								v->NumberOfDSCSlices[k] / 4.0,
+								v->OutputFormat[k],
+								v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+			}
+			v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
+		} else {
+			v->DSCDelay[k] = 0;
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k)
+		for (j = 0; j < v->NumberOfActivePlanes; ++j) // NumberOfPlanes
+			if (j != k && v->BlendingAndTiming[k] == j && v->DSCEnabled[j])
+				v->DSCDelay[k] = v->DSCDelay[j];
+
+	// Prefetch
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		unsigned int PDEAndMetaPTEBytesFrameY;
+		unsigned int PixelPTEBytesPerRowY;
+		unsigned int MetaRowByteY;
+		unsigned int MetaRowByteC;
+		unsigned int PDEAndMetaPTEBytesFrameC;
+		unsigned int PixelPTEBytesPerRowC;
+		bool PTEBufferSizeNotExceededY;
+		bool PTEBufferSizeNotExceededC;
+
+		if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
+				|| v->SourcePixelFormat[k] == dm_rgbe_alpha) {
+			if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) && v->SourceScan[k] != dm_vert) {
+				v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma) / 2;
+				v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
+			} else {
+				v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
+				v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
+			}
+
+			PDEAndMetaPTEBytesFrameC = CalculateVMAndRowBytes(
+					mode_lib,
+					v->DCCEnable[k],
+					v->BlockHeight256BytesC[k],
+					v->BlockWidth256BytesC[k],
+					v->SourcePixelFormat[k],
+					v->SurfaceTiling[k],
+					v->BytePerPixelC[k],
+					v->SourceScan[k],
+					v->SwathWidthC[k],
+					v->ViewportHeightChroma[k],
+					v->GPUVMEnable,
+					v->HostVMEnable,
+					v->HostVMMaxNonCachedPageTableLevels,
+					v->GPUVMMinPageSize,
+					v->HostVMMinPageSize,
+					v->PTEBufferSizeInRequestsForChroma,
+					v->PitchC[k],
+					v->DCCMetaPitchC[k],
+					&v->MacroTileWidthC[k],
+					&MetaRowByteC,
+					&PixelPTEBytesPerRowC,
+					&PTEBufferSizeNotExceededC,
+					&v->dpte_row_width_chroma_ub[k],
+					&v->dpte_row_height_chroma[k],
+					&v->meta_req_width_chroma[k],
+					&v->meta_req_height_chroma[k],
+					&v->meta_row_width_chroma[k],
+					&v->meta_row_height_chroma[k],
+					&v->dummyinteger1,
+					&v->dummyinteger2,
+					&v->PixelPTEReqWidthC[k],
+					&v->PixelPTEReqHeightC[k],
+					&v->PTERequestSizeC[k],
+					&v->dpde0_bytes_per_frame_ub_c[k],
+					&v->meta_pte_bytes_per_frame_ub_c[k]);
+
+			v->PrefetchSourceLinesC[k] = CalculatePrefetchSourceLines(
+					mode_lib,
+					v->VRatioChroma[k],
+					v->VTAPsChroma[k],
+					v->Interlace[k],
+					v->ProgressiveToInterlaceUnitInOPP,
+					v->SwathHeightC[k],
+					v->ViewportYStartC[k],
+					&v->VInitPreFillC[k],
+					&v->MaxNumSwathC[k]);
+		} else {
+			v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
+			v->PTEBufferSizeInRequestsForChroma = 0;
+			PixelPTEBytesPerRowC = 0;
+			PDEAndMetaPTEBytesFrameC = 0;
+			MetaRowByteC = 0;
+			v->MaxNumSwathC[k] = 0;
+			v->PrefetchSourceLinesC[k] = 0;
+		}
+
+		PDEAndMetaPTEBytesFrameY = CalculateVMAndRowBytes(
+				mode_lib,
+				v->DCCEnable[k],
+				v->BlockHeight256BytesY[k],
+				v->BlockWidth256BytesY[k],
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				v->BytePerPixelY[k],
+				v->SourceScan[k],
+				v->SwathWidthY[k],
+				v->ViewportHeight[k],
+				v->GPUVMEnable,
+				v->HostVMEnable,
+				v->HostVMMaxNonCachedPageTableLevels,
+				v->GPUVMMinPageSize,
+				v->HostVMMinPageSize,
+				v->PTEBufferSizeInRequestsForLuma,
+				v->PitchY[k],
+				v->DCCMetaPitchY[k],
+				&v->MacroTileWidthY[k],
+				&MetaRowByteY,
+				&PixelPTEBytesPerRowY,
+				&PTEBufferSizeNotExceededY,
+				&v->dpte_row_width_luma_ub[k],
+				&v->dpte_row_height[k],
+				&v->meta_req_width[k],
+				&v->meta_req_height[k],
+				&v->meta_row_width[k],
+				&v->meta_row_height[k],
+				&v->vm_group_bytes[k],
+				&v->dpte_group_bytes[k],
+				&v->PixelPTEReqWidthY[k],
+				&v->PixelPTEReqHeightY[k],
+				&v->PTERequestSizeY[k],
+				&v->dpde0_bytes_per_frame_ub_l[k],
+				&v->meta_pte_bytes_per_frame_ub_l[k]);
+
+		v->PrefetchSourceLinesY[k] = CalculatePrefetchSourceLines(
+				mode_lib,
+				v->VRatio[k],
+				v->vtaps[k],
+				v->Interlace[k],
+				v->ProgressiveToInterlaceUnitInOPP,
+				v->SwathHeightY[k],
+				v->ViewportYStartY[k],
+				&v->VInitPreFillY[k],
+				&v->MaxNumSwathY[k]);
+		v->PixelPTEBytesPerRow[k] = PixelPTEBytesPerRowY + PixelPTEBytesPerRowC;
+		v->PDEAndMetaPTEBytesFrame[k] = PDEAndMetaPTEBytesFrameY + PDEAndMetaPTEBytesFrameC;
+		v->MetaRowByte[k] = MetaRowByteY + MetaRowByteC;
+
+		CalculateRowBandwidth(
+				v->GPUVMEnable,
+				v->SourcePixelFormat[k],
+				v->VRatio[k],
+				v->VRatioChroma[k],
+				v->DCCEnable[k],
+				v->HTotal[k] / v->PixelClock[k],
+				MetaRowByteY,
+				MetaRowByteC,
+				v->meta_row_height[k],
+				v->meta_row_height_chroma[k],
+				PixelPTEBytesPerRowY,
+				PixelPTEBytesPerRowC,
+				v->dpte_row_height[k],
+				v->dpte_row_height_chroma[k],
+				&v->meta_row_bw[k],
+				&v->dpte_row_bw[k]);
+	}
+
+	v->TotalDCCActiveDPP = 0;
+	v->TotalActiveDPP = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->TotalActiveDPP = v->TotalActiveDPP + v->DPPPerPlane[k];
+		if (v->DCCEnable[k])
+			v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + v->DPPPerPlane[k];
+		if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12
+				|| v->SourcePixelFormat[k] == dm_rgbe_alpha)
+			NoChromaPlanes = false;
+	}
+
+	ReorderBytes = v->NumberOfChannels
+			* dml_max3(
+					v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	VMDataOnlyReturnBW = dml_min(
+			dml_min(v->ReturnBusWidth * v->DCFCLK, v->FabricClock * v->FabricDatapathToDCNDataReturn)
+					* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+			v->DRAMSpeed * v->NumberOfChannels * v->DRAMChannelWidth
+					* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: v->ReturnBusWidth = %f\n", __func__, v->ReturnBusWidth);
+	dml_print("DML::%s: v->DCFCLK = %f\n", __func__, v->DCFCLK);
+	dml_print("DML::%s: v->FabricClock = %f\n", __func__, v->FabricClock);
+	dml_print("DML::%s: v->FabricDatapathToDCNDataReturn = %f\n", __func__, v->FabricDatapathToDCNDataReturn);
+	dml_print("DML::%s: v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = %f\n", __func__, v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency);
+	dml_print("DML::%s: v->DRAMSpeed = %f\n", __func__, v->DRAMSpeed);
+	dml_print("DML::%s: v->NumberOfChannels = %f\n", __func__, v->NumberOfChannels);
+	dml_print("DML::%s: v->DRAMChannelWidth = %f\n", __func__, v->DRAMChannelWidth);
+	dml_print("DML::%s: v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = %f\n", __func__, v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly);
+	dml_print("DML::%s: VMDataOnlyReturnBW = %f\n", __func__, VMDataOnlyReturnBW);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, v->ReturnBW);
+#endif
+
+	if (v->GPUVMEnable && v->HostVMEnable)
+		HostVMInefficiencyFactor = v->ReturnBW / VMDataOnlyReturnBW;
+
+	v->UrgentExtraLatency = CalculateExtraLatency(
+			v->RoundTripPingLatencyCycles,
+			ReorderBytes,
+			v->DCFCLK,
+			v->TotalActiveDPP,
+			v->PixelChunkSizeInKByte,
+			v->TotalDCCActiveDPP,
+			v->MetaChunkSize,
+			v->ReturnBW,
+			v->GPUVMEnable,
+			v->HostVMEnable,
+			v->NumberOfActivePlanes,
+			v->DPPPerPlane,
+			v->dpte_group_bytes,
+			HostVMInefficiencyFactor,
+			v->HostVMMinPageSize,
+			v->HostVMMaxNonCachedPageTableLevels);
+
+	v->TCalc = 24.0 / v->DCFCLKDeepSleep;
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k) {
+			if (v->WritebackEnable[k] == true) {
+				v->WritebackDelay[v->VoltageLevel][k] = v->WritebackLatency
+						+ CalculateWriteBackDelay(
+								v->WritebackPixelFormat[k],
+								v->WritebackHRatio[k],
+								v->WritebackVRatio[k],
+								v->WritebackVTaps[k],
+								v->WritebackDestinationWidth[k],
+								v->WritebackDestinationHeight[k],
+								v->WritebackSourceHeight[k],
+								v->HTotal[k]) / v->DISPCLK;
+			} else
+				v->WritebackDelay[v->VoltageLevel][k] = 0;
+			for (j = 0; j < v->NumberOfActivePlanes; ++j) {
+				if (v->BlendingAndTiming[j] == k && v->WritebackEnable[j] == true) {
+					v->WritebackDelay[v->VoltageLevel][k] = dml_max(
+							v->WritebackDelay[v->VoltageLevel][k],
+							v->WritebackLatency
+									+ CalculateWriteBackDelay(
+											v->WritebackPixelFormat[j],
+											v->WritebackHRatio[j],
+											v->WritebackVRatio[j],
+											v->WritebackVTaps[j],
+											v->WritebackDestinationWidth[j],
+											v->WritebackDestinationHeight[j],
+											v->WritebackSourceHeight[j],
+											v->HTotal[k]) / v->DISPCLK);
+				}
+			}
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k)
+		for (j = 0; j < v->NumberOfActivePlanes; ++j)
+			if (v->BlendingAndTiming[k] == j)
+				v->WritebackDelay[v->VoltageLevel][k] = v->WritebackDelay[v->VoltageLevel][j];
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->MaxVStartupLines[k] =
+				(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
+						dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
+						v->VTotal[k] - v->VActive[k]
+								- dml_max(
+										1.0,
+										dml_ceil(
+												(double) v->WritebackDelay[v->VoltageLevel][k]
+														/ (v->HTotal[k] / v->PixelClock[k]),
+												1));
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d VoltageLevel = %d\n", __func__, k, v->VoltageLevel);
+		dml_print("DML::%s: k=%d WritebackDelay = %f\n", __func__, k, v->WritebackDelay[v->VoltageLevel][k]);
+#endif
+	}
+
+	v->MaximumMaxVStartupLines = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k)
+		v->MaximumMaxVStartupLines = dml_max(v->MaximumMaxVStartupLines, v->MaxVStartupLines[k]);
+
+	// VBA_DELTA
+	// We don't really care to iterate between the various prefetch modes
+	//v->PrefetchERROR = CalculateMinAndMaxPrefetchMode(v->AllowDRAMSelfRefreshOrDRAMClockChangeInVblank, &v->MinPrefetchMode, &v->MaxPrefetchMode);
+
+	v->UrgentLatency = CalculateUrgentLatency(
+			v->UrgentLatencyPixelDataOnly,
+			v->UrgentLatencyPixelMixedWithVMData,
+			v->UrgentLatencyVMDataOnly,
+			v->DoUrgentLatencyAdjustment,
+			v->UrgentLatencyAdjustmentFabricClockComponent,
+			v->UrgentLatencyAdjustmentFabricClockReference,
+			v->FabricClock);
+
+	v->FractionOfUrgentBandwidth = 0.0;
+	v->FractionOfUrgentBandwidthImmediateFlip = 0.0;
+
+	v->VStartupLines = __DML_VBA_MIN_VSTARTUP__;
+
+	do {
+		double MaxTotalRDBandwidthNoUrgentBurst = 0.0;
+		bool DestinationLineTimesForPrefetchLessThan2 = false;
+		bool VRatioPrefetchMoreThan4 = false;
+		double TWait = CalculateTWait(PrefetchMode, v->DRAMClockChangeLatency, v->UrgentLatency, v->SREnterPlusExitTime);
+		MaxTotalRDBandwidth = 0;
+
+		dml_print("DML::%s: Start loop: VStartup = %d\n", __func__, v->VStartupLines);
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			Pipe myPipe;
+
+			myPipe.DPPCLK = v->DPPCLK[k];
+			myPipe.DISPCLK = v->DISPCLK;
+			myPipe.PixelClock = v->PixelClock[k];
+			myPipe.DCFCLKDeepSleep = v->DCFCLKDeepSleep;
+			myPipe.DPPPerPlane = v->DPPPerPlane[k];
+			myPipe.ScalerEnabled = v->ScalerEnabled[k];
+			myPipe.SourceScan = v->SourceScan[k];
+			myPipe.BlockWidth256BytesY = v->BlockWidth256BytesY[k];
+			myPipe.BlockHeight256BytesY = v->BlockHeight256BytesY[k];
+			myPipe.BlockWidth256BytesC = v->BlockWidth256BytesC[k];
+			myPipe.BlockHeight256BytesC = v->BlockHeight256BytesC[k];
+			myPipe.InterlaceEnable = v->Interlace[k];
+			myPipe.NumberOfCursors = v->NumberOfCursors[k];
+			myPipe.VBlank = v->VTotal[k] - v->VActive[k];
+			myPipe.HTotal = v->HTotal[k];
+			myPipe.DCCEnable = v->DCCEnable[k];
+			myPipe.ODMCombineIsEnabled = v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1
+					|| v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1;
+			myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
+			myPipe.BytePerPixelY = v->BytePerPixelY[k];
+			myPipe.BytePerPixelC = v->BytePerPixelC[k];
+			myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
+			v->ErrorResult[k] = CalculatePrefetchSchedule(
+					mode_lib,
+					HostVMInefficiencyFactor,
+					&myPipe,
+					v->DSCDelay[k],
+					v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
+					v->DPPCLKDelaySCL,
+					v->DPPCLKDelaySCLLBOnly,
+					v->DPPCLKDelayCNVCCursor,
+					v->DISPCLKDelaySubtotal,
+					(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
+					v->OutputFormat[k],
+					v->MaxInterDCNTileRepeaters,
+					dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
+					v->MaxVStartupLines[k],
+					v->GPUVMMaxPageTableLevels,
+					v->GPUVMEnable,
+					v->HostVMEnable,
+					v->HostVMMaxNonCachedPageTableLevels,
+					v->HostVMMinPageSize,
+					v->DynamicMetadataEnable[k],
+					v->DynamicMetadataVMEnabled,
+					v->DynamicMetadataLinesBeforeActiveRequired[k],
+					v->DynamicMetadataTransmittedBytes[k],
+					v->UrgentLatency,
+					v->UrgentExtraLatency,
+					v->TCalc,
+					v->PDEAndMetaPTEBytesFrame[k],
+					v->MetaRowByte[k],
+					v->PixelPTEBytesPerRow[k],
+					v->PrefetchSourceLinesY[k],
+					v->SwathWidthY[k],
+					v->VInitPreFillY[k],
+					v->MaxNumSwathY[k],
+					v->PrefetchSourceLinesC[k],
+					v->SwathWidthC[k],
+					v->VInitPreFillC[k],
+					v->MaxNumSwathC[k],
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					v->SwathHeightY[k],
+					v->SwathHeightC[k],
+					TWait,
+					&v->DSTXAfterScaler[k],
+					&v->DSTYAfterScaler[k],
+					&v->DestinationLinesForPrefetch[k],
+					&v->PrefetchBandwidth[k],
+					&v->DestinationLinesToRequestVMInVBlank[k],
+					&v->DestinationLinesToRequestRowInVBlank[k],
+					&v->VRatioPrefetchY[k],
+					&v->VRatioPrefetchC[k],
+					&v->RequiredPrefetchPixDataBWLuma[k],
+					&v->RequiredPrefetchPixDataBWChroma[k],
+					&v->NotEnoughTimeForDynamicMetadata[k],
+					&v->Tno_bw[k],
+					&v->prefetch_vmrow_bw[k],
+					&v->Tdmdl_vm[k],
+					&v->Tdmdl[k],
+					&v->TSetup[k],
+					&v->VUpdateOffsetPix[k],
+					&v->VUpdateWidthPix[k],
+					&v->VReadyOffsetPix[k]);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d Prefetch cal result=%0d\n", __func__, k, v->ErrorResult[k]);
+#endif
+			v->VStartup[k] = dml_min(v->VStartupLines, v->MaxVStartupLines[k]);
+		}
+
+		v->NoEnoughUrgentLatencyHiding = false;
+		v->NoEnoughUrgentLatencyHidingPre = false;
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+					/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
+			v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+					/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPrefetchY[k];
+
+			CalculateUrgentBurstFactor(
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					v->SwathHeightY[k],
+					v->SwathHeightC[k],
+					v->HTotal[k] / v->PixelClock[k],
+					v->UrgentLatency,
+					v->CursorBufferSize,
+					v->CursorWidth[k][0],
+					v->CursorBPP[k][0],
+					v->VRatio[k],
+					v->VRatioChroma[k],
+					v->BytePerPixelDETY[k],
+					v->BytePerPixelDETC[k],
+					v->DETBufferSizeY[k],
+					v->DETBufferSizeC[k],
+					&v->UrgBurstFactorCursor[k],
+					&v->UrgBurstFactorLuma[k],
+					&v->UrgBurstFactorChroma[k],
+					&v->NoUrgentLatencyHiding[k]);
+
+			CalculateUrgentBurstFactor(
+					v->swath_width_luma_ub[k],
+					v->swath_width_chroma_ub[k],
+					v->SwathHeightY[k],
+					v->SwathHeightC[k],
+					v->HTotal[k] / v->PixelClock[k],
+					v->UrgentLatency,
+					v->CursorBufferSize,
+					v->CursorWidth[k][0],
+					v->CursorBPP[k][0],
+					v->VRatioPrefetchY[k],
+					v->VRatioPrefetchC[k],
+					v->BytePerPixelDETY[k],
+					v->BytePerPixelDETC[k],
+					v->DETBufferSizeY[k],
+					v->DETBufferSizeC[k],
+					&v->UrgBurstFactorCursorPre[k],
+					&v->UrgBurstFactorLumaPre[k],
+					&v->UrgBurstFactorChromaPre[k],
+					&v->NoUrgentLatencyHidingPre[k]);
+
+			MaxTotalRDBandwidth = MaxTotalRDBandwidth
+					+ dml_max3(
+							v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+							v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
+									+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
+									+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k]
+									+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
+							v->DPPPerPlane[k]
+									* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
+											+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
+									+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
+
+			MaxTotalRDBandwidthNoUrgentBurst = MaxTotalRDBandwidthNoUrgentBurst
+					+ dml_max3(
+							v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+							v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k]
+									+ v->DPPPerPlane[k] * (v->meta_row_bw[k] + v->dpte_row_bw[k]),
+							v->DPPPerPlane[k] * (v->RequiredPrefetchPixDataBWLuma[k] + v->RequiredPrefetchPixDataBWChroma[k])
+									+ v->cursor_bw_pre[k]);
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: k=%0d DPPPerPlane=%d\n", __func__, k, v->DPPPerPlane[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLuma=%f\n", __func__, k, v->UrgBurstFactorLuma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChroma=%f\n", __func__, k, v->UrgBurstFactorChroma[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorLumaPre=%f\n", __func__, k, v->UrgBurstFactorLumaPre[k]);
+			dml_print("DML::%s: k=%0d UrgBurstFactorChromaPre=%f\n", __func__, k, v->UrgBurstFactorChromaPre[k]);
+
+			dml_print("DML::%s: k=%0d VRatioPrefetchY=%f\n", __func__, k, v->VRatioPrefetchY[k]);
+			dml_print("DML::%s: k=%0d VRatioY=%f\n", __func__, k, v->VRatio[k]);
+
+			dml_print("DML::%s: k=%0d prefetch_vmrow_bw=%f\n", __func__, k, v->prefetch_vmrow_bw[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma=%f\n", __func__, k, v->ReadBandwidthPlaneLuma[k]);
+			dml_print("DML::%s: k=%0d ReadBandwidthPlaneChroma=%f\n", __func__, k, v->ReadBandwidthPlaneChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw=%f\n", __func__, k, v->cursor_bw[k]);
+			dml_print("DML::%s: k=%0d meta_row_bw=%f\n", __func__, k, v->meta_row_bw[k]);
+			dml_print("DML::%s: k=%0d dpte_row_bw=%f\n", __func__, k, v->dpte_row_bw[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWLuma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWLuma[k]);
+			dml_print("DML::%s: k=%0d RequiredPrefetchPixDataBWChroma=%f\n", __func__, k, v->RequiredPrefetchPixDataBWChroma[k]);
+			dml_print("DML::%s: k=%0d cursor_bw_pre=%f\n", __func__, k, v->cursor_bw_pre[k]);
+			dml_print("DML::%s: k=%0d MaxTotalRDBandwidthNoUrgentBurst=%f\n", __func__, k, MaxTotalRDBandwidthNoUrgentBurst);
+#endif
+
+			if (v->DestinationLinesForPrefetch[k] < 2)
+				DestinationLineTimesForPrefetchLessThan2 = true;
+
+			if (v->VRatioPrefetchY[k] > 4 || v->VRatioPrefetchC[k] > 4)
+				VRatioPrefetchMoreThan4 = true;
+
+			if (v->NoUrgentLatencyHiding[k] == true)
+				v->NoEnoughUrgentLatencyHiding = true;
+
+			if (v->NoUrgentLatencyHidingPre[k] == true)
+				v->NoEnoughUrgentLatencyHidingPre = true;
+		}
+
+		v->FractionOfUrgentBandwidth = MaxTotalRDBandwidthNoUrgentBurst / v->ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: MaxTotalRDBandwidthNoUrgentBurst=%f \n", __func__, MaxTotalRDBandwidthNoUrgentBurst);
+		dml_print("DML::%s: ReturnBW=%f \n", __func__, v->ReturnBW);
+		dml_print("DML::%s: FractionOfUrgentBandwidth=%f \n", __func__, v->FractionOfUrgentBandwidth);
+#endif
+
+		if (MaxTotalRDBandwidth <= v->ReturnBW && v->NoEnoughUrgentLatencyHiding == 0 && v->NoEnoughUrgentLatencyHidingPre == 0
+				&& !VRatioPrefetchMoreThan4 && !DestinationLineTimesForPrefetchLessThan2)
+			v->PrefetchModeSupported = true;
+		else {
+			v->PrefetchModeSupported = false;
+			dml_print("DML::%s: ***failed***. Bandwidth violation. Results are NOT valid\n", __func__);
+			dml_print("DML::%s: MaxTotalRDBandwidth:%f AvailReturnBandwidth:%f\n", __func__, MaxTotalRDBandwidth, v->ReturnBW);
+			dml_print("DML::%s: VRatioPrefetch %s more than 4\n", __func__, (VRatioPrefetchMoreThan4) ? "is" : "is not");
+			dml_print("DML::%s: DestinationLines for Prefetch %s less than 2\n", __func__, (DestinationLineTimesForPrefetchLessThan2) ? "is" : "is not");
+		}
+
+		// PREVIOUS_ERROR
+		// This error result check was done after the PrefetchModeSupported. So we will
+		// still try to calculate flip schedule even prefetch mode not supported
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->ErrorResult[k] == true || v->NotEnoughTimeForDynamicMetadata[k] == true) {
+				v->PrefetchModeSupported = false;
+				dml_print("DML::%s: ***failed***. Prefetch schedule violation. Results are NOT valid\n", __func__);
+			}
+		}
+
+		if (v->PrefetchModeSupported == true && v->ImmediateFlipSupport == true) {
+			v->BandwidthAvailableForImmediateFlip = v->ReturnBW;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
+						- dml_max(
+								v->ReadBandwidthPlaneLuma[k] * v->UrgBurstFactorLuma[k]
+										+ v->ReadBandwidthPlaneChroma[k] * v->UrgBurstFactorChroma[k]
+										+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
+								v->DPPPerPlane[k]
+										* (v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
+												+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
+										+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
+			}
+
+			v->TotImmediateFlipBytes = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
+						+ v->DPPPerPlane[k] * (v->PDEAndMetaPTEBytesFrame[k] + v->MetaRowByte[k] + v->PixelPTEBytesPerRow[k]);
+			}
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				CalculateFlipSchedule(
+						mode_lib,
+						HostVMInefficiencyFactor,
+						v->UrgentExtraLatency,
+						v->UrgentLatency,
+						v->GPUVMMaxPageTableLevels,
+						v->HostVMEnable,
+						v->HostVMMaxNonCachedPageTableLevels,
+						v->GPUVMEnable,
+						v->HostVMMinPageSize,
+						v->PDEAndMetaPTEBytesFrame[k],
+						v->MetaRowByte[k],
+						v->PixelPTEBytesPerRow[k],
+						v->BandwidthAvailableForImmediateFlip,
+						v->TotImmediateFlipBytes,
+						v->SourcePixelFormat[k],
+						v->HTotal[k] / v->PixelClock[k],
+						v->VRatio[k],
+						v->VRatioChroma[k],
+						v->Tno_bw[k],
+						v->DCCEnable[k],
+						v->dpte_row_height[k],
+						v->meta_row_height[k],
+						v->dpte_row_height_chroma[k],
+						v->meta_row_height_chroma[k],
+						&v->DestinationLinesToRequestVMInImmediateFlip[k],
+						&v->DestinationLinesToRequestRowInImmediateFlip[k],
+						&v->final_flip_bw[k],
+						&v->ImmediateFlipSupportedForPipe[k]);
+			}
+
+			v->total_dcn_read_bw_with_flip = 0.0;
+			v->total_dcn_read_bw_with_flip_no_urgent_burst = 0.0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
+						+ dml_max3(
+								v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+								v->DPPPerPlane[k] * v->final_flip_bw[k]
+										+ v->ReadBandwidthLuma[k] * v->UrgBurstFactorLuma[k]
+										+ v->ReadBandwidthChroma[k] * v->UrgBurstFactorChroma[k]
+										+ v->cursor_bw[k] * v->UrgBurstFactorCursor[k],
+								v->DPPPerPlane[k]
+										* (v->final_flip_bw[k]
+												+ v->RequiredPrefetchPixDataBWLuma[k] * v->UrgBurstFactorLumaPre[k]
+												+ v->RequiredPrefetchPixDataBWChroma[k] * v->UrgBurstFactorChromaPre[k])
+										+ v->cursor_bw_pre[k] * v->UrgBurstFactorCursorPre[k]);
+				v->total_dcn_read_bw_with_flip_no_urgent_burst = v->total_dcn_read_bw_with_flip_no_urgent_burst
+						+ dml_max3(
+								v->DPPPerPlane[k] * v->prefetch_vmrow_bw[k],
+								v->DPPPerPlane[k] * v->final_flip_bw[k] + v->ReadBandwidthPlaneLuma[k]
+										+ v->ReadBandwidthPlaneChroma[k] + v->cursor_bw[k],
+								v->DPPPerPlane[k]
+										* (v->final_flip_bw[k] + v->RequiredPrefetchPixDataBWLuma[k]
+												+ v->RequiredPrefetchPixDataBWChroma[k]) + v->cursor_bw_pre[k]);
+			}
+			v->FractionOfUrgentBandwidthImmediateFlip = v->total_dcn_read_bw_with_flip_no_urgent_burst / v->ReturnBW;
+
+			v->ImmediateFlipSupported = true;
+			if (v->total_dcn_read_bw_with_flip > v->ReturnBW) {
+#ifdef __DML_VBA_DEBUG__
+				dml_print("DML::%s: total_dcn_read_bw_with_flip %f (bw w/ flip too high!)\n", __func__, v->total_dcn_read_bw_with_flip);
+#endif
+				v->ImmediateFlipSupported = false;
+				v->total_dcn_read_bw_with_flip = MaxTotalRDBandwidth;
+			}
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				if (v->ImmediateFlipSupportedForPipe[k] == false) {
+#ifdef __DML_VBA_DEBUG__
+					dml_print("DML::%s: Pipe %0d not supporting iflip\n",
+						  __func__, k);
+#endif
+					v->ImmediateFlipSupported = false;
+				}
+			}
+		} else {
+			v->ImmediateFlipSupported = false;
+		}
+
+		v->PrefetchAndImmediateFlipSupported =
+				(v->PrefetchModeSupported == true
+						&& ((!v->ImmediateFlipSupport && !v->HostVMEnable
+								&& v->ImmediateFlipRequirement != dm_immediate_flip_required) || v->ImmediateFlipSupported)) ?
+						true : false;
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
+		dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
+		dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
+		dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
+		dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
+		dml_print("DML::%s: PrefetchAndImmediateFlipSupported %d\n", __func__, v->PrefetchAndImmediateFlipSupported);
+#endif
+		dml_print("DML::%s: Done loop: Vstartup=%d, Max Vstartup is %d\n", __func__, v->VStartupLines, v->MaximumMaxVStartupLines);
+
+		v->VStartupLines = v->VStartupLines + 1;
+	} while (!v->PrefetchAndImmediateFlipSupported && v->VStartupLines <= v->MaximumMaxVStartupLines);
+	ASSERT(v->PrefetchAndImmediateFlipSupported);
+
+	// Unbounded Request Enabled
+	CalculateUnboundedRequestAndCompressedBufferSize(
+			v->DETBufferSizeInKByte[0],
+			v->ConfigReturnBufferSizeInKByte,
+			v->UseUnboundedRequesting,
+			v->TotalActiveDPP,
+			NoChromaPlanes,
+			v->MaxNumDPP,
+			v->CompressedBufferSegmentSizeInkByte,
+			v->Output,
+			&v->UnboundedRequestEnabled,
+			&v->CompressedBufferSizeInkByte);
+
+	//Watermarks and NB P-State/DRAM Clock Change Support
+	{
+		enum clock_change_support DRAMClockChangeSupport; // dummy
+		CalculateWatermarksAndDRAMSpeedChangeSupport(
+				mode_lib,
+				PrefetchMode,
+				v->NumberOfActivePlanes,
+				v->MaxLineBufferLines,
+				v->LineBufferSize,
+				v->WritebackInterfaceBufferSize,
+				v->DCFCLK,
+				v->ReturnBW,
+				v->SynchronizedVBlank,
+				v->dpte_group_bytes,
+				v->MetaChunkSize,
+				v->UrgentLatency,
+				v->UrgentExtraLatency,
+				v->WritebackLatency,
+				v->WritebackChunkSize,
+				v->SOCCLK,
+				v->DRAMClockChangeLatency,
+				v->SRExitTime,
+				v->SREnterPlusExitTime,
+				v->SRExitZ8Time,
+				v->SREnterPlusExitZ8Time,
+				v->DCFCLKDeepSleep,
+				v->DETBufferSizeY,
+				v->DETBufferSizeC,
+				v->SwathHeightY,
+				v->SwathHeightC,
+				v->LBBitPerPixel,
+				v->SwathWidthY,
+				v->SwathWidthC,
+				v->HRatio,
+				v->HRatioChroma,
+				v->vtaps,
+				v->VTAPsChroma,
+				v->VRatio,
+				v->VRatioChroma,
+				v->HTotal,
+				v->PixelClock,
+				v->BlendingAndTiming,
+				v->DPPPerPlane,
+				v->BytePerPixelDETY,
+				v->BytePerPixelDETC,
+				v->DSTXAfterScaler,
+				v->DSTYAfterScaler,
+				v->WritebackEnable,
+				v->WritebackPixelFormat,
+				v->WritebackDestinationWidth,
+				v->WritebackDestinationHeight,
+				v->WritebackSourceHeight,
+				v->UnboundedRequestEnabled,
+				v->CompressedBufferSizeInkByte,
+				&DRAMClockChangeSupport,
+				&v->UrgentWatermark,
+				&v->WritebackUrgentWatermark,
+				&v->DRAMClockChangeWatermark,
+				&v->WritebackDRAMClockChangeWatermark,
+				&v->StutterExitWatermark,
+				&v->StutterEnterPlusExitWatermark,
+				&v->Z8StutterExitWatermark,
+				&v->Z8StutterEnterPlusExitWatermark,
+				&v->MinActiveDRAMClockChangeLatencySupported);
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->WritebackEnable[k] == true) {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(
+						0,
+						v->VStartup[k] * v->HTotal[k] / v->PixelClock[k] - v->WritebackDRAMClockChangeWatermark);
+			} else {
+				v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
+			}
+		}
+	}
+
+	//Display Pipeline Delivery Time in Prefetch, Groups
+	CalculatePixelDeliveryTimes(
+			v->NumberOfActivePlanes,
+			v->VRatio,
+			v->VRatioChroma,
+			v->VRatioPrefetchY,
+			v->VRatioPrefetchC,
+			v->swath_width_luma_ub,
+			v->swath_width_chroma_ub,
+			v->DPPPerPlane,
+			v->HRatio,
+			v->HRatioChroma,
+			v->PixelClock,
+			v->PSCL_THROUGHPUT_LUMA,
+			v->PSCL_THROUGHPUT_CHROMA,
+			v->DPPCLK,
+			v->BytePerPixelC,
+			v->SourceScan,
+			v->NumberOfCursors,
+			v->CursorWidth,
+			v->CursorBPP,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesC,
+			v->BlockHeight256BytesC,
+			v->DisplayPipeLineDeliveryTimeLuma,
+			v->DisplayPipeLineDeliveryTimeChroma,
+			v->DisplayPipeLineDeliveryTimeLumaPrefetch,
+			v->DisplayPipeLineDeliveryTimeChromaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeLuma,
+			v->DisplayPipeRequestDeliveryTimeChroma,
+			v->DisplayPipeRequestDeliveryTimeLumaPrefetch,
+			v->DisplayPipeRequestDeliveryTimeChromaPrefetch,
+			v->CursorRequestDeliveryTime,
+			v->CursorRequestDeliveryTimePrefetch);
+
+	CalculateMetaAndPTETimes(
+			v->NumberOfActivePlanes,
+			v->GPUVMEnable,
+			v->MetaChunkSize,
+			v->MinMetaChunkSizeBytes,
+			v->HTotal,
+			v->VRatio,
+			v->VRatioChroma,
+			v->DestinationLinesToRequestRowInVBlank,
+			v->DestinationLinesToRequestRowInImmediateFlip,
+			v->DCCEnable,
+			v->PixelClock,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->SourceScan,
+			v->dpte_row_height,
+			v->dpte_row_height_chroma,
+			v->meta_row_width,
+			v->meta_row_width_chroma,
+			v->meta_row_height,
+			v->meta_row_height_chroma,
+			v->meta_req_width,
+			v->meta_req_width_chroma,
+			v->meta_req_height,
+			v->meta_req_height_chroma,
+			v->dpte_group_bytes,
+			v->PTERequestSizeY,
+			v->PTERequestSizeC,
+			v->PixelPTEReqWidthY,
+			v->PixelPTEReqHeightY,
+			v->PixelPTEReqWidthC,
+			v->PixelPTEReqHeightC,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+			v->DST_Y_PER_PTE_ROW_NOM_L,
+			v->DST_Y_PER_PTE_ROW_NOM_C,
+			v->DST_Y_PER_META_ROW_NOM_L,
+			v->DST_Y_PER_META_ROW_NOM_C,
+			v->TimePerMetaChunkNominal,
+			v->TimePerChromaMetaChunkNominal,
+			v->TimePerMetaChunkVBlank,
+			v->TimePerChromaMetaChunkVBlank,
+			v->TimePerMetaChunkFlip,
+			v->TimePerChromaMetaChunkFlip,
+			v->time_per_pte_group_nom_luma,
+			v->time_per_pte_group_vblank_luma,
+			v->time_per_pte_group_flip_luma,
+			v->time_per_pte_group_nom_chroma,
+			v->time_per_pte_group_vblank_chroma,
+			v->time_per_pte_group_flip_chroma);
+
+	CalculateVMGroupAndRequestTimes(
+			v->NumberOfActivePlanes,
+			v->GPUVMEnable,
+			v->GPUVMMaxPageTableLevels,
+			v->HTotal,
+			v->BytePerPixelC,
+			v->DestinationLinesToRequestVMInVBlank,
+			v->DestinationLinesToRequestVMInImmediateFlip,
+			v->DCCEnable,
+			v->PixelClock,
+			v->dpte_row_width_luma_ub,
+			v->dpte_row_width_chroma_ub,
+			v->vm_group_bytes,
+			v->dpde0_bytes_per_frame_ub_l,
+			v->dpde0_bytes_per_frame_ub_c,
+			v->meta_pte_bytes_per_frame_ub_l,
+			v->meta_pte_bytes_per_frame_ub_c,
+			v->TimePerVMGroupVBlank,
+			v->TimePerVMGroupFlip,
+			v->TimePerVMRequestVBlank,
+			v->TimePerVMRequestFlip);
+
+	// Min TTUVBlank
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (PrefetchMode == 0) {
+			v->AllowDRAMClockChangeDuringVBlank[k] = true;
+			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
+			v->MinTTUVBlank[k] = dml_max(
+					v->DRAMClockChangeWatermark,
+					dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
+		} else if (PrefetchMode == 1) {
+			v->AllowDRAMClockChangeDuringVBlank[k] = false;
+			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
+			v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
+		} else {
+			v->AllowDRAMClockChangeDuringVBlank[k] = false;
+			v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
+			v->MinTTUVBlank[k] = v->UrgentWatermark;
+		}
+		if (!v->DynamicMetadataEnable[k])
+			v->MinTTUVBlank[k] = v->TCalc + v->MinTTUVBlank[k];
+	}
+
+	// DCC Configuration
+	v->ActiveDPPs = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		CalculateDCCConfiguration(v->DCCEnable[k], false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
+				v->SourcePixelFormat[k],
+				v->SurfaceWidthY[k],
+				v->SurfaceWidthC[k],
+				v->SurfaceHeightY[k],
+				v->SurfaceHeightC[k],
+				v->DETBufferSizeInKByte[0] * 1024,
+				v->BlockHeight256BytesY[k],
+				v->BlockHeight256BytesC[k],
+				v->SurfaceTiling[k],
+				v->BytePerPixelY[k],
+				v->BytePerPixelC[k],
+				v->BytePerPixelDETY[k],
+				v->BytePerPixelDETC[k],
+				v->SourceScan[k],
+				&v->DCCYMaxUncompressedBlock[k],
+				&v->DCCCMaxUncompressedBlock[k],
+				&v->DCCYMaxCompressedBlock[k],
+				&v->DCCCMaxCompressedBlock[k],
+				&v->DCCYIndependentBlock[k],
+				&v->DCCCIndependentBlock[k]);
+	}
+
+	// VStartup Adjustment
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		bool isInterlaceTiming;
+		double Tvstartup_margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k] / v->PixelClock[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f (before margin)\n", __func__, k, v->MinTTUVBlank[k]);
+#endif
+
+		v->MinTTUVBlank[k] = v->MinTTUVBlank[k] + Tvstartup_margin;
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, Tvstartup_margin = %f\n", __func__, k, Tvstartup_margin);
+		dml_print("DML::%s: k=%d, MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, MinTTUVBlank = %f\n", __func__, k, v->MinTTUVBlank[k]);
+#endif
+
+		v->Tdmdl[k] = v->Tdmdl[k] + Tvstartup_margin;
+		if (v->DynamicMetadataEnable[k] && v->DynamicMetadataVMEnabled) {
+			v->Tdmdl_vm[k] = v->Tdmdl_vm[k] + Tvstartup_margin;
+		}
+
+		isInterlaceTiming = (v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP);
+
+		v->MIN_DST_Y_NEXT_START[k] = ((isInterlaceTiming ? dml_floor((v->VTotal[k] - v->VFrontPorch[k]) / 2.0, 1.0) : v->VTotal[k])
+				- v->VFrontPorch[k])
+				+ dml_max(1.0, dml_ceil(v->WritebackDelay[v->VoltageLevel][k] / (v->HTotal[k] / v->PixelClock[k]), 1.0))
+				+ dml_floor(4.0 * v->TSetup[k] / (v->HTotal[k] / v->PixelClock[k]), 1.0) / 4.0;
+
+		v->VStartup[k] = (isInterlaceTiming ? (2 * v->MaxVStartupLines[k]) : v->MaxVStartupLines[k]);
+
+		if (((v->VUpdateOffsetPix[k] + v->VUpdateWidthPix[k] + v->VReadyOffsetPix[k]) / v->HTotal[k])
+				<= (isInterlaceTiming ?
+						dml_floor((v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]) / 2.0, 1.0) :
+						(int) (v->VTotal[k] - v->VActive[k] - v->VFrontPorch[k] - v->VStartup[k]))) {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = true;
+		} else {
+			v->VREADY_AT_OR_AFTER_VSYNC[k] = false;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d, VStartup = %d (max)\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, VUpdateOffsetPix = %d\n", __func__, k, v->VUpdateOffsetPix[k]);
+		dml_print("DML::%s: k=%d, VUpdateWidthPix = %d\n", __func__, k, v->VUpdateWidthPix[k]);
+		dml_print("DML::%s: k=%d, VReadyOffsetPix = %d\n", __func__, k, v->VReadyOffsetPix[k]);
+		dml_print("DML::%s: k=%d, HTotal = %d\n", __func__, k, v->HTotal[k]);
+		dml_print("DML::%s: k=%d, VTotal = %d\n", __func__, k, v->VTotal[k]);
+		dml_print("DML::%s: k=%d, VActive = %d\n", __func__, k, v->VActive[k]);
+		dml_print("DML::%s: k=%d, VFrontPorch = %d\n", __func__, k, v->VFrontPorch[k]);
+		dml_print("DML::%s: k=%d, VStartup = %d\n", __func__, k, v->VStartup[k]);
+		dml_print("DML::%s: k=%d, MIN_DST_Y_NEXT_START = %f\n", __func__, k, v->MIN_DST_Y_NEXT_START[k]);
+		dml_print("DML::%s: k=%d, VREADY_AT_OR_AFTER_VSYNC = %d\n", __func__, k, v->VREADY_AT_OR_AFTER_VSYNC[k]);
+#endif
+	}
+
+	{
+		//Maximum Bandwidth Used
+		double TotalWRBandwidth = 0;
+		double MaxPerPlaneVActiveWRBandwidth = 0;
+		double WRBandwidth = 0;
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_32) {
+				WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+						/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 4;
+			} else if (v->WritebackEnable[k] == true) {
+				WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+						/ (v->HTotal[k] * v->WritebackSourceHeight[k] / v->PixelClock[k]) * 8;
+			}
+			TotalWRBandwidth = TotalWRBandwidth + WRBandwidth;
+			MaxPerPlaneVActiveWRBandwidth = dml_max(MaxPerPlaneVActiveWRBandwidth, WRBandwidth);
+		}
+
+		v->TotalDataReadBandwidth = 0;
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			v->TotalDataReadBandwidth = v->TotalDataReadBandwidth + v->ReadBandwidthPlaneLuma[k] + v->ReadBandwidthPlaneChroma[k];
+		}
+	}
+	// Stutter Efficiency
+	CalculateStutterEfficiency(
+			mode_lib,
+			v->CompressedBufferSizeInkByte,
+			v->UnboundedRequestEnabled,
+			v->ConfigReturnBufferSizeInKByte,
+			v->MetaFIFOSizeInKEntries,
+			v->ZeroSizeBufferEntries,
+			v->NumberOfActivePlanes,
+			v->ROBBufferSizeInKByte,
+			v->TotalDataReadBandwidth,
+			v->DCFCLK,
+			v->ReturnBW,
+			v->COMPBUF_RESERVED_SPACE_64B,
+			v->COMPBUF_RESERVED_SPACE_ZS,
+			v->SRExitTime,
+			v->SRExitZ8Time,
+			v->SynchronizedVBlank,
+			v->StutterEnterPlusExitWatermark,
+			v->Z8StutterEnterPlusExitWatermark,
+			v->ProgressiveToInterlaceUnitInOPP,
+			v->Interlace,
+			v->MinTTUVBlank,
+			v->DPPPerPlane,
+			v->DETBufferSizeY,
+			v->BytePerPixelY,
+			v->BytePerPixelDETY,
+			v->SwathWidthY,
+			v->SwathHeightY,
+			v->SwathHeightC,
+			v->DCCRateLuma,
+			v->DCCRateChroma,
+			v->DCCFractionOfZeroSizeRequestsLuma,
+			v->DCCFractionOfZeroSizeRequestsChroma,
+			v->HTotal,
+			v->VTotal,
+			v->PixelClock,
+			v->VRatio,
+			v->SourceScan,
+			v->BlockHeight256BytesY,
+			v->BlockWidth256BytesY,
+			v->BlockHeight256BytesC,
+			v->BlockWidth256BytesC,
+			v->DCCYMaxUncompressedBlock,
+			v->DCCCMaxUncompressedBlock,
+			v->VActive,
+			v->DCCEnable,
+			v->WritebackEnable,
+			v->ReadBandwidthPlaneLuma,
+			v->ReadBandwidthPlaneChroma,
+			v->meta_row_bw,
+			v->dpte_row_bw,
+			&v->StutterEfficiencyNotIncludingVBlank,
+			&v->StutterEfficiency,
+			&v->NumberOfStutterBurstsPerFrame,
+			&v->Z8StutterEfficiencyNotIncludingVBlank,
+			&v->Z8StutterEfficiency,
+			&v->Z8NumberOfStutterBurstsPerFrame,
+			&v->StutterPeriod);
+}
+
+static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	// Display Pipe Configuration
+	double BytePerPixDETY[DC__NUM_DPP__MAX];
+	double BytePerPixDETC[DC__NUM_DPP__MAX];
+	int BytePerPixY[DC__NUM_DPP__MAX];
+	int BytePerPixC[DC__NUM_DPP__MAX];
+	int Read256BytesBlockHeightY[DC__NUM_DPP__MAX];
+	int Read256BytesBlockHeightC[DC__NUM_DPP__MAX];
+	int Read256BytesBlockWidthY[DC__NUM_DPP__MAX];
+	int Read256BytesBlockWidthC[DC__NUM_DPP__MAX];
+	double dummy1[DC__NUM_DPP__MAX];
+	double dummy2[DC__NUM_DPP__MAX];
+	double dummy3[DC__NUM_DPP__MAX];
+	double dummy4[DC__NUM_DPP__MAX];
+	int dummy5[DC__NUM_DPP__MAX];
+	int dummy6[DC__NUM_DPP__MAX];
+	bool dummy7[DC__NUM_DPP__MAX];
+	bool dummysinglestring;
+
+	unsigned int k;
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+
+		CalculateBytePerPixelAnd256BBlockSizes(
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				&BytePerPixY[k],
+				&BytePerPixC[k],
+				&BytePerPixDETY[k],
+				&BytePerPixDETC[k],
+				&Read256BytesBlockHeightY[k],
+				&Read256BytesBlockHeightC[k],
+				&Read256BytesBlockWidthY[k],
+				&Read256BytesBlockWidthC[k]);
+	}
+
+	CalculateSwathAndDETConfiguration(
+			false,
+			v->NumberOfActivePlanes,
+			v->DETBufferSizeInKByte[0],
+			dummy1,
+			dummy2,
+			v->SourceScan,
+			v->SourcePixelFormat,
+			v->SurfaceTiling,
+			v->ViewportWidth,
+			v->ViewportHeight,
+			v->SurfaceWidthY,
+			v->SurfaceWidthC,
+			v->SurfaceHeightY,
+			v->SurfaceHeightC,
+			Read256BytesBlockHeightY,
+			Read256BytesBlockHeightC,
+			Read256BytesBlockWidthY,
+			Read256BytesBlockWidthC,
+			v->ODMCombineEnabled,
+			v->BlendingAndTiming,
+			BytePerPixY,
+			BytePerPixC,
+			BytePerPixDETY,
+			BytePerPixDETC,
+			v->HActive,
+			v->HRatio,
+			v->HRatioChroma,
+			v->DPPPerPlane,
+			dummy5,
+			dummy6,
+			dummy3,
+			dummy4,
+			v->SwathHeightY,
+			v->SwathHeightC,
+			v->DETBufferSizeY,
+			v->DETBufferSizeC,
+			dummy7,
+			&dummysinglestring);
+}
+
+static bool CalculateBytePerPixelAnd256BBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double *BytePerPixelDETY,
+		double *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC)
+{
+	if (SourcePixelFormat == dm_444_64) {
+		*BytePerPixelDETY = 8;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 8;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_rgbe_alpha) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 1;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 1;
+	} else if (SourcePixelFormat == dm_420_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 2;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 2;
+	} else if (SourcePixelFormat == dm_420_12) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 4;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	} else {
+		*BytePerPixelDETY = 4.0 / 3;
+		*BytePerPixelDETC = 8.0 / 3;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	}
+
+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16
+			|| SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+		} else if (SourcePixelFormat == dm_444_64) {
+			*BlockHeight256BytesY = 4;
+		} else if (SourcePixelFormat == dm_444_8) {
+			*BlockHeight256BytesY = 16;
+		} else {
+			*BlockHeight256BytesY = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockHeight256BytesC = 0;
+		*BlockWidth256BytesC = 0;
+	} else {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+			*BlockHeight256BytesC = 1;
+		} else if (SourcePixelFormat == dm_rgbe_alpha) {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 16;
+		} else if (SourcePixelFormat == dm_420_8) {
+			*BlockHeight256BytesY = 16;
+			*BlockHeight256BytesC = 8;
+		} else {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
+	}
+	return true;
+}
+
+static double CalculateTWait(unsigned int PrefetchMode, double DRAMClockChangeLatency, double UrgentLatency, double SREnterPlusExitTime)
+{
+	if (PrefetchMode == 0) {
+		return dml_max(DRAMClockChangeLatency + UrgentLatency, dml_max(SREnterPlusExitTime, UrgentLatency));
+	} else if (PrefetchMode == 1) {
+		return dml_max(SREnterPlusExitTime, UrgentLatency);
+	} else {
+		return UrgentLatency;
+	}
+}
+
+double dml31_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		long WritebackSourceWidth,
+		long WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize)
+{
+	double DISPCLK_H, DISPCLK_V, DISPCLK_HB;
+
+	DISPCLK_H = PixelClock * dml_ceil(WritebackHTaps / 8.0, 1) / WritebackHRatio;
+	DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
+	DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
+	return dml_max3(DISPCLK_H, DISPCLK_V, DISPCLK_HB);
+}
+
+static double CalculateWriteBackDelay(
+		enum source_format_class WritebackPixelFormat,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackVTaps,
+		int WritebackDestinationWidth,
+		int WritebackDestinationHeight,
+		int WritebackSourceHeight,
+		unsigned int HTotal)
+{
+	double CalculateWriteBackDelay;
+	double Line_length;
+	double Output_lines_last_notclamped;
+	double WritebackVInit;
+
+	WritebackVInit = (WritebackVRatio + WritebackVTaps + 1) / 2;
+	Line_length = dml_max((double) WritebackDestinationWidth, dml_ceil(WritebackDestinationWidth / 6.0, 1) * WritebackVTaps);
+	Output_lines_last_notclamped = WritebackDestinationHeight - 1 - dml_ceil((WritebackSourceHeight - WritebackVInit) / WritebackVRatio, 1);
+	if (Output_lines_last_notclamped < 0) {
+		CalculateWriteBackDelay = 0;
+	} else {
+		CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length + (HTotal - WritebackDestinationWidth) + 80;
+	}
+	return CalculateWriteBackDelay;
+}
+
+static void CalculateVupdateAndDynamicMetadataParameters(
+		int MaxInterDCNTileRepeaters,
+		double DPPCLK,
+		double DISPCLK,
+		double DCFClkDeepSleep,
+		double PixelClock,
+		int HTotal,
+		int VBlank,
+		int DynamicMetadataTransmittedBytes,
+		int DynamicMetadataLinesBeforeActiveRequired,
+		int InterlaceEnable,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double *TSetup,
+		double *Tdmbf,
+		double *Tdmec,
+		double *Tdmsks,
+		int *VUpdateOffsetPix,
+		double *VUpdateWidthPix,
+		double *VReadyOffsetPix)
+{
+	double TotalRepeaterDelayTime;
+
+	TotalRepeaterDelayTime = MaxInterDCNTileRepeaters * (2 / DPPCLK + 3 / DISPCLK);
+	*VUpdateWidthPix = dml_ceil((14.0 / DCFClkDeepSleep + 12.0 / DPPCLK + TotalRepeaterDelayTime) * PixelClock, 1.0);
+	*VReadyOffsetPix = dml_ceil(dml_max(150.0 / DPPCLK, TotalRepeaterDelayTime + 20.0 / DCFClkDeepSleep + 10.0 / DPPCLK) * PixelClock, 1.0);
+	*VUpdateOffsetPix = dml_ceil(HTotal / 4.0, 1);
+	*TSetup = (*VUpdateOffsetPix + *VUpdateWidthPix + *VReadyOffsetPix) / PixelClock;
+	*Tdmbf = DynamicMetadataTransmittedBytes / 4.0 / DISPCLK;
+	*Tdmec = HTotal / PixelClock;
+	if (DynamicMetadataLinesBeforeActiveRequired == 0) {
+		*Tdmsks = VBlank * HTotal / PixelClock / 2.0;
+	} else {
+		*Tdmsks = DynamicMetadataLinesBeforeActiveRequired * HTotal / PixelClock;
+	}
+	if (InterlaceEnable == 1 && ProgressiveToInterlaceUnitInOPP == false) {
+		*Tdmsks = *Tdmsks / 2;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VUpdateWidthPix = %d\n", __func__, *VUpdateWidthPix);
+	dml_print("DML::%s: VReadyOffsetPix = %d\n", __func__, *VReadyOffsetPix);
+	dml_print("DML::%s: VUpdateOffsetPix = %d\n", __func__, *VUpdateOffsetPix);
+#endif
+}
+
+static void CalculateRowBandwidth(
+		bool GPUVMEnable,
+		enum source_format_class SourcePixelFormat,
+		double VRatio,
+		double VRatioChroma,
+		bool DCCEnable,
+		double LineTime,
+		unsigned int MetaRowByteLuma,
+		unsigned int MetaRowByteChroma,
+		unsigned int meta_row_height_luma,
+		unsigned int meta_row_height_chroma,
+		unsigned int PixelPTEBytesPerRowLuma,
+		unsigned int PixelPTEBytesPerRowChroma,
+		unsigned int dpte_row_height_luma,
+		unsigned int dpte_row_height_chroma,
+		double *meta_row_bw,
+		double *dpte_row_bw)
+{
+	if (DCCEnable != true) {
+		*meta_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || SourcePixelFormat == dm_rgbe_alpha) {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime) + VRatioChroma * MetaRowByteChroma / (meta_row_height_chroma * LineTime);
+	} else {
+		*meta_row_bw = VRatio * MetaRowByteLuma / (meta_row_height_luma * LineTime);
+	}
+
+	if (GPUVMEnable != true) {
+		*dpte_row_bw = 0;
+	} else if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_420_12 || SourcePixelFormat == dm_rgbe_alpha) {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime)
+				+ VRatioChroma * PixelPTEBytesPerRowChroma / (dpte_row_height_chroma * LineTime);
+	} else {
+		*dpte_row_bw = VRatio * PixelPTEBytesPerRowLuma / (dpte_row_height_luma * LineTime);
+	}
+}
+
+static void CalculateFlipSchedule(
+		struct display_mode_lib *mode_lib,
+		double HostVMInefficiencyFactor,
+		double UrgentExtraLatency,
+		double UrgentLatency,
+		unsigned int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		unsigned int HostVMMaxNonCachedPageTableLevels,
+		bool GPUVMEnable,
+		double HostVMMinPageSize,
+		double PDEAndMetaPTEBytesPerFrame,
+		double MetaRowBytes,
+		double DPTEBytesPerRow,
+		double BandwidthAvailableForImmediateFlip,
+		unsigned int TotImmediateFlipBytes,
+		enum source_format_class SourcePixelFormat,
+		double LineTime,
+		double VRatio,
+		double VRatioChroma,
+		double Tno_bw,
+		bool DCCEnable,
+		unsigned int dpte_row_height,
+		unsigned int meta_row_height,
+		unsigned int dpte_row_height_chroma,
+		unsigned int meta_row_height_chroma,
+		double *DestinationLinesToRequestVMInImmediateFlip,
+		double *DestinationLinesToRequestRowInImmediateFlip,
+		double *final_flip_bw,
+		bool *ImmediateFlipSupportedForPipe)
+{
+	double min_row_time = 0.0;
+	unsigned int HostVMDynamicLevelsTrips;
+	double TimeForFetchingMetaPTEImmediateFlip;
+	double TimeForFetchingRowInVBlankImmediateFlip;
+	double ImmediateFlipBW;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels;
+	} else {
+		HostVMDynamicLevelsTrips = 0;
+	}
+
+	if (GPUVMEnable == true || DCCEnable == true) {
+		ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes;
+	}
+
+	if (GPUVMEnable == true) {
+		TimeForFetchingMetaPTEImmediateFlip = dml_max3(
+				Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW,
+				UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1),
+				LineTime / 4.0);
+	} else {
+		TimeForFetchingMetaPTEImmediateFlip = 0;
+	}
+
+	*DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0;
+	if ((GPUVMEnable == true || DCCEnable == true)) {
+		TimeForFetchingRowInVBlankImmediateFlip = dml_max3(
+				(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW,
+				UrgentLatency * (HostVMDynamicLevelsTrips + 1),
+				LineTime / 4);
+	} else {
+		TimeForFetchingRowInVBlankImmediateFlip = 0;
+	}
+
+	*DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0;
+
+	if (GPUVMEnable == true) {
+		*final_flip_bw = dml_max(
+				PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime),
+				(MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime));
+	} else if ((GPUVMEnable == true || DCCEnable == true)) {
+		*final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime);
+	} else {
+		*final_flip_bw = 0;
+	}
+
+	if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma);
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma);
+		} else {
+			min_row_time = dml_min4(
+					dpte_row_height * LineTime / VRatio,
+					meta_row_height * LineTime / VRatio,
+					dpte_row_height_chroma * LineTime / VRatioChroma,
+					meta_row_height_chroma * LineTime / VRatioChroma);
+		}
+	} else {
+		if (GPUVMEnable == true && DCCEnable != true) {
+			min_row_time = dpte_row_height * LineTime / VRatio;
+		} else if (GPUVMEnable != true && DCCEnable == true) {
+			min_row_time = meta_row_height * LineTime / VRatio;
+		} else {
+			min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio);
+		}
+	}
+
+	if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16
+			|| TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) {
+		*ImmediateFlipSupportedForPipe = false;
+	} else {
+		*ImmediateFlipSupportedForPipe = true;
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestVMInImmediateFlip);
+	dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestRowInImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip);
+	dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", __func__, TimeForFetchingRowInVBlankImmediateFlip);
+	dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time);
+	dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe);
+#endif
+
+}
+
+static double TruncToValidBPP(
+		double LinkBitRate,
+		int Lanes,
+		int HTotal,
+		int HActive,
+		double PixelClock,
+		double DesiredBPP,
+		bool DSCEnable,
+		enum output_encoder_class Output,
+		enum output_format_class Format,
+		unsigned int DSCInputBitPerComponent,
+		int DSCSlices,
+		int AudioRate,
+		int AudioLayout,
+		enum odm_combine_mode ODMCombine)
+{
+	double MaxLinkBPP;
+	int MinDSCBPP;
+	double MaxDSCBPP;
+	int NonDSCBPP0;
+	int NonDSCBPP1;
+	int NonDSCBPP2;
+
+	if (Format == dm_420) {
+		NonDSCBPP0 = 12;
+		NonDSCBPP1 = 15;
+		NonDSCBPP2 = 18;
+		MinDSCBPP = 6;
+		MaxDSCBPP = 1.5 * DSCInputBitPerComponent - 1 / 16;
+	} else if (Format == dm_444) {
+		NonDSCBPP0 = 24;
+		NonDSCBPP1 = 30;
+		NonDSCBPP2 = 36;
+		MinDSCBPP = 8;
+		MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16;
+	} else {
+		if (Output == dm_hdmi) {
+			NonDSCBPP0 = 24;
+			NonDSCBPP1 = 24;
+			NonDSCBPP2 = 24;
+		} else {
+			NonDSCBPP0 = 16;
+			NonDSCBPP1 = 20;
+			NonDSCBPP2 = 24;
+		}
+		if (Format == dm_n422) {
+			MinDSCBPP = 7;
+			MaxDSCBPP = 2 * DSCInputBitPerComponent - 1.0 / 16.0;
+		} else {
+			MinDSCBPP = 8;
+			MaxDSCBPP = 3 * DSCInputBitPerComponent - 1.0 / 16.0;
+		}
+	}
+
+	if (DSCEnable && Output == dm_dp) {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock * (1 - 2.4 / 100);
+	} else {
+		MaxLinkBPP = LinkBitRate / 10 * 8 * Lanes / PixelClock;
+	}
+
+	if (ODMCombine == dm_odm_combine_mode_4to1 && MaxLinkBPP > 16) {
+		MaxLinkBPP = 16;
+	} else if (ODMCombine == dm_odm_combine_mode_2to1 && MaxLinkBPP > 32) {
+		MaxLinkBPP = 32;
+	}
+
+	if (DesiredBPP == 0) {
+		if (DSCEnable) {
+			if (MaxLinkBPP < MinDSCBPP) {
+				return BPP_INVALID;
+			} else if (MaxLinkBPP >= MaxDSCBPP) {
+				return MaxDSCBPP;
+			} else {
+				return dml_floor(16.0 * MaxLinkBPP, 1.0) / 16.0;
+			}
+		} else {
+			if (MaxLinkBPP >= NonDSCBPP2) {
+				return NonDSCBPP2;
+			} else if (MaxLinkBPP >= NonDSCBPP1) {
+				return NonDSCBPP1;
+			} else if (MaxLinkBPP >= NonDSCBPP0) {
+				return 16.0;
+			} else {
+				return BPP_INVALID;
+			}
+		}
+	} else {
+		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0))
+				|| (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
+			return BPP_INVALID;
+		} else {
+			return DesiredBPP;
+		}
+	}
+	return BPP_INVALID;
+}
+
+void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+
+	int i, j;
+	unsigned int k, m;
+	int ReorderingBytes;
+	int MinPrefetchMode = 0, MaxPrefetchMode = 2;
+	bool NoChroma = true;
+	bool EnoughWritebackUnits = true;
+	bool P2IWith420 = false;
+	bool DSCOnlyIfNecessaryWithBPP = false;
+	bool DSC422NativeNotSupported = false;
+	double MaxTotalVActiveRDBandwidth;
+	bool ViewportExceedsSurface = false;
+	bool FMTBufferExceeded = false;
+
+	/*MODE SUPPORT, VOLTAGE STATE AND SOC CONFIGURATION*/
+
+	CalculateMinAndMaxPrefetchMode(
+		mode_lib->vba.AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
+		&MinPrefetchMode, &MaxPrefetchMode);
+
+	/*Scale Ratio, taps Support Check*/
+
+	v->ScaleRatioAndTapsSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->ScalerEnabled[k] == false
+				&& ((v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
+						&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
+						&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
+						&& v->SourcePixelFormat[k] != dm_rgbe_alpha) || v->HRatio[k] != 1.0 || v->htaps[k] != 1.0
+						|| v->VRatio[k] != 1.0 || v->vtaps[k] != 1.0)) {
+			v->ScaleRatioAndTapsSupport = false;
+		} else if (v->vtaps[k] < 1.0 || v->vtaps[k] > 8.0 || v->htaps[k] < 1.0 || v->htaps[k] > 8.0
+				|| (v->htaps[k] > 1.0 && (v->htaps[k] % 2) == 1) || v->HRatio[k] > v->MaxHSCLRatio
+				|| v->VRatio[k] > v->MaxVSCLRatio || v->HRatio[k] > v->htaps[k]
+				|| v->VRatio[k] > v->vtaps[k]
+				|| (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32
+						&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_mono_16
+						&& v->SourcePixelFormat[k] != dm_mono_8 && v->SourcePixelFormat[k] != dm_rgbe
+						&& (v->VTAPsChroma[k] < 1 || v->VTAPsChroma[k] > 8 || v->HTAPsChroma[k] < 1
+								|| v->HTAPsChroma[k] > 8 || (v->HTAPsChroma[k] > 1 && v->HTAPsChroma[k] % 2 == 1)
+								|| v->HRatioChroma[k] > v->MaxHSCLRatio
+								|| v->VRatioChroma[k] > v->MaxVSCLRatio
+								|| v->HRatioChroma[k] > v->HTAPsChroma[k]
+								|| v->VRatioChroma[k] > v->VTAPsChroma[k]))) {
+			v->ScaleRatioAndTapsSupport = false;
+		}
+	}
+	/*Source Format, Pixel Format and Scan Support Check*/
+
+	v->SourceFormatPixelAndScanSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if ((v->SurfaceTiling[k] == dm_sw_linear && (!(v->SourceScan[k] != dm_vert) || v->DCCEnable[k] == true))
+				|| ((v->SurfaceTiling[k] == dm_sw_64kb_d || v->SurfaceTiling[k] == dm_sw_64kb_d_t
+						|| v->SurfaceTiling[k] == dm_sw_64kb_d_x) && !(v->SourcePixelFormat[k] == dm_444_64))) {
+			v->SourceFormatPixelAndScanSupport = false;
+		}
+	}
+	/*Bandwidth Support Check*/
+
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		CalculateBytePerPixelAnd256BBlockSizes(
+				v->SourcePixelFormat[k],
+				v->SurfaceTiling[k],
+				&v->BytePerPixelY[k],
+				&v->BytePerPixelC[k],
+				&v->BytePerPixelInDETY[k],
+				&v->BytePerPixelInDETC[k],
+				&v->Read256BlockHeightY[k],
+				&v->Read256BlockHeightC[k],
+				&v->Read256BlockWidthY[k],
+				&v->Read256BlockWidthC[k]);
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->SourceScan[k] != dm_vert) {
+			v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
+			v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
+		} else {
+			v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
+			v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
+		}
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		v->ReadBandwidthLuma[k] = v->SwathWidthYSingleDPP[k] * dml_ceil(v->BytePerPixelInDETY[k], 1.0)
+				/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
+		v->ReadBandwidthChroma[k] = v->SwathWidthYSingleDPP[k] / 2 * dml_ceil(v->BytePerPixelInDETC[k], 2.0)
+				/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k] / 2.0;
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true && v->WritebackPixelFormat[k] == dm_444_64) {
+			v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+					/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 8.0;
+		} else if (v->WritebackEnable[k] == true) {
+			v->WriteBandwidth[k] = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
+					/ (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4.0;
+		} else {
+			v->WriteBandwidth[k] = 0.0;
+		}
+	}
+
+	/*Writeback Latency support check*/
+
+	v->WritebackLatencySupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true && (v->WriteBandwidth[k] > v->WritebackInterfaceBufferSize * 1024 / v->WritebackLatency)) {
+			v->WritebackLatencySupport = false;
+		}
+	}
+
+	/*Writeback Mode Support Check*/
+
+	v->TotalNumberOfActiveWriteback = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true) {
+			v->TotalNumberOfActiveWriteback = v->TotalNumberOfActiveWriteback + 1;
+		}
+	}
+
+	if (v->TotalNumberOfActiveWriteback > v->MaxNumWriteback) {
+		EnoughWritebackUnits = false;
+	}
+
+	/*Writeback Scale Ratio and Taps Support Check*/
+
+	v->WritebackScaleRatioAndTapsSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true) {
+			if (v->WritebackHRatio[k] > v->WritebackMaxHSCLRatio || v->WritebackVRatio[k] > v->WritebackMaxVSCLRatio
+					|| v->WritebackHRatio[k] < v->WritebackMinHSCLRatio
+					|| v->WritebackVRatio[k] < v->WritebackMinVSCLRatio
+					|| v->WritebackHTaps[k] > v->WritebackMaxHSCLTaps
+					|| v->WritebackVTaps[k] > v->WritebackMaxVSCLTaps
+					|| v->WritebackHRatio[k] > v->WritebackHTaps[k] || v->WritebackVRatio[k] > v->WritebackVTaps[k]
+					|| (v->WritebackHTaps[k] > 2.0 && ((v->WritebackHTaps[k] % 2) == 1))) {
+				v->WritebackScaleRatioAndTapsSupport = false;
+			}
+			if (2.0 * v->WritebackDestinationWidth[k] * (v->WritebackVTaps[k] - 1) * 57 > v->WritebackLineBufferSize) {
+				v->WritebackScaleRatioAndTapsSupport = false;
+			}
+		}
+	}
+	/*Maximum DISPCLK/DPPCLK Support check*/
+
+	v->WritebackRequiredDISPCLK = 0.0;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->WritebackEnable[k] == true) {
+			v->WritebackRequiredDISPCLK = dml_max(
+					v->WritebackRequiredDISPCLK,
+					dml31_CalculateWriteBackDISPCLK(
+							v->WritebackPixelFormat[k],
+							v->PixelClock[k],
+							v->WritebackHRatio[k],
+							v->WritebackVRatio[k],
+							v->WritebackHTaps[k],
+							v->WritebackVTaps[k],
+							v->WritebackSourceWidth[k],
+							v->WritebackDestinationWidth[k],
+							v->HTotal[k],
+							v->WritebackLineBufferSize));
+		}
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->HRatio[k] > 1.0) {
+			v->PSCL_FACTOR[k] = dml_min(
+					v->MaxDCHUBToPSCLThroughput,
+					v->MaxPSCLToLBThroughput * v->HRatio[k] / dml_ceil(v->htaps[k] / 6.0, 1.0));
+		} else {
+			v->PSCL_FACTOR[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+		}
+		if (v->BytePerPixelC[k] == 0.0) {
+			v->PSCL_FACTOR_CHROMA[k] = 0.0;
+			v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
+					* dml_max3(
+							v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
+							v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
+							1.0);
+			if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0) && v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
+				v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
+			}
+		} else {
+			if (v->HRatioChroma[k] > 1.0) {
+				v->PSCL_FACTOR_CHROMA[k] = dml_min(
+						v->MaxDCHUBToPSCLThroughput,
+						v->MaxPSCLToLBThroughput * v->HRatioChroma[k] / dml_ceil(v->HTAPsChroma[k] / 6.0, 1.0));
+			} else {
+				v->PSCL_FACTOR_CHROMA[k] = dml_min(v->MaxDCHUBToPSCLThroughput, v->MaxPSCLToLBThroughput);
+			}
+			v->MinDPPCLKUsingSingleDPP[k] = v->PixelClock[k]
+					* dml_max5(
+							v->vtaps[k] / 6.0 * dml_min(1.0, v->HRatio[k]),
+							v->HRatio[k] * v->VRatio[k] / v->PSCL_FACTOR[k],
+							v->VTAPsChroma[k] / 6.0 * dml_min(1.0, v->HRatioChroma[k]),
+							v->HRatioChroma[k] * v->VRatioChroma[k] / v->PSCL_FACTOR_CHROMA[k],
+							1.0);
+			if ((v->htaps[k] > 6.0 || v->vtaps[k] > 6.0 || v->HTAPsChroma[k] > 6.0 || v->VTAPsChroma[k] > 6.0)
+					&& v->MinDPPCLKUsingSingleDPP[k] < 2.0 * v->PixelClock[k]) {
+				v->MinDPPCLKUsingSingleDPP[k] = 2.0 * v->PixelClock[k];
+			}
+		}
+	}
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		int MaximumSwathWidthSupportLuma;
+		int MaximumSwathWidthSupportChroma;
+
+		if (v->SurfaceTiling[k] == dm_sw_linear) {
+			MaximumSwathWidthSupportLuma = 8192.0;
+		} else if (v->SourceScan[k] == dm_vert && v->BytePerPixelC[k] > 0) {
+			MaximumSwathWidthSupportLuma = 2880.0;
+		} else if (v->SourcePixelFormat[k] == dm_rgbe_alpha) {
+			MaximumSwathWidthSupportLuma = 3840.0;
+		} else {
+			MaximumSwathWidthSupportLuma = 5760.0;
+		}
+
+		if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12) {
+			MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma / 2.0;
+		} else {
+			MaximumSwathWidthSupportChroma = MaximumSwathWidthSupportLuma;
+		}
+		v->MaximumSwathWidthInLineBufferLuma = v->LineBufferSize * dml_max(v->HRatio[k], 1.0) / v->LBBitPerPixel[k]
+				/ (v->vtaps[k] + dml_max(dml_ceil(v->VRatio[k], 1.0) - 2, 0.0));
+		if (v->BytePerPixelC[k] == 0.0) {
+			v->MaximumSwathWidthInLineBufferChroma = 0;
+		} else {
+			v->MaximumSwathWidthInLineBufferChroma = v->LineBufferSize * dml_max(v->HRatioChroma[k], 1.0) / v->LBBitPerPixel[k]
+					/ (v->VTAPsChroma[k] + dml_max(dml_ceil(v->VRatioChroma[k], 1.0) - 2, 0.0));
+		}
+		v->MaximumSwathWidthLuma[k] = dml_min(MaximumSwathWidthSupportLuma, v->MaximumSwathWidthInLineBufferLuma);
+		v->MaximumSwathWidthChroma[k] = dml_min(MaximumSwathWidthSupportChroma, v->MaximumSwathWidthInLineBufferChroma);
+	}
+
+	CalculateSwathAndDETConfiguration(
+			true,
+			v->NumberOfActivePlanes,
+			v->DETBufferSizeInKByte[0],
+			v->MaximumSwathWidthLuma,
+			v->MaximumSwathWidthChroma,
+			v->SourceScan,
+			v->SourcePixelFormat,
+			v->SurfaceTiling,
+			v->ViewportWidth,
+			v->ViewportHeight,
+			v->SurfaceWidthY,
+			v->SurfaceWidthC,
+			v->SurfaceHeightY,
+			v->SurfaceHeightC,
+			v->Read256BlockHeightY,
+			v->Read256BlockHeightC,
+			v->Read256BlockWidthY,
+			v->Read256BlockWidthC,
+			v->odm_combine_dummy,
+			v->BlendingAndTiming,
+			v->BytePerPixelY,
+			v->BytePerPixelC,
+			v->BytePerPixelInDETY,
+			v->BytePerPixelInDETC,
+			v->HActive,
+			v->HRatio,
+			v->HRatioChroma,
+			v->NoOfDPPThisState,
+			v->swath_width_luma_ub_this_state,
+			v->swath_width_chroma_ub_this_state,
+			v->SwathWidthYThisState,
+			v->SwathWidthCThisState,
+			v->SwathHeightYThisState,
+			v->SwathHeightCThisState,
+			v->DETBufferSizeYThisState,
+			v->DETBufferSizeCThisState,
+			v->SingleDPPViewportSizeSupportPerPlane,
+			&v->ViewportSizeSupport[0][0]);
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			v->MaxDispclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDispclk[i], v->DISPCLKDPPCLKVCOSpeed);
+			v->MaxDppclkRoundedDownToDFSGranularity = RoundToDFSGranularityDown(v->MaxDppclk[i], v->DISPCLKDPPCLKVCOSpeed);
+			v->RequiredDISPCLK[i][j] = 0.0;
+			v->DISPCLK_DPPCLK_Support[i][j] = true;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						* (1.0 + v->DISPCLKRampingMargin / 100.0);
+				if ((v->PlaneRequiredDISPCLKWithoutODMCombine >= v->MaxDispclk[i]
+						&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+					v->PlaneRequiredDISPCLKWithoutODMCombine = v->PixelClock[k]
+							* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				}
+				v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						* (1 + v->DISPCLKRampingMargin / 100.0);
+				if ((v->PlaneRequiredDISPCLKWithODMCombine2To1 >= v->MaxDispclk[i]
+						&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+					v->PlaneRequiredDISPCLKWithODMCombine2To1 = v->PixelClock[k] / 2
+							* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				}
+				v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4 * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						* (1 + v->DISPCLKRampingMargin / 100.0);
+				if ((v->PlaneRequiredDISPCLKWithODMCombine4To1 >= v->MaxDispclk[i]
+						&& v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+						&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+					v->PlaneRequiredDISPCLKWithODMCombine4To1 = v->PixelClock[k] / 4
+							* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				}
+
+				if (v->ODMCombinePolicy == dm_odm_combine_policy_none
+						|| !(v->Output[k] == dm_dp ||
+						     v->Output[k] == dm_edp)) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
+
+					if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
+						FMTBufferExceeded = true;
+				} else if (v->ODMCombinePolicy == dm_odm_combine_policy_2to1) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+				} else if (v->ODMCombinePolicy == dm_odm_combine_policy_4to1
+						|| v->PlaneRequiredDISPCLKWithODMCombine2To1 > v->MaxDispclkRoundedDownToDFSGranularity) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+				} else if (v->PlaneRequiredDISPCLKWithoutODMCombine > v->MaxDispclkRoundedDownToDFSGranularity) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+				} else {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
+					v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithoutODMCombine;
+				}
+				if (v->DSCEnabled[k] && v->HActive[k] > DCN31_MAX_DSC_IMAGE_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN31_MAX_DSC_IMAGE_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
+						&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
+					if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
+
+						if (v->HActive[k] / 4 > DCN31_MAX_FMT_420_BUFFER_WIDTH)
+							FMTBufferExceeded = true;
+					} else {
+						v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
+						v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine2To1;
+					}
+				}
+				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					v->MPCCombine[i][j][k] = false;
+					v->NoOfDPP[i][j][k] = 4;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 4;
+				} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					v->MPCCombine[i][j][k] = false;
+					v->NoOfDPP[i][j][k] = 2;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2;
+				} else if ((v->WhenToDoMPCCombine == dm_mpc_never
+						|| (v->MinDPPCLKUsingSingleDPP[k] * (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+								<= v->MaxDppclkRoundedDownToDFSGranularity && v->SingleDPPViewportSizeSupportPerPlane[k] == true))) {
+					v->MPCCombine[i][j][k] = false;
+					v->NoOfDPP[i][j][k] = 1;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+				} else {
+					v->MPCCombine[i][j][k] = true;
+					v->NoOfDPP[i][j][k] = 2;
+					v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
+				}
+				v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
+				if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+						> v->MaxDppclkRoundedDownToDFSGranularity)
+						|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
+					v->DISPCLK_DPPCLK_Support[i][j] = false;
+				}
+			}
+			v->TotalNumberOfActiveDPP[i][j] = 0;
+			v->TotalNumberOfSingleDPPPlanes[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
+				if (v->NoOfDPP[i][j][k] == 1)
+					v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] + 1;
+				if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
+						|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha)
+					NoChroma = false;
+			}
+
+			// UPTO
+			if (j == 1 && v->WhenToDoMPCCombine != dm_mpc_never
+					&& !UnboundedRequest(v->UseUnboundedRequesting, v->TotalNumberOfActiveDPP[i][j], NoChroma, v->Output[0])) {
+				while (!(v->TotalNumberOfActiveDPP[i][j] >= v->MaxNumDPP || v->TotalNumberOfSingleDPPPlanes[i][j] == 0)) {
+					double BWOfNonSplitPlaneOfMaximumBandwidth;
+					unsigned int NumberOfNonSplitPlaneOfMaximumBandwidth;
+					BWOfNonSplitPlaneOfMaximumBandwidth = 0;
+					NumberOfNonSplitPlaneOfMaximumBandwidth = 0;
+					for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+						if (v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k] > BWOfNonSplitPlaneOfMaximumBandwidth
+								&& v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled && v->MPCCombine[i][j][k] == false) {
+							BWOfNonSplitPlaneOfMaximumBandwidth = v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
+							NumberOfNonSplitPlaneOfMaximumBandwidth = k;
+						}
+					}
+					v->MPCCombine[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = true;
+					v->NoOfDPP[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] = 2;
+					v->RequiredDPPCLK[i][j][NumberOfNonSplitPlaneOfMaximumBandwidth] =
+							v->MinDPPCLKUsingSingleDPP[NumberOfNonSplitPlaneOfMaximumBandwidth]
+									* (1 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100) / 2;
+					v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + 1;
+					v->TotalNumberOfSingleDPPPlanes[i][j] = v->TotalNumberOfSingleDPPPlanes[i][j] - 1;
+				}
+			}
+			if (v->TotalNumberOfActiveDPP[i][j] > v->MaxNumDPP) {
+				v->RequiredDISPCLK[i][j] = 0.0;
+				v->DISPCLK_DPPCLK_Support[i][j] = true;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_disabled;
+					if (v->SingleDPPViewportSizeSupportPerPlane[k] == false && v->WhenToDoMPCCombine != dm_mpc_never) {
+						v->MPCCombine[i][j][k] = true;
+						v->NoOfDPP[i][j][k] = 2;
+						v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
+								* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0) / 2.0;
+					} else {
+						v->MPCCombine[i][j][k] = false;
+						v->NoOfDPP[i][j][k] = 1;
+						v->RequiredDPPCLK[i][j][k] = v->MinDPPCLKUsingSingleDPP[k]
+								* (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+					}
+					if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
+							&& v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
+						v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+								* (1.0 + v->DISPCLKRampingMargin / 100.0);
+					} else {
+						v->PlaneRequiredDISPCLK = v->PixelClock[k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
+					}
+					v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->PlaneRequiredDISPCLK);
+					if ((v->MinDPPCLKUsingSingleDPP[k] / v->NoOfDPP[i][j][k] * (1.0 + v->DISPCLKDPPCLKDSCCLKDownSpreading / 100.0)
+							> v->MaxDppclkRoundedDownToDFSGranularity)
+							|| (v->PlaneRequiredDISPCLK > v->MaxDispclkRoundedDownToDFSGranularity)) {
+						v->DISPCLK_DPPCLK_Support[i][j] = false;
+					}
+				}
+				v->TotalNumberOfActiveDPP[i][j] = 0.0;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					v->TotalNumberOfActiveDPP[i][j] = v->TotalNumberOfActiveDPP[i][j] + v->NoOfDPP[i][j][k];
+				}
+			}
+			v->RequiredDISPCLK[i][j] = dml_max(v->RequiredDISPCLK[i][j], v->WritebackRequiredDISPCLK);
+			if (v->MaxDispclkRoundedDownToDFSGranularity < v->WritebackRequiredDISPCLK) {
+				v->DISPCLK_DPPCLK_Support[i][j] = false;
+			}
+		}
+	}
+
+	/*Total Available Pipes Support Check*/
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			if (v->TotalNumberOfActiveDPP[i][j] <= v->MaxNumDPP) {
+				v->TotalAvailablePipesSupport[i][j] = true;
+			} else {
+				v->TotalAvailablePipesSupport[i][j] = false;
+			}
+		}
+	}
+	/*Display IO and DSC Support Check*/
+
+	v->NonsupportedDSCInputBPC = false;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (!(v->DSCInputBitPerComponent[k] == 12.0 || v->DSCInputBitPerComponent[k] == 10.0 || v->DSCInputBitPerComponent[k] == 8.0)
+				|| v->DSCInputBitPerComponent[k] > v->MaximumDSCBitsPerComponent) {
+			v->NonsupportedDSCInputBPC = true;
+		}
+	}
+
+	/*Number Of DSC Slices*/
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k) {
+			if (v->PixelClockBackEnd[k] > 3200) {
+				v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0);
+			} else if (v->PixelClockBackEnd[k] > 1360) {
+				v->NumberOfDSCSlices[k] = 8;
+			} else if (v->PixelClockBackEnd[k] > 680) {
+				v->NumberOfDSCSlices[k] = 4;
+			} else if (v->PixelClockBackEnd[k] > 340) {
+				v->NumberOfDSCSlices[k] = 2;
+			} else {
+				v->NumberOfDSCSlices[k] = 1;
+			}
+		} else {
+			v->NumberOfDSCSlices[k] = 0;
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			v->RequiresDSC[i][k] = false;
+			v->RequiresFEC[i][k] = false;
+			if (v->BlendingAndTiming[k] == k) {
+				if (v->Output[k] == dm_hdmi) {
+					v->RequiresDSC[i][k] = false;
+					v->RequiresFEC[i][k] = false;
+					v->OutputBppPerState[i][k] = TruncToValidBPP(
+							dml_min(600.0, v->PHYCLKPerState[i]) * 10,
+							3,
+							v->HTotal[k],
+							v->HActive[k],
+							v->PixelClockBackEnd[k],
+							v->ForcedOutputLinkBPP[k],
+							false,
+							v->Output[k],
+							v->OutputFormat[k],
+							v->DSCInputBitPerComponent[k],
+							v->NumberOfDSCSlices[k],
+							v->AudioSampleRate[k],
+							v->AudioSampleLayout[k],
+							v->ODMCombineEnablePerState[i][k]);
+				} else if (v->Output[k] == dm_dp || v->Output[k] == dm_edp) {
+					if (v->DSCEnable[k] == true) {
+						v->RequiresDSC[i][k] = true;
+						v->LinkDSCEnable = true;
+						if (v->Output[k] == dm_dp) {
+							v->RequiresFEC[i][k] = true;
+						} else {
+							v->RequiresFEC[i][k] = false;
+						}
+					} else {
+						v->RequiresDSC[i][k] = false;
+						v->LinkDSCEnable = false;
+						v->RequiresFEC[i][k] = false;
+					}
+
+					v->Outbpp = BPP_INVALID;
+					if (v->PHYCLKPerState[i] >= 270.0) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 2700,
+								v->OutputLinkDPLanes[k],
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						// TODO: Need some other way to handle this nonsense
+						// v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR"
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 540.0) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 5400,
+								v->OutputLinkDPLanes[k],
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						// TODO: Need some other way to handle this nonsense
+						// v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR2"
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKPerState[i] >= 810.0) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 8100,
+								v->OutputLinkDPLanes[k],
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						// TODO: Need some other way to handle this nonsense
+						// v->OutputTypeAndRatePerState[i][k] = v->Output[k] & " HBR3"
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[i] >= 10000.0 / 18) {
+						v->Outbpp = TruncToValidBPP(
+								(1.0 - v->Downspreading / 100.0) * 10000,
+								4,
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						//v->OutputTypeAndRatePerState[i][k] = v->Output[k] & "10x4";
+					}
+					if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[i] >= 12000.0 / 18) {
+						v->Outbpp = TruncToValidBPP(
+								12000,
+								4,
+								v->HTotal[k],
+								v->HActive[k],
+								v->PixelClockBackEnd[k],
+								v->ForcedOutputLinkBPP[k],
+								v->LinkDSCEnable,
+								v->Output[k],
+								v->OutputFormat[k],
+								v->DSCInputBitPerComponent[k],
+								v->NumberOfDSCSlices[k],
+								v->AudioSampleRate[k],
+								v->AudioSampleLayout[k],
+								v->ODMCombineEnablePerState[i][k]);
+						v->OutputBppPerState[i][k] = v->Outbpp;
+						//v->OutputTypeAndRatePerState[i][k] = v->Output[k] & "12x4";
+					}
+				}
+			} else {
+				v->OutputBppPerState[i][k] = 0;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		v->LinkCapacitySupport[i] = true;
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			if (v->BlendingAndTiming[k] == k
+					&& (v->Output[k] == dm_dp ||
+					    v->Output[k] == dm_edp ||
+					    v->Output[k] == dm_hdmi) && v->OutputBppPerState[i][k] == 0) {
+				v->LinkCapacitySupport[i] = false;
+			}
+		}
+	}
+
+	// UPTO 2172
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k
+				&& (v->Output[k] == dm_dp ||
+				    v->Output[k] == dm_edp ||
+				    v->Output[k] == dm_hdmi)) {
+			if (v->OutputFormat[k] == dm_420 && v->Interlace[k] == 1 && v->ProgressiveToInterlaceUnitInOPP == true) {
+				P2IWith420 = true;
+			}
+			if (v->DSCEnable[k] == true && v->OutputFormat[k] == dm_n422
+					&& !v->DSC422NativeSupport) {
+				DSC422NativeNotSupported = true;
+			}
+		}
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		v->ODMCombine4To1SupportCheckOK[i] = true;
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->BlendingAndTiming[k] == k && v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
+					&& (v->ODMCombine4To1Supported == false || v->Output[k] == dm_dp || v->Output[k] == dm_edp
+							|| v->Output[k] == dm_hdmi)) {
+				v->ODMCombine4To1SupportCheckOK[i] = false;
+			}
+		}
+	}
+
+	/* Skip dscclk validation: as long as dispclk is supported, dscclk is also implicitly supported */
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		v->NotEnoughDSCUnits[i] = false;
+		v->TotalDSCUnitsRequired = 0.0;
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			if (v->RequiresDSC[i][k] == true) {
+				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1) {
+					v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 4.0;
+				} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 2.0;
+				} else {
+					v->TotalDSCUnitsRequired = v->TotalDSCUnitsRequired + 1.0;
+				}
+			}
+		}
+		if (v->TotalDSCUnitsRequired > v->NumberOfDSC) {
+			v->NotEnoughDSCUnits[i] = true;
+		}
+	}
+	/*DSC Delay per state*/
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			if (v->OutputBppPerState[i][k] == BPP_INVALID) {
+				v->BPP = 0.0;
+			} else {
+				v->BPP = v->OutputBppPerState[i][k];
+			}
+			if (v->RequiresDSC[i][k] == true && v->BPP != 0.0) {
+				if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_disabled) {
+					v->DSCDelayPerState[i][k] = dscceComputeDelay(
+							v->DSCInputBitPerComponent[k],
+							v->BPP,
+							dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
+							v->NumberOfDSCSlices[k],
+							v->OutputFormat[k],
+							v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]);
+				} else if (v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1) {
+					v->DSCDelayPerState[i][k] = 2.0
+							* (dscceComputeDelay(
+									v->DSCInputBitPerComponent[k],
+									v->BPP,
+									dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
+									v->NumberOfDSCSlices[k] / 2,
+									v->OutputFormat[k],
+									v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+				} else {
+					v->DSCDelayPerState[i][k] = 4.0
+							* (dscceComputeDelay(
+									v->DSCInputBitPerComponent[k],
+									v->BPP,
+									dml_ceil(1.0 * v->HActive[k] / v->NumberOfDSCSlices[k], 1.0),
+									v->NumberOfDSCSlices[k] / 4,
+									v->OutputFormat[k],
+									v->Output[k]) + dscComputeDelay(v->OutputFormat[k], v->Output[k]));
+				}
+				v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][k] * v->PixelClock[k] / v->PixelClockBackEnd[k];
+			} else {
+				v->DSCDelayPerState[i][k] = 0.0;
+			}
+		}
+		for (k = 0; k < v->NumberOfActivePlanes; k++) {
+			for (m = 0; m < v->NumberOfActivePlanes; m++) {
+				if (v->BlendingAndTiming[k] == m && v->RequiresDSC[i][m] == true) {
+					v->DSCDelayPerState[i][k] = v->DSCDelayPerState[i][m];
+				}
+			}
+		}
+	}
+
+	//Calculate Swath, DET Configuration, DCFCLKDeepSleep
+	//
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->RequiredDPPCLKThisState[k] = v->RequiredDPPCLK[i][j][k];
+				v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
+				v->ODMCombineEnableThisState[k] = v->ODMCombineEnablePerState[i][k];
+			}
+
+			CalculateSwathAndDETConfiguration(
+					false,
+					v->NumberOfActivePlanes,
+					v->DETBufferSizeInKByte[0],
+					v->MaximumSwathWidthLuma,
+					v->MaximumSwathWidthChroma,
+					v->SourceScan,
+					v->SourcePixelFormat,
+					v->SurfaceTiling,
+					v->ViewportWidth,
+					v->ViewportHeight,
+					v->SurfaceWidthY,
+					v->SurfaceWidthC,
+					v->SurfaceHeightY,
+					v->SurfaceHeightC,
+					v->Read256BlockHeightY,
+					v->Read256BlockHeightC,
+					v->Read256BlockWidthY,
+					v->Read256BlockWidthC,
+					v->ODMCombineEnableThisState,
+					v->BlendingAndTiming,
+					v->BytePerPixelY,
+					v->BytePerPixelC,
+					v->BytePerPixelInDETY,
+					v->BytePerPixelInDETC,
+					v->HActive,
+					v->HRatio,
+					v->HRatioChroma,
+					v->NoOfDPPThisState,
+					v->swath_width_luma_ub_this_state,
+					v->swath_width_chroma_ub_this_state,
+					v->SwathWidthYThisState,
+					v->SwathWidthCThisState,
+					v->SwathHeightYThisState,
+					v->SwathHeightCThisState,
+					v->DETBufferSizeYThisState,
+					v->DETBufferSizeCThisState,
+					v->dummystring,
+					&v->ViewportSizeSupport[i][j]);
+
+			CalculateDCFCLKDeepSleep(
+					mode_lib,
+					v->NumberOfActivePlanes,
+					v->BytePerPixelY,
+					v->BytePerPixelC,
+					v->VRatio,
+					v->VRatioChroma,
+					v->SwathWidthYThisState,
+					v->SwathWidthCThisState,
+					v->NoOfDPPThisState,
+					v->HRatio,
+					v->HRatioChroma,
+					v->PixelClock,
+					v->PSCL_FACTOR,
+					v->PSCL_FACTOR_CHROMA,
+					v->RequiredDPPCLKThisState,
+					v->ReadBandwidthLuma,
+					v->ReadBandwidthChroma,
+					v->ReturnBusWidth,
+					&v->ProjectedDCFCLKDeepSleep[i][j]);
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->swath_width_luma_ub_all_states[i][j][k] = v->swath_width_luma_ub_this_state[k];
+				v->swath_width_chroma_ub_all_states[i][j][k] = v->swath_width_chroma_ub_this_state[k];
+				v->SwathWidthYAllStates[i][j][k] = v->SwathWidthYThisState[k];
+				v->SwathWidthCAllStates[i][j][k] = v->SwathWidthCThisState[k];
+				v->SwathHeightYAllStates[i][j][k] = v->SwathHeightYThisState[k];
+				v->SwathHeightCAllStates[i][j][k] = v->SwathHeightCThisState[k];
+				v->DETBufferSizeYAllStates[i][j][k] = v->DETBufferSizeYThisState[k];
+				v->DETBufferSizeCAllStates[i][j][k] = v->DETBufferSizeCThisState[k];
+			}
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		v->cursor_bw[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+				/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatio[k];
+	}
+
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			bool NotUrgentLatencyHiding[DC__NUM_DPP__MAX];
+
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
+				v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
+				v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
+				v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
+				v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
+				v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
+				v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
+				v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
+			}
+
+			v->TotalNumberOfDCCActiveDPP[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				if (v->DCCEnable[k] == true) {
+					v->TotalNumberOfDCCActiveDPP[i][j] = v->TotalNumberOfDCCActiveDPP[i][j] + v->NoOfDPP[i][j][k];
+				}
+			}
+
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10
+						|| v->SourcePixelFormat[k] == dm_420_12 || v->SourcePixelFormat[k] == dm_rgbe_alpha) {
+
+					if ((v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_420_12)
+							&& v->SourceScan[k] != dm_vert) {
+						v->PTEBufferSizeInRequestsForLuma = (v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma)
+								/ 2;
+						v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsForLuma;
+					} else {
+						v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma;
+						v->PTEBufferSizeInRequestsForChroma = v->PTEBufferSizeInRequestsChroma;
+					}
+
+					v->PDEAndMetaPTEBytesPerFrameC = CalculateVMAndRowBytes(
+							mode_lib,
+							v->DCCEnable[k],
+							v->Read256BlockHeightC[k],
+							v->Read256BlockWidthC[k],
+							v->SourcePixelFormat[k],
+							v->SurfaceTiling[k],
+							v->BytePerPixelC[k],
+							v->SourceScan[k],
+							v->SwathWidthCThisState[k],
+							v->ViewportHeightChroma[k],
+							v->GPUVMEnable,
+							v->HostVMEnable,
+							v->HostVMMaxNonCachedPageTableLevels,
+							v->GPUVMMinPageSize,
+							v->HostVMMinPageSize,
+							v->PTEBufferSizeInRequestsForChroma,
+							v->PitchC[k],
+							0.0,
+							&v->MacroTileWidthC[k],
+							&v->MetaRowBytesC,
+							&v->DPTEBytesPerRowC,
+							&v->PTEBufferSizeNotExceededC[i][j][k],
+							&v->dummyinteger7,
+							&v->dpte_row_height_chroma[k],
+							&v->dummyinteger28,
+							&v->dummyinteger26,
+							&v->dummyinteger23,
+							&v->meta_row_height_chroma[k],
+							&v->dummyinteger8,
+							&v->dummyinteger9,
+							&v->dummyinteger19,
+							&v->dummyinteger20,
+							&v->dummyinteger17,
+							&v->dummyinteger10,
+							&v->dummyinteger11);
+
+					v->PrefetchLinesC[i][j][k] = CalculatePrefetchSourceLines(
+							mode_lib,
+							v->VRatioChroma[k],
+							v->VTAPsChroma[k],
+							v->Interlace[k],
+							v->ProgressiveToInterlaceUnitInOPP,
+							v->SwathHeightCThisState[k],
+							v->ViewportYStartC[k],
+							&v->PrefillC[k],
+							&v->MaxNumSwC[k]);
+				} else {
+					v->PTEBufferSizeInRequestsForLuma = v->PTEBufferSizeInRequestsLuma + v->PTEBufferSizeInRequestsChroma;
+					v->PTEBufferSizeInRequestsForChroma = 0;
+					v->PDEAndMetaPTEBytesPerFrameC = 0.0;
+					v->MetaRowBytesC = 0.0;
+					v->DPTEBytesPerRowC = 0.0;
+					v->PrefetchLinesC[i][j][k] = 0.0;
+					v->PTEBufferSizeNotExceededC[i][j][k] = true;
+				}
+				v->PDEAndMetaPTEBytesPerFrameY = CalculateVMAndRowBytes(
+						mode_lib,
+						v->DCCEnable[k],
+						v->Read256BlockHeightY[k],
+						v->Read256BlockWidthY[k],
+						v->SourcePixelFormat[k],
+						v->SurfaceTiling[k],
+						v->BytePerPixelY[k],
+						v->SourceScan[k],
+						v->SwathWidthYThisState[k],
+						v->ViewportHeight[k],
+						v->GPUVMEnable,
+						v->HostVMEnable,
+						v->HostVMMaxNonCachedPageTableLevels,
+						v->GPUVMMinPageSize,
+						v->HostVMMinPageSize,
+						v->PTEBufferSizeInRequestsForLuma,
+						v->PitchY[k],
+						v->DCCMetaPitchY[k],
+						&v->MacroTileWidthY[k],
+						&v->MetaRowBytesY,
+						&v->DPTEBytesPerRowY,
+						&v->PTEBufferSizeNotExceededY[i][j][k],
+						&v->dummyinteger7,
+						&v->dpte_row_height[k],
+						&v->dummyinteger29,
+						&v->dummyinteger27,
+						&v->dummyinteger24,
+						&v->meta_row_height[k],
+						&v->dummyinteger25,
+						&v->dpte_group_bytes[k],
+						&v->dummyinteger21,
+						&v->dummyinteger22,
+						&v->dummyinteger18,
+						&v->dummyinteger5,
+						&v->dummyinteger6);
+				v->PrefetchLinesY[i][j][k] = CalculatePrefetchSourceLines(
+						mode_lib,
+						v->VRatio[k],
+						v->vtaps[k],
+						v->Interlace[k],
+						v->ProgressiveToInterlaceUnitInOPP,
+						v->SwathHeightYThisState[k],
+						v->ViewportYStartY[k],
+						&v->PrefillY[k],
+						&v->MaxNumSwY[k]);
+				v->PDEAndMetaPTEBytesPerFrame[i][j][k] = v->PDEAndMetaPTEBytesPerFrameY + v->PDEAndMetaPTEBytesPerFrameC;
+				v->MetaRowBytes[i][j][k] = v->MetaRowBytesY + v->MetaRowBytesC;
+				v->DPTEBytesPerRow[i][j][k] = v->DPTEBytesPerRowY + v->DPTEBytesPerRowC;
+
+				CalculateRowBandwidth(
+						v->GPUVMEnable,
+						v->SourcePixelFormat[k],
+						v->VRatio[k],
+						v->VRatioChroma[k],
+						v->DCCEnable[k],
+						v->HTotal[k] / v->PixelClock[k],
+						v->MetaRowBytesY,
+						v->MetaRowBytesC,
+						v->meta_row_height[k],
+						v->meta_row_height_chroma[k],
+						v->DPTEBytesPerRowY,
+						v->DPTEBytesPerRowC,
+						v->dpte_row_height[k],
+						v->dpte_row_height_chroma[k],
+						&v->meta_row_bandwidth[i][j][k],
+						&v->dpte_row_bandwidth[i][j][k]);
+			}
+			v->UrgLatency[i] = CalculateUrgentLatency(
+					v->UrgentLatencyPixelDataOnly,
+					v->UrgentLatencyPixelMixedWithVMData,
+					v->UrgentLatencyVMDataOnly,
+					v->DoUrgentLatencyAdjustment,
+					v->UrgentLatencyAdjustmentFabricClockComponent,
+					v->UrgentLatencyAdjustmentFabricClockReference,
+					v->FabricClockPerState[i]);
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				CalculateUrgentBurstFactor(
+						v->swath_width_luma_ub_this_state[k],
+						v->swath_width_chroma_ub_this_state[k],
+						v->SwathHeightYThisState[k],
+						v->SwathHeightCThisState[k],
+						v->HTotal[k] / v->PixelClock[k],
+						v->UrgLatency[i],
+						v->CursorBufferSize,
+						v->CursorWidth[k][0],
+						v->CursorBPP[k][0],
+						v->VRatio[k],
+						v->VRatioChroma[k],
+						v->BytePerPixelInDETY[k],
+						v->BytePerPixelInDETC[k],
+						v->DETBufferSizeYThisState[k],
+						v->DETBufferSizeCThisState[k],
+						&v->UrgentBurstFactorCursor[k],
+						&v->UrgentBurstFactorLuma[k],
+						&v->UrgentBurstFactorChroma[k],
+						&NotUrgentLatencyHiding[k]);
+			}
+
+			v->NotEnoughUrgentLatencyHidingA[i][j] = false;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				if (NotUrgentLatencyHiding[k]) {
+					v->NotEnoughUrgentLatencyHidingA[i][j] = true;
+				}
+			}
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->VActivePixelBandwidth[i][j][k] = v->ReadBandwidthLuma[k] * v->UrgentBurstFactorLuma[k]
+						+ v->ReadBandwidthChroma[k] * v->UrgentBurstFactorChroma[k];
+				v->VActiveCursorBandwidth[i][j][k] = v->cursor_bw[k] * v->UrgentBurstFactorCursor[k];
+			}
+
+			v->TotalVActivePixelBandwidth[i][j] = 0;
+			v->TotalVActiveCursorBandwidth[i][j] = 0;
+			v->TotalMetaRowBandwidth[i][j] = 0;
+			v->TotalDPTERowBandwidth[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->TotalVActivePixelBandwidth[i][j] = v->TotalVActivePixelBandwidth[i][j] + v->VActivePixelBandwidth[i][j][k];
+				v->TotalVActiveCursorBandwidth[i][j] = v->TotalVActiveCursorBandwidth[i][j] + v->VActiveCursorBandwidth[i][j][k];
+				v->TotalMetaRowBandwidth[i][j] = v->TotalMetaRowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->meta_row_bandwidth[i][j][k];
+				v->TotalDPTERowBandwidth[i][j] = v->TotalDPTERowBandwidth[i][j] + v->NoOfDPP[i][j][k] * v->dpte_row_bandwidth[i][j][k];
+			}
+		}
+	}
+
+	//Calculate Return BW
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				if (v->BlendingAndTiming[k] == k) {
+					if (v->WritebackEnable[k] == true) {
+						v->WritebackDelayTime[k] = v->WritebackLatency
+								+ CalculateWriteBackDelay(
+										v->WritebackPixelFormat[k],
+										v->WritebackHRatio[k],
+										v->WritebackVRatio[k],
+										v->WritebackVTaps[k],
+										v->WritebackDestinationWidth[k],
+										v->WritebackDestinationHeight[k],
+										v->WritebackSourceHeight[k],
+										v->HTotal[k]) / v->RequiredDISPCLK[i][j];
+					} else {
+						v->WritebackDelayTime[k] = 0.0;
+					}
+					for (m = 0; m < v->NumberOfActivePlanes; m++) {
+						if (v->BlendingAndTiming[m] == k && v->WritebackEnable[m] == true) {
+							v->WritebackDelayTime[k] = dml_max(
+									v->WritebackDelayTime[k],
+									v->WritebackLatency
+											+ CalculateWriteBackDelay(
+													v->WritebackPixelFormat[m],
+													v->WritebackHRatio[m],
+													v->WritebackVRatio[m],
+													v->WritebackVTaps[m],
+													v->WritebackDestinationWidth[m],
+													v->WritebackDestinationHeight[m],
+													v->WritebackSourceHeight[m],
+													v->HTotal[m]) / v->RequiredDISPCLK[i][j]);
+						}
+					}
+				}
+			}
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				for (m = 0; m < v->NumberOfActivePlanes; m++) {
+					if (v->BlendingAndTiming[k] == m) {
+						v->WritebackDelayTime[k] = v->WritebackDelayTime[m];
+					}
+				}
+			}
+			v->MaxMaxVStartup[i][j] = 0;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				v->MaximumVStartup[i][j][k] =
+						(v->Interlace[k] && !v->ProgressiveToInterlaceUnitInOPP) ?
+								dml_floor((v->VTotal[k] - v->VActive[k]) / 2.0, 1.0) :
+								v->VTotal[k] - v->VActive[k]
+										- dml_max(
+												1.0,
+												dml_ceil(
+														1.0 * v->WritebackDelayTime[k]
+																/ (v->HTotal[k]
+																		/ v->PixelClock[k]),
+														1.0));
+				v->MaxMaxVStartup[i][j] = dml_max(v->MaxMaxVStartup[i][j], v->MaximumVStartup[i][j][k]);
+			}
+		}
+	}
+
+	ReorderingBytes = v->NumberOfChannels
+			* dml_max3(
+					v->UrgentOutOfOrderReturnPerChannelPixelDataOnly,
+					v->UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData,
+					v->UrgentOutOfOrderReturnPerChannelVMDataOnly);
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			v->DCFCLKState[i][j] = v->DCFCLKPerState[i];
+		}
+	}
+
+	if (v->UseMinimumRequiredDCFCLK == true) {
+		UseMinimumDCFCLK(
+				mode_lib,
+				v->MaxInterDCNTileRepeaters,
+				MaxPrefetchMode,
+				v->DRAMClockChangeLatency,
+				v->SREnterPlusExitTime,
+				v->ReturnBusWidth,
+				v->RoundTripPingLatencyCycles,
+				ReorderingBytes,
+				v->PixelChunkSizeInKByte,
+				v->MetaChunkSize,
+				v->GPUVMEnable,
+				v->GPUVMMaxPageTableLevels,
+				v->HostVMEnable,
+				v->NumberOfActivePlanes,
+				v->HostVMMinPageSize,
+				v->HostVMMaxNonCachedPageTableLevels,
+				v->DynamicMetadataVMEnabled,
+				v->ImmediateFlipRequirement,
+				v->ProgressiveToInterlaceUnitInOPP,
+				v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,
+				v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+				v->VTotal,
+				v->VActive,
+				v->DynamicMetadataTransmittedBytes,
+				v->DynamicMetadataLinesBeforeActiveRequired,
+				v->Interlace,
+				v->RequiredDPPCLK,
+				v->RequiredDISPCLK,
+				v->UrgLatency,
+				v->NoOfDPP,
+				v->ProjectedDCFCLKDeepSleep,
+				v->MaximumVStartup,
+				v->TotalVActivePixelBandwidth,
+				v->TotalVActiveCursorBandwidth,
+				v->TotalMetaRowBandwidth,
+				v->TotalDPTERowBandwidth,
+				v->TotalNumberOfActiveDPP,
+				v->TotalNumberOfDCCActiveDPP,
+				v->dpte_group_bytes,
+				v->PrefetchLinesY,
+				v->PrefetchLinesC,
+				v->swath_width_luma_ub_all_states,
+				v->swath_width_chroma_ub_all_states,
+				v->BytePerPixelY,
+				v->BytePerPixelC,
+				v->HTotal,
+				v->PixelClock,
+				v->PDEAndMetaPTEBytesPerFrame,
+				v->DPTEBytesPerRow,
+				v->MetaRowBytes,
+				v->DynamicMetadataEnable,
+				v->VActivePixelBandwidth,
+				v->VActiveCursorBandwidth,
+				v->ReadBandwidthLuma,
+				v->ReadBandwidthChroma,
+				v->DCFCLKPerState,
+				v->DCFCLKState);
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double IdealFabricAndSDPPortBandwidthPerState = dml_min(
+					v->ReturnBusWidth * v->DCFCLKState[i][j],
+					v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn);
+			double IdealDRAMBandwidthPerState = v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth;
+			double PixelDataOnlyReturnBWPerState = dml_min(
+					IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+					IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly / 100.0);
+			double PixelMixedWithVMDataReturnBWPerState = dml_min(
+					IdealFabricAndSDPPortBandwidthPerState * v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+					IdealDRAMBandwidthPerState * v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData / 100.0);
+
+			if (v->HostVMEnable != true) {
+				v->ReturnBWPerState[i][j] = PixelDataOnlyReturnBWPerState;
+			} else {
+				v->ReturnBWPerState[i][j] = PixelMixedWithVMDataReturnBWPerState;
+			}
+		}
+	}
+
+	//Re-ordering Buffer Support Check
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			if ((v->ROBBufferSizeInKByte - v->PixelChunkSizeInKByte) * 1024 / v->ReturnBWPerState[i][j]
+					> (v->RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / v->DCFCLKState[i][j] + ReorderingBytes / v->ReturnBWPerState[i][j]) {
+				v->ROBSupport[i][j] = true;
+			} else {
+				v->ROBSupport[i][j] = false;
+			}
+		}
+	}
+
+	//Vertical Active BW support check
+
+	MaxTotalVActiveRDBandwidth = 0;
+	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+		MaxTotalVActiveRDBandwidth = MaxTotalVActiveRDBandwidth + v->ReadBandwidthLuma[k] + v->ReadBandwidthChroma[k];
+	}
+
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			v->MaxTotalVerticalActiveAvailableBandwidth[i][j] = dml_min(
+					dml_min(
+							v->ReturnBusWidth * v->DCFCLKState[i][j],
+							v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
+							* v->MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100,
+					v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
+							* v->MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation / 100);
+
+			if (MaxTotalVActiveRDBandwidth <= v->MaxTotalVerticalActiveAvailableBandwidth[i][j]) {
+				v->TotalVerticalActiveBandwidthSupport[i][j] = true;
+			} else {
+				v->TotalVerticalActiveBandwidthSupport[i][j] = false;
+			}
+		}
+	}
+
+	v->UrgentLatency = CalculateUrgentLatency(
+			v->UrgentLatencyPixelDataOnly,
+			v->UrgentLatencyPixelMixedWithVMData,
+			v->UrgentLatencyVMDataOnly,
+			v->DoUrgentLatencyAdjustment,
+			v->UrgentLatencyAdjustmentFabricClockComponent,
+			v->UrgentLatencyAdjustmentFabricClockReference,
+			v->FabricClock);
+	//Prefetch Check
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double VMDataOnlyReturnBWPerState;
+			double HostVMInefficiencyFactor = 1;
+			int NextPrefetchModeState = MinPrefetchMode;
+			bool UnboundedRequestEnabledThisState = false;
+			int CompressedBufferSizeInkByteThisState = 0;
+			double dummy;
+
+			v->TimeCalc = 24 / v->ProjectedDCFCLKDeepSleep[i][j];
+
+			v->BandwidthWithoutPrefetchSupported[i][j] = true;
+			if (v->TotalVActivePixelBandwidth[i][j] + v->TotalVActiveCursorBandwidth[i][j] + v->TotalMetaRowBandwidth[i][j]
+					+ v->TotalDPTERowBandwidth[i][j] > v->ReturnBWPerState[i][j] || v->NotEnoughUrgentLatencyHidingA[i][j]) {
+				v->BandwidthWithoutPrefetchSupported[i][j] = false;
+			}
+
+			for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+				v->NoOfDPPThisState[k] = v->NoOfDPP[i][j][k];
+				v->swath_width_luma_ub_this_state[k] = v->swath_width_luma_ub_all_states[i][j][k];
+				v->swath_width_chroma_ub_this_state[k] = v->swath_width_chroma_ub_all_states[i][j][k];
+				v->SwathWidthYThisState[k] = v->SwathWidthYAllStates[i][j][k];
+				v->SwathWidthCThisState[k] = v->SwathWidthCAllStates[i][j][k];
+				v->SwathHeightYThisState[k] = v->SwathHeightYAllStates[i][j][k];
+				v->SwathHeightCThisState[k] = v->SwathHeightCAllStates[i][j][k];
+				v->DETBufferSizeYThisState[k] = v->DETBufferSizeYAllStates[i][j][k];
+				v->DETBufferSizeCThisState[k] = v->DETBufferSizeCAllStates[i][j][k];
+			}
+
+			VMDataOnlyReturnBWPerState = dml_min(
+					dml_min(
+							v->ReturnBusWidth * v->DCFCLKState[i][j],
+							v->FabricClockPerState[i] * v->FabricDatapathToDCNDataReturn)
+							* v->PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0,
+					v->DRAMSpeedPerState[i] * v->NumberOfChannels * v->DRAMChannelWidth
+							* v->PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly / 100.0);
+			if (v->GPUVMEnable && v->HostVMEnable)
+				HostVMInefficiencyFactor = v->ReturnBWPerState[i][j] / VMDataOnlyReturnBWPerState;
+
+			v->ExtraLatency = CalculateExtraLatency(
+					v->RoundTripPingLatencyCycles,
+					ReorderingBytes,
+					v->DCFCLKState[i][j],
+					v->TotalNumberOfActiveDPP[i][j],
+					v->PixelChunkSizeInKByte,
+					v->TotalNumberOfDCCActiveDPP[i][j],
+					v->MetaChunkSize,
+					v->ReturnBWPerState[i][j],
+					v->GPUVMEnable,
+					v->HostVMEnable,
+					v->NumberOfActivePlanes,
+					v->NoOfDPPThisState,
+					v->dpte_group_bytes,
+					HostVMInefficiencyFactor,
+					v->HostVMMinPageSize,
+					v->HostVMMaxNonCachedPageTableLevels);
+
+			v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
+			do {
+				v->PrefetchModePerState[i][j] = NextPrefetchModeState;
+				v->MaxVStartup = v->NextMaxVStartup;
+
+				v->TWait = CalculateTWait(
+						v->PrefetchModePerState[i][j],
+						v->DRAMClockChangeLatency,
+						v->UrgLatency[i],
+						v->SREnterPlusExitTime);
+
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					Pipe myPipe;
+
+					myPipe.DPPCLK = v->RequiredDPPCLK[i][j][k];
+					myPipe.DISPCLK = v->RequiredDISPCLK[i][j];
+					myPipe.PixelClock = v->PixelClock[k];
+					myPipe.DCFCLKDeepSleep = v->ProjectedDCFCLKDeepSleep[i][j];
+					myPipe.DPPPerPlane = v->NoOfDPP[i][j][k];
+					myPipe.ScalerEnabled = v->ScalerEnabled[k];
+					myPipe.SourceScan = v->SourceScan[k];
+					myPipe.BlockWidth256BytesY = v->Read256BlockWidthY[k];
+					myPipe.BlockHeight256BytesY = v->Read256BlockHeightY[k];
+					myPipe.BlockWidth256BytesC = v->Read256BlockWidthC[k];
+					myPipe.BlockHeight256BytesC = v->Read256BlockHeightC[k];
+					myPipe.InterlaceEnable = v->Interlace[k];
+					myPipe.NumberOfCursors = v->NumberOfCursors[k];
+					myPipe.VBlank = v->VTotal[k] - v->VActive[k];
+					myPipe.HTotal = v->HTotal[k];
+					myPipe.DCCEnable = v->DCCEnable[k];
+					myPipe.ODMCombineIsEnabled = v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_4to1
+							|| v->ODMCombineEnablePerState[i][k] == dm_odm_combine_mode_2to1;
+					myPipe.SourcePixelFormat = v->SourcePixelFormat[k];
+					myPipe.BytePerPixelY = v->BytePerPixelY[k];
+					myPipe.BytePerPixelC = v->BytePerPixelC[k];
+					myPipe.ProgressiveToInterlaceUnitInOPP = v->ProgressiveToInterlaceUnitInOPP;
+					v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
+							mode_lib,
+							HostVMInefficiencyFactor,
+							&myPipe,
+							v->DSCDelayPerState[i][k],
+							v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
+							v->DPPCLKDelaySCL,
+							v->DPPCLKDelaySCLLBOnly,
+							v->DPPCLKDelayCNVCCursor,
+							v->DISPCLKDelaySubtotal,
+							v->SwathWidthYThisState[k] / v->HRatio[k],
+							v->OutputFormat[k],
+							v->MaxInterDCNTileRepeaters,
+							dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
+							v->MaximumVStartup[i][j][k],
+							v->GPUVMMaxPageTableLevels,
+							v->GPUVMEnable,
+							v->HostVMEnable,
+							v->HostVMMaxNonCachedPageTableLevels,
+							v->HostVMMinPageSize,
+							v->DynamicMetadataEnable[k],
+							v->DynamicMetadataVMEnabled,
+							v->DynamicMetadataLinesBeforeActiveRequired[k],
+							v->DynamicMetadataTransmittedBytes[k],
+							v->UrgLatency[i],
+							v->ExtraLatency,
+							v->TimeCalc,
+							v->PDEAndMetaPTEBytesPerFrame[i][j][k],
+							v->MetaRowBytes[i][j][k],
+							v->DPTEBytesPerRow[i][j][k],
+							v->PrefetchLinesY[i][j][k],
+							v->SwathWidthYThisState[k],
+							v->PrefillY[k],
+							v->MaxNumSwY[k],
+							v->PrefetchLinesC[i][j][k],
+							v->SwathWidthCThisState[k],
+							v->PrefillC[k],
+							v->MaxNumSwC[k],
+							v->swath_width_luma_ub_this_state[k],
+							v->swath_width_chroma_ub_this_state[k],
+							v->SwathHeightYThisState[k],
+							v->SwathHeightCThisState[k],
+							v->TWait,
+							&v->DSTXAfterScaler[k],
+							&v->DSTYAfterScaler[k],
+							&v->LineTimesForPrefetch[k],
+							&v->PrefetchBW[k],
+							&v->LinesForMetaPTE[k],
+							&v->LinesForMetaAndDPTERow[k],
+							&v->VRatioPreY[i][j][k],
+							&v->VRatioPreC[i][j][k],
+							&v->RequiredPrefetchPixelDataBWLuma[i][j][k],
+							&v->RequiredPrefetchPixelDataBWChroma[i][j][k],
+							&v->NoTimeForDynamicMetadata[i][j][k],
+							&v->Tno_bw[k],
+							&v->prefetch_vmrow_bw[k],
+							&v->dummy7[k],
+							&v->dummy8[k],
+							&v->dummy13[k],
+							&v->VUpdateOffsetPix[k],
+							&v->VUpdateWidthPix[k],
+							&v->VReadyOffsetPix[k]);
+				}
+
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					CalculateUrgentBurstFactor(
+							v->swath_width_luma_ub_this_state[k],
+							v->swath_width_chroma_ub_this_state[k],
+							v->SwathHeightYThisState[k],
+							v->SwathHeightCThisState[k],
+							v->HTotal[k] / v->PixelClock[k],
+							v->UrgentLatency,
+							v->CursorBufferSize,
+							v->CursorWidth[k][0],
+							v->CursorBPP[k][0],
+							v->VRatioPreY[i][j][k],
+							v->VRatioPreC[i][j][k],
+							v->BytePerPixelInDETY[k],
+							v->BytePerPixelInDETC[k],
+							v->DETBufferSizeYThisState[k],
+							v->DETBufferSizeCThisState[k],
+							&v->UrgentBurstFactorCursorPre[k],
+							&v->UrgentBurstFactorLumaPre[k],
+							&v->UrgentBurstFactorChroma[k],
+							&v->NotUrgentLatencyHidingPre[k]);
+				}
+
+				v->MaximumReadBandwidthWithPrefetch = 0.0;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					v->cursor_bw_pre[k] = v->NumberOfCursors[k] * v->CursorWidth[k][0] * v->CursorBPP[k][0] / 8.0
+							/ (v->HTotal[k] / v->PixelClock[k]) * v->VRatioPreY[i][j][k];
+
+					v->MaximumReadBandwidthWithPrefetch =
+							v->MaximumReadBandwidthWithPrefetch
+									+ dml_max4(
+											v->VActivePixelBandwidth[i][j][k],
+											v->VActiveCursorBandwidth[i][j][k]
+													+ v->NoOfDPP[i][j][k]
+															* (v->meta_row_bandwidth[i][j][k]
+																	+ v->dpte_row_bandwidth[i][j][k]),
+											v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
+											v->NoOfDPP[i][j][k]
+													* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
+															* v->UrgentBurstFactorLumaPre[k]
+															+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
+																	* v->UrgentBurstFactorChromaPre[k])
+													+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
+				}
+
+				v->NotEnoughUrgentLatencyHidingPre = false;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					if (v->NotUrgentLatencyHidingPre[k] == true) {
+						v->NotEnoughUrgentLatencyHidingPre = true;
+					}
+				}
+
+				v->PrefetchSupported[i][j] = true;
+				if (v->BandwidthWithoutPrefetchSupported[i][j] == false || v->MaximumReadBandwidthWithPrefetch > v->ReturnBWPerState[i][j]
+						|| v->NotEnoughUrgentLatencyHidingPre == 1) {
+					v->PrefetchSupported[i][j] = false;
+				}
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					if (v->LineTimesForPrefetch[k] < 2.0 || v->LinesForMetaPTE[k] >= 32.0 || v->LinesForMetaAndDPTERow[k] >= 16.0
+							|| v->NoTimeForPrefetch[i][j][k] == true) {
+						v->PrefetchSupported[i][j] = false;
+					}
+				}
+
+				v->DynamicMetadataSupported[i][j] = true;
+				for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+					if (v->NoTimeForDynamicMetadata[i][j][k] == true) {
+						v->DynamicMetadataSupported[i][j] = false;
+					}
+				}
+
+				v->VRatioInPrefetchSupported[i][j] = true;
+				for (k = 0; k < v->NumberOfActivePlanes; k++) {
+					if (v->VRatioPreY[i][j][k] > 4.0 || v->VRatioPreC[i][j][k] > 4.0 || v->NoTimeForPrefetch[i][j][k] == true) {
+						v->VRatioInPrefetchSupported[i][j] = false;
+					}
+				}
+				v->AnyLinesForVMOrRowTooLarge = false;
+				for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+					if (v->LinesForMetaAndDPTERow[k] >= 16 || v->LinesForMetaPTE[k] >= 32) {
+						v->AnyLinesForVMOrRowTooLarge = true;
+					}
+				}
+
+				v->NextPrefetchMode = v->NextPrefetchMode + 1;
+
+				if (v->PrefetchSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true) {
+					v->BandwidthAvailableForImmediateFlip = v->ReturnBWPerState[i][j];
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						v->BandwidthAvailableForImmediateFlip = v->BandwidthAvailableForImmediateFlip
+								- dml_max(
+										v->VActivePixelBandwidth[i][j][k] + v->VActiveCursorBandwidth[i][j][k],
+										v->NoOfDPP[i][j][k]
+												* (v->RequiredPrefetchPixelDataBWLuma[i][j][k]
+														* v->UrgentBurstFactorLumaPre[k]
+														+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
+																* v->UrgentBurstFactorChromaPre[k])
+												+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
+					}
+					v->TotImmediateFlipBytes = 0.0;
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						v->TotImmediateFlipBytes = v->TotImmediateFlipBytes
+								+ v->NoOfDPP[i][j][k] * v->PDEAndMetaPTEBytesPerFrame[i][j][k] + v->MetaRowBytes[i][j][k]
+								+ v->DPTEBytesPerRow[i][j][k];
+					}
+
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						CalculateFlipSchedule(
+								mode_lib,
+								HostVMInefficiencyFactor,
+								v->ExtraLatency,
+								v->UrgLatency[i],
+								v->GPUVMMaxPageTableLevels,
+								v->HostVMEnable,
+								v->HostVMMaxNonCachedPageTableLevels,
+								v->GPUVMEnable,
+								v->HostVMMinPageSize,
+								v->PDEAndMetaPTEBytesPerFrame[i][j][k],
+								v->MetaRowBytes[i][j][k],
+								v->DPTEBytesPerRow[i][j][k],
+								v->BandwidthAvailableForImmediateFlip,
+								v->TotImmediateFlipBytes,
+								v->SourcePixelFormat[k],
+								v->HTotal[k] / v->PixelClock[k],
+								v->VRatio[k],
+								v->VRatioChroma[k],
+								v->Tno_bw[k],
+								v->DCCEnable[k],
+								v->dpte_row_height[k],
+								v->meta_row_height[k],
+								v->dpte_row_height_chroma[k],
+								v->meta_row_height_chroma[k],
+								&v->DestinationLinesToRequestVMInImmediateFlip[k],
+								&v->DestinationLinesToRequestRowInImmediateFlip[k],
+								&v->final_flip_bw[k],
+								&v->ImmediateFlipSupportedForPipe[k]);
+					}
+					v->total_dcn_read_bw_with_flip = 0.0;
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						v->total_dcn_read_bw_with_flip = v->total_dcn_read_bw_with_flip
+								+ dml_max3(
+										v->NoOfDPP[i][j][k] * v->prefetch_vmrow_bw[k],
+										v->NoOfDPP[i][j][k] * v->final_flip_bw[k] + v->VActivePixelBandwidth[i][j][k]
+												+ v->VActiveCursorBandwidth[i][j][k],
+										v->NoOfDPP[i][j][k]
+												* (v->final_flip_bw[k]
+														+ v->RequiredPrefetchPixelDataBWLuma[i][j][k]
+																* v->UrgentBurstFactorLumaPre[k]
+														+ v->RequiredPrefetchPixelDataBWChroma[i][j][k]
+																* v->UrgentBurstFactorChromaPre[k])
+												+ v->cursor_bw_pre[k] * v->UrgentBurstFactorCursorPre[k]);
+					}
+					v->ImmediateFlipSupportedForState[i][j] = true;
+					if (v->total_dcn_read_bw_with_flip > v->ReturnBWPerState[i][j]) {
+						v->ImmediateFlipSupportedForState[i][j] = false;
+					}
+					for (k = 0; k < v->NumberOfActivePlanes; k++) {
+						if (v->ImmediateFlipSupportedForPipe[k] == false) {
+							v->ImmediateFlipSupportedForState[i][j] = false;
+						}
+					}
+				} else {
+					v->ImmediateFlipSupportedForState[i][j] = false;
+				}
+
+				if (v->MaxVStartup <= __DML_VBA_MIN_VSTARTUP__ || v->AnyLinesForVMOrRowTooLarge == false) {
+					v->NextMaxVStartup = v->MaxMaxVStartup[i][j];
+					NextPrefetchModeState = NextPrefetchModeState + 1;
+				} else {
+					v->NextMaxVStartup = v->NextMaxVStartup - 1;
+				}
+				v->NextPrefetchMode = v->NextPrefetchMode + 1;
+			} while (!((v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
+					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)
+							|| v->ImmediateFlipSupportedForState[i][j] == true))
+					|| (v->NextMaxVStartup == v->MaxMaxVStartup[i][j] && NextPrefetchModeState > MaxPrefetchMode)));
+
+			CalculateUnboundedRequestAndCompressedBufferSize(
+					v->DETBufferSizeInKByte[0],
+					v->ConfigReturnBufferSizeInKByte,
+					v->UseUnboundedRequesting,
+					v->TotalNumberOfActiveDPP[i][j],
+					NoChroma,
+					v->MaxNumDPP,
+					v->CompressedBufferSegmentSizeInkByte,
+					v->Output,
+					&UnboundedRequestEnabledThisState,
+					&CompressedBufferSizeInkByteThisState);
+
+			CalculateWatermarksAndDRAMSpeedChangeSupport(
+					mode_lib,
+					v->PrefetchModePerState[i][j],
+					v->NumberOfActivePlanes,
+					v->MaxLineBufferLines,
+					v->LineBufferSize,
+					v->WritebackInterfaceBufferSize,
+					v->DCFCLKState[i][j],
+					v->ReturnBWPerState[i][j],
+					v->SynchronizedVBlank,
+					v->dpte_group_bytes,
+					v->MetaChunkSize,
+					v->UrgLatency[i],
+					v->ExtraLatency,
+					v->WritebackLatency,
+					v->WritebackChunkSize,
+					v->SOCCLKPerState[i],
+					v->DRAMClockChangeLatency,
+					v->SRExitTime,
+					v->SREnterPlusExitTime,
+					v->SRExitZ8Time,
+					v->SREnterPlusExitZ8Time,
+					v->ProjectedDCFCLKDeepSleep[i][j],
+					v->DETBufferSizeYThisState,
+					v->DETBufferSizeCThisState,
+					v->SwathHeightYThisState,
+					v->SwathHeightCThisState,
+					v->LBBitPerPixel,
+					v->SwathWidthYThisState,
+					v->SwathWidthCThisState,
+					v->HRatio,
+					v->HRatioChroma,
+					v->vtaps,
+					v->VTAPsChroma,
+					v->VRatio,
+					v->VRatioChroma,
+					v->HTotal,
+					v->PixelClock,
+					v->BlendingAndTiming,
+					v->NoOfDPPThisState,
+					v->BytePerPixelInDETY,
+					v->BytePerPixelInDETC,
+					v->DSTXAfterScaler,
+					v->DSTYAfterScaler,
+					v->WritebackEnable,
+					v->WritebackPixelFormat,
+					v->WritebackDestinationWidth,
+					v->WritebackDestinationHeight,
+					v->WritebackSourceHeight,
+					UnboundedRequestEnabledThisState,
+					CompressedBufferSizeInkByteThisState,
+					&v->DRAMClockChangeSupport[i][j],
+					&v->UrgentWatermark,
+					&v->WritebackUrgentWatermark,
+					&v->DRAMClockChangeWatermark,
+					&v->WritebackDRAMClockChangeWatermark,
+					&dummy,
+					&dummy,
+					&dummy,
+					&dummy,
+					&v->MinActiveDRAMClockChangeLatencySupported);
+		}
+	}
+
+	/*PTE Buffer Size Check*/
+	for (i = 0; i < v->soc.num_states; i++) {
+		for (j = 0; j < 2; j++) {
+			v->PTEBufferSizeNotExceeded[i][j] = true;
+			for (k = 0; k < v->NumberOfActivePlanes; k++) {
+				if (v->PTEBufferSizeNotExceededY[i][j][k] == false || v->PTEBufferSizeNotExceededC[i][j][k] == false) {
+					v->PTEBufferSizeNotExceeded[i][j] = false;
+				}
+			}
+		}
+	}
+
+	/*Cursor Support Check*/
+	v->CursorSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->CursorWidth[k][0] > 0.0) {
+			if (v->CursorBPP[k][0] == 64 && v->Cursor64BppSupport == false) {
+				v->CursorSupport = false;
+			}
+		}
+	}
+
+	/*Valid Pitch Check*/
+	v->PitchSupport = true;
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		v->AlignedYPitch[k] = dml_ceil(dml_max(v->PitchY[k], v->SurfaceWidthY[k]), v->MacroTileWidthY[k]);
+		if (v->DCCEnable[k] == true) {
+			v->AlignedDCCMetaPitchY[k] = dml_ceil(dml_max(v->DCCMetaPitchY[k], v->SurfaceWidthY[k]), 64.0 * v->Read256BlockWidthY[k]);
+		} else {
+			v->AlignedDCCMetaPitchY[k] = v->DCCMetaPitchY[k];
+		}
+		if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
+				&& v->SourcePixelFormat[k] != dm_mono_16 && v->SourcePixelFormat[k] != dm_rgbe
+				&& v->SourcePixelFormat[k] != dm_mono_8) {
+			v->AlignedCPitch[k] = dml_ceil(dml_max(v->PitchC[k], v->SurfaceWidthC[k]), v->MacroTileWidthC[k]);
+			if (v->DCCEnable[k] == true) {
+				v->AlignedDCCMetaPitchC[k] = dml_ceil(
+						dml_max(v->DCCMetaPitchC[k], v->SurfaceWidthC[k]),
+						64.0 * v->Read256BlockWidthC[k]);
+			} else {
+				v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
+			}
+		} else {
+			v->AlignedCPitch[k] = v->PitchC[k];
+			v->AlignedDCCMetaPitchC[k] = v->DCCMetaPitchC[k];
+		}
+		if (v->AlignedYPitch[k] > v->PitchY[k] || v->AlignedCPitch[k] > v->PitchC[k]
+				|| v->AlignedDCCMetaPitchY[k] > v->DCCMetaPitchY[k] || v->AlignedDCCMetaPitchC[k] > v->DCCMetaPitchC[k]) {
+			v->PitchSupport = false;
+		}
+	}
+
+	for (k = 0; k < v->NumberOfActivePlanes; k++) {
+		if (v->ViewportWidth[k] > v->SurfaceWidthY[k] || v->ViewportHeight[k] > v->SurfaceHeightY[k]) {
+			ViewportExceedsSurface = true;
+			if (v->SourcePixelFormat[k] != dm_444_64 && v->SourcePixelFormat[k] != dm_444_32 && v->SourcePixelFormat[k] != dm_444_16
+					&& v->SourcePixelFormat[k] != dm_444_16 && v->SourcePixelFormat[k] != dm_444_8
+					&& v->SourcePixelFormat[k] != dm_rgbe) {
+				if (v->ViewportWidthChroma[k] > v->SurfaceWidthC[k]
+						|| v->ViewportHeightChroma[k] > v->SurfaceHeightC[k]) {
+					ViewportExceedsSurface = true;
+				}
+			}
+		}
+	}
+
+	/*Mode Support, Voltage State and SOC Configuration*/
+	for (i = v->soc.num_states - 1; i >= 0; i--) {
+		for (j = 0; j < 2; j++) {
+			if (v->ScaleRatioAndTapsSupport == true && v->SourceFormatPixelAndScanSupport == true && v->ViewportSizeSupport[i][j] == true
+					&& v->LinkCapacitySupport[i] == true && !P2IWith420 && !DSCOnlyIfNecessaryWithBPP
+					&& !DSC422NativeNotSupported && v->ODMCombine4To1SupportCheckOK[i] == true && v->NotEnoughDSCUnits[i] == false
+					&& v->DTBCLKRequiredMoreThanSupported[i] == false
+					&& v->ROBSupport[i][j] == true && v->DISPCLK_DPPCLK_Support[i][j] == true
+					&& v->TotalAvailablePipesSupport[i][j] == true && EnoughWritebackUnits == true
+					&& v->WritebackLatencySupport == true && v->WritebackScaleRatioAndTapsSupport == true
+					&& v->CursorSupport == true && v->PitchSupport == true && ViewportExceedsSurface == false
+					&& v->PrefetchSupported[i][j] == true && v->DynamicMetadataSupported[i][j] == true
+					&& v->TotalVerticalActiveBandwidthSupport[i][j] == true && v->VRatioInPrefetchSupported[i][j] == true
+					&& v->PTEBufferSizeNotExceeded[i][j] == true && v->NonsupportedDSCInputBPC == false
+					&& ((v->HostVMEnable == false && v->ImmediateFlipRequirement != dm_immediate_flip_required)
+							|| v->ImmediateFlipSupportedForState[i][j] == true)
+					&& FMTBufferExceeded == false) {
+				v->ModeSupport[i][j] = true;
+			} else {
+				v->ModeSupport[i][j] = false;
+			}
+		}
+	}
+
+	{
+		unsigned int MaximumMPCCombine = 0;
+		for (i = v->soc.num_states; i >= 0; i--) {
+			if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
+				v->VoltageLevel = i;
+				v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
+				if (v->ModeSupport[i][0] == true) {
+					MaximumMPCCombine = 0;
+				} else {
+					MaximumMPCCombine = 1;
+				}
+			}
+		}
+		v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
+		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
+			v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
+			v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
+		}
+		v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
+		v->DRAMSpeed = v->DRAMSpeedPerState[v->VoltageLevel];
+		v->FabricClock = v->FabricClockPerState[v->VoltageLevel];
+		v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
+		v->ReturnBW = v->ReturnBWPerState[v->VoltageLevel][MaximumMPCCombine];
+		v->maxMpcComb = MaximumMPCCombine;
+	}
+}
+
+static void CalculateWatermarksAndDRAMSpeedChangeSupport(
+		struct display_mode_lib *mode_lib,
+		unsigned int PrefetchMode,
+		unsigned int NumberOfActivePlanes,
+		unsigned int MaxLineBufferLines,
+		unsigned int LineBufferSize,
+		unsigned int WritebackInterfaceBufferSize,
+		double DCFCLK,
+		double ReturnBW,
+		bool SynchronizedVBlank,
+		unsigned int dpte_group_bytes[],
+		unsigned int MetaChunkSize,
+		double UrgentLatency,
+		double ExtraLatency,
+		double WritebackLatency,
+		double WritebackChunkSize,
+		double SOCCLK,
+		double DRAMClockChangeLatency,
+		double SRExitTime,
+		double SREnterPlusExitTime,
+		double SRExitZ8Time,
+		double SREnterPlusExitZ8Time,
+		double DCFCLKDeepSleep,
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		unsigned int SwathHeightY[],
+		unsigned int SwathHeightC[],
+		unsigned int LBBitPerPixel[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		double HRatio[],
+		double HRatioChroma[],
+		unsigned int vtaps[],
+		unsigned int VTAPsChroma[],
+		double VRatio[],
+		double VRatioChroma[],
+		unsigned int HTotal[],
+		double PixelClock[],
+		unsigned int BlendingAndTiming[],
+		unsigned int DPPPerPlane[],
+		double BytePerPixelDETY[],
+		double BytePerPixelDETC[],
+		double DSTXAfterScaler[],
+		double DSTYAfterScaler[],
+		bool WritebackEnable[],
+		enum source_format_class WritebackPixelFormat[],
+		double WritebackDestinationWidth[],
+		double WritebackDestinationHeight[],
+		double WritebackSourceHeight[],
+		bool UnboundedRequestEnabled,
+		int unsigned CompressedBufferSizeInkByte,
+		enum clock_change_support *DRAMClockChangeSupport,
+		double *UrgentWatermark,
+		double *WritebackUrgentWatermark,
+		double *DRAMClockChangeWatermark,
+		double *WritebackDRAMClockChangeWatermark,
+		double *StutterExitWatermark,
+		double *StutterEnterPlusExitWatermark,
+		double *Z8StutterExitWatermark,
+		double *Z8StutterEnterPlusExitWatermark,
+		double *MinActiveDRAMClockChangeLatencySupported)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	double EffectiveLBLatencyHidingY;
+	double EffectiveLBLatencyHidingC;
+	double LinesInDETY[DC__NUM_DPP__MAX];
+	double LinesInDETC;
+	unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
+	unsigned int LinesInDETCRoundedDownToSwath;
+	double FullDETBufferingTimeY;
+	double FullDETBufferingTimeC;
+	double ActiveDRAMClockChangeLatencyMarginY;
+	double ActiveDRAMClockChangeLatencyMarginC;
+	double WritebackDRAMClockChangeLatencyMargin;
+	double PlaneWithMinActiveDRAMClockChangeMargin;
+	double SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank;
+	double WritebackDRAMClockChangeLatencyHiding;
+	double TotalPixelBW = 0.0;
+	int k, j;
+
+	*UrgentWatermark = UrgentLatency + ExtraLatency;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency);
+	dml_print("DML::%s: ExtraLatency = %f\n", __func__, ExtraLatency);
+	dml_print("DML::%s: UrgentWatermark = %f\n", __func__, *UrgentWatermark);
+#endif
+
+	*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, DRAMClockChangeLatency);
+	dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, *DRAMClockChangeWatermark);
+#endif
+
+	v->TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (WritebackEnable[k] == true) {
+			v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
+		}
+	}
+
+	if (v->TotalActiveWriteback <= 1) {
+		*WritebackUrgentWatermark = WritebackLatency;
+	} else {
+		*WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+	}
+
+	if (v->TotalActiveWriteback <= 1) {
+		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency;
+	} else {
+		*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		TotalPixelBW = TotalPixelBW
+				+ DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k])
+						/ (HTotal[k] / PixelClock[k]);
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		double EffectiveDETBufferSizeY = DETBufferSizeY[k];
+
+		v->LBLatencyHidingSourceLinesY = dml_min(
+				(double) MaxLineBufferLines,
+				dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1);
+
+		v->LBLatencyHidingSourceLinesC = dml_min(
+				(double) MaxLineBufferLines,
+				dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1);
+
+		EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]);
+
+		EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]);
+
+		if (UnboundedRequestEnabled) {
+			EffectiveDETBufferSizeY = EffectiveDETBufferSizeY
+					+ CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] / (HTotal[k] / PixelClock[k]) / TotalPixelBW;
+		}
+
+		LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
+		FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k];
+		if (BytePerPixelDETC[k] > 0) {
+			LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
+			LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
+			FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k];
+		} else {
+			LinesInDETC = 0;
+			FullDETBufferingTimeC = 999999;
+		}
+
+		ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY
+				- ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark;
+
+		if (NumberOfActivePlanes > 1) {
+			ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY
+					- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k];
+		}
+
+		if (BytePerPixelDETC[k] > 0) {
+			ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC
+					- ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark;
+
+			if (NumberOfActivePlanes > 1) {
+				ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC
+						- (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k];
+			}
+			v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
+		} else {
+			v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
+		}
+
+		if (WritebackEnable[k] == true) {
+			WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024
+					/ (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4);
+			if (WritebackPixelFormat[k] == dm_444_64) {
+				WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2;
+			}
+			WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
+			v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
+		}
+	}
+
+	v->MinActiveDRAMClockChangeMargin = 999999;
+	PlaneWithMinActiveDRAMClockChangeMargin = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
+			v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
+			if (BlendingAndTiming[k] == k) {
+				PlaneWithMinActiveDRAMClockChangeMargin = k;
+			} else {
+				for (j = 0; j < NumberOfActivePlanes; ++j) {
+					if (BlendingAndTiming[k] == j) {
+						PlaneWithMinActiveDRAMClockChangeMargin = j;
+					}
+				}
+			}
+		}
+	}
+
+	*MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency;
+
+	SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin)
+				&& v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
+			SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
+		}
+	}
+
+	v->TotalNumberOfActiveOTG = 0;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (BlendingAndTiming[k] == k) {
+			v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
+		}
+	}
+
+	if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) {
+		*DRAMClockChangeSupport = dm_dram_clock_change_vactive;
+	} else if ((SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1
+			|| SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0) {
+		*DRAMClockChangeSupport = dm_dram_clock_change_vblank;
+	} else {
+		*DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
+	}
+
+	*StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
+	*StutterEnterPlusExitWatermark = (SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep);
+	*Z8StutterExitWatermark = SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
+	*Z8StutterEnterPlusExitWatermark = SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, *StutterExitWatermark);
+	dml_print("DML::%s: StutterEnterPlusExitWatermark = %f\n", __func__, *StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: Z8StutterExitWatermark = %f\n", __func__, *Z8StutterExitWatermark);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, *Z8StutterEnterPlusExitWatermark);
+#endif
+}
+
+static void CalculateDCFCLKDeepSleep(
+		struct display_mode_lib *mode_lib,
+		unsigned int NumberOfActivePlanes,
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		double VRatio[],
+		double VRatioChroma[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		int ReturnBusWidth,
+		double *DCFCLKDeepSleep)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	double DisplayPipeLineDeliveryTimeLuma;
+	double DisplayPipeLineDeliveryTimeChroma;
+	double ReadBandwidth = 0.0;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma = SwathWidthY[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
+		}
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma = SwathWidthC[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
+			}
+		}
+
+		if (BytePerPixelC[k] > 0) {
+			v->DCFCLKDeepSleepPerPlane[k] = dml_max(__DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 32.0 / DisplayPipeLineDeliveryTimeLuma,
+			__DML_MIN_DCFCLK_FACTOR__ * SwathWidthC[k] * BytePerPixelC[k] / 32.0 / DisplayPipeLineDeliveryTimeChroma);
+		} else {
+			v->DCFCLKDeepSleepPerPlane[k] = __DML_MIN_DCFCLK_FACTOR__ * SwathWidthY[k] * BytePerPixelY[k] / 64.0 / DisplayPipeLineDeliveryTimeLuma;
+		}
+		v->DCFCLKDeepSleepPerPlane[k] = dml_max(v->DCFCLKDeepSleepPerPlane[k], PixelClock[k] / 16);
+
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		ReadBandwidth = ReadBandwidth + ReadBandwidthLuma[k] + ReadBandwidthChroma[k];
+	}
+
+	*DCFCLKDeepSleep = dml_max(8.0, __DML_MIN_DCFCLK_FACTOR__ * ReadBandwidth / ReturnBusWidth);
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		*DCFCLKDeepSleep = dml_max(*DCFCLKDeepSleep, v->DCFCLKDeepSleepPerPlane[k]);
+	}
+}
+
+static void CalculateUrgentBurstFactor(
+		int swath_width_luma_ub,
+		int swath_width_chroma_ub,
+		unsigned int SwathHeightY,
+		unsigned int SwathHeightC,
+		double LineTime,
+		double UrgentLatency,
+		double CursorBufferSize,
+		unsigned int CursorWidth,
+		unsigned int CursorBPP,
+		double VRatio,
+		double VRatioC,
+		double BytePerPixelInDETY,
+		double BytePerPixelInDETC,
+		double DETBufferSizeY,
+		double DETBufferSizeC,
+		double *UrgentBurstFactorCursor,
+		double *UrgentBurstFactorLuma,
+		double *UrgentBurstFactorChroma,
+		bool *NotEnoughUrgentLatencyHiding)
+{
+	double LinesInDETLuma;
+	double LinesInDETChroma;
+	unsigned int LinesInCursorBuffer;
+	double CursorBufferSizeInTime;
+	double DETBufferSizeInTimeLuma;
+	double DETBufferSizeInTimeChroma;
+
+	*NotEnoughUrgentLatencyHiding = 0;
+
+	if (CursorWidth > 0) {
+		LinesInCursorBuffer = 1 << (unsigned int) dml_floor(dml_log2(CursorBufferSize * 1024.0 / (CursorWidth * CursorBPP / 8.0)), 1.0);
+		if (VRatio > 0) {
+			CursorBufferSizeInTime = LinesInCursorBuffer * LineTime / VRatio;
+			if (CursorBufferSizeInTime - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorCursor = 0;
+			} else {
+				*UrgentBurstFactorCursor = CursorBufferSizeInTime / (CursorBufferSizeInTime - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorCursor = 1;
+		}
+	}
+
+	LinesInDETLuma = DETBufferSizeY / BytePerPixelInDETY / swath_width_luma_ub;
+	if (VRatio > 0) {
+		DETBufferSizeInTimeLuma = dml_floor(LinesInDETLuma, SwathHeightY) * LineTime / VRatio;
+		if (DETBufferSizeInTimeLuma - UrgentLatency <= 0) {
+			*NotEnoughUrgentLatencyHiding = 1;
+			*UrgentBurstFactorLuma = 0;
+		} else {
+			*UrgentBurstFactorLuma = DETBufferSizeInTimeLuma / (DETBufferSizeInTimeLuma - UrgentLatency);
+		}
+	} else {
+		*UrgentBurstFactorLuma = 1;
+	}
+
+	if (BytePerPixelInDETC > 0) {
+		LinesInDETChroma = DETBufferSizeC / BytePerPixelInDETC / swath_width_chroma_ub;
+		if (VRatio > 0) {
+			DETBufferSizeInTimeChroma = dml_floor(LinesInDETChroma, SwathHeightC) * LineTime / VRatio;
+			if (DETBufferSizeInTimeChroma - UrgentLatency <= 0) {
+				*NotEnoughUrgentLatencyHiding = 1;
+				*UrgentBurstFactorChroma = 0;
+			} else {
+				*UrgentBurstFactorChroma = DETBufferSizeInTimeChroma / (DETBufferSizeInTimeChroma - UrgentLatency);
+			}
+		} else {
+			*UrgentBurstFactorChroma = 1;
+		}
+	}
+}
+
+static void CalculatePixelDeliveryTimes(
+		unsigned int NumberOfActivePlanes,
+		double VRatio[],
+		double VRatioChroma[],
+		double VRatioPrefetchY[],
+		double VRatioPrefetchC[],
+		unsigned int swath_width_luma_ub[],
+		unsigned int swath_width_chroma_ub[],
+		unsigned int DPPPerPlane[],
+		double HRatio[],
+		double HRatioChroma[],
+		double PixelClock[],
+		double PSCL_THROUGHPUT[],
+		double PSCL_THROUGHPUT_CHROMA[],
+		double DPPCLK[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		unsigned int NumberOfCursors[],
+		unsigned int CursorWidth[][DC__NUM_CURSOR__MAX],
+		unsigned int CursorBPP[][DC__NUM_CURSOR__MAX],
+		unsigned int BlockWidth256BytesY[],
+		unsigned int BlockHeight256BytesY[],
+		unsigned int BlockWidth256BytesC[],
+		unsigned int BlockHeight256BytesC[],
+		double DisplayPipeLineDeliveryTimeLuma[],
+		double DisplayPipeLineDeliveryTimeChroma[],
+		double DisplayPipeLineDeliveryTimeLumaPrefetch[],
+		double DisplayPipeLineDeliveryTimeChromaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeLuma[],
+		double DisplayPipeRequestDeliveryTimeChroma[],
+		double DisplayPipeRequestDeliveryTimeLumaPrefetch[],
+		double DisplayPipeRequestDeliveryTimeChromaPrefetch[],
+		double CursorRequestDeliveryTime[],
+		double CursorRequestDeliveryTimePrefetch[])
+{
+	double req_per_swath_ub;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (VRatio[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLuma[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChroma[k] = 0;
+		} else {
+			if (VRatioChroma[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChroma[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
+			}
+		}
+
+		if (VRatioPrefetchY[k] <= 1) {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] * DPPPerPlane[k] / HRatio[k] / PixelClock[k];
+		} else {
+			DisplayPipeLineDeliveryTimeLumaPrefetch[k] = swath_width_luma_ub[k] / PSCL_THROUGHPUT[k] / DPPCLK[k];
+		}
+
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeLineDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (VRatioPrefetchC[k] <= 1) {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] * DPPPerPlane[k] / HRatioChroma[k] / PixelClock[k];
+			} else {
+				DisplayPipeLineDeliveryTimeChromaPrefetch[k] = swath_width_chroma_ub[k] / PSCL_THROUGHPUT_CHROMA[k] / DPPCLK[k];
+			}
+		}
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (SourceScan[k] != dm_vert) {
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockWidth256BytesY[k];
+		} else {
+			req_per_swath_ub = swath_width_luma_ub[k] / BlockHeight256BytesY[k];
+		}
+		DisplayPipeRequestDeliveryTimeLuma[k] = DisplayPipeLineDeliveryTimeLuma[k] / req_per_swath_ub;
+		DisplayPipeRequestDeliveryTimeLumaPrefetch[k] = DisplayPipeLineDeliveryTimeLumaPrefetch[k] / req_per_swath_ub;
+		if (BytePerPixelC[k] == 0) {
+			DisplayPipeRequestDeliveryTimeChroma[k] = 0;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = 0;
+		} else {
+			if (SourceScan[k] != dm_vert) {
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockWidth256BytesC[k];
+			} else {
+				req_per_swath_ub = swath_width_chroma_ub[k] / BlockHeight256BytesC[k];
+			}
+			DisplayPipeRequestDeliveryTimeChroma[k] = DisplayPipeLineDeliveryTimeChroma[k] / req_per_swath_ub;
+			DisplayPipeRequestDeliveryTimeChromaPrefetch[k] = DisplayPipeLineDeliveryTimeChromaPrefetch[k] / req_per_swath_ub;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : HRatio = %f\n", __func__, k, HRatio[k]);
+		dml_print("DML::%s: k=%d : VRatio = %f\n", __func__, k, VRatio[k]);
+		dml_print("DML::%s: k=%d : HRatioChroma = %f\n", __func__, k, HRatioChroma[k]);
+		dml_print("DML::%s: k=%d : VRatioChroma = %f\n", __func__, k, VRatioChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeLineDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeLineDeliveryTimeChromaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLuma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLuma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeLumaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeLumaPrefetch[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChroma = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChroma[k]);
+		dml_print("DML::%s: k=%d : DisplayPipeRequestDeliveryTimeChromaPrefetch = %f\n", __func__, k, DisplayPipeRequestDeliveryTimeChromaPrefetch[k]);
+#endif
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		int cursor_req_per_width;
+		cursor_req_per_width = dml_ceil(CursorWidth[k][0] * CursorBPP[k][0] / 256 / 8, 1);
+		if (NumberOfCursors[k] > 0) {
+			if (VRatio[k] <= 1) {
+				CursorRequestDeliveryTime[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTime[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
+			}
+			if (VRatioPrefetchY[k] <= 1) {
+				CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / HRatio[k] / PixelClock[k] / cursor_req_per_width;
+			} else {
+				CursorRequestDeliveryTimePrefetch[k] = CursorWidth[k][0] / PSCL_THROUGHPUT[k] / DPPCLK[k] / cursor_req_per_width;
+			}
+		} else {
+			CursorRequestDeliveryTime[k] = 0;
+			CursorRequestDeliveryTimePrefetch[k] = 0;
+		}
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d : NumberOfCursors = %d\n", __func__, k, NumberOfCursors[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTime = %f\n", __func__, k, CursorRequestDeliveryTime[k]);
+		dml_print("DML::%s: k=%d : CursorRequestDeliveryTimePrefetch = %f\n", __func__, k, CursorRequestDeliveryTimePrefetch[k]);
+#endif
+	}
+}
+
+static void CalculateMetaAndPTETimes(
+		int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		int MetaChunkSize,
+		int MinMetaChunkSizeBytes,
+		int HTotal[],
+		double VRatio[],
+		double VRatioChroma[],
+		double DestinationLinesToRequestRowInVBlank[],
+		double DestinationLinesToRequestRowInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		enum scan_direction_class SourceScan[],
+		int dpte_row_height[],
+		int dpte_row_height_chroma[],
+		int meta_row_width[],
+		int meta_row_width_chroma[],
+		int meta_row_height[],
+		int meta_row_height_chroma[],
+		int meta_req_width[],
+		int meta_req_width_chroma[],
+		int meta_req_height[],
+		int meta_req_height_chroma[],
+		int dpte_group_bytes[],
+		int PTERequestSizeY[],
+		int PTERequestSizeC[],
+		int PixelPTEReqWidthY[],
+		int PixelPTEReqHeightY[],
+		int PixelPTEReqWidthC[],
+		int PixelPTEReqHeightC[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		double DST_Y_PER_PTE_ROW_NOM_L[],
+		double DST_Y_PER_PTE_ROW_NOM_C[],
+		double DST_Y_PER_META_ROW_NOM_L[],
+		double DST_Y_PER_META_ROW_NOM_C[],
+		double TimePerMetaChunkNominal[],
+		double TimePerChromaMetaChunkNominal[],
+		double TimePerMetaChunkVBlank[],
+		double TimePerChromaMetaChunkVBlank[],
+		double TimePerMetaChunkFlip[],
+		double TimePerChromaMetaChunkFlip[],
+		double time_per_pte_group_nom_luma[],
+		double time_per_pte_group_vblank_luma[],
+		double time_per_pte_group_flip_luma[],
+		double time_per_pte_group_nom_chroma[],
+		double time_per_pte_group_vblank_chroma[],
+		double time_per_pte_group_flip_chroma[])
+{
+	unsigned int meta_chunk_width;
+	unsigned int min_meta_chunk_width;
+	unsigned int meta_chunk_per_row_int;
+	unsigned int meta_row_remainder;
+	unsigned int meta_chunk_threshold;
+	unsigned int meta_chunks_per_row_ub;
+	unsigned int meta_chunk_width_chroma;
+	unsigned int min_meta_chunk_width_chroma;
+	unsigned int meta_chunk_per_row_int_chroma;
+	unsigned int meta_row_remainder_chroma;
+	unsigned int meta_chunk_threshold_chroma;
+	unsigned int meta_chunks_per_row_ub_chroma;
+	unsigned int dpte_group_width_luma;
+	unsigned int dpte_groups_per_row_luma_ub;
+	unsigned int dpte_group_width_chroma;
+	unsigned int dpte_groups_per_row_chroma_ub;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		DST_Y_PER_PTE_ROW_NOM_L[k] = dpte_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0) {
+			DST_Y_PER_PTE_ROW_NOM_C[k] = 0;
+		} else {
+			DST_Y_PER_PTE_ROW_NOM_C[k] = dpte_row_height_chroma[k] / VRatioChroma[k];
+		}
+		DST_Y_PER_META_ROW_NOM_L[k] = meta_row_height[k] / VRatio[k];
+		if (BytePerPixelC[k] == 0) {
+			DST_Y_PER_META_ROW_NOM_C[k] = 0;
+		} else {
+			DST_Y_PER_META_ROW_NOM_C[k] = meta_row_height_chroma[k] / VRatioChroma[k];
+		}
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (DCCEnable[k] == true) {
+			meta_chunk_width = MetaChunkSize * 1024 * 256 / BytePerPixelY[k] / meta_row_height[k];
+			min_meta_chunk_width = MinMetaChunkSizeBytes * 256 / BytePerPixelY[k] / meta_row_height[k];
+			meta_chunk_per_row_int = meta_row_width[k] / meta_chunk_width;
+			meta_row_remainder = meta_row_width[k] % meta_chunk_width;
+			if (SourceScan[k] != dm_vert) {
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
+			} else {
+				meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
+			}
+			if (meta_row_remainder <= meta_chunk_threshold) {
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+			} else {
+				meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+			}
+			TimePerMetaChunkNominal[k] = meta_row_height[k] / VRatio[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			TimePerMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub;
+			if (BytePerPixelC[k] == 0) {
+				TimePerChromaMetaChunkNominal[k] = 0;
+				TimePerChromaMetaChunkVBlank[k] = 0;
+				TimePerChromaMetaChunkFlip[k] = 0;
+			} else {
+				meta_chunk_width_chroma = MetaChunkSize * 1024 * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
+				min_meta_chunk_width_chroma = MinMetaChunkSizeBytes * 256 / BytePerPixelC[k] / meta_row_height_chroma[k];
+				meta_chunk_per_row_int_chroma = (double) meta_row_width_chroma[k] / meta_chunk_width_chroma;
+				meta_row_remainder_chroma = meta_row_width_chroma[k] % meta_chunk_width_chroma;
+				if (SourceScan[k] != dm_vert) {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_width_chroma[k];
+				} else {
+					meta_chunk_threshold_chroma = 2 * min_meta_chunk_width_chroma - meta_req_height_chroma[k];
+				}
+				if (meta_row_remainder_chroma <= meta_chunk_threshold_chroma) {
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 1;
+				} else {
+					meta_chunks_per_row_ub_chroma = meta_chunk_per_row_int_chroma + 2;
+				}
+				TimePerChromaMetaChunkNominal[k] = meta_row_height_chroma[k] / VRatioChroma[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkVBlank[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+				TimePerChromaMetaChunkFlip[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / meta_chunks_per_row_ub_chroma;
+			}
+		} else {
+			TimePerMetaChunkNominal[k] = 0;
+			TimePerMetaChunkVBlank[k] = 0;
+			TimePerMetaChunkFlip[k] = 0;
+			TimePerChromaMetaChunkNominal[k] = 0;
+			TimePerChromaMetaChunkVBlank[k] = 0;
+			TimePerChromaMetaChunkFlip[k] = 0;
+		}
+	}
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (GPUVMEnable == true) {
+			if (SourceScan[k] != dm_vert) {
+				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqWidthY[k];
+			} else {
+				dpte_group_width_luma = dpte_group_bytes[k] / PTERequestSizeY[k] * PixelPTEReqHeightY[k];
+			}
+			dpte_groups_per_row_luma_ub = dml_ceil(1.0 * dpte_row_width_luma_ub[k] / dpte_group_width_luma, 1);
+			time_per_pte_group_nom_luma[k] = DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_vblank_luma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			time_per_pte_group_flip_luma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_luma_ub;
+			if (BytePerPixelC[k] == 0) {
+				time_per_pte_group_nom_chroma[k] = 0;
+				time_per_pte_group_vblank_chroma[k] = 0;
+				time_per_pte_group_flip_chroma[k] = 0;
+			} else {
+				if (SourceScan[k] != dm_vert) {
+					dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqWidthC[k];
+				} else {
+					dpte_group_width_chroma = dpte_group_bytes[k] / PTERequestSizeC[k] * PixelPTEReqHeightC[k];
+				}
+				dpte_groups_per_row_chroma_ub = dml_ceil(1.0 * dpte_row_width_chroma_ub[k] / dpte_group_width_chroma, 1);
+				time_per_pte_group_nom_chroma[k] = DST_Y_PER_PTE_ROW_NOM_C[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_vblank_chroma[k] = DestinationLinesToRequestRowInVBlank[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+				time_per_pte_group_flip_chroma[k] = DestinationLinesToRequestRowInImmediateFlip[k] * HTotal[k] / PixelClock[k] / dpte_groups_per_row_chroma_ub;
+			}
+		} else {
+			time_per_pte_group_nom_luma[k] = 0;
+			time_per_pte_group_vblank_luma[k] = 0;
+			time_per_pte_group_flip_luma[k] = 0;
+			time_per_pte_group_nom_chroma[k] = 0;
+			time_per_pte_group_vblank_chroma[k] = 0;
+			time_per_pte_group_flip_chroma[k] = 0;
+		}
+	}
+}
+
+static void CalculateVMGroupAndRequestTimes(
+		unsigned int NumberOfActivePlanes,
+		bool GPUVMEnable,
+		unsigned int GPUVMMaxPageTableLevels,
+		unsigned int HTotal[],
+		int BytePerPixelC[],
+		double DestinationLinesToRequestVMInVBlank[],
+		double DestinationLinesToRequestVMInImmediateFlip[],
+		bool DCCEnable[],
+		double PixelClock[],
+		int dpte_row_width_luma_ub[],
+		int dpte_row_width_chroma_ub[],
+		int vm_group_bytes[],
+		unsigned int dpde0_bytes_per_frame_ub_l[],
+		unsigned int dpde0_bytes_per_frame_ub_c[],
+		int meta_pte_bytes_per_frame_ub_l[],
+		int meta_pte_bytes_per_frame_ub_c[],
+		double TimePerVMGroupVBlank[],
+		double TimePerVMGroupFlip[],
+		double TimePerVMRequestVBlank[],
+		double TimePerVMRequestFlip[])
+{
+	int num_group_per_lower_vm_stage;
+	int num_req_per_lower_vm_stage;
+	int k;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (GPUVMEnable == true && (DCCEnable[k] == true || GPUVMMaxPageTableLevels > 1)) {
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+							+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
+				} else {
+					num_group_per_lower_vm_stage = dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
+					} else {
+						num_group_per_lower_vm_stage = dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_group_per_lower_vm_stage = 2 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (dpde0_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_c[k]) / (double) (vm_group_bytes[k]), 1);
+					} else {
+						num_group_per_lower_vm_stage = 1 + dml_ceil((double) (dpde0_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1)
+								+ dml_ceil((double) (meta_pte_bytes_per_frame_ub_l[k]) / (double) (vm_group_bytes[k]), 1);
+					}
+				}
+			}
+
+			if (DCCEnable[k] == false) {
+				if (BytePerPixelC[k] > 0) {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64;
+				} else {
+					num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64;
+				}
+			} else {
+				if (GPUVMMaxPageTableLevels == 1) {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				} else {
+					if (BytePerPixelC[k] > 0) {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + dpde0_bytes_per_frame_ub_c[k] / 64
+								+ meta_pte_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_c[k] / 64;
+					} else {
+						num_req_per_lower_vm_stage = dpde0_bytes_per_frame_ub_l[k] / 64 + meta_pte_bytes_per_frame_ub_l[k] / 64;
+					}
+				}
+			}
+
+			TimePerVMGroupVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMGroupFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_group_per_lower_vm_stage;
+			TimePerVMRequestVBlank[k] = DestinationLinesToRequestVMInVBlank[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+			TimePerVMRequestFlip[k] = DestinationLinesToRequestVMInImmediateFlip[k] * HTotal[k] / PixelClock[k] / num_req_per_lower_vm_stage;
+
+			if (GPUVMMaxPageTableLevels > 2) {
+				TimePerVMGroupVBlank[k] = TimePerVMGroupVBlank[k] / 2;
+				TimePerVMGroupFlip[k] = TimePerVMGroupFlip[k] / 2;
+				TimePerVMRequestVBlank[k] = TimePerVMRequestVBlank[k] / 2;
+				TimePerVMRequestFlip[k] = TimePerVMRequestFlip[k] / 2;
+			}
+
+		} else {
+			TimePerVMGroupVBlank[k] = 0;
+			TimePerVMGroupFlip[k] = 0;
+			TimePerVMRequestVBlank[k] = 0;
+			TimePerVMRequestFlip[k] = 0;
+		}
+	}
+}
+
+static void CalculateStutterEfficiency(
+		struct display_mode_lib *mode_lib,
+		int CompressedBufferSizeInkByte,
+		bool UnboundedRequestEnabled,
+		int ConfigReturnBufferSizeInKByte,
+		int MetaFIFOSizeInKEntries,
+		int ZeroSizeBufferEntries,
+		int NumberOfActivePlanes,
+		int ROBBufferSizeInKByte,
+		double TotalDataReadBandwidth,
+		double DCFCLK,
+		double ReturnBW,
+		double COMPBUF_RESERVED_SPACE_64B,
+		double COMPBUF_RESERVED_SPACE_ZS,
+		double SRExitTime,
+		double SRExitZ8Time,
+		bool SynchronizedVBlank,
+		double Z8StutterEnterPlusExitWatermark,
+		double StutterEnterPlusExitWatermark,
+		bool ProgressiveToInterlaceUnitInOPP,
+		bool Interlace[],
+		double MinTTUVBlank[],
+		int DPPPerPlane[],
+		unsigned int DETBufferSizeY[],
+		int BytePerPixelY[],
+		double BytePerPixelDETY[],
+		double SwathWidthY[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		double NetDCCRateLuma[],
+		double NetDCCRateChroma[],
+		double DCCFractionOfZeroSizeRequestsLuma[],
+		double DCCFractionOfZeroSizeRequestsChroma[],
+		int HTotal[],
+		int VTotal[],
+		double PixelClock[],
+		double VRatio[],
+		enum scan_direction_class SourceScan[],
+		int BlockHeight256BytesY[],
+		int BlockWidth256BytesY[],
+		int BlockHeight256BytesC[],
+		int BlockWidth256BytesC[],
+		int DCCYMaxUncompressedBlock[],
+		int DCCCMaxUncompressedBlock[],
+		int VActive[],
+		bool DCCEnable[],
+		bool WritebackEnable[],
+		double ReadBandwidthPlaneLuma[],
+		double ReadBandwidthPlaneChroma[],
+		double meta_row_bw[],
+		double dpte_row_bw[],
+		double *StutterEfficiencyNotIncludingVBlank,
+		double *StutterEfficiency,
+		int *NumberOfStutterBurstsPerFrame,
+		double *Z8StutterEfficiencyNotIncludingVBlank,
+		double *Z8StutterEfficiency,
+		int *Z8NumberOfStutterBurstsPerFrame,
+		double *StutterPeriod)
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+
+	double DETBufferingTimeY;
+	double SwathWidthYCriticalPlane = 0;
+	double VActiveTimeCriticalPlane = 0;
+	double FrameTimeCriticalPlane = 0;
+	int BytePerPixelYCriticalPlane = 0;
+	double LinesToFinishSwathTransferStutterCriticalPlane = 0;
+	double MinTTUVBlankCriticalPlane = 0;
+	double TotalCompressedReadBandwidth;
+	double TotalRowReadBandwidth;
+	double AverageDCCCompressionRate;
+	double EffectiveCompressedBufferSize;
+	double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer;
+	double StutterBurstTime;
+	int TotalActiveWriteback;
+	double LinesInDETY;
+	double LinesInDETYRoundedDownToSwath;
+	double MaximumEffectiveCompressionLuma;
+	double MaximumEffectiveCompressionChroma;
+	double TotalZeroSizeRequestReadBandwidth;
+	double TotalZeroSizeCompressedReadBandwidth;
+	double AverageDCCZeroSizeFraction;
+	double AverageZeroSizeCompressionRate;
+	int TotalNumberOfActiveOTG = 0;
+	double LastStutterPeriod = 0.0;
+	double LastZ8StutterPeriod = 0.0;
+	int k;
+
+	TotalZeroSizeRequestReadBandwidth = 0;
+	TotalZeroSizeCompressedReadBandwidth = 0;
+	TotalRowReadBandwidth = 0;
+	TotalCompressedReadBandwidth = 0;
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (DCCEnable[k] == true) {
+			if ((SourceScan[k] == dm_vert && BlockWidth256BytesY[k] > SwathHeightY[k]) || (SourceScan[k] != dm_vert && BlockHeight256BytesY[k] > SwathHeightY[k])
+					|| DCCYMaxUncompressedBlock[k] < 256) {
+				MaximumEffectiveCompressionLuma = 2;
+			} else {
+				MaximumEffectiveCompressionLuma = 4;
+			}
+			TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] / dml_min(NetDCCRateLuma[k], MaximumEffectiveCompressionLuma);
+			TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k];
+			TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+					+ ReadBandwidthPlaneLuma[k] * DCCFractionOfZeroSizeRequestsLuma[k] / MaximumEffectiveCompressionLuma;
+			if (ReadBandwidthPlaneChroma[k] > 0) {
+				if ((SourceScan[k] == dm_vert && BlockWidth256BytesC[k] > SwathHeightC[k])
+						|| (SourceScan[k] != dm_vert && BlockHeight256BytesC[k] > SwathHeightC[k]) || DCCCMaxUncompressedBlock[k] < 256) {
+					MaximumEffectiveCompressionChroma = 2;
+				} else {
+					MaximumEffectiveCompressionChroma = 4;
+				}
+				TotalCompressedReadBandwidth = TotalCompressedReadBandwidth
+						+ ReadBandwidthPlaneChroma[k] / dml_min(NetDCCRateChroma[k], MaximumEffectiveCompressionChroma);
+				TotalZeroSizeRequestReadBandwidth = TotalZeroSizeRequestReadBandwidth + ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k];
+				TotalZeroSizeCompressedReadBandwidth = TotalZeroSizeCompressedReadBandwidth
+						+ ReadBandwidthPlaneChroma[k] * DCCFractionOfZeroSizeRequestsChroma[k] / MaximumEffectiveCompressionChroma;
+			}
+		} else {
+			TotalCompressedReadBandwidth = TotalCompressedReadBandwidth + ReadBandwidthPlaneLuma[k] + ReadBandwidthPlaneChroma[k];
+		}
+		TotalRowReadBandwidth = TotalRowReadBandwidth + DPPPerPlane[k] * (meta_row_bw[k] + dpte_row_bw[k]);
+	}
+
+	AverageDCCCompressionRate = TotalDataReadBandwidth / TotalCompressedReadBandwidth;
+	AverageDCCZeroSizeFraction = TotalZeroSizeRequestReadBandwidth / TotalDataReadBandwidth;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotalCompressedReadBandwidth = %f\n", __func__, TotalCompressedReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeRequestReadBandwidth = %f\n", __func__, TotalZeroSizeRequestReadBandwidth);
+	dml_print("DML::%s: TotalZeroSizeCompressedReadBandwidth = %f\n", __func__, TotalZeroSizeCompressedReadBandwidth);
+	dml_print("DML::%s: MaximumEffectiveCompressionLuma = %f\n", __func__, MaximumEffectiveCompressionLuma);
+	dml_print("DML::%s: MaximumEffectiveCompressionChroma = %f\n", __func__, MaximumEffectiveCompressionChroma);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: AverageDCCZeroSizeFraction = %f\n", __func__, AverageDCCZeroSizeFraction);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, CompressedBufferSizeInkByte);
+#endif
+
+	if (AverageDCCZeroSizeFraction == 1) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth / TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = MetaFIFOSizeInKEntries * 1024 * 64 * AverageZeroSizeCompressionRate + (ZeroSizeBufferEntries - COMPBUF_RESERVED_SPACE_ZS) * 64 * AverageZeroSizeCompressionRate;
+	} else if (AverageDCCZeroSizeFraction > 0) {
+		AverageZeroSizeCompressionRate = TotalZeroSizeRequestReadBandwidth / TotalZeroSizeCompressedReadBandwidth;
+		EffectiveCompressedBufferSize = dml_min(
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				MetaFIFOSizeInKEntries * 1024 * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / AverageDCCCompressionRate))
+					+ dml_min((ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate,
+						(ZeroSizeBufferEntries - COMPBUF_RESERVED_SPACE_ZS) * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+		dml_print("DML::%s: min 1 = %f\n", __func__, CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print(
+				"DML::%s: min 2 = %f\n",
+				__func__,
+				MetaFIFOSizeInKEntries * 1024 * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate + 1 / AverageDCCCompressionRate));
+		dml_print("DML::%s: min 3 = %f\n", __func__, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 4 = %f\n", __func__, ZeroSizeBufferEntries * 64 / (AverageDCCZeroSizeFraction / AverageZeroSizeCompressionRate));
+	} else {
+		EffectiveCompressedBufferSize = dml_min(
+				CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate,
+				MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate) + (ROBBufferSizeInKByte * 1024 - COMPBUF_RESERVED_SPACE_64B * 64) * AverageDCCCompressionRate;
+		dml_print("DML::%s: min 1 = %f\n", __func__, CompressedBufferSizeInkByte * 1024 * AverageDCCCompressionRate);
+		dml_print("DML::%s: min 2 = %f\n", __func__, MetaFIFOSizeInKEntries * 1024 * 64 * AverageDCCCompressionRate);
+	}
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: MetaFIFOSizeInKEntries = %d\n", __func__, MetaFIFOSizeInKEntries);
+	dml_print("DML::%s: AverageZeroSizeCompressionRate = %f\n", __func__, AverageZeroSizeCompressionRate);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+#endif
+
+	*StutterPeriod = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		LinesInDETY = (DETBufferSizeY[k] + (UnboundedRequestEnabled == true ? EffectiveCompressedBufferSize : 0) * ReadBandwidthPlaneLuma[k] / TotalDataReadBandwidth)
+				/ BytePerPixelDETY[k] / SwathWidthY[k];
+		LinesInDETYRoundedDownToSwath = dml_floor(LinesInDETY, SwathHeightY[k]);
+		DETBufferingTimeY = LinesInDETYRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatio[k];
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%0d DETBufferSizeY = %f\n", __func__, k, DETBufferSizeY[k]);
+		dml_print("DML::%s: k=%0d BytePerPixelDETY = %f\n", __func__, k, BytePerPixelDETY[k]);
+		dml_print("DML::%s: k=%0d SwathWidthY = %f\n", __func__, k, SwathWidthY[k]);
+		dml_print("DML::%s: k=%0d ReadBandwidthPlaneLuma = %f\n", __func__, k, ReadBandwidthPlaneLuma[k]);
+		dml_print("DML::%s: k=%0d TotalDataReadBandwidth = %f\n", __func__, k, TotalDataReadBandwidth);
+		dml_print("DML::%s: k=%0d LinesInDETY = %f\n", __func__, k, LinesInDETY);
+		dml_print("DML::%s: k=%0d LinesInDETYRoundedDownToSwath = %f\n", __func__, k, LinesInDETYRoundedDownToSwath);
+		dml_print("DML::%s: k=%0d HTotal = %d\n", __func__, k, HTotal[k]);
+		dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
+		dml_print("DML::%s: k=%0d VRatio = %f\n", __func__, k, VRatio[k]);
+		dml_print("DML::%s: k=%0d DETBufferingTimeY = %f\n", __func__, k, DETBufferingTimeY);
+		dml_print("DML::%s: k=%0d PixelClock = %f\n", __func__, k, PixelClock[k]);
+#endif
+
+		if (k == 0 || DETBufferingTimeY < *StutterPeriod) {
+			bool isInterlaceTiming = Interlace[k] && !ProgressiveToInterlaceUnitInOPP;
+
+			*StutterPeriod = DETBufferingTimeY;
+			FrameTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VTotal[k] / 2.0, 1.0) : VTotal[k]) * HTotal[k] / PixelClock[k];
+			VActiveTimeCriticalPlane = (isInterlaceTiming ? dml_floor(VActive[k] / 2.0, 1.0) : VActive[k]) * HTotal[k] / PixelClock[k];
+			BytePerPixelYCriticalPlane = BytePerPixelY[k];
+			SwathWidthYCriticalPlane = SwathWidthY[k];
+			LinesToFinishSwathTransferStutterCriticalPlane = SwathHeightY[k] - (LinesInDETY - LinesInDETYRoundedDownToSwath);
+			MinTTUVBlankCriticalPlane = MinTTUVBlank[k];
+
+#ifdef __DML_VBA_DEBUG__
+			dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+			dml_print("DML::%s: MinTTUVBlankCriticalPlane = %f\n", __func__, MinTTUVBlankCriticalPlane);
+			dml_print("DML::%s: FrameTimeCriticalPlane = %f\n", __func__, FrameTimeCriticalPlane);
+			dml_print("DML::%s: VActiveTimeCriticalPlane = %f\n", __func__, VActiveTimeCriticalPlane);
+			dml_print("DML::%s: BytePerPixelYCriticalPlane = %d\n", __func__, BytePerPixelYCriticalPlane);
+			dml_print("DML::%s: SwathWidthYCriticalPlane = %f\n", __func__, SwathWidthYCriticalPlane);
+			dml_print("DML::%s: LinesToFinishSwathTransferStutterCriticalPlane = %f\n", __func__, LinesToFinishSwathTransferStutterCriticalPlane);
+#endif
+		}
+	}
+
+	PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = dml_min(*StutterPeriod * TotalDataReadBandwidth, EffectiveCompressedBufferSize);
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: ROBBufferSizeInKByte = %d\n", __func__, ROBBufferSizeInKByte);
+	dml_print("DML::%s: AverageDCCCompressionRate = %f\n", __func__, AverageDCCCompressionRate);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", __func__, *StutterPeriod * TotalDataReadBandwidth);
+	dml_print("DML::%s: ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate + EffectiveCompressedBufferSize = %f\n", __func__, ROBBufferSizeInKByte * 1024 * AverageDCCCompressionRate + EffectiveCompressedBufferSize);
+	dml_print("DML::%s: EffectiveCompressedBufferSize = %f\n", __func__, EffectiveCompressedBufferSize);
+	dml_print("DML::%s: PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer);
+	dml_print("DML::%s: ReturnBW = %f\n", __func__, ReturnBW);
+	dml_print("DML::%s: TotalDataReadBandwidth = %f\n", __func__, TotalDataReadBandwidth);
+	dml_print("DML::%s: TotalRowReadBandwidth = %f\n", __func__, TotalRowReadBandwidth);
+	dml_print("DML::%s: DCFCLK = %f\n", __func__, DCFCLK);
+#endif
+
+	StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / ReturnBW
+			+ (*StutterPeriod * TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64)
+			+ *StutterPeriod * TotalRowReadBandwidth / ReturnBW;
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: Part 1 = %f\n", __func__, PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / ReturnBW);
+	dml_print("DML::%s: StutterPeriod * TotalDataReadBandwidth = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth));
+	dml_print("DML::%s: Part 2 = %f\n", __func__, (*StutterPeriod * TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (DCFCLK * 64));
+	dml_print("DML::%s: Part 3 = %f\n", __func__, *StutterPeriod * TotalRowReadBandwidth / ReturnBW);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+#endif
+	StutterBurstTime = dml_max(StutterBurstTime, LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
+
+	dml_print(
+			"DML::%s: Time to finish residue swath=%f\n",
+			__func__,
+			LinesToFinishSwathTransferStutterCriticalPlane * BytePerPixelYCriticalPlane * SwathWidthYCriticalPlane / ReturnBW);
+
+	TotalActiveWriteback = 0;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (WritebackEnable[k]) {
+			TotalActiveWriteback = TotalActiveWriteback + 1;
+		}
+	}
+
+	if (TotalActiveWriteback == 0) {
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: SRExitTime = %f\n", __func__, SRExitTime);
+		dml_print("DML::%s: SRExitZ8Time = %f\n", __func__, SRExitZ8Time);
+		dml_print("DML::%s: StutterBurstTime = %f (final)\n", __func__, StutterBurstTime);
+		dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+#endif
+		*StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitTime + StutterBurstTime) / *StutterPeriod) * 100;
+		*Z8StutterEfficiencyNotIncludingVBlank = dml_max(0., 1 - (SRExitZ8Time + StutterBurstTime) / *StutterPeriod) * 100;
+		*NumberOfStutterBurstsPerFrame = (*StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0);
+		*Z8NumberOfStutterBurstsPerFrame = (*Z8StutterEfficiencyNotIncludingVBlank > 0 ? dml_ceil(VActiveTimeCriticalPlane / *StutterPeriod, 1) : 0);
+	} else {
+		*StutterEfficiencyNotIncludingVBlank = 0.;
+		*Z8StutterEfficiencyNotIncludingVBlank = 0.;
+		*NumberOfStutterBurstsPerFrame = 0;
+		*Z8NumberOfStutterBurstsPerFrame = 0;
+	}
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: VActiveTimeCriticalPlane = %f\n", __func__, VActiveTimeCriticalPlane);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *Z8StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: NumberOfStutterBurstsPerFrame = %d\n", __func__, *NumberOfStutterBurstsPerFrame);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+#endif
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (v->BlendingAndTiming[k] == k) {
+			TotalNumberOfActiveOTG = TotalNumberOfActiveOTG + 1;
+		}
+	}
+
+	if (*StutterEfficiencyNotIncludingVBlank > 0) {
+		LastStutterPeriod = VActiveTimeCriticalPlane - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+
+		if ((SynchronizedVBlank || TotalNumberOfActiveOTG == 1) && LastStutterPeriod + MinTTUVBlankCriticalPlane > StutterEnterPlusExitWatermark) {
+			*StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitTime + StutterBurstTime * VActiveTimeCriticalPlane
+					/ *StutterPeriod) / FrameTimeCriticalPlane) * 100;
+		} else {
+			*StutterEfficiency = *StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*StutterEfficiency = 0;
+	}
+
+	if (*Z8StutterEfficiencyNotIncludingVBlank > 0) {
+		LastZ8StutterPeriod = VActiveTimeCriticalPlane - (*NumberOfStutterBurstsPerFrame - 1) * *StutterPeriod;
+		if ((SynchronizedVBlank || TotalNumberOfActiveOTG == 1) && LastZ8StutterPeriod + MinTTUVBlankCriticalPlane > Z8StutterEnterPlusExitWatermark) {
+			*Z8StutterEfficiency = (1 - (*NumberOfStutterBurstsPerFrame * SRExitZ8Time + StutterBurstTime * VActiveTimeCriticalPlane
+					/ *StutterPeriod) / FrameTimeCriticalPlane) * 100;
+		} else {
+			*Z8StutterEfficiency = *Z8StutterEfficiencyNotIncludingVBlank;
+		}
+	} else {
+		*Z8StutterEfficiency = 0.;
+	}
+
+	dml_print("DML::%s: LastZ8StutterPeriod = %f\n", __func__, LastZ8StutterPeriod);
+	dml_print("DML::%s: Z8StutterEnterPlusExitWatermark = %f\n", __func__, Z8StutterEnterPlusExitWatermark);
+	dml_print("DML::%s: StutterBurstTime = %f\n", __func__, StutterBurstTime);
+	dml_print("DML::%s: StutterPeriod = %f\n", __func__, *StutterPeriod);
+	dml_print("DML::%s: StutterEfficiency = %f\n", __func__, *StutterEfficiency);
+	dml_print("DML::%s: Z8StutterEfficiency = %f\n", __func__, *Z8StutterEfficiency);
+	dml_print("DML::%s: StutterEfficiencyNotIncludingVBlank = %f\n", __func__, *StutterEfficiencyNotIncludingVBlank);
+	dml_print("DML::%s: Z8NumberOfStutterBurstsPerFrame = %d\n", __func__, *Z8NumberOfStutterBurstsPerFrame);
+}
+
+static void CalculateSwathAndDETConfiguration(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		unsigned int DETBufferSizeInKByte,
+		double MaximumSwathWidthLuma[],
+		double MaximumSwathWidthChroma[],
+		enum scan_direction_class SourceScan[],
+		enum source_format_class SourcePixelFormat[],
+		enum dm_swizzle_mode SurfaceTiling[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BlendingAndTiming[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		double BytePerPixDETY[],
+		double BytePerPixDETC[],
+		int HActive[],
+		double HRatio[],
+		double HRatioChroma[],
+		int DPPPerPlane[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[],
+		double SwathWidth[],
+		double SwathWidthChroma[],
+		int SwathHeightY[],
+		int SwathHeightC[],
+		unsigned int DETBufferSizeY[],
+		unsigned int DETBufferSizeC[],
+		bool ViewportSizeSupportPerPlane[],
+		bool *ViewportSizeSupport)
+{
+	int MaximumSwathHeightY[DC__NUM_DPP__MAX];
+	int MaximumSwathHeightC[DC__NUM_DPP__MAX];
+	int MinimumSwathHeightY;
+	int MinimumSwathHeightC;
+	int RoundedUpMaxSwathSizeBytesY;
+	int RoundedUpMaxSwathSizeBytesC;
+	int RoundedUpMinSwathSizeBytesY;
+	int RoundedUpMinSwathSizeBytesC;
+	int RoundedUpSwathSizeBytesY;
+	int RoundedUpSwathSizeBytesC;
+	double SwathWidthSingleDPP[DC__NUM_DPP__MAX];
+	double SwathWidthSingleDPPChroma[DC__NUM_DPP__MAX];
+	int k;
+
+	CalculateSwathWidth(
+			ForceSingleDPP,
+			NumberOfActivePlanes,
+			SourcePixelFormat,
+			SourceScan,
+			ViewportWidth,
+			ViewportHeight,
+			SurfaceWidthY,
+			SurfaceWidthC,
+			SurfaceHeightY,
+			SurfaceHeightC,
+			ODMCombineEnabled,
+			BytePerPixY,
+			BytePerPixC,
+			Read256BytesBlockHeightY,
+			Read256BytesBlockHeightC,
+			Read256BytesBlockWidthY,
+			Read256BytesBlockWidthC,
+			BlendingAndTiming,
+			HActive,
+			HRatio,
+			DPPPerPlane,
+			SwathWidthSingleDPP,
+			SwathWidthSingleDPPChroma,
+			SwathWidth,
+			SwathWidthChroma,
+			MaximumSwathHeightY,
+			MaximumSwathHeightC,
+			swath_width_luma_ub,
+			swath_width_chroma_ub);
+
+	*ViewportSizeSupport = true;
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if ((SourcePixelFormat[k] == dm_444_64 || SourcePixelFormat[k] == dm_444_32 || SourcePixelFormat[k] == dm_444_16 || SourcePixelFormat[k] == dm_mono_16
+				|| SourcePixelFormat[k] == dm_mono_8 || SourcePixelFormat[k] == dm_rgbe)) {
+			if (SurfaceTiling[k] == dm_sw_linear
+					|| (SourcePixelFormat[k] == dm_444_64
+							&& (SurfaceTiling[k] == dm_sw_64kb_s || SurfaceTiling[k] == dm_sw_64kb_s_t || SurfaceTiling[k] == dm_sw_64kb_s_x)
+							&& SourceScan[k] != dm_vert)) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+			} else if (SourcePixelFormat[k] == dm_444_8 && SourceScan[k] == dm_vert) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+			} else {
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+			}
+			MinimumSwathHeightC = MaximumSwathHeightC[k];
+		} else {
+			if (SurfaceTiling[k] == dm_sw_linear) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+				MinimumSwathHeightC = MaximumSwathHeightC[k];
+			} else if (SourcePixelFormat[k] == dm_rgbe_alpha && SourceScan[k] == dm_vert) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+				MinimumSwathHeightC = MaximumSwathHeightC[k];
+			} else if (SourcePixelFormat[k] == dm_rgbe_alpha) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+				MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
+			} else if (SourcePixelFormat[k] == dm_420_8 && SourceScan[k] == dm_vert) {
+				MinimumSwathHeightY = MaximumSwathHeightY[k];
+				MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
+			} else {
+				MinimumSwathHeightC = MaximumSwathHeightC[k] / 2;
+				MinimumSwathHeightY = MaximumSwathHeightY[k] / 2;
+			}
+		}
+
+		RoundedUpMaxSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MaximumSwathHeightY[k];
+		RoundedUpMinSwathSizeBytesY = swath_width_luma_ub[k] * BytePerPixDETY[k] * MinimumSwathHeightY;
+		if (SourcePixelFormat[k] == dm_420_10) {
+			RoundedUpMaxSwathSizeBytesY = dml_ceil((double) RoundedUpMaxSwathSizeBytesY, 256);
+			RoundedUpMinSwathSizeBytesY = dml_ceil((double) RoundedUpMinSwathSizeBytesY, 256);
+		}
+		RoundedUpMaxSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MaximumSwathHeightC[k];
+		RoundedUpMinSwathSizeBytesC = swath_width_chroma_ub[k] * BytePerPixDETC[k] * MinimumSwathHeightC;
+		if (SourcePixelFormat[k] == dm_420_10) {
+			RoundedUpMaxSwathSizeBytesC = dml_ceil(RoundedUpMaxSwathSizeBytesC, 256);
+			RoundedUpMinSwathSizeBytesC = dml_ceil(RoundedUpMinSwathSizeBytesC, 256);
+		}
+
+		if (RoundedUpMaxSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
+		} else if (RoundedUpMaxSwathSizeBytesY >= 1.5 * RoundedUpMaxSwathSizeBytesC
+				&& RoundedUpMinSwathSizeBytesY + RoundedUpMaxSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) {
+			SwathHeightY[k] = MinimumSwathHeightY;
+			SwathHeightC[k] = MaximumSwathHeightC[k];
+			RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMaxSwathSizeBytesC;
+		} else if (RoundedUpMaxSwathSizeBytesY < 1.5 * RoundedUpMaxSwathSizeBytesC
+				&& RoundedUpMaxSwathSizeBytesY + RoundedUpMinSwathSizeBytesC <= DETBufferSizeInKByte * 1024 / 2) {
+			SwathHeightY[k] = MaximumSwathHeightY[k];
+			SwathHeightC[k] = MinimumSwathHeightC;
+			RoundedUpSwathSizeBytesY = RoundedUpMaxSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMinSwathSizeBytesC;
+		} else {
+			SwathHeightY[k] = MinimumSwathHeightY;
+			SwathHeightC[k] = MinimumSwathHeightC;
+			RoundedUpSwathSizeBytesY = RoundedUpMinSwathSizeBytesY;
+			RoundedUpSwathSizeBytesC = RoundedUpMinSwathSizeBytesC;
+		}
+		{
+		double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
+		if (SwathHeightC[k] == 0) {
+			DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024;
+			DETBufferSizeC[k] = 0;
+		} else if (RoundedUpSwathSizeBytesY <= 1.5 * RoundedUpSwathSizeBytesC) {
+			DETBufferSizeY[k] = actDETBufferSizeInKByte * 1024 / 2;
+			DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 2;
+		} else {
+			DETBufferSizeY[k] = dml_floor(actDETBufferSizeInKByte * 1024 * 2 / 3, 1024);
+			DETBufferSizeC[k] = actDETBufferSizeInKByte * 1024 / 3;
+		}
+
+		if (RoundedUpMinSwathSizeBytesY + RoundedUpMinSwathSizeBytesC > actDETBufferSizeInKByte * 1024 / 2 || SwathWidth[k] > MaximumSwathWidthLuma[k]
+				|| (SwathHeightC[k] > 0 && SwathWidthChroma[k] > MaximumSwathWidthChroma[k])) {
+			*ViewportSizeSupport = false;
+			ViewportSizeSupportPerPlane[k] = false;
+		} else {
+			ViewportSizeSupportPerPlane[k] = true;
+		}
+		}
+	}
+}
+
+static void CalculateSwathWidth(
+		bool ForceSingleDPP,
+		int NumberOfActivePlanes,
+		enum source_format_class SourcePixelFormat[],
+		enum scan_direction_class SourceScan[],
+		int ViewportWidth[],
+		int ViewportHeight[],
+		int SurfaceWidthY[],
+		int SurfaceWidthC[],
+		int SurfaceHeightY[],
+		int SurfaceHeightC[],
+		enum odm_combine_mode ODMCombineEnabled[],
+		int BytePerPixY[],
+		int BytePerPixC[],
+		int Read256BytesBlockHeightY[],
+		int Read256BytesBlockHeightC[],
+		int Read256BytesBlockWidthY[],
+		int Read256BytesBlockWidthC[],
+		int BlendingAndTiming[],
+		int HActive[],
+		double HRatio[],
+		int DPPPerPlane[],
+		double SwathWidthSingleDPPY[],
+		double SwathWidthSingleDPPC[],
+		double SwathWidthY[],
+		double SwathWidthC[],
+		int MaximumSwathHeightY[],
+		int MaximumSwathHeightC[],
+		int swath_width_luma_ub[],
+		int swath_width_chroma_ub[])
+{
+	enum odm_combine_mode MainPlaneODMCombine;
+	int j, k;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: NumberOfActivePlanes = %d\n", __func__, NumberOfActivePlanes);
+#endif
+
+	for (k = 0; k < NumberOfActivePlanes; ++k) {
+		if (SourceScan[k] != dm_vert) {
+			SwathWidthSingleDPPY[k] = ViewportWidth[k];
+		} else {
+			SwathWidthSingleDPPY[k] = ViewportHeight[k];
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d ViewportWidth=%d\n", __func__, k, ViewportWidth[k]);
+		dml_print("DML::%s: k=%d ViewportHeight=%d\n", __func__, k, ViewportHeight[k]);
+#endif
+
+		MainPlaneODMCombine = ODMCombineEnabled[k];
+		for (j = 0; j < NumberOfActivePlanes; ++j) {
+			if (BlendingAndTiming[k] == j) {
+				MainPlaneODMCombine = ODMCombineEnabled[j];
+			}
+		}
+
+		if (MainPlaneODMCombine == dm_odm_combine_mode_4to1) {
+			SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 4.0 * HRatio[k]));
+		} else if (MainPlaneODMCombine == dm_odm_combine_mode_2to1) {
+			SwathWidthY[k] = dml_min(SwathWidthSingleDPPY[k], dml_round(HActive[k] / 2.0 * HRatio[k]));
+		} else if (DPPPerPlane[k] == 2) {
+			SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2;
+		} else {
+			SwathWidthY[k] = SwathWidthSingleDPPY[k];
+		}
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d SwathWidthSingleDPPY=%f\n", __func__, k, SwathWidthSingleDPPY[k]);
+		dml_print("DML::%s: k=%d SwathWidthY=%f\n", __func__, k, SwathWidthY[k]);
+#endif
+
+		if (SourcePixelFormat[k] == dm_420_8 || SourcePixelFormat[k] == dm_420_10 || SourcePixelFormat[k] == dm_420_12) {
+			SwathWidthC[k] = SwathWidthY[k] / 2;
+			SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2;
+		} else {
+			SwathWidthC[k] = SwathWidthY[k];
+			SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k];
+		}
+
+		if (ForceSingleDPP == true) {
+			SwathWidthY[k] = SwathWidthSingleDPPY[k];
+			SwathWidthC[k] = SwathWidthSingleDPPC[k];
+		}
+		{
+		int surface_width_ub_l = dml_ceil(SurfaceWidthY[k], Read256BytesBlockWidthY[k]);
+		int surface_height_ub_l = dml_ceil(SurfaceHeightY[k], Read256BytesBlockHeightY[k]);
+		int surface_width_ub_c = dml_ceil(SurfaceWidthC[k], Read256BytesBlockWidthC[k]);
+		int surface_height_ub_c = dml_ceil(SurfaceHeightC[k], Read256BytesBlockHeightC[k]);
+
+#ifdef __DML_VBA_DEBUG__
+		dml_print("DML::%s: k=%d surface_width_ub_l=%0d\n", __func__, k, surface_width_ub_l);
+#endif
+
+		if (SourceScan[k] != dm_vert) {
+			MaximumSwathHeightY[k] = Read256BytesBlockHeightY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockHeightC[k];
+			swath_width_luma_ub[k] = dml_min(surface_width_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockWidthY[k]) + Read256BytesBlockWidthY[k]);
+			if (BytePerPixC[k] > 0) {
+				swath_width_chroma_ub[k] = dml_min(
+						surface_width_ub_c,
+						(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockWidthC[k]) + Read256BytesBlockWidthC[k]);
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		} else {
+			MaximumSwathHeightY[k] = Read256BytesBlockWidthY[k];
+			MaximumSwathHeightC[k] = Read256BytesBlockWidthC[k];
+			swath_width_luma_ub[k] = dml_min(surface_height_ub_l, (int) dml_ceil(SwathWidthY[k] - 1, Read256BytesBlockHeightY[k]) + Read256BytesBlockHeightY[k]);
+			if (BytePerPixC[k] > 0) {
+				swath_width_chroma_ub[k] = dml_min(
+						surface_height_ub_c,
+						(int) dml_ceil(SwathWidthC[k] - 1, Read256BytesBlockHeightC[k]) + Read256BytesBlockHeightC[k]);
+			} else {
+				swath_width_chroma_ub[k] = 0;
+			}
+		}
+		}
+	}
+}
+
+static double CalculateExtraLatency(
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		double DCFCLK,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		double ReturnBW,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels)
+{
+	double ExtraLatencyBytes;
+	double ExtraLatency;
+
+	ExtraLatencyBytes = CalculateExtraLatencyBytes(
+			ReorderingBytes,
+			TotalNumberOfActiveDPP,
+			PixelChunkSizeInKByte,
+			TotalNumberOfDCCActiveDPP,
+			MetaChunkSize,
+			GPUVMEnable,
+			HostVMEnable,
+			NumberOfActivePlanes,
+			NumberOfDPP,
+			dpte_group_bytes,
+			HostVMInefficiencyFactor,
+			HostVMMinPageSize,
+			HostVMMaxNonCachedPageTableLevels);
+
+	ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: RoundTripPingLatencyCycles=%d\n", __func__, RoundTripPingLatencyCycles);
+	dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK);
+	dml_print("DML::%s: ExtraLatencyBytes=%f\n", __func__, ExtraLatencyBytes);
+	dml_print("DML::%s: ReturnBW=%f\n", __func__, ReturnBW);
+	dml_print("DML::%s: ExtraLatency=%f\n", __func__, ExtraLatency);
+#endif
+
+	return ExtraLatency;
+}
+
+static double CalculateExtraLatencyBytes(
+		int ReorderingBytes,
+		int TotalNumberOfActiveDPP,
+		int PixelChunkSizeInKByte,
+		int TotalNumberOfDCCActiveDPP,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		int NumberOfDPP[],
+		int dpte_group_bytes[],
+		double HostVMInefficiencyFactor,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels)
+{
+	double ret;
+	int HostVMDynamicLevels = 0, k;
+
+	if (GPUVMEnable == true && HostVMEnable == true) {
+		if (HostVMMinPageSize < 2048) {
+			HostVMDynamicLevels = HostVMMaxNonCachedPageTableLevels;
+		} else if (HostVMMinPageSize >= 2048 && HostVMMinPageSize < 1048576) {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 1);
+		} else {
+			HostVMDynamicLevels = dml_max(0, (int) HostVMMaxNonCachedPageTableLevels - 2);
+		}
+	} else {
+		HostVMDynamicLevels = 0;
+	}
+
+	ret = ReorderingBytes + (TotalNumberOfActiveDPP * PixelChunkSizeInKByte + TotalNumberOfDCCActiveDPP * MetaChunkSize) * 1024.0;
+
+	if (GPUVMEnable == true) {
+		for (k = 0; k < NumberOfActivePlanes; ++k) {
+			ret = ret + NumberOfDPP[k] * dpte_group_bytes[k] * (1 + 8 * HostVMDynamicLevels) * HostVMInefficiencyFactor;
+		}
+	}
+	return ret;
+}
+
+static double CalculateUrgentLatency(
+		double UrgentLatencyPixelDataOnly,
+		double UrgentLatencyPixelMixedWithVMData,
+		double UrgentLatencyVMDataOnly,
+		bool DoUrgentLatencyAdjustment,
+		double UrgentLatencyAdjustmentFabricClockComponent,
+		double UrgentLatencyAdjustmentFabricClockReference,
+		double FabricClock)
+{
+	double ret;
+
+	ret = dml_max3(UrgentLatencyPixelDataOnly, UrgentLatencyPixelMixedWithVMData, UrgentLatencyVMDataOnly);
+	if (DoUrgentLatencyAdjustment == true) {
+		ret = ret + UrgentLatencyAdjustmentFabricClockComponent * (UrgentLatencyAdjustmentFabricClockReference / FabricClock - 1);
+	}
+	return ret;
+}
+
+static void UseMinimumDCFCLK(
+		struct display_mode_lib *mode_lib,
+		int MaxInterDCNTileRepeaters,
+		int MaxPrefetchMode,
+		double FinalDRAMClockChangeLatency,
+		double SREnterPlusExitTime,
+		int ReturnBusWidth,
+		int RoundTripPingLatencyCycles,
+		int ReorderingBytes,
+		int PixelChunkSizeInKByte,
+		int MetaChunkSize,
+		bool GPUVMEnable,
+		int GPUVMMaxPageTableLevels,
+		bool HostVMEnable,
+		int NumberOfActivePlanes,
+		double HostVMMinPageSize,
+		int HostVMMaxNonCachedPageTableLevels,
+		bool DynamicMetadataVMEnabled,
+		enum immediate_flip_requirement ImmediateFlipRequirement,
+		bool ProgressiveToInterlaceUnitInOPP,
+		double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation,
+		double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency,
+		int VTotal[],
+		int VActive[],
+		int DynamicMetadataTransmittedBytes[],
+		int DynamicMetadataLinesBeforeActiveRequired[],
+		bool Interlace[],
+		double RequiredDPPCLK[][2][DC__NUM_DPP__MAX],
+		double RequiredDISPCLK[][2],
+		double UrgLatency[],
+		unsigned int NoOfDPP[][2][DC__NUM_DPP__MAX],
+		double ProjectedDCFCLKDeepSleep[][2],
+		double MaximumVStartup[][2][DC__NUM_DPP__MAX],
+		double TotalVActivePixelBandwidth[][2],
+		double TotalVActiveCursorBandwidth[][2],
+		double TotalMetaRowBandwidth[][2],
+		double TotalDPTERowBandwidth[][2],
+		unsigned int TotalNumberOfActiveDPP[][2],
+		unsigned int TotalNumberOfDCCActiveDPP[][2],
+		int dpte_group_bytes[],
+		double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
+		double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
+		int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
+		int BytePerPixelY[],
+		int BytePerPixelC[],
+		int HTotal[],
+		double PixelClock[],
+		double PDEAndMetaPTEBytesPerFrame[][2][DC__NUM_DPP__MAX],
+		double DPTEBytesPerRow[][2][DC__NUM_DPP__MAX],
+		double MetaRowBytes[][2][DC__NUM_DPP__MAX],
+		bool DynamicMetadataEnable[],
+		double VActivePixelBandwidth[][2][DC__NUM_DPP__MAX],
+		double VActiveCursorBandwidth[][2][DC__NUM_DPP__MAX],
+		double ReadBandwidthLuma[],
+		double ReadBandwidthChroma[],
+		double DCFCLKPerState[],
+		double DCFCLKState[][2])
+{
+	struct vba_vars_st *v = &mode_lib->vba;
+	int dummy1, i, j, k;
+	double NormalEfficiency,  dummy2, dummy3;
+	double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2];
+
+	NormalEfficiency = PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency / 100.0;
+	for (i = 0; i < v->soc.num_states; ++i) {
+		for (j = 0; j <= 1; ++j) {
+			double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX];
+			double PrefetchPixelLinesTime[DC__NUM_DPP__MAX];
+			double DCFCLKRequiredForPeakBandwidthPerPlane[DC__NUM_DPP__MAX];
+			double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX];
+			double MinimumTWait;
+			double NonDPTEBandwidth;
+			double DPTEBandwidth;
+			double DCFCLKRequiredForAverageBandwidth;
+			double ExtraLatencyBytes;
+			double ExtraLatencyCycles;
+			double DCFCLKRequiredForPeakBandwidth;
+			int NoOfDPPState[DC__NUM_DPP__MAX];
+			double MinimumTvmPlus2Tr0;
+
+			TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = 0;
+			for (k = 0; k < NumberOfActivePlanes; ++k) {
+				TotalMaxPrefetchFlipDPTERowBandwidth[i][j] = TotalMaxPrefetchFlipDPTERowBandwidth[i][j]
+						+ NoOfDPP[i][j][k] * DPTEBytesPerRow[i][j][k] / (15.75 * HTotal[k] / PixelClock[k]);
+			}
+
+			for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
+				NoOfDPPState[k] = NoOfDPP[i][j][k];
+			}
+
+			MinimumTWait = CalculateTWait(MaxPrefetchMode, FinalDRAMClockChangeLatency, UrgLatency[i], SREnterPlusExitTime);
+			NonDPTEBandwidth = TotalVActivePixelBandwidth[i][j] + TotalVActiveCursorBandwidth[i][j] + TotalMetaRowBandwidth[i][j];
+			DPTEBandwidth = (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) ?
+					TotalMaxPrefetchFlipDPTERowBandwidth[i][j] : TotalDPTERowBandwidth[i][j];
+			DCFCLKRequiredForAverageBandwidth = dml_max3(
+					ProjectedDCFCLKDeepSleep[i][j],
+					(NonDPTEBandwidth + TotalDPTERowBandwidth[i][j]) / ReturnBusWidth
+							/ (MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation / 100),
+					(NonDPTEBandwidth + DPTEBandwidth / NormalEfficiency) / NormalEfficiency / ReturnBusWidth);
+
+			ExtraLatencyBytes = CalculateExtraLatencyBytes(
+					ReorderingBytes,
+					TotalNumberOfActiveDPP[i][j],
+					PixelChunkSizeInKByte,
+					TotalNumberOfDCCActiveDPP[i][j],
+					MetaChunkSize,
+					GPUVMEnable,
+					HostVMEnable,
+					NumberOfActivePlanes,
+					NoOfDPPState,
+					dpte_group_bytes,
+					1,
+					HostVMMinPageSize,
+					HostVMMaxNonCachedPageTableLevels);
+			ExtraLatencyCycles = RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__ + ExtraLatencyBytes / NormalEfficiency / ReturnBusWidth;
+			for (k = 0; k < NumberOfActivePlanes; ++k) {
+				double DCFCLKCyclesRequiredInPrefetch;
+				double ExpectedPrefetchBWAcceleration;
+				double PrefetchTime;
+
+				PixelDCFCLKCyclesRequiredInPrefetch[k] = (PrefetchLinesY[i][j][k] * swath_width_luma_ub_all_states[i][j][k] * BytePerPixelY[k]
+						+ PrefetchLinesC[i][j][k] * swath_width_chroma_ub_all_states[i][j][k] * BytePerPixelC[k]) / NormalEfficiency / ReturnBusWidth;
+				DCFCLKCyclesRequiredInPrefetch = 2 * ExtraLatencyCycles / NoOfDPPState[k]
+						+ PDEAndMetaPTEBytesPerFrame[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth * (GPUVMMaxPageTableLevels > 2 ? 1 : 0)
+						+ 2 * DPTEBytesPerRow[i][j][k] / NormalEfficiency / NormalEfficiency / ReturnBusWidth
+						+ 2 * MetaRowBytes[i][j][k] / NormalEfficiency / ReturnBusWidth + PixelDCFCLKCyclesRequiredInPrefetch[k];
+				PrefetchPixelLinesTime[k] = dml_max(PrefetchLinesY[i][j][k], PrefetchLinesC[i][j][k]) * HTotal[k] / PixelClock[k];
+				ExpectedPrefetchBWAcceleration = (VActivePixelBandwidth[i][j][k] + VActiveCursorBandwidth[i][j][k])
+						/ (ReadBandwidthLuma[k] + ReadBandwidthChroma[k]);
+				DynamicMetadataVMExtraLatency[k] =
+						(GPUVMEnable == true && DynamicMetadataEnable[k] == true && DynamicMetadataVMEnabled == true) ?
+								UrgLatency[i] * GPUVMMaxPageTableLevels * (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) : 0;
+				PrefetchTime = (MaximumVStartup[i][j][k] - 1) * HTotal[k] / PixelClock[k] - MinimumTWait
+						- UrgLatency[i]
+								* ((GPUVMMaxPageTableLevels <= 2 ? GPUVMMaxPageTableLevels : GPUVMMaxPageTableLevels - 2)
+										* (HostVMEnable == true ? HostVMMaxNonCachedPageTableLevels + 1 : 1) - 1)
+						- DynamicMetadataVMExtraLatency[k];
+
+				if (PrefetchTime > 0) {
+					double ExpectedVRatioPrefetch;
+					ExpectedVRatioPrefetch = PrefetchPixelLinesTime[k]
+							/ (PrefetchTime * PixelDCFCLKCyclesRequiredInPrefetch[k] / DCFCLKCyclesRequiredInPrefetch);
+					DCFCLKRequiredForPeakBandwidthPerPlane[k] = NoOfDPPState[k] * PixelDCFCLKCyclesRequiredInPrefetch[k] / PrefetchPixelLinesTime[k]
+							* dml_max(1.0, ExpectedVRatioPrefetch) * dml_max(1.0, ExpectedVRatioPrefetch / 4) * ExpectedPrefetchBWAcceleration;
+					if (HostVMEnable == true || ImmediateFlipRequirement == dm_immediate_flip_required) {
+						DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKRequiredForPeakBandwidthPerPlane[k]
+								+ NoOfDPPState[k] * DPTEBandwidth / NormalEfficiency / NormalEfficiency / ReturnBusWidth;
+					}
+				} else {
+					DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
+				}
+				if (DynamicMetadataEnable[k] == true) {
+					double TSetupPipe;
+					double TdmbfPipe;
+					double TdmsksPipe;
+					double TdmecPipe;
+					double AllowedTimeForUrgentExtraLatency;
+
+					CalculateVupdateAndDynamicMetadataParameters(
+							MaxInterDCNTileRepeaters,
+							RequiredDPPCLK[i][j][k],
+							RequiredDISPCLK[i][j],
+							ProjectedDCFCLKDeepSleep[i][j],
+							PixelClock[k],
+							HTotal[k],
+							VTotal[k] - VActive[k],
+							DynamicMetadataTransmittedBytes[k],
+							DynamicMetadataLinesBeforeActiveRequired[k],
+							Interlace[k],
+							ProgressiveToInterlaceUnitInOPP,
+							&TSetupPipe,
+							&TdmbfPipe,
+							&TdmecPipe,
+							&TdmsksPipe,
+							&dummy1,
+							&dummy2,
+							&dummy3);
+					AllowedTimeForUrgentExtraLatency = MaximumVStartup[i][j][k] * HTotal[k] / PixelClock[k] - MinimumTWait - TSetupPipe - TdmbfPipe - TdmecPipe
+							- TdmsksPipe - DynamicMetadataVMExtraLatency[k];
+					if (AllowedTimeForUrgentExtraLatency > 0) {
+						DCFCLKRequiredForPeakBandwidthPerPlane[k] = dml_max(
+								DCFCLKRequiredForPeakBandwidthPerPlane[k],
+								ExtraLatencyCycles / AllowedTimeForUrgentExtraLatency);
+					} else {
+						DCFCLKRequiredForPeakBandwidthPerPlane[k] = DCFCLKPerState[i];
+					}
+				}
+			}
+			DCFCLKRequiredForPeakBandwidth = 0;
+			for (k = 0; k <= NumberOfActivePlanes - 1; ++k) {
+				DCFCLKRequiredForPeakBandwidth = DCFCLKRequiredForPeakBandwidth + DCFCLKRequiredForPeakBandwidthPerPlane[k];
+			}
+			MinimumTvmPlus2Tr0 = UrgLatency[i]
+					* (GPUVMEnable == true ?
+							(HostVMEnable == true ?
+									(GPUVMMaxPageTableLevels + 2) * (HostVMMaxNonCachedPageTableLevels + 1) - 1 : GPUVMMaxPageTableLevels + 1) :
+							0);
+			for (k = 0; k < NumberOfActivePlanes; ++k) {
+				double MaximumTvmPlus2Tr0PlusTsw;
+				MaximumTvmPlus2Tr0PlusTsw = (MaximumVStartup[i][j][k] - 2) * HTotal[k] / PixelClock[k] - MinimumTWait - DynamicMetadataVMExtraLatency[k];
+				if (MaximumTvmPlus2Tr0PlusTsw <= MinimumTvmPlus2Tr0 + PrefetchPixelLinesTime[k] / 4) {
+					DCFCLKRequiredForPeakBandwidth = DCFCLKPerState[i];
+				} else {
+					DCFCLKRequiredForPeakBandwidth = dml_max3(
+							DCFCLKRequiredForPeakBandwidth,
+							2 * ExtraLatencyCycles / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0 - PrefetchPixelLinesTime[k] / 4),
+							(2 * ExtraLatencyCycles + PixelDCFCLKCyclesRequiredInPrefetch[k]) / (MaximumTvmPlus2Tr0PlusTsw - MinimumTvmPlus2Tr0));
+				}
+			}
+			DCFCLKState[i][j] = dml_min(DCFCLKPerState[i], 1.05 * dml_max(DCFCLKRequiredForAverageBandwidth, DCFCLKRequiredForPeakBandwidth));
+		}
+	}
+}
+
+static void CalculateUnboundedRequestAndCompressedBufferSize(
+		unsigned int DETBufferSizeInKByte,
+		int ConfigReturnBufferSizeInKByte,
+		enum unbounded_requesting_policy UseUnboundedRequestingFinal,
+		int TotalActiveDPP,
+		bool NoChromaPlanes,
+		int MaxNumDPP,
+		int CompressedBufferSegmentSizeInkByteFinal,
+		enum output_encoder_class *Output,
+		bool *UnboundedRequestEnabled,
+		int *CompressedBufferSizeInkByte)
+{
+	double actDETBufferSizeInKByte = dml_ceil(DETBufferSizeInKByte, 64);
+
+	*UnboundedRequestEnabled = UnboundedRequest(UseUnboundedRequestingFinal, TotalActiveDPP, NoChromaPlanes, Output[0]);
+	*CompressedBufferSizeInkByte = (
+			*UnboundedRequestEnabled == true ?
+					ConfigReturnBufferSizeInKByte - TotalActiveDPP * actDETBufferSizeInKByte :
+					ConfigReturnBufferSizeInKByte - MaxNumDPP * actDETBufferSizeInKByte);
+	*CompressedBufferSizeInkByte = *CompressedBufferSizeInkByte * CompressedBufferSegmentSizeInkByteFinal / 64;
+
+#ifdef __DML_VBA_DEBUG__
+	dml_print("DML::%s: TotalActiveDPP = %d\n", __func__, TotalActiveDPP);
+	dml_print("DML::%s: DETBufferSizeInKByte = %d\n", __func__, DETBufferSizeInKByte);
+	dml_print("DML::%s: ConfigReturnBufferSizeInKByte = %d\n", __func__, ConfigReturnBufferSizeInKByte);
+	dml_print("DML::%s: UseUnboundedRequestingFinal = %d\n", __func__, UseUnboundedRequestingFinal);
+	dml_print("DML::%s: actDETBufferSizeInKByte = %f\n", __func__, actDETBufferSizeInKByte);
+	dml_print("DML::%s: UnboundedRequestEnabled = %d\n", __func__, *UnboundedRequestEnabled);
+	dml_print("DML::%s: CompressedBufferSizeInkByte = %d\n", __func__, *CompressedBufferSizeInkByte);
+#endif
+}
+
+static bool UnboundedRequest(enum unbounded_requesting_policy UseUnboundedRequestingFinal, int TotalNumberOfActiveDPP, bool NoChroma, enum output_encoder_class Output)
+{
+	bool ret_val = false;
+
+	ret_val = (UseUnboundedRequestingFinal != dm_unbounded_requesting_disable && TotalNumberOfActiveDPP == 1 && NoChroma);
+	if (UseUnboundedRequestingFinal == dm_unbounded_requesting_edp_only && Output != dm_edp) {
+		ret_val = false;
+	}
+	return (ret_val);
+}
+
+#endif /* CONFIG_DRM_AMD_DC_DCN3_1 */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
new file mode 100644
index 000000000000..90be612f26b2
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML31_DISPLAY_MODE_VBA_H__
+#define __DML31_DISPLAY_MODE_VBA_H__
+
+void dml31_recalculate(struct display_mode_lib *mode_lib);
+void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
+double dml31_CalculateWriteBackDISPCLK(
+		enum source_format_class WritebackPixelFormat,
+		double PixelClock,
+		double WritebackHRatio,
+		double WritebackVRatio,
+		unsigned int WritebackHTaps,
+		unsigned int WritebackVTaps,
+		long   WritebackSourceWidth,
+		long   WritebackDestinationWidth,
+		unsigned int HTotal,
+		unsigned int WritebackLineBufferSize);
+
+#endif /* __DML31_DISPLAY_MODE_VBA_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
new file mode 100644
index 000000000000..cb15525ddb49
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c
@@ -0,0 +1,1727 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+
+#include "../display_mode_lib.h"
+#include "../display_mode_vba.h"
+#include "../dml_inline_defs.h"
+#include "display_rq_dlg_calc_31.h"
+
+static bool CalculateBytePerPixelAnd256BBlockSizes(
+		enum source_format_class SourcePixelFormat,
+		enum dm_swizzle_mode SurfaceTiling,
+		unsigned int *BytePerPixelY,
+		unsigned int *BytePerPixelC,
+		double *BytePerPixelDETY,
+		double *BytePerPixelDETC,
+		unsigned int *BlockHeight256BytesY,
+		unsigned int *BlockHeight256BytesC,
+		unsigned int *BlockWidth256BytesY,
+		unsigned int *BlockWidth256BytesC)
+{
+	if (SourcePixelFormat == dm_444_64) {
+		*BytePerPixelDETY = 8;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 8;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_16) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_444_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 0;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 0;
+	} else if (SourcePixelFormat == dm_rgbe_alpha) {
+		*BytePerPixelDETY = 4;
+		*BytePerPixelDETC = 1;
+		*BytePerPixelY = 4;
+		*BytePerPixelC = 1;
+	} else if (SourcePixelFormat == dm_420_8) {
+		*BytePerPixelDETY = 1;
+		*BytePerPixelDETC = 2;
+		*BytePerPixelY = 1;
+		*BytePerPixelC = 2;
+	} else if (SourcePixelFormat == dm_420_12) {
+		*BytePerPixelDETY = 2;
+		*BytePerPixelDETC = 4;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	} else {
+		*BytePerPixelDETY = 4.0 / 3;
+		*BytePerPixelDETC = 8.0 / 3;
+		*BytePerPixelY = 2;
+		*BytePerPixelC = 4;
+	}
+
+	if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 || SourcePixelFormat == dm_mono_16
+			|| SourcePixelFormat == dm_mono_8 || SourcePixelFormat == dm_rgbe)) {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+		} else if (SourcePixelFormat == dm_444_64) {
+			*BlockHeight256BytesY = 4;
+		} else if (SourcePixelFormat == dm_444_8) {
+			*BlockHeight256BytesY = 16;
+		} else {
+			*BlockHeight256BytesY = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockHeight256BytesC = 0;
+		*BlockWidth256BytesC = 0;
+	} else {
+		if (SurfaceTiling == dm_sw_linear) {
+			*BlockHeight256BytesY = 1;
+			*BlockHeight256BytesC = 1;
+		} else if (SourcePixelFormat == dm_rgbe_alpha) {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 16;
+		} else if (SourcePixelFormat == dm_420_8) {
+			*BlockHeight256BytesY = 16;
+			*BlockHeight256BytesC = 8;
+		} else {
+			*BlockHeight256BytesY = 8;
+			*BlockHeight256BytesC = 8;
+		}
+		*BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY;
+		*BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC;
+	}
+	return true;
+}
+
+static bool is_dual_plane(enum source_format_class source_format)
+{
+	bool ret_val = 0;
+
+	if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha))
+		ret_val = 1;
+
+	return ret_val;
+}
+
+static double get_refcyc_per_delivery(
+		struct display_mode_lib *mode_lib,
+		double refclk_freq_in_mhz,
+		double pclk_freq_in_mhz,
+		unsigned int odm_combine,
+		unsigned int recout_width,
+		unsigned int hactive,
+		double vratio,
+		double hscale_pixel_rate,
+		unsigned int delivery_width,
+		unsigned int req_per_swath_ub)
+{
+	double refcyc_per_delivery = 0.0;
+
+	if (vratio <= 1.0) {
+		if (odm_combine)
+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) ((unsigned int) odm_combine * 2)
+					* dml_min((double) recout_width, (double) hactive / ((unsigned int) odm_combine * 2)) / pclk_freq_in_mhz / (double) req_per_swath_ub;
+		else
+			refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width / pclk_freq_in_mhz / (double) req_per_swath_ub;
+	} else {
+		refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width / (double) hscale_pixel_rate / (double) req_per_swath_ub;
+	}
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
+	dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
+	dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
+	dml_print("DML_DLG: %s: hscale_pixel_rate  = %3.2f\n", __func__, hscale_pixel_rate);
+	dml_print("DML_DLG: %s: delivery_width     = %d\n", __func__, delivery_width);
+	dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
+#endif
+
+	return refcyc_per_delivery;
+
+}
+
+static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
+{
+	if (tile_size == dm_256k_tile)
+		return (256 * 1024);
+	else if (tile_size == dm_64k_tile)
+		return (64 * 1024);
+	else
+		return (4 * 1024);
+}
+
+static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, display_data_rq_regs_st *rq_regs, const display_data_rq_sizing_params_st rq_sizing)
+{
+	print__data_rq_sizing_params_st(mode_lib, rq_sizing);
+
+	rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
+
+	if (rq_sizing.min_chunk_bytes == 0)
+		rq_regs->min_chunk_size = 0;
+	else
+		rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
+
+	rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
+	if (rq_sizing.min_meta_chunk_bytes == 0)
+		rq_regs->min_meta_chunk_size = 0;
+	else
+		rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
+
+	rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
+	rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
+}
+
+static void extract_rq_regs(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_rq_params_st rq_param)
+{
+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
+	unsigned int detile_buf_plane1_addr = 0;
+
+	extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
+
+	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 1) - 3;
+
+	if (rq_param.yuv420) {
+		extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
+		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 1) - 3;
+	}
+
+	rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
+	rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
+
+	// FIXME: take the max between luma, chroma chunk size?
+	// okay for now, as we are setting chunk_bytes to 8kb anyways
+	if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param.yuv420 && rq_param.sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb
+		rq_regs->drq_expansion_mode = 0;
+	} else {
+		rq_regs->drq_expansion_mode = 2;
+	}
+	rq_regs->prq_expansion_mode = 1;
+	rq_regs->mrq_expansion_mode = 1;
+	rq_regs->crq_expansion_mode = 1;
+
+	// Note: detile_buf_plane1_addr is in unit of 1KB
+	if (rq_param.yuv420) {
+		if ((double) rq_param.misc.rq_l.stored_swath_bytes / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
+			detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 1024.0); // half to chroma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+					dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/2 to chroma)\n", __func__, detile_buf_plane1_addr);
+#endif
+		} else {
+			detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 1024, 0) / 1024.0; // 2/3 to luma
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+					dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d (1/3 chroma)\n", __func__, detile_buf_plane1_addr);
+#endif
+		}
+	}
+	rq_regs->plane1_base_address = detile_buf_plane1_addr;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
+	dml_print("DML_DLG: %s: detile_buf_plane1_addr = %0d\n", __func__, detile_buf_plane1_addr);
+	dml_print("DML_DLG: %s: plane1_base_address = %0d\n", __func__, rq_regs->plane1_base_address);
+	dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_l.stored_swath_bytes);
+	dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param.misc.rq_c.stored_swath_bytes);
+	dml_print("DML_DLG: %s: rq_l.swath_height = %0d\n", __func__, rq_param.dlg.rq_l.swath_height);
+	dml_print("DML_DLG: %s: rq_c.swath_height = %0d\n", __func__, rq_param.dlg.rq_c.swath_height);
+#endif
+}
+
+static void handle_det_buf_split(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_source_params_st pipe_src_param)
+{
+	unsigned int total_swath_bytes = 0;
+	unsigned int swath_bytes_l = 0;
+	unsigned int swath_bytes_c = 0;
+	unsigned int full_swath_bytes_packed_l = 0;
+	unsigned int full_swath_bytes_packed_c = 0;
+	bool req128_l = 0;
+	bool req128_c = 0;
+	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
+	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
+	unsigned int log2_swath_height_l = 0;
+	unsigned int log2_swath_height_c = 0;
+	unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
+
+	full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
+	full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
+#endif
+
+	if (rq_param->yuv420_10bpc) {
+		full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
+		full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, 256, 1) + 256;
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+		dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_l);
+		dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d (3-2 packing)\n", __func__, full_swath_bytes_packed_c);
+#endif
+	}
+
+	if (rq_param->yuv420)
+		total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
+	else
+		total_swath_bytes = 2 * full_swath_bytes_packed_l;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
+	dml_print("DML_DLG: %s: detile_buf_size_in_bytes = %0d\n", __func__, detile_buf_size_in_bytes);
+#endif
+
+	if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
+		req128_l = 0;
+		req128_c = 0;
+		swath_bytes_l = full_swath_bytes_packed_l;
+		swath_bytes_c = full_swath_bytes_packed_c;
+	} else if (!rq_param->yuv420) {
+		req128_l = 1;
+		req128_c = 0;
+		swath_bytes_c = full_swath_bytes_packed_c;
+		swath_bytes_l = full_swath_bytes_packed_l / 2;
+	} else if ((double) full_swath_bytes_packed_l / (double) full_swath_bytes_packed_c < 1.5) {
+		req128_l = 0;
+		req128_c = 1;
+		swath_bytes_l = full_swath_bytes_packed_l;
+		swath_bytes_c = full_swath_bytes_packed_c / 2;
+
+		total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
+
+		if (total_swath_bytes > detile_buf_size_in_bytes) {
+			req128_l = 1;
+			swath_bytes_l = full_swath_bytes_packed_l / 2;
+		}
+	} else {
+		req128_l = 1;
+		req128_c = 0;
+		swath_bytes_l = full_swath_bytes_packed_l / 2;
+		swath_bytes_c = full_swath_bytes_packed_c;
+
+		total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
+
+		if (total_swath_bytes > detile_buf_size_in_bytes) {
+			req128_c = 1;
+			swath_bytes_c = full_swath_bytes_packed_c / 2;
+		}
+	}
+
+	if (rq_param->yuv420)
+		total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c;
+	else
+		total_swath_bytes = 2 * swath_bytes_l;
+
+	rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
+	rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: total_swath_bytes = %0d\n", __func__, total_swath_bytes);
+	dml_print("DML_DLG: %s: rq_l.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_l.stored_swath_bytes);
+	dml_print("DML_DLG: %s: rq_c.stored_swath_bytes = %0d\n", __func__, rq_param->misc.rq_c.stored_swath_bytes);
+#endif
+	if (surf_linear) {
+		log2_swath_height_l = 0;
+		log2_swath_height_c = 0;
+	} else {
+		unsigned int swath_height_l;
+		unsigned int swath_height_c;
+
+		if (!surf_vert) {
+			swath_height_l = rq_param->misc.rq_l.blk256_height;
+			swath_height_c = rq_param->misc.rq_c.blk256_height;
+		} else {
+			swath_height_l = rq_param->misc.rq_l.blk256_width;
+			swath_height_c = rq_param->misc.rq_c.blk256_width;
+		}
+
+		if (swath_height_l > 0)
+			log2_swath_height_l = dml_log2(swath_height_l);
+
+		if (req128_l && log2_swath_height_l > 0)
+			log2_swath_height_l -= 1;
+
+		if (swath_height_c > 0)
+			log2_swath_height_c = dml_log2(swath_height_c);
+
+		if (req128_c && log2_swath_height_c > 0)
+			log2_swath_height_c -= 1;
+	}
+
+	rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
+	rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
+
+#ifdef __DML_RQ_DLG_CALC_DEBUG__
+	dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
+	dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", __func__, full_swath_bytes_packed_l);
+	dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", __func__, full_swath_bytes_packed_c);
+	dml_print("DML_DLG: %s: swath_height luma = %0d\n", __func__, rq_param->dlg.rq_l.swath_height);
+	dml_print("DML_DLG: %s: swath_height chroma = %0d\n", __func__, rq_param->dlg.rq_c.swath_height);
+#endif
+}
+
+static void get_meta_and_pte_attr(
+		struct display_mode_lib *mode_lib,
+		display_data_rq_dlg_params_st *rq_dlg_param,
+		display_data_rq_misc_params_st *rq_misc_param,
+		display_data_rq_sizing_params_st *rq_sizing_param,
+		unsigned int vp_width,
+		unsigned int vp_height,
+		unsigned int data_pitch,
+		unsigned int meta_pitch,
+		unsigned int source_format,
+		unsigned int tiling,
+		unsigned int macro_tile_size,
+		unsigned int source_scan,
+		unsigned int hostvm_enable,
+		unsigned int is_chroma,
+		unsigned int surface_height)
+{
+	bool surf_linear = (tiling == dm_sw_linear);
+	bool surf_vert = (source_scan == dm_vert);
+
+	unsigned int bytes_per_element;
+	unsigned int bytes_per_element_y;
+	unsigned int bytes_per_element_c;
+
+	unsigned int blk256_width = 0;
+	unsigned int blk256_height = 0;
+
+	unsigned int blk256_width_y = 0;
+	unsigned int blk256_height_y = 0;
+	unsigned int blk256_width_c = 0;
+	unsigned int blk256_height_c = 0;
+	unsigned int log2_bytes_per_element;
+	unsigned int log2_blk256_width;
+	unsigned int log2_blk256_height;
+	unsigned int blk_bytes;
+	unsigned int log2_blk_bytes;
+	unsigned int log2_blk_height;
+	unsigned int log2_blk_width;
+	unsigned int log2_meta_req_bytes;
+	unsigned int log2_meta_req_height;
+	unsigned int log2_meta_req_width;
+	unsigned int meta_req_width;
+	unsigned int meta_req_height;
+	unsigned int log2_meta_row_height;
+	unsigned int meta_row_width_ub;
+	unsigned int log2_meta_chunk_bytes;
+	unsigned int log2_meta_chunk_height;
+
+	//full sized meta chunk width in unit of data elements
+	unsigned int log2_meta_chunk_width;
+	unsigned int log2_min_meta_chunk_bytes;
+	unsigned int min_meta_chunk_width;
+	unsigned int meta_chunk_width;
+	unsigned int meta_chunk_per_row_int;
+	unsigned int meta_row_remainder;
+	unsigned int meta_chunk_threshold;
+	unsigned int meta_blk_height;
+	unsigned int meta_surface_bytes;
+	unsigned int vmpg_bytes;
+	unsigned int meta_pte_req_per_frame_ub;
+	unsigned int meta_pte_bytes_per_frame_ub;
+	const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes);
+	const bool dual_plane_en = is_dual_plane((enum source_format_class) (source_format));
+	const unsigned int dpte_buf_in_pte_reqs =
+			dual_plane_en ? (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma
+							+ mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma);
+
+	unsigned int log2_vmpg_height = 0;
+	unsigned int log2_vmpg_width = 0;
+	unsigned int log2_dpte_req_height_ptes = 0;
+	unsigned int log2_dpte_req_height = 0;
+	unsigned int log2_dpte_req_width = 0;
+	unsigned int log2_dpte_row_height_linear = 0;
+	unsigned int log2_dpte_row_height = 0;
+	unsigned int log2_dpte_group_width = 0;
+	unsigned int dpte_row_width_ub = 0;
+	unsigned int dpte_req_height = 0;
+	unsigned int dpte_req_width = 0;
+	unsigned int dpte_group_width = 0;
+	unsigned int log2_dpte_group_bytes = 0;
+	unsigned int log2_dpte_group_length = 0;
+	double byte_per_pixel_det_y;
+	double byte_per_pixel_det_c;
+
+	CalculateBytePerPixelAnd256BBlockSizes(
+			(enum source_format_class) (source_format),
+			(enum dm_swizzle_mode) (tiling),
+			&bytes_per_element_y,
+			&bytes_per_element_c,
+			&byte_per_pixel_det_y,
+			&byte_per_pixel_det_c,
+			&blk256_height_y,
+			&blk256_height_c,
+			&blk256_width_y,
+			&blk256_width_c);
+
+	if (!is_chroma) {
+		blk256_width = blk256_width_y;
+		blk256_height = blk256_height_y;
+		bytes_per_element = bytes_per_element_y;
+	} else {
+		blk256_width = blk256_width_c;
+		blk256_height = blk256_height_c;
+		bytes_per_element = bytes_per_element_c;
+	}
+
+	log2_bytes_per_element = dml_log2(bytes_per_element);
+
+	dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
+	dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
+	dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
+	dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
+
+	log2_blk256_width = dml_log2((double) blk256_width);
+	log2_blk256_height = dml_log2((double) blk256_height);
+	blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
+	log2_blk_bytes = dml_log2((double) blk_bytes);
+	log2_blk_height = 0;
+	log2_blk_width = 0;
+
+	// remember log rule
+	// "+" in log is multiply
+	// "-" in log is divide
+	// "/2" is like square root
+	// blk is vertical biased
+	if (tiling != dm_sw_linear)
+		log2_blk_height = log2_blk256_height + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
+	else
+		log2_blk_height = 0;	// blk height of 1
+
+	log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
+
+	if (!surf_vert) {
+		int unsigned temp;
+
+		temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width;
+		if (data_pitch < blk256_width) {
+			dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width);
+		} else {
+			if (temp > data_pitch) {
+				if (data_pitch >= vp_width)
+					temp = data_pitch;
+				else
+					dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width);
+			}
+		}
+		rq_dlg_param->swath_width_ub = temp;
+		rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width;
+	} else {
+		int unsigned temp;
+
+		temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height;
+		if (surface_height < blk256_height) {
+			dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height);
+		} else {
+			if (temp > surface_height) {
+				if (surface_height >= vp_height)
+					temp = surface_height;
+				else
+					dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height);
+			}
+		}
+		rq_dlg_param->swath_width_ub = temp;
+		rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height;
+	}
+
+	if (!surf_vert)
+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height * bytes_per_element;
+	else
+		rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width * bytes_per_element;
+
+	rq_misc_param->blk256_height = blk256_height;
+	rq_misc_param->blk256_width = blk256_width;
+
+	// -------
+	// meta
+	// -------
+	log2_meta_req_bytes = 6;	// meta request is 64b and is 8x8byte meta element
+
+	// each 64b meta request for dcn is 8x8 meta elements and
+	// a meta element covers one 256b block of the the data surface.
+	log2_meta_req_height = log2_blk256_height + 3;	// meta req is 8x8 byte, each byte represent 1 blk256
+	log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height;
+	meta_req_width = 1 << log2_meta_req_width;
+	meta_req_height = 1 << log2_meta_req_height;
+	log2_meta_row_height = 0;
+	meta_row_width_ub = 0;
+
+	// the dimensions of a meta row are meta_row_width x meta_row_height in elements.
+	// calculate upper bound of the meta_row_width
+	if (!surf_vert) {
+		log2_meta_row_height = log2_meta_req_height;
+		meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width;
+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
+	} else {
+		log2_meta_row_height = log2_meta_req_width;
+		meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height;
+		rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
+	}
+	rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
+
+	rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
+
+	log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
+	log2_meta_chunk_height = log2_meta_row_height;
+
+	//full sized meta chunk width in unit of data elements
+	log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height;
+	log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
+	min_meta_chunk_width = 1 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element - log2_meta_chunk_height);
+	meta_chunk_width = 1 << log2_meta_chunk_width;
+	meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
+	meta_row_remainder = meta_row_width_ub % meta_chunk_width;
+	meta_chunk_threshold = 0;
+	meta_blk_height = blk256_height * 64;
+	meta_surface_bytes = meta_pitch * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) * bytes_per_element / 256;
+	vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes;
+	meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 8 * vmpg_bytes, 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
+	meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64;	//64B mpte request
+	rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
+
+	dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
+	dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
+	dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n", __func__, meta_pte_req_per_frame_ub);
+	dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", __func__, meta_pte_bytes_per_frame_ub);
+
+	if (!surf_vert)
+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
+	else
+		meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
+
+	if (meta_row_remainder <= meta_chunk_threshold)
+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
+	else
+		rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
+
+	// ------
+	// dpte
+	// ------
+	if (surf_linear) {
+		log2_vmpg_height = 0;   // one line high
+	} else {
+		log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
+	}
+	log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
+
+	// only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
+	if (surf_linear) { //one 64B PTE request returns 8 PTEs
+		log2_dpte_req_height_ptes = 0;
+		log2_dpte_req_width = log2_vmpg_width + 3;
+		log2_dpte_req_height = 0;
+	} else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
+		//one 64B req gives 8x1 PTEs for 4KB tile
+		log2_dpte_req_height_ptes = 0;
+		log2_dpte_req_width = log2_blk_width + 3;
+		log2_dpte_req_height = log2_blk_height + 0;
+	} else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
+		//two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
+		log2_dpte_req_height_ptes = 4;
+		log2_dpte_req_width = log2_blk256_width + 4;		// log2_64KB_width
+		log2_dpte_req_height = log2_blk256_height + 4;		// log2_64KB_height
+	} else { //64KB page size and must 64KB tile block
+		 //one 64B req gives 8x1 PTEs for 64KB tile
+		log2_dpte_req_height_ptes = 0;
+		log2_dpte_req_width = log2_blk_width + 3;
+		log2_dpte_req_height = log2_blk_height + 0;
+	}
+
+	// The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
+	// log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
+	// That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
+	//log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
+	//log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
+	dpte_req_height = 1 << log2_dpte_req_height;
+	dpte_req_width = 1 << log2_dpte_req_width;
+
+	// calculate pitch dpte row buffer can hold
+	// round the result down to a power of two.
+	if (surf_linear) {
+		unsigned int dpte_row_height;
+
+		log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1);
+
+		dml_print("DML_DLG: %s: is_chroma                   = %d\n", __func__, is_chroma);
+		dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs        = %d\n", __func__, dpte_buf_in_pte_reqs);
+		dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear);
+
+		ASSERT(log2_dpte_row_height_linear >= 3);
+
+		if (log2_dpte_row_height_linear > 7)
+			log2_dpte_row_height_linear = 7;
+
+		log2_dpte_row_height = log2_dpte_row_height_linear;
+		// For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
+		// the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
+		dpte_row_height = 1 << log2_dpte_row_height;
+		dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, dpte_req_width, 1) + dpte_req_width;
+		rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
+	} else {
+		// the upper bound of the dpte_row_width without dependency on viewport position follows.
+		// for tiled mode, row height is the same as req height and row store up to vp size upper bound
+		if (!surf_vert) {
+			log2_dpte_row_height = log2_dpte_req_height;
+			dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) + dpte_req_width;
+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
+		} else {
+			log2_dpte_row_height = (log2_blk_width < log2_dpte_req_width) ? log2_blk_width : log2_dpte_req_width;
+			dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) + dpte_req_height;
+			rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
+		}
+	}
+	if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
+	else
+		rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
+
+	rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
+
+	// the dpte_group_bytes is reduced for the specific case of vertical
+	// access of a tile surface that has dpte request of 8x1 ptes.
+	if (hostvm_enable)
+		rq_sizing_param->dpte_group_bytes = 512;
+	else {
+		if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
+			rq_sizing_param->dpte_group_bytes = 512;
+		else
+			rq_sizing_param->dpte_group_bytes = 2048;
+	}
+
+	//since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
+	log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
+	log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
+
+	// full sized data pte group width in elements
+	if (!surf_vert)
+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
+	else
+		log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
+
+	//But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
+	if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
+		log2_dpte_group_width = log2_dpte_group_width - 1;
+
+	dpte_group_width = 1 << log2_dpte_group_width;
+
+	// since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
+	// the upper bound for the dpte groups per row is as follows.
+	rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 1);
+}
+
+static void get_surf_rq_param(
+		struct display_mode_lib *mode_lib,
+		display_data_rq_sizing_params_st *rq_sizing_param,
+		display_data_rq_dlg_params_st *rq_dlg_param,
+		display_data_rq_misc_params_st *rq_misc_param,
+		const display_pipe_params_st pipe_param,
+		bool is_chroma,
+		bool is_alpha)
+{
+	bool mode_422 = 0;
+	unsigned int vp_width = 0;
+	unsigned int vp_height = 0;
+	unsigned int data_pitch = 0;
+	unsigned int meta_pitch = 0;
+	unsigned int surface_height = 0;
+	unsigned int ppe = mode_422 ? 2 : 1;
+
+	// FIXME check if ppe apply for both luma and chroma in 422 case
+	if (is_chroma | is_alpha) {
+		vp_width = pipe_param.src.viewport_width_c / ppe;
+		vp_height = pipe_param.src.viewport_height_c;
+		data_pitch = pipe_param.src.data_pitch_c;
+		meta_pitch = pipe_param.src.meta_pitch_c;
+		surface_height = pipe_param.src.surface_height_y / 2.0;
+	} else {
+		vp_width = pipe_param.src.viewport_width / ppe;
+		vp_height = pipe_param.src.viewport_height;
+		data_pitch = pipe_param.src.data_pitch;
+		meta_pitch = pipe_param.src.meta_pitch;
+		surface_height = pipe_param.src.surface_height_y;
+	}
+
+	if (pipe_param.dest.odm_combine) {
+		unsigned int access_dir;
+		unsigned int full_src_vp_width;
+		unsigned int hactive_odm;
+		unsigned int src_hactive_odm;
+
+		access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
+		hactive_odm = pipe_param.dest.hactive / ((unsigned int) pipe_param.dest.odm_combine * 2);
+		if (is_chroma) {
+			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
+			src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_odm;
+		} else {
+			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
+			src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio * hactive_odm;
+		}
+
+		if (access_dir == 0) {
+			vp_width = dml_min(full_src_vp_width, src_hactive_odm);
+			dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width);
+		} else {
+			vp_height = dml_min(full_src_vp_width, src_hactive_odm);
+			dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height);
+
+		}
+		dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width);
+		dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm);
+		dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm);
+	}
+
+	rq_sizing_param->chunk_bytes = 8192;
+
+	if (is_alpha) {
+		rq_sizing_param->chunk_bytes = 4096;
+	}
+
+	if (rq_sizing_param->chunk_bytes == 64 * 1024)
+		rq_sizing_param->min_chunk_bytes = 0;
+	else
+		rq_sizing_param->min_chunk_bytes = 1024;
+
+	rq_sizing_param->meta_chunk_bytes = 2048;
+	rq_sizing_param->min_meta_chunk_bytes = 256;
+
+	if (pipe_param.src.hostvm)
+		rq_sizing_param->mpte_group_bytes = 512;
+	else
+		rq_sizing_param->mpte_group_bytes = 2048;
+
+	get_meta_and_pte_attr(
+			mode_lib,
+			rq_dlg_param,
+			rq_misc_param,
+			rq_sizing_param,
+			vp_width,
+			vp_height,
+			data_pitch,
+			meta_pitch,
+			pipe_param.src.source_format,
+			pipe_param.src.sw_mode,
+			pipe_param.src.macro_tile_size,
+			pipe_param.src.source_scan,
+			pipe_param.src.hostvm,
+			is_chroma,
+			surface_height);
+}
+
+static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, display_rq_params_st *rq_param, const display_pipe_params_st pipe_param)
+{
+	// get param for luma surface
+	rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 || pipe_param.src.source_format == dm_420_10 || pipe_param.src.source_format == dm_rgbe_alpha
+			|| pipe_param.src.source_format == dm_420_12;
+
+	rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
+
+	rq_param->rgbe_alpha = (pipe_param.src.source_format == dm_rgbe_alpha) ? 1 : 0;
+
+	get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_l), &(rq_param->dlg.rq_l), &(rq_param->misc.rq_l), pipe_param, 0, 0);
+
+	if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
+		// get param for chroma surface
+		get_surf_rq_param(mode_lib, &(rq_param->sizing.rq_c), &(rq_param->dlg.rq_c), &(rq_param->misc.rq_c), pipe_param, 1, rq_param->rgbe_alpha);
+	}
+
+	// calculate how to split the det buffer space between luma and chroma
+	handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
+	print__rq_params_st(mode_lib, *rq_param);
+}
+
+void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, display_rq_regs_st *rq_regs, const display_pipe_params_st pipe_param)
+{
+	display_rq_params_st rq_param = {0};
+
+	memset(rq_regs, 0, sizeof(*rq_regs));
+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
+	extract_rq_regs(mode_lib, rq_regs, rq_param);
+
+	print__rq_regs_st(mode_lib, *rq_regs);
+}
+
+static void calculate_ttu_cursor(
+		struct display_mode_lib *mode_lib,
+		double *refcyc_per_req_delivery_pre_cur,
+		double *refcyc_per_req_delivery_cur,
+		double refclk_freq_in_mhz,
+		double ref_freq_to_pix_freq,
+		double hscale_pixel_rate_l,
+		double hscl_ratio,
+		double vratio_pre_l,
+		double vratio_l,
+		unsigned int cur_width,
+		enum cursor_bpp cur_bpp)
+{
+	unsigned int cur_src_width = cur_width;
+	unsigned int cur_req_size = 0;
+	unsigned int cur_req_width = 0;
+	double cur_width_ub = 0.0;
+	double cur_req_per_width = 0.0;
+	double hactive_cur = 0.0;
+
+	ASSERT(cur_src_width <= 256);
+
+	*refcyc_per_req_delivery_pre_cur = 0.0;
+	*refcyc_per_req_delivery_cur = 0.0;
+	if (cur_src_width > 0) {
+		unsigned int cur_bit_per_pixel = 0;
+
+		if (cur_bpp == dm_cur_2bit) {
+			cur_req_size = 64; // byte
+			cur_bit_per_pixel = 2;
+		} else { // 32bit
+			cur_bit_per_pixel = 32;
+			if (cur_src_width >= 1 && cur_src_width <= 16)
+				cur_req_size = 64;
+			else if (cur_src_width >= 17 && cur_src_width <= 31)
+				cur_req_size = 128;
+			else
+				cur_req_size = 256;
+		}
+
+		cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
+		cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) * (double) cur_req_width;
+		cur_req_per_width = cur_width_ub / (double) cur_req_width;
+		hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
+
+		if (vratio_pre_l <= 1.0) {
+			*refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
+		} else {
+			*refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
+		}
+
+		ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
+
+		if (vratio_l <= 1.0) {
+			*refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq / (double) cur_req_per_width;
+		} else {
+			*refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz * (double) cur_src_width / hscale_pixel_rate_l / (double) cur_req_per_width;
+		}
+
+		dml_print("DML_DLG: %s: cur_req_width                     = %d\n", __func__, cur_req_width);
+		dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n", __func__, cur_width_ub);
+		dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n", __func__, cur_req_per_width);
+		dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n", __func__, hactive_cur);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n", __func__, *refcyc_per_req_delivery_pre_cur);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n", __func__, *refcyc_per_req_delivery_cur);
+
+		ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
+	}
+}
+
+// Note: currently taken in as is.
+// Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
+static void dml_rq_dlg_get_dlg_params(
+		struct display_mode_lib *mode_lib,
+		const display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx,
+		display_dlg_regs_st *disp_dlg_regs,
+		display_ttu_regs_st *disp_ttu_regs,
+		const display_rq_dlg_params_st rq_dlg_param,
+		const display_dlg_sys_params_st dlg_sys_param,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en,
+		const bool ignore_viewport_pos,
+		const bool immediate_flip_support)
+{
+	const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
+	const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
+	const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
+	const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
+	const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
+	const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
+	unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX];
+
+	// -------------------------
+	// Section 1.15.2.1: OTG dependent Params
+	// -------------------------
+	// Timing
+	unsigned int htotal = dst->htotal;
+	unsigned int hblank_end = dst->hblank_end;
+	unsigned int vblank_start = dst->vblank_start;
+	unsigned int vblank_end = dst->vblank_end;
+
+	double dppclk_freq_in_mhz = clks->dppclk_mhz;
+	double refclk_freq_in_mhz = clks->refclk_mhz;
+	double pclk_freq_in_mhz = dst->pixel_rate_mhz;
+	bool interlaced = dst->interlaced;
+	double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
+	double min_ttu_vblank;
+	unsigned int dlg_vblank_start;
+	bool dual_plane;
+	bool mode_422;
+	unsigned int access_dir;
+	unsigned int vp_height_l;
+	unsigned int vp_width_l;
+	unsigned int vp_height_c;
+	unsigned int vp_width_c;
+
+	// Scaling
+	unsigned int htaps_l;
+	unsigned int htaps_c;
+	double hratio_l;
+	double hratio_c;
+	double vratio_l;
+	double vratio_c;
+	bool scl_enable;
+
+	unsigned int swath_width_ub_l;
+	unsigned int dpte_groups_per_row_ub_l;
+	unsigned int swath_width_ub_c;
+	unsigned int dpte_groups_per_row_ub_c;
+
+	unsigned int meta_chunks_per_row_ub_l;
+	unsigned int meta_chunks_per_row_ub_c;
+	unsigned int vupdate_offset;
+	unsigned int vupdate_width;
+	unsigned int vready_offset;
+
+	unsigned int dppclk_delay_subtotal;
+	unsigned int dispclk_delay_subtotal;
+
+	unsigned int vstartup_start;
+	unsigned int dst_x_after_scaler;
+	unsigned int dst_y_after_scaler;
+	double dst_y_prefetch;
+	double dst_y_per_vm_vblank;
+	double dst_y_per_row_vblank;
+	double dst_y_per_vm_flip;
+	double dst_y_per_row_flip;
+	double max_dst_y_per_vm_vblank;
+	double max_dst_y_per_row_vblank;
+	double vratio_pre_l;
+	double vratio_pre_c;
+	unsigned int req_per_swath_ub_l;
+	unsigned int req_per_swath_ub_c;
+	unsigned int meta_row_height_l;
+	unsigned int meta_row_height_c;
+	unsigned int swath_width_pixels_ub_l;
+	unsigned int swath_width_pixels_ub_c;
+	unsigned int scaler_rec_in_width_l;
+	unsigned int scaler_rec_in_width_c;
+	unsigned int dpte_row_height_l;
+	unsigned int dpte_row_height_c;
+	double hscale_pixel_rate_l;
+	double hscale_pixel_rate_c;
+	double min_hratio_fact_l;
+	double min_hratio_fact_c;
+	double refcyc_per_line_delivery_pre_l;
+	double refcyc_per_line_delivery_pre_c;
+	double refcyc_per_line_delivery_l;
+	double refcyc_per_line_delivery_c;
+
+	double refcyc_per_req_delivery_pre_l;
+	double refcyc_per_req_delivery_pre_c;
+	double refcyc_per_req_delivery_l;
+	double refcyc_per_req_delivery_c;
+
+	unsigned int full_recout_width;
+	double refcyc_per_req_delivery_pre_cur0;
+	double refcyc_per_req_delivery_cur0;
+	double refcyc_per_req_delivery_pre_cur1;
+	double refcyc_per_req_delivery_cur1;
+	int unsigned vba__min_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
+	int unsigned vba__vready_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+
+	float vba__refcyc_per_line_delivery_pre_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+	float vba__refcyc_per_line_delivery_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	float vba__refcyc_per_req_delivery_pre_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+	float vba__refcyc_per_req_delivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+
+	memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
+	memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
+
+	dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en);
+	dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en);
+	dml_print("DML_DLG: %s: vm_en     = %d\n", __func__, vm_en);
+	dml_print("DML_DLG: %s: ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
+	dml_print("DML_DLG: %s: immediate_flip_support  = %d\n", __func__, immediate_flip_support);
+
+	dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
+	dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced); ASSERT(ref_freq_to_pix_freq < 4.0);
+
+	disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
+	disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));
+	disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end;	// 15 bits
+
+	//set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
+	min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);	// From VBA
+
+	dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
+
+	disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));
+
+	dml_print("DML_DLG: %s: min_ttu_vblank (us)         = %3.2f\n", __func__, min_ttu_vblank);
+	dml_print("DML_DLG: %s: min_dst_y_next_start        = 0x%0x\n", __func__, disp_dlg_regs->min_dst_y_next_start);
+	dml_print("DML_DLG: %s: dlg_vblank_start            = 0x%0x\n", __func__, dlg_vblank_start);
+	dml_print("DML_DLG: %s: ref_freq_to_pix_freq        = %3.2f\n", __func__, ref_freq_to_pix_freq);
+	dml_print("DML_DLG: %s: vba__min_dst_y_next_start   = 0x%0x\n", __func__, vba__min_dst_y_next_start);
+
+	//old_impl_vs_vba_impl("min_dst_y_next_start", dlg_vblank_start, vba__min_dst_y_next_start);
+
+	// -------------------------
+	// Section 1.15.2.2: Prefetch, Active and TTU
+	// -------------------------
+	// Prefetch Calc
+	// Source
+	dual_plane = is_dual_plane((enum source_format_class) (src->source_format));
+	mode_422 = 0;
+	access_dir = (src->source_scan == dm_vert);	// vp access direction: horizontal or vertical accessed
+	vp_height_l = src->viewport_height;
+	vp_width_l = src->viewport_width;
+	vp_height_c = src->viewport_height_c;
+	vp_width_c = src->viewport_width_c;
+
+	// Scaling
+	htaps_l = taps->htaps;
+	htaps_c = taps->htaps_c;
+	hratio_l = scl->hscl_ratio;
+	hratio_c = scl->hscl_ratio_c;
+	vratio_l = scl->vscl_ratio;
+	vratio_c = scl->vscl_ratio_c;
+	scl_enable = scl->scl_enable;
+
+	swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
+	dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
+	swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
+	dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
+
+	meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
+	meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
+	vupdate_offset = dst->vupdate_offset;
+	vupdate_width = dst->vupdate_width;
+	vready_offset = dst->vready_offset;
+
+	dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
+	dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
+
+	if (scl_enable)
+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
+	else
+		dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
+
+	dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
+
+	if (dout->dsc_enable) {
+		double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA
+		dispclk_delay_subtotal += dsc_delay;
+	}
+
+	vstartup_start = dst->vstartup_start;
+	if (interlaced) {
+		if (vstartup_start / 2.0 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end / 2.0)
+			disp_dlg_regs->vready_after_vcount0 = 1;
+		else
+			disp_dlg_regs->vready_after_vcount0 = 0;
+	} else {
+		if (vstartup_start - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal <= vblank_end)
+			disp_dlg_regs->vready_after_vcount0 = 1;
+		else
+			disp_dlg_regs->vready_after_vcount0 = 0;
+	}
+
+	dml_print("DML_DLG: %s: vready_after_vcount0 = %d\n", __func__, disp_dlg_regs->vready_after_vcount0);
+	dml_print("DML_DLG: %s: vba__vready_after_vcount0 = %d\n", __func__, vba__vready_after_vcount0);
+	//old_impl_vs_vba_impl("vready_after_vcount0", disp_dlg_regs->vready_after_vcount0, vba__vready_after_vcount0);
+
+	if (interlaced)
+		vstartup_start = vstartup_start / 2;
+
+	dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+	dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA
+
+	// do some adjustment on the dst_after scaler to account for odm combine mode
+	dml_print("DML_DLG: %s: input dst_x_after_scaler   = %d\n", __func__, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: input dst_y_after_scaler   = %d\n", __func__, dst_y_after_scaler);
+
+	// need to figure out which side of odm combine we're in
+	if (dst->odm_combine) {
+		// figure out which pipes go together
+		bool visited[DC__NUM_PIPES__MAX];
+		unsigned int i, j, k;
+
+		for (k = 0; k < num_pipes; ++k) {
+			visited[k] = false;
+			pipe_index_in_combine[k] = 0;
+		}
+
+		for (i = 0; i < num_pipes; i++) {
+			if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
+
+				unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
+				unsigned int grp_idx = 0;
+
+				for (j = i; j < num_pipes; j++) {
+					if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) {
+						pipe_index_in_combine[j] = grp_idx;
+						dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx);
+						grp_idx++;
+						visited[j] = true;
+					}
+				}
+			}
+		}
+
+	}
+
+	if (dst->odm_combine == dm_odm_combine_mode_disabled) {
+		disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end * ref_freq_to_pix_freq);
+	} else {
+		unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4
+		unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx];
+		disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq);
+	} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));
+
+	dml_print("DML_DLG: %s: htotal                     = %d\n", __func__, htotal);
+	dml_print("DML_DLG: %s: dst_x_after_scaler[%d]     = %d\n", __func__, pipe_idx, dst_x_after_scaler);
+	dml_print("DML_DLG: %s: dst_y_after_scaler[%d]     = %d\n", __func__, pipe_idx, dst_y_after_scaler);
+
+	dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+	dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);        // From VBA
+
+	max_dst_y_per_vm_vblank = 32.0;        //U5.2
+	max_dst_y_per_row_vblank = 16.0;        //U4.2
+
+	// magic!
+	if (htotal <= 75) {
+		max_dst_y_per_vm_vblank = 100.0;
+		max_dst_y_per_row_vblank = 100.0;
+	}
+
+	dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
+	dml_print("DML_DLG: %s: dst_y_per_vm_flip    = %3.2f\n", __func__, dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: dst_y_per_row_flip   = %3.2f\n", __func__, dst_y_per_row_flip);
+	dml_print("DML_DLG: %s: dst_y_per_vm_vblank  = %3.2f\n", __func__, dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank);
+
+	ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank); ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank);
+
+	ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
+
+	vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+	vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);    // From VBA
+
+	dml_print("DML_DLG: %s: vratio_pre_l = %3.2f\n", __func__, vratio_pre_l);
+	dml_print("DML_DLG: %s: vratio_pre_c = %3.2f\n", __func__, vratio_pre_c);
+
+	// Active
+	req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
+	req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
+	meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
+	meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
+	swath_width_pixels_ub_l = 0;
+	swath_width_pixels_ub_c = 0;
+	scaler_rec_in_width_l = 0;
+	scaler_rec_in_width_c = 0;
+	dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
+	dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
+
+	if (mode_422) {
+		swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
+		swath_width_pixels_ub_c = swath_width_ub_c * 2;
+	} else {
+		swath_width_pixels_ub_l = swath_width_ub_l * 1;
+		swath_width_pixels_ub_c = swath_width_ub_c * 1;
+	}
+
+	hscale_pixel_rate_l = 0.;
+	hscale_pixel_rate_c = 0.;
+	min_hratio_fact_l = 1.0;
+	min_hratio_fact_c = 1.0;
+
+	if (hratio_l <= 1)
+		min_hratio_fact_l = 2.0;
+	else if (htaps_l <= 6) {
+		if ((hratio_l * 2.0) > 4.0)
+			min_hratio_fact_l = 4.0;
+		else
+			min_hratio_fact_l = hratio_l * 2.0;
+	} else {
+		if (hratio_l > 4.0)
+			min_hratio_fact_l = 4.0;
+		else
+			min_hratio_fact_l = hratio_l;
+	}
+
+	hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
+
+	dml_print("DML_DLG: %s: hratio_l = %3.2f\n", __func__, hratio_l);
+	dml_print("DML_DLG: %s: min_hratio_fact_l = %3.2f\n", __func__, min_hratio_fact_l);
+	dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", __func__, hscale_pixel_rate_l);
+
+	if (hratio_c <= 1)
+		min_hratio_fact_c = 2.0;
+	else if (htaps_c <= 6) {
+		if ((hratio_c * 2.0) > 4.0)
+			min_hratio_fact_c = 4.0;
+		else
+			min_hratio_fact_c = hratio_c * 2.0;
+	} else {
+		if (hratio_c > 4.0)
+			min_hratio_fact_c = 4.0;
+		else
+			min_hratio_fact_c = hratio_c;
+	}
+
+	hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
+
+	refcyc_per_line_delivery_pre_l = 0.;
+	refcyc_per_line_delivery_pre_c = 0.;
+	refcyc_per_line_delivery_l = 0.;
+	refcyc_per_line_delivery_c = 0.;
+
+	refcyc_per_req_delivery_pre_l = 0.;
+	refcyc_per_req_delivery_pre_c = 0.;
+	refcyc_per_req_delivery_l = 0.;
+	refcyc_per_req_delivery_c = 0.;
+
+	full_recout_width = 0;
+	// In ODM
+	if (src->is_hsplit) {
+		// This "hack"  is only allowed (and valid) for MPC combine. In ODM
+		// combine, you MUST specify the full_recout_width...according to Oswin
+		if (dst->full_recout_width == 0 && !dst->odm_combine) {
+			dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", __func__);
+			full_recout_width = dst->recout_width * 2; // assume half split for dcn1
+		} else
+			full_recout_width = dst->full_recout_width;
+	} else
+		full_recout_width = dst->recout_width;
+
+	// As of DCN2, mpc_combine and odm_combine are mutually exclusive
+	refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_pre_l,
+			hscale_pixel_rate_l,
+			swath_width_pixels_ub_l,
+			1); // per line
+
+	refcyc_per_line_delivery_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_l,
+			hscale_pixel_rate_l,
+			swath_width_pixels_ub_l,
+			1); // per line
+
+	dml_print("DML_DLG: %s: full_recout_width              = %d\n", __func__, full_recout_width);
+	dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n", __func__, hscale_pixel_rate_l);
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, refcyc_per_line_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n", __func__, refcyc_per_line_delivery_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_l     = %3.2f\n", __func__, vba__refcyc_per_line_delivery_l);
+
+	//old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_l", refcyc_per_line_delivery_pre_l, vba__refcyc_per_line_delivery_pre_l);
+	//old_impl_vs_vba_impl("refcyc_per_line_delivery_l", refcyc_per_line_delivery_l, vba__refcyc_per_line_delivery_l);
+
+	if (dual_plane) {
+		float vba__refcyc_per_line_delivery_pre_c = get_refcyc_per_line_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+		float vba__refcyc_per_line_delivery_c = get_refcyc_per_line_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+		refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_pre_c,
+				hscale_pixel_rate_c,
+				swath_width_pixels_ub_c,
+				1); // per line
+
+		refcyc_per_line_delivery_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_c,
+				hscale_pixel_rate_c,
+				swath_width_pixels_ub_c,
+				1); // per line
+
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, refcyc_per_line_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n", __func__, refcyc_per_line_delivery_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_line_delivery_pre_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_line_delivery_c     = %3.2f\n", __func__, vba__refcyc_per_line_delivery_c);
+
+		//old_impl_vs_vba_impl("refcyc_per_line_delivery_pre_c", refcyc_per_line_delivery_pre_c, vba__refcyc_per_line_delivery_pre_c);
+		//old_impl_vs_vba_impl("refcyc_per_line_delivery_c", refcyc_per_line_delivery_c, vba__refcyc_per_line_delivery_c);
+	}
+
+	if (src->dynamic_metadata_enable && src->gpuvm)
+		disp_dlg_regs->refcyc_per_vm_dmdata = get_refcyc_per_vm_dmdata_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	disp_dlg_regs->dmdata_dl_delta = get_dmdata_dl_delta_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+	// TTU - Luma / Chroma
+	if (access_dir) {  // vertical access
+		scaler_rec_in_width_l = vp_height_l;
+		scaler_rec_in_width_c = vp_height_c;
+	} else {
+		scaler_rec_in_width_l = vp_width_l;
+		scaler_rec_in_width_c = vp_width_c;
+	}
+
+	refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_pre_l,
+			hscale_pixel_rate_l,
+			scaler_rec_in_width_l,
+			req_per_swath_ub_l);  // per req
+
+	refcyc_per_req_delivery_l = get_refcyc_per_delivery(
+			mode_lib,
+			refclk_freq_in_mhz,
+			pclk_freq_in_mhz,
+			dst->odm_combine,
+			full_recout_width,
+			dst->hactive,
+			vratio_l,
+			hscale_pixel_rate_l,
+			scaler_rec_in_width_l,
+			req_per_swath_ub_l);  // per req
+
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, refcyc_per_req_delivery_pre_l);
+	dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n", __func__, refcyc_per_req_delivery_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_l = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_l);
+	dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_l     = %3.2f\n", __func__, vba__refcyc_per_req_delivery_l);
+
+	//old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_l", refcyc_per_req_delivery_pre_l, vba__refcyc_per_req_delivery_pre_l);
+	//old_impl_vs_vba_impl("refcyc_per_req_delivery_l", refcyc_per_req_delivery_l, vba__refcyc_per_req_delivery_l);
+
+	ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
+
+	if (dual_plane) {
+		float vba__refcyc_per_req_delivery_pre_c = get_refcyc_per_req_delivery_pre_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+		float vba__refcyc_per_req_delivery_c = get_refcyc_per_req_delivery_c_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;  // From VBA
+
+		refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_pre_c,
+				hscale_pixel_rate_c,
+				scaler_rec_in_width_c,
+				req_per_swath_ub_c);  // per req
+		refcyc_per_req_delivery_c = get_refcyc_per_delivery(
+				mode_lib,
+				refclk_freq_in_mhz,
+				pclk_freq_in_mhz,
+				dst->odm_combine,
+				full_recout_width,
+				dst->hactive,
+				vratio_c,
+				hscale_pixel_rate_c,
+				scaler_rec_in_width_c,
+				req_per_swath_ub_c);  // per req
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, refcyc_per_req_delivery_pre_c);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n", __func__, refcyc_per_req_delivery_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_c = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_c);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_c     = %3.2f\n", __func__, vba__refcyc_per_req_delivery_c);
+
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_c", refcyc_per_req_delivery_pre_c, vba__refcyc_per_req_delivery_pre_c);
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_c", refcyc_per_req_delivery_c, vba__refcyc_per_req_delivery_c);
+
+		ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
+	}
+
+	// TTU - Cursor
+	refcyc_per_req_delivery_pre_cur0 = 0.0;
+	refcyc_per_req_delivery_cur0 = 0.0;
+
+	ASSERT(src->num_cursors <= 1);
+
+	if (src->num_cursors > 0) {
+		float vba__refcyc_per_req_delivery_pre_cur0;
+		float vba__refcyc_per_req_delivery_cur0;
+
+		calculate_ttu_cursor(
+				mode_lib,
+				&refcyc_per_req_delivery_pre_cur0,
+				&refcyc_per_req_delivery_cur0,
+				refclk_freq_in_mhz,
+				ref_freq_to_pix_freq,
+				hscale_pixel_rate_l,
+				scl->hscl_ratio,
+				vratio_pre_l,
+				vratio_l,
+				src->cur0_src_width,
+				(enum cursor_bpp) (src->cur0_bpp));
+
+		vba__refcyc_per_req_delivery_pre_cur0 = get_refcyc_per_cursor_req_delivery_pre_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+		vba__refcyc_per_req_delivery_cur0 = get_refcyc_per_cursor_req_delivery_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; // From VBA
+
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, refcyc_per_req_delivery_pre_cur0);
+		dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur0     = %3.2f\n", __func__, refcyc_per_req_delivery_cur0);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_pre_cur0 = %3.2f\n", __func__, vba__refcyc_per_req_delivery_pre_cur0);
+		dml_print("DML_DLG: %s: vba__refcyc_per_req_delivery_cur0     = %3.2f\n", __func__, vba__refcyc_per_req_delivery_cur0);
+
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_pre_cur0", refcyc_per_req_delivery_pre_cur0, vba__refcyc_per_req_delivery_pre_cur0);
+		//old_impl_vs_vba_impl("refcyc_per_req_delivery_cur0", refcyc_per_req_delivery_cur0, vba__refcyc_per_req_delivery_cur0);
+	}
+
+	refcyc_per_req_delivery_pre_cur1 = 0.0;
+	refcyc_per_req_delivery_cur1 = 0.0;
+
+	// TTU - Misc
+	// all hard-coded
+
+	// Assignment to register structures
+	disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler;	// in terms of line
+	ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8);
+	disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq;	// in terms of refclk
+	ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));
+	disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
+	disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
+
+	disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
+	disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
+
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank  = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank);
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank);
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip    = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip);
+	dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip   = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip);
+
+	// hack for FPGA
+	if (mode_lib->project == DML_PROJECT_DCN31_FPGA) {
+		if (disp_dlg_regs->vratio_prefetch >= (unsigned int) dml_pow(2, 22)) {
+			disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 22) - 1;
+			dml_print("vratio_prefetch exceed the max value, the register field is [21:0]\n");
+		}
+	}
+
+	disp_dlg_regs->refcyc_per_pte_group_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
+	ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));
+
+	if (dual_plane) {
+		disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_c);
+		ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));
+	}
+
+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
+	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
+
+	disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
+
+	disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
+	disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
+
+	if (dual_plane) {
+		disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
+		disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
+	}
+
+	disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;            // From VBA
+	disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;            // From VBA
+	disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); // From VBA
+	disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10);   // From VBA
+
+	// Clamp to max for now
+	if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1;
+
+	if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1;
+
+	if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1;
+
+	if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1;
+
+	disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));
+	if (dual_plane) {
+		disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));
+		if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
+			dml_print(
+					"DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
+					__func__,
+					disp_dlg_regs->dst_y_per_pte_row_nom_c,
+					(unsigned int) dml_pow(2, 17) - 1);
+		}
+	}
+
+	disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));
+
+	disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));
+	ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));
+
+	disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
+			/ (double) dpte_groups_per_row_ub_l);
+	if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
+	disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
+			/ (double) meta_chunks_per_row_ub_l);
+	if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
+		disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
+
+	if (dual_plane) {
+		disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
+				/ (double) dpte_groups_per_row_ub_c);
+		if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
+			disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
+
+		// TODO: Is this the right calculation? Does htotal need to be halved?
+		disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * (double) htotal * ref_freq_to_pix_freq
+				/ (double) meta_chunks_per_row_ub_c);
+		if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
+			disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
+	}
+
+	disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1);
+	disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1);
+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));
+
+	disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1);
+	disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1);
+	ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));
+
+	disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
+	disp_dlg_regs->dst_y_offset_cur0 = 0;
+	disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
+	disp_dlg_regs->dst_y_offset_cur1 = 0;
+
+	disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
+
+	disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
+	disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));
+
+	disp_ttu_regs->qos_level_low_wm = 0;
+	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
+
+	disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal * ref_freq_to_pix_freq);
+	ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
+
+	disp_ttu_regs->qos_level_flip = 14;
+	disp_ttu_regs->qos_level_fixed_l = 8;
+	disp_ttu_regs->qos_level_fixed_c = 8;
+	disp_ttu_regs->qos_level_fixed_cur0 = 8;
+	disp_ttu_regs->qos_ramp_disable_l = 0;
+	disp_ttu_regs->qos_ramp_disable_c = 0;
+	disp_ttu_regs->qos_ramp_disable_cur0 = 0;
+
+	disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
+	ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
+
+	print__ttu_regs_st(mode_lib, *disp_ttu_regs);
+	print__dlg_regs_st(mode_lib, *disp_dlg_regs);
+}
+
+void dml31_rq_dlg_get_dlg_reg(
+		struct display_mode_lib *mode_lib,
+		display_dlg_regs_st *dlg_regs,
+		display_ttu_regs_st *ttu_regs,
+		display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en,
+		const bool ignore_viewport_pos,
+		const bool immediate_flip_support)
+{
+	display_rq_params_st rq_param = {0};
+	display_dlg_sys_params_st dlg_sys_param = {0};
+
+	// Get watermark and Tex.
+	dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, e2e_pipe_param, num_pipes);
+	dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, e2e_pipe_param, num_pipes);
+
+	print__dlg_sys_params_st(mode_lib, dlg_sys_param);
+
+	// system parameter calculation done
+
+	dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
+	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe);
+	dml_rq_dlg_get_dlg_params(
+			mode_lib,
+			e2e_pipe_param,
+			num_pipes,
+			pipe_idx,
+			dlg_regs,
+			ttu_regs,
+			rq_param.dlg,
+			dlg_sys_param,
+			cstate_en,
+			pstate_en,
+			vm_en,
+			ignore_viewport_pos,
+			immediate_flip_support);
+	dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
+}
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
new file mode 100644
index 000000000000..adf8518f761f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef __DML31_DISPLAY_RQ_DLG_CALC_H__
+#define __DML31_DISPLAY_RQ_DLG_CALC_H__
+
+#include "../display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+// Function: dml_rq_dlg_get_rq_reg
+//  Main entry point for test to get the register values out of this DML class.
+//  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
+//  and then populate the rq_regs struct
+// Input:
+//  pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
+// Output:
+//  rq_regs - struct that holds all the RQ registers field value.
+//            See also: <display_rq_regs_st>
+void dml31_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
+		display_rq_regs_st *rq_regs,
+		const display_pipe_params_st pipe_param);
+
+// Function: dml_rq_dlg_get_dlg_reg
+//   Calculate and return DLG and TTU register struct given the system setting
+// Output:
+//  dlg_regs - output DLG register struct
+//  ttu_regs - output DLG TTU register struct
+// Input:
+//  e2e_pipe_param - "compacted" array of e2e pipe param struct
+//  num_pipes - num of active "pipe" or "route"
+//  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+//  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+//           Added for legacy or unrealistic timing tests.
+void dml31_rq_dlg_get_dlg_reg(struct display_mode_lib             *mode_lib,
+		display_dlg_regs_st          *dlg_regs,
+		display_ttu_regs_st          *ttu_regs,
+		display_e2e_pipe_params_st   *e2e_pipe_param,
+		const unsigned int            num_pipes,
+		const unsigned int            pipe_idx,
+		const bool                    cstate_en,
+		const bool                    pstate_en,
+		const bool                    vm_en,
+		const bool                    ignore_viewport_pos,
+		const bool                    immediate_flip_support);
+
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
index 1f7b6ddf3020..9bb3b00e8be1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c
@@ -34,6 +34,10 @@
 #include "dcn30/display_mode_vba_30.h"
 #include "dcn30/display_rq_dlg_calc_30.h"
 #include "dml_logger.h"
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+#include "dcn31/display_mode_vba_31.h"
+#include "dcn31/display_rq_dlg_calc_31.h"
+#endif
 
 const struct dml_funcs dml20_funcs = {
 	.validate = dml20_ModeSupportAndSystemConfigurationFull,
@@ -62,6 +66,14 @@ const struct dml_funcs dml30_funcs = {
 	.rq_dlg_get_dlg_reg = dml30_rq_dlg_get_dlg_reg,
 	.rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg
 };
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+const struct dml_funcs dml31_funcs = {
+	.validate = dml31_ModeSupportAndSystemConfigurationFull,
+	.recalculate = dml31_recalculate,
+	.rq_dlg_get_dlg_reg = dml31_rq_dlg_get_dlg_reg,
+	.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
+};
+#endif
 
 void dml_init_instance(struct display_mode_lib *lib,
 		const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
@@ -84,7 +96,13 @@ void dml_init_instance(struct display_mode_lib *lib,
 	case DML_PROJECT_DCN30:
 		lib->funcs = dml30_funcs;
 		break;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case DML_PROJECT_DCN31:
+	case DML_PROJECT_DCN31_FPGA:
+		lib->funcs = dml31_funcs;
+		break;
 
+#endif
 	default:
 		break;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index 6ae5df58a4fc..7b7f1500a91e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -38,6 +38,10 @@ enum dml_project {
 	DML_PROJECT_NAVI10v2,
 	DML_PROJECT_DCN21,
 	DML_PROJECT_DCN30,
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	DML_PROJECT_DCN31,
+	DML_PROJECT_DCN31_FPGA,
+#endif
 };
 
 struct display_mode_lib;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index a0f0c54c863b..bdd075576573 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -74,6 +74,10 @@ struct _vcs_dpi_soc_bounding_box_st {
 	unsigned int num_states;
 	double sr_exit_time_us;
 	double sr_enter_plus_exit_time_us;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	double sr_exit_z8_time_us;
+	double sr_enter_plus_exit_z8_time_us;
+#endif
 	double urgent_latency_us;
 	double urgent_latency_pixel_data_only_us;
 	double urgent_latency_pixel_mixed_with_vm_data_us;
@@ -209,6 +213,14 @@ struct _vcs_dpi_ip_params_st {
 	unsigned int is_line_buffer_bpp_fixed;
 	unsigned int line_buffer_fixed_bpp;
 	unsigned int dcc_supported;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	unsigned int config_return_buffer_size_in_kbytes;
+	unsigned int compressed_buffer_segment_size_in_kbytes;
+	unsigned int meta_fifo_size_in_kentries;
+	unsigned int zero_size_buffer_entries;
+	unsigned int compbuf_reserved_space_64b;
+	unsigned int compbuf_reserved_space_zs;
+#endif
 
 	unsigned int IsLineBufferBppFixed;
 	unsigned int LineBufferFixedBpp;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index a4a1b96967c0..345d2d409a6e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -89,6 +89,12 @@ dml_get_attr_func(wm_memory_trip, mode_lib->vba.UrgentLatency);
 dml_get_attr_func(wm_writeback_urgent, mode_lib->vba.WritebackUrgentWatermark);
 dml_get_attr_func(wm_stutter_exit, mode_lib->vba.StutterExitWatermark);
 dml_get_attr_func(wm_stutter_enter_exit, mode_lib->vba.StutterEnterPlusExitWatermark);
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+dml_get_attr_func(wm_z8_stutter_exit, mode_lib->vba.Z8StutterExitWatermark);
+dml_get_attr_func(wm_z8_stutter_enter_exit, mode_lib->vba.Z8StutterEnterPlusExitWatermark);
+dml_get_attr_func(stutter_efficiency_z8, mode_lib->vba.Z8StutterEfficiency);
+dml_get_attr_func(stutter_num_bursts_z8, mode_lib->vba.Z8NumberOfStutterBurstsPerFrame);
+#endif
 dml_get_attr_func(wm_dram_clock_change, mode_lib->vba.DRAMClockChangeWatermark);
 dml_get_attr_func(wm_writeback_dram_clock_change, mode_lib->vba.WritebackDRAMClockChangeWatermark);
 dml_get_attr_func(stutter_efficiency, mode_lib->vba.StutterEfficiency);
@@ -158,6 +164,10 @@ dml_get_pipe_attr_func(vstartup, mode_lib->vba.VStartup);
 dml_get_pipe_attr_func(vupdate_offset, mode_lib->vba.VUpdateOffsetPix);
 dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
 dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);
+dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
+#endif
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -226,6 +236,16 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.WritebackLatency = soc->writeback_latency_us;
 	mode_lib->vba.SRExitTime = soc->sr_exit_time_us;
 	mode_lib->vba.SREnterPlusExitTime = soc->sr_enter_plus_exit_time_us;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	mode_lib->vba.PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency = soc->pct_ideal_sdp_bw_after_urgent;
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
+	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly = soc->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
+	mode_lib->vba.MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation =
+			soc->max_avg_sdp_bw_use_normal_percent;
+	mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us;
+	mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us;
+#endif
 	mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
 	mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
 	mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
@@ -300,6 +320,16 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.MaxPSCLToLBThroughput = ip->max_pscl_lb_bw_pix_per_clk;
 	mode_lib->vba.ROBBufferSizeInKByte = ip->rob_buffer_size_kbytes;
 	mode_lib->vba.DETBufferSizeInKByte[0] = ip->det_buffer_size_kbytes;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	mode_lib->vba.ConfigReturnBufferSizeInKByte = ip->config_return_buffer_size_in_kbytes;
+	mode_lib->vba.CompressedBufferSegmentSizeInkByte = ip->compressed_buffer_segment_size_in_kbytes;
+	mode_lib->vba.MetaFIFOSizeInKEntries = ip->meta_fifo_size_in_kentries;
+	mode_lib->vba.ZeroSizeBufferEntries = ip->zero_size_buffer_entries;
+	mode_lib->vba.COMPBUF_RESERVED_SPACE_64B = ip->compbuf_reserved_space_64b;
+	mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs;
+	mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component;
+	mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support;
+#endif
 
 	mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
 	mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
@@ -429,6 +459,11 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c;
 		mode_lib->vba.HTotal[mode_lib->vba.NumberOfActivePlanes] = dst->htotal;
 		mode_lib->vba.VTotal[mode_lib->vba.NumberOfActivePlanes] = dst->vtotal;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+		mode_lib->vba.VFrontPorch[mode_lib->vba.NumberOfActivePlanes] = dst->vfront_porch;
+		mode_lib->vba.DCCFractionOfZeroSizeRequestsLuma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_luma;
+		mode_lib->vba.DCCFractionOfZeroSizeRequestsChroma[mode_lib->vba.NumberOfActivePlanes] = src->dcc_fraction_of_zs_req_chroma;
+#endif
 		mode_lib->vba.DCCEnable[mode_lib->vba.NumberOfActivePlanes] =
 				src->dcc_use_global ?
 						ip->dcc_supported : src->dcc && ip->dcc_supported;
@@ -675,6 +710,13 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		}
 	}
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
+	for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
+		if (pipes[k].pipe.src.unbounded_req_mode == 0)
+			mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting_disable;
+	}
+#endif
 	// TODO: ODMCombineEnabled => 2 * DPPPerPlane...actually maybe not since all pipes are specified
 	// Do we want the dscclk to automatically be halved? Guess not since the value is specified
 	mode_lib->vba.SynchronizedVBlank = pipes[0].pipe.dest.synchronized_vblank_all_planes;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 86db86b7153e..fad7bb57e668 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -39,6 +39,12 @@ dml_get_attr_decl(wm_memory_trip);
 dml_get_attr_decl(wm_writeback_urgent);
 dml_get_attr_decl(wm_stutter_exit);
 dml_get_attr_decl(wm_stutter_enter_exit);
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+dml_get_attr_decl(wm_z8_stutter_exit);
+dml_get_attr_decl(wm_z8_stutter_enter_exit);
+dml_get_attr_decl(stutter_efficiency_z8);
+dml_get_attr_decl(stutter_num_bursts_z8);
+#endif
 dml_get_attr_decl(wm_dram_clock_change);
 dml_get_attr_decl(wm_writeback_dram_clock_change);
 dml_get_attr_decl(stutter_efficiency_no_vblank);
@@ -102,6 +108,10 @@ dml_get_pipe_attr_decl(vstartup);
 dml_get_pipe_attr_decl(vupdate_offset);
 dml_get_pipe_attr_decl(vupdate_width);
 dml_get_pipe_attr_decl(vready_offset);
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+dml_get_pipe_attr_decl(vready_at_or_after_vsync);
+dml_get_pipe_attr_decl(min_dst_y_next_start);
+#endif
 
 double get_total_immediate_flip_bytes(
 		struct display_mode_lib *mode_lib,
@@ -923,6 +933,48 @@ struct vba_vars_st {
 	bool ClampMinDCFCLK;
 	bool AllowDramClockChangeOneDisplayVactive;
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
+	double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
+	double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
+	double SRExitZ8Time;
+	double SREnterPlusExitZ8Time;
+	double Z8StutterExitWatermark;
+	double Z8StutterEnterPlusExitWatermark;
+	double Z8StutterEfficiencyNotIncludingVBlank;
+	double Z8StutterEfficiency;
+	double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
+	double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
+	double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
+	double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
+	double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
+	double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
+	double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
+	double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
+	bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
+	bool LinkCapacitySupport[DC__NUM_DPP__MAX];
+	bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
+	unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
+	unsigned int VFrontPorch[DC__NUM_DPP__MAX];
+	int ConfigReturnBufferSizeInKByte;
+	enum unbounded_requesting_policy UseUnboundedRequesting;
+	int CompressedBufferSegmentSizeInkByte;
+	int CompressedBufferSizeInkByte;
+	int MetaFIFOSizeInKEntries;
+	int ZeroSizeBufferEntries;
+	int COMPBUF_RESERVED_SPACE_64B;
+	int COMPBUF_RESERVED_SPACE_ZS;
+	bool UnboundedRequestEnabled;
+	bool DSC422NativeSupport;
+	bool NoEnoughUrgentLatencyHiding;
+	bool NoEnoughUrgentLatencyHidingPre;
+	int NumberOfStutterBurstsPerFrame;
+	int Z8NumberOfStutterBurstsPerFrame;
+	unsigned int MaximumDSCBitsPerComponent;
+	unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
+#endif
 };
 
 bool CalculateMinAndMaxPrefetchMode(
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
index 5aa714e831dd..fbf71ff0a402 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
@@ -112,6 +112,9 @@ bool dal_hw_factory_init(
 	case DCN_VERSION_3_01:
 	case DCN_VERSION_3_02:
 	case DCN_VERSION_3_03:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case DCN_VERSION_3_1:
+#endif
 		dal_hw_factory_dcn30_init(factory);
 		return true;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
index 199a9dd0e0e3..89794687f6a0 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
@@ -107,6 +107,9 @@ bool dal_hw_translate_init(
 	case DCN_VERSION_3_01:
 	case DCN_VERSION_3_02:
 	case DCN_VERSION_3_03:
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case DCN_VERSION_3_1:
+#endif
 		dal_hw_translate_dcn30_init(translate);
 		return true;
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 81b92f20d5b6..0d1c3260b68e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -338,6 +338,9 @@ union pipe_update_flags {
 		uint32_t scaler : 1;
 		uint32_t viewport : 1;
 		uint32_t plane_changed : 1;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+		uint32_t det_size : 1;
+#endif
 	} bits;
 	uint32_t raw;
 };
@@ -365,6 +368,10 @@ struct pipe_ctx {
 	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
 	struct _vcs_dpi_display_rq_regs_st rq_regs;
 	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	int det_buffer_size_kb;
+	bool unbounded_req;
+#endif
 #endif
 	union pipe_update_flags update_flags;
 	struct dwbc *dwbc;
@@ -415,6 +422,9 @@ struct dcn_bw_output {
 	struct dc_clocks clk;
 	struct dcn_watermark_set watermarks;
 	struct dcn_bw_writeback bw_writeback;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	int compbuf_size_kb;
+#endif
 };
 
 union bw_output {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index bbb054f58fe2..883c3af51022 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -130,6 +130,12 @@ bool dp_is_cr_done(enum dc_lane_count ln_count,
 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
 	union lane_status *dpcd_lane_status);
 
+bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
+	union lane_status *dpcd_lane_status);
+bool dp_is_symbol_locked(enum dc_lane_count ln_count,
+	union lane_status *dpcd_lane_status);
+bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
+
 bool dp_is_max_vs_reached(
 	const struct link_training_settings *lt_settings);
 
@@ -137,6 +143,8 @@ void dp_update_drive_settings(
 	struct link_training_settings *dest,
 	struct link_training_settings src);
 
+uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
+
 enum dpcd_training_patterns
 	dc_dp_training_pattern_to_dpcd_training_pattern(
 	struct dc_link *link,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 5dc8d02b40c3..90dbe26bf954 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -91,6 +91,9 @@ struct clk_limit_table_entry {
 	unsigned int dispclk_mhz;
 	unsigned int dppclk_mhz;
 	unsigned int phyclk_mhz;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	unsigned int wck_ratio;
+#endif
 };
 
 /* This table is contiguous */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 336c80a18175..fc11f8e1ab59 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -29,11 +29,44 @@
 #include "dc_types.h"
 #include "hw_shared.h"
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+enum phyd32clk_clock_source {
+	PHYD32CLKA,
+	PHYD32CLKB,
+	PHYD32CLKC,
+	PHYD32CLKD,
+	PHYD32CLKE,
+	PHYD32CLKF,
+	PHYD32CLKG,
+};
+
+enum physymclk_clock_source {
+	PHYSYMCLK_FORCE_SRC_SYMCLK,    // Select symclk as source of clock which is output to PHY through DCIO.
+	PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
+	PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
+};
+
+enum hdmistreamclk_source {
+	REFCLK,                   // Selects REFCLK as source for hdmistreamclk.
+	DTBCLK0,                  // Selects DTBCLK0 as source for hdmistreamclk.
+};
+
+enum dentist_dispclk_change_mode {
+	DISPCLK_CHANGE_MODE_IMMEDIATE,
+	DISPCLK_CHANGE_MODE_RAMPING,
+};
+#endif
+
 struct dccg {
 	struct dc_context *ctx;
 	const struct dccg_funcs *funcs;
 	int pipe_dppclk_khz[MAX_PIPES];
 	int ref_dppclk;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	int dtbclk_khz[MAX_PIPES];
+	int audio_dtbclk_khz;
+	int ref_dtbclk_khz;
+#endif
 };
 
 struct dccg_funcs {
@@ -43,7 +76,36 @@ struct dccg_funcs {
 	void (*get_dccg_ref_freq)(struct dccg *dccg,
 			unsigned int xtalin_freq_inKhz,
 			unsigned int *dccg_ref_freq_inKhz);
+	void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
+			bool en);
+	void (*otg_add_pixel)(struct dccg *dccg,
+			uint32_t otg_inst);
+	void (*otg_drop_pixel)(struct dccg *dccg,
+			uint32_t otg_inst);
 	void (*dccg_init)(struct dccg *dccg);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+
+	void (*set_physymclk)(
+			struct dccg *dccg,
+			int phy_inst,
+			enum physymclk_clock_source clk_src,
+			bool force_enable);
+
+	void (*set_dtbclk_dto)(
+			struct dccg *dccg,
+			int dtbclk_inst,
+			int req_dtbclk_khz,
+			int num_odm_segments,
+			const struct dc_crtc_timing *timing);
+
+	void (*set_audio_dtbclk_dto)(
+			struct dccg *dccg,
+			uint32_t req_audio_dtbclk_khz);
+
+	void (*set_dispclk_change_mode)(
+			struct dccg *dccg,
+			enum dentist_dispclk_change_mode change_mode);
+#endif
 };
 
 #endif //__DAL_DCCG_H__
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index d9fd28b34f2a..d2611b865695 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -152,6 +152,11 @@ struct hubbub_funcs {
 	void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
 
 	void (*init_watermarks)(struct hubbub *hubbub);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	void (*program_det_size)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_in_kbyte);
+	void (*program_compbuf_size)(struct hubbub *hubbub, unsigned compbuf_size_kb, bool safe_to_increase);
+	void (*init_crb)(struct hubbub *hubbub);
+#endif
 };
 
 struct hubbub {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 80bc99500645..f643fe3ed064 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -127,6 +127,14 @@ struct link_enc_state {
 
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	enum encoder_type_select {
+		ENCODER_TYPE_DIG = 0,
+		ENCODER_TYPE_HDMI_FRL = 1,
+		ENCODER_TYPE_DP_128B132B = 2
+	};
+#endif
+
 struct link_encoder_funcs {
 	void (*read_state)(
 			struct link_encoder *enc, struct link_enc_state *s);
@@ -185,6 +193,12 @@ struct link_encoder_funcs {
 
 	enum signal_type (*get_dig_mode)(
 		struct link_encoder *enc);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	void (*set_dio_phy_mux)(
+		struct link_encoder *enc,
+		enum encoder_type_select sel,
+		uint32_t hpo_inst);
+#endif
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 2e2310f1901a..dd562dcd03b2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -33,6 +33,10 @@
 struct dchub_init_data;
 struct cstate_pstate_watermarks_st {
 	uint32_t cstate_exit_ns;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	uint32_t cstate_exit_z8_ns;
+	uint32_t cstate_enter_plus_exit_z8_ns;
+#endif
 	uint32_t cstate_enter_plus_exit_ns;
 	uint32_t pstate_change_ns;
 };
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 75c77ad9cbfe..640bb432bd6a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -363,6 +363,9 @@ struct mpc_funcs {
 			struct mpc *mpc,
 			int opp_id);
 
+	void (*set_bg_color)(struct mpc *mpc,
+			struct tg_color *bg_color,
+			int mpcc_id);
 };
 
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 9ff68b67780c..8f06e273e703 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -173,6 +173,9 @@ struct timing_generator_funcs {
 
 	bool (*enable_crtc)(struct timing_generator *tg);
 	bool (*disable_crtc)(struct timing_generator *tg);
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	bool (*immediate_disable_crtc)(struct timing_generator *tg);
+#endif
 	bool (*is_counter_moving)(struct timing_generator *tg);
 	void (*get_position)(struct timing_generator *tg,
 				struct crtc_position *position);
@@ -223,6 +226,8 @@ struct timing_generator_funcs {
 	void (*enable_advanced_request)(struct timing_generator *tg,
 					bool enable, const struct dc_crtc_timing *timing);
 	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
+	void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
+	void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
 	void (*set_static_screen_control)(struct timing_generator *tg,
 						uint32_t event_triggers,
 						uint32_t num_frames);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 1d5853c95448..e3ab4e43f673 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -235,6 +235,15 @@ struct hw_sequencer_funcs {
 			enum dc_color_depth color_depth,
 			const struct tg_color *solid_color,
 			int width, int height, int offset);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	void (*z10_restore)(struct dc *dc);
+#endif
+
+	void (*update_visual_confirm_color)(struct dc *dc,
+			struct pipe_ctx *pipe_ctx,
+			struct tg_color *color,
+			int mpcc_id);
 };
 
 void color_space_to_black_color(
@@ -249,4 +258,17 @@ const uint16_t *find_color_matrix(
 		enum dc_color_space color_space,
 		uint32_t *array_size);
 
+void get_surface_visual_confirm_color(
+		const struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
+
+void get_hdr_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
+void get_mpctree_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
+void get_surface_tile_visual_confirm_color(
+		struct pipe_ctx *pipe_ctx,
+		struct tg_color *color);
 #endif /* __DC_HW_SEQUENCER_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
index 36e906bb6bfc..f7f7e4fff0c2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
@@ -127,11 +127,6 @@ struct hwseq_private_funcs {
 			const struct dc_stream_state *stream,
 			struct dc_state *context);
 	bool (*s0i3_golden_init_wa)(struct dc *dc);
-	void (*get_surface_visual_confirm_color)(
-			const struct pipe_ctx *pipe_ctx,
-			struct tg_color *color);
-	void (*get_hdr_visual_confirm_color)(struct pipe_ctx *pipe_ctx,
-			struct tg_color *color);
 	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
 	void (*verify_allow_pstate_change_high)(struct dc *dc);
 	void (*program_pipe)(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index e9fabb85741f..ea4943c5d552 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -118,3 +118,14 @@ AMD_DAL_IRQ_DCN3_03 = $(addprefix $(AMDDALPATH)/dc/irq/dcn303/,$(IRQ_DCN3_03))
 
 AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN3_03)
 endif
+
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+###############################################################################
+# DCN 31
+###############################################################################
+IRQ_DCN31 = irq_service_dcn31.o
+
+AMD_DAL_IRQ_DCN31= $(addprefix $(AMDDALPATH)/dc/irq/dcn31/,$(IRQ_DCN31))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN31)
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
new file mode 100644
index 000000000000..38e0ade60c7b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "include/logger_interface.h"
+#include "../dce110/irq_service_dce110.h"
+
+
+#include "yellow_carp_offset.h"
+#include "dcn/dcn_3_1_2_offset.h"
+#include "dcn/dcn_3_1_2_sh_mask.h"
+
+#include "irq_service_dcn31.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+enum dc_irq_source to_dal_irq_source_dcn31(
+		struct irq_service *irq_service,
+		uint32_t src_id,
+		uint32_t ext_id)
+{
+	switch (src_id) {
+	case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK1;
+	case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK2;
+	case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK3;
+	case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK4;
+	case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK5;
+	case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+		return DC_IRQ_SOURCE_VBLANK6;
+	case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC1_VLINE0;
+	case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC2_VLINE0;
+	case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC3_VLINE0;
+	case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC4_VLINE0;
+	case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC5_VLINE0;
+	case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
+		return DC_IRQ_SOURCE_DC6_VLINE0;
+	case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP1;
+	case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP2;
+	case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP3;
+	case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP4;
+	case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP5;
+	case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+		return DC_IRQ_SOURCE_PFLIP6;
+	case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE1;
+	case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE2;
+	case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE3;
+	case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE4;
+	case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE5;
+	case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
+		return DC_IRQ_SOURCE_VUPDATE6;
+	case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
+		return DC_IRQ_SOURCE_DMCUB_OUTBOX;
+	case DCN_1_0__SRCID__DC_HPD1_INT:
+		/* generic src_id for all HPD and HPDRX interrupts */
+		switch (ext_id) {
+		case DCN_1_0__CTXID__DC_HPD1_INT:
+			return DC_IRQ_SOURCE_HPD1;
+		case DCN_1_0__CTXID__DC_HPD2_INT:
+			return DC_IRQ_SOURCE_HPD2;
+		case DCN_1_0__CTXID__DC_HPD3_INT:
+			return DC_IRQ_SOURCE_HPD3;
+		case DCN_1_0__CTXID__DC_HPD4_INT:
+			return DC_IRQ_SOURCE_HPD4;
+		case DCN_1_0__CTXID__DC_HPD5_INT:
+			return DC_IRQ_SOURCE_HPD5;
+		case DCN_1_0__CTXID__DC_HPD6_INT:
+			return DC_IRQ_SOURCE_HPD6;
+		case DCN_1_0__CTXID__DC_HPD1_RX_INT:
+			return DC_IRQ_SOURCE_HPD1RX;
+		case DCN_1_0__CTXID__DC_HPD2_RX_INT:
+			return DC_IRQ_SOURCE_HPD2RX;
+		case DCN_1_0__CTXID__DC_HPD3_RX_INT:
+			return DC_IRQ_SOURCE_HPD3RX;
+		case DCN_1_0__CTXID__DC_HPD4_RX_INT:
+			return DC_IRQ_SOURCE_HPD4RX;
+		case DCN_1_0__CTXID__DC_HPD5_RX_INT:
+			return DC_IRQ_SOURCE_HPD5RX;
+		case DCN_1_0__CTXID__DC_HPD6_RX_INT:
+			return DC_IRQ_SOURCE_HPD6RX;
+		default:
+			return DC_IRQ_SOURCE_INVALID;
+		}
+		break;
+
+	default:
+		return DC_IRQ_SOURCE_INVALID;
+	}
+}
+
+static bool hpd_ack(
+	struct irq_service *irq_service,
+	const struct irq_source_info *info)
+{
+	uint32_t addr = info->status_reg;
+	uint32_t value = dm_read_reg(irq_service->ctx, addr);
+	uint32_t current_status =
+		get_reg_field_value(
+			value,
+			HPD0_DC_HPD_INT_STATUS,
+			DC_HPD_SENSE_DELAYED);
+
+	dal_irq_service_ack_generic(irq_service, info);
+
+	value = dm_read_reg(irq_service->ctx, info->enable_reg);
+
+	set_reg_field_value(
+		value,
+		current_status ? 0 : 1,
+		HPD0_DC_HPD_INT_CONTROL,
+		DC_HPD_INT_POLARITY);
+
+	dm_write_reg(irq_service->ctx, info->enable_reg, value);
+
+	return true;
+}
+
+static const struct irq_source_info_funcs hpd_irq_info_funcs = {
+	.set = NULL,
+	.ack = hpd_ack
+};
+
+static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs pflip_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vblank_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs outbox_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+static const struct irq_source_info_funcs vline0_irq_info_funcs = {
+	.set = NULL,
+	.ack = NULL
+};
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+/* compile time expand base address. */
+#define BASE(seg) \
+	BASE_INNER(seg)
+
+#define SRI(reg_name, block, id)\
+	BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+			reg ## block ## id ## _ ## reg_name
+
+#define SRI_DMUB(reg_name)\
+	BASE(reg ## reg_name ## _BASE_IDX) + \
+			reg ## reg_name
+
+#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI(reg1, block, reg_num),\
+	.enable_mask = \
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
+		~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI(reg2, block, reg_num),\
+	.ack_mask = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
+
+#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
+	.enable_reg = SRI_DMUB(reg1),\
+	.enable_mask = \
+		reg1 ## __ ## mask1 ## _MASK,\
+	.enable_value = {\
+		reg1 ## __ ## mask1 ## _MASK,\
+		~reg1 ## __ ## mask1 ## _MASK \
+	},\
+	.ack_reg = SRI_DMUB(reg2),\
+	.ack_mask = \
+		reg2 ## __ ## mask2 ## _MASK,\
+	.ack_value = \
+		reg2 ## __ ## mask2 ## _MASK \
+
+#define hpd_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1 + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_irq_info_funcs\
+	}
+
+#define hpd_rx_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
+		IRQ_REG_ENTRY(HPD, reg_num,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
+			DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
+		.status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
+		.funcs = &hpd_rx_irq_info_funcs\
+	}
+#define pflip_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
+		IRQ_REG_ENTRY(HUBPREQ, reg_num,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
+			DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
+		.funcs = &pflip_irq_info_funcs\
+	}
+
+/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
+ * of DCE's DC_IRQ_SOURCE_VUPDATEx.
+ */
+#define vupdate_no_lock_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
+		.funcs = &vupdate_no_lock_irq_info_funcs\
+	}
+
+#define vblank_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
+			OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
+		.funcs = &vblank_irq_info_funcs\
+	}
+
+#define vline0_int_entry(reg_num)\
+	[DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
+		IRQ_REG_ENTRY(OTG, reg_num,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
+			OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
+		.funcs = &vline0_irq_info_funcs\
+	}
+#define dmub_outbox_int_entry()\
+	[DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
+		IRQ_REG_ENTRY_DMUB(\
+			DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
+			DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
+		.funcs = &outbox_irq_info_funcs\
+	}
+
+#define dummy_irq_entry() \
+	{\
+		.funcs = &dummy_irq_info_funcs\
+	}
+
+#define i2c_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
+
+#define dp_sink_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
+
+#define gpio_pad_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
+
+#define dc_underflow_int_entry(reg_num) \
+	[DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
+
+static const struct irq_source_info_funcs dummy_irq_info_funcs = {
+	.set = dal_irq_service_dummy_set,
+	.ack = dal_irq_service_dummy_ack
+};
+
+static const struct irq_source_info
+irq_source_info_dcn31[DAL_IRQ_SOURCES_NUMBER] = {
+	[DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
+	hpd_int_entry(0),
+	hpd_int_entry(1),
+	hpd_int_entry(2),
+	hpd_int_entry(3),
+	hpd_int_entry(4),
+	hpd_rx_int_entry(0),
+	hpd_rx_int_entry(1),
+	hpd_rx_int_entry(2),
+	hpd_rx_int_entry(3),
+	hpd_rx_int_entry(4),
+	i2c_int_entry(1),
+	i2c_int_entry(2),
+	i2c_int_entry(3),
+	i2c_int_entry(4),
+	i2c_int_entry(5),
+	i2c_int_entry(6),
+	dp_sink_int_entry(1),
+	dp_sink_int_entry(2),
+	dp_sink_int_entry(3),
+	dp_sink_int_entry(4),
+	dp_sink_int_entry(5),
+	dp_sink_int_entry(6),
+	[DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
+	pflip_int_entry(0),
+	pflip_int_entry(1),
+	pflip_int_entry(2),
+	pflip_int_entry(3),
+	[DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
+	gpio_pad_int_entry(0),
+	gpio_pad_int_entry(1),
+	gpio_pad_int_entry(2),
+	gpio_pad_int_entry(3),
+	gpio_pad_int_entry(4),
+	gpio_pad_int_entry(5),
+	gpio_pad_int_entry(6),
+	gpio_pad_int_entry(7),
+	gpio_pad_int_entry(8),
+	gpio_pad_int_entry(9),
+	gpio_pad_int_entry(10),
+	gpio_pad_int_entry(11),
+	gpio_pad_int_entry(12),
+	gpio_pad_int_entry(13),
+	gpio_pad_int_entry(14),
+	gpio_pad_int_entry(15),
+	gpio_pad_int_entry(16),
+	gpio_pad_int_entry(17),
+	gpio_pad_int_entry(18),
+	gpio_pad_int_entry(19),
+	gpio_pad_int_entry(20),
+	gpio_pad_int_entry(21),
+	gpio_pad_int_entry(22),
+	gpio_pad_int_entry(23),
+	gpio_pad_int_entry(24),
+	gpio_pad_int_entry(25),
+	gpio_pad_int_entry(26),
+	gpio_pad_int_entry(27),
+	gpio_pad_int_entry(28),
+	gpio_pad_int_entry(29),
+	gpio_pad_int_entry(30),
+	dc_underflow_int_entry(1),
+	dc_underflow_int_entry(2),
+	dc_underflow_int_entry(3),
+	dc_underflow_int_entry(4),
+	dc_underflow_int_entry(5),
+	dc_underflow_int_entry(6),
+	[DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
+	vupdate_no_lock_int_entry(0),
+	vupdate_no_lock_int_entry(1),
+	vupdate_no_lock_int_entry(2),
+	vupdate_no_lock_int_entry(3),
+	vblank_int_entry(0),
+	vblank_int_entry(1),
+	vblank_int_entry(2),
+	vblank_int_entry(3),
+	vline0_int_entry(0),
+	vline0_int_entry(1),
+	vline0_int_entry(2),
+	vline0_int_entry(3),
+	[DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(),
+	[DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(),
+	dmub_outbox_int_entry(),
+};
+
+static const struct irq_service_funcs irq_service_funcs_dcn31 = {
+		.to_dal_irq_source = to_dal_irq_source_dcn31
+};
+
+static void dcn31_irq_construct(
+	struct irq_service *irq_service,
+	struct irq_service_init_data *init_data)
+{
+	dal_irq_service_construct(irq_service, init_data);
+
+	irq_service->info = irq_source_info_dcn31;
+	irq_service->funcs = &irq_service_funcs_dcn31;
+}
+
+struct irq_service *dal_irq_service_dcn31_create(
+	struct irq_service_init_data *init_data)
+{
+	struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
+						  GFP_KERNEL);
+
+	if (!irq_service)
+		return NULL;
+
+	dcn31_irq_construct(irq_service, init_data);
+	return irq_service;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h
new file mode 100644
index 000000000000..d6c845f6bfbf
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+
+#ifndef __DAL_IRQ_SERVICE_DCN31_H__
+#define __DAL_IRQ_SERVICE_DCN31_H__
+
+#include "../irq_service.h"
+
+struct irq_service *dal_irq_service_dcn31_create(
+	struct irq_service_init_data *init_data);
+
+#endif /* __DAL_IRQ_SERVICE_DCN31_H__ */
+#endif /* CONFIG_DRM_AMD_DC_DCN3_1 */
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ed58abc5b3f9..7634e8d94543 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -73,6 +73,9 @@ extern "C" {
 /* Forward declarations */
 struct dmub_srv;
 struct dmub_srv_common_regs;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+struct dmub_srv_dcn31_regs;
+#endif
 
 struct dmcub_trace_buf_entry;
 
@@ -94,6 +97,9 @@ enum dmub_asic {
 	DMUB_ASIC_DCN301,
 	DMUB_ASIC_DCN302,
 	DMUB_ASIC_DCN303,
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	DMUB_ASIC_DCN31,
+#endif
 	DMUB_ASIC_MAX,
 };
 
@@ -232,6 +238,9 @@ struct dmub_srv_hw_params {
 	uint32_t psp_version;
 	bool load_inst_const;
 	bool skip_panel_power_sequence;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	bool disable_z10;
+#endif
 };
 
 /**
@@ -364,6 +373,9 @@ struct dmub_srv {
 
 	/* private: internal use only */
 	const struct dmub_srv_common_regs *regs;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	const struct dmub_srv_dcn31_regs *regs_dcn31;
+#endif
 
 	struct dmub_srv_base_funcs funcs;
 	struct dmub_srv_hw_funcs hw_funcs;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 0b351da48563..ff1f4ec1531e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x992f4893d
+#define DMUB_FW_VERSION_GIT_HASH 0xefd666c1
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 66
+#define DMUB_FW_VERSION_REVISION 69
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
@@ -117,12 +117,21 @@
 /* Maximum number of planes on any ASIC. */
 #define DMUB_MAX_PLANES 6
 
-#define DMUB_MAX_SUBVP_STREAMS 2
-
 /* Trace buffer offset for entry */
 #define TRACE_BUFFER_ENTRY_OFFSET  16
 
 /**
+ *
+ * PSR control version legacy
+ */
+#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
+/**
+ * PSR control version with multi edp support
+ */
+#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
+
+
+/**
  * ABM control version legacy
  */
 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
@@ -337,7 +346,11 @@ union dmub_fw_boot_options {
 		uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
 		uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
 		uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+		uint32_t z10_disable: 1; /**< 1 to disable z10 */
+#else
 		uint32_t reserved_unreleased: 1; /**< reserved for an unreleased feature */
+#endif
 		uint32_t reserved : 25; /**< reserved */
 	} bits; /**< boot bits */
 	uint32_t all; /**< 32-bit access to bits */
@@ -602,6 +615,20 @@ enum dmub_cmd_type {
 	 * Command type used for OUTBOX1 notification enable
 	 */
 	DMUB_CMD__OUTBOX1_ENABLE = 71,
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	/**
+	 * Command type used for all idle optimization commands.
+	 */
+	DMUB_CMD__IDLE_OPT = 72,
+	/**
+	 * Command type used for all clock manager commands.
+	 */
+	DMUB_CMD__CLK_MGR = 73,
+	/**
+	 * Command type used for all panel control commands.
+	 */
+	DMUB_CMD__PANEL_CNTL = 74,
+#endif
 	/**
 	 * Command type used for all VBIOS interface commands.
 	 */
@@ -620,10 +647,6 @@ enum dmub_out_cmd_type {
 	 * Command type used for DP AUX Reply data notification
 	 */
 	DMUB_OUT_CMD__DP_AUX_REPLY = 1,
-	/**
-	 * Command type used for DP HPD event notification
-	 */
-	DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
 };
 
 #pragma pack(push, 1)
@@ -811,6 +834,53 @@ struct dmub_rb_cmd_mall {
 	uint8_t reserved2; /**< Reserved bits */
 };
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+
+/**
+ * enum dmub_cmd_idle_opt_type - Idle optimization command type.
+ */
+enum dmub_cmd_idle_opt_type {
+	/**
+	 * DCN hardware restore.
+	 */
+	DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
+};
+
+/**
+ * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
+ */
+struct dmub_rb_cmd_idle_opt_dcn_restore {
+	struct dmub_cmd_header header; /**< header */
+};
+
+/**
+ * struct dmub_clocks - Clock update notification.
+ */
+struct dmub_clocks {
+	uint32_t dispclk_khz; /**< dispclk kHz */
+	uint32_t dppclk_khz; /**< dppclk kHz */
+	uint32_t dcfclk_khz; /**< dcfclk kHz */
+	uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
+};
+
+/**
+ * enum dmub_cmd_clk_mgr_type - Clock manager commands.
+ */
+enum dmub_cmd_clk_mgr_type {
+	/**
+	 * Notify DMCUB of clock update.
+	 */
+	DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
+};
+
+/**
+ * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
+ */
+struct dmub_rb_cmd_clk_mgr_notify_clocks {
+	struct dmub_cmd_header header; /**< header */
+	struct dmub_clocks clocks; /**< clock data */
+};
+#endif
 /**
  * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
  */
@@ -1315,9 +1385,15 @@ struct dmub_cmd_psr_copy_settings_data {
 	 */
 	uint8_t fec_enable_delay_in100us;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * PSR control version.
 	 */
-	uint8_t pad3[2];
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
 };
 
 /**
@@ -1342,10 +1418,16 @@ struct dmub_cmd_psr_set_level_data {
 	 * 16-bit value dicated by driver that will enable/disable different functionality.
 	 */
 	uint16_t psr_level;
+		/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
 	/**
-	 * Explicit padding to 4 byte boundary.
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
 	 */
-	uint8_t pad[2];
+	uint8_t panel_inst;
 };
 
 /**
@@ -1362,6 +1444,23 @@ struct dmub_rb_cmd_psr_set_level {
 	struct dmub_cmd_psr_set_level_data psr_set_level_data;
 };
 
+struct dmub_rb_cmd_psr_enable_data {
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
+};
+
 /**
  * Definition of a DMUB_CMD__PSR_ENABLE command.
  * PSR enable/disable is controlled using the sub_type.
@@ -1371,6 +1470,8 @@ struct dmub_rb_cmd_psr_enable {
 	 * Command header.
 	 */
 	struct dmub_cmd_header header;
+
+	struct dmub_rb_cmd_psr_enable_data data;
 };
 
 /**
@@ -1381,6 +1482,20 @@ struct dmub_cmd_psr_set_version_data {
 	 * PSR version that FW should implement.
 	 */
 	enum psr_version version;
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
@@ -1397,6 +1512,23 @@ struct dmub_rb_cmd_psr_set_version {
 	struct dmub_cmd_psr_set_version_data psr_set_version_data;
 };
 
+struct dmub_cmd_psr_force_static_data {
+	/**
+	 * PSR control version.
+	 */
+	uint8_t cmd_version;
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which psr_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
+};
+
 /**
  * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
  */
@@ -1405,6 +1537,10 @@ struct dmub_rb_cmd_psr_force_static {
 	 * Command header.
 	 */
 	struct dmub_cmd_header header;
+	/**
+	 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
+	 */
+	struct dmub_cmd_psr_force_static_data psr_force_static_data;
 };
 
 /**
@@ -1479,7 +1615,6 @@ enum hw_lock_client {
 	 * Driver is the client of HW Lock Manager.
 	 */
 	HW_LOCK_CLIENT_DRIVER = 0,
-	HW_LOCK_CLIENT_SUBVP = 3,
 	/**
 	 * Invalid client.
 	 */
@@ -1956,6 +2091,43 @@ struct dmub_rb_cmd_drr_update {
 		struct dmub_optc_state dmub_optc_state_req;
 };
 
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+/**
+ * enum dmub_cmd_panel_cntl_type - Panel control command.
+ */
+enum dmub_cmd_panel_cntl_type {
+	/**
+	 * Initializes embedded panel hardware blocks.
+	 */
+	DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
+	/**
+	 * Queries backlight info for the embedded panel.
+	 */
+	DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
+};
+
+/**
+ * struct dmub_cmd_panel_cntl_data - Panel control data.
+ */
+struct dmub_cmd_panel_cntl_data {
+	uint32_t inst; /**< panel instance */
+	uint32_t current_backlight; /* in/out */
+	uint32_t bl_pwm_cntl; /* in/out */
+	uint32_t bl_pwm_period_cntl; /* in/out */
+	uint32_t bl_pwm_ref_div1; /* in/out */
+	uint8_t is_backlight_on : 1; /* in/out */
+	uint8_t is_powered_on : 1; /* in/out */
+};
+
+/**
+ * struct dmub_rb_cmd_panel_cntl - Panel control command.
+ */
+struct dmub_rb_cmd_panel_cntl {
+	struct dmub_cmd_header header; /**< header */
+	struct dmub_cmd_panel_cntl_data data; /**< payload */
+};
+#endif
+
 /**
  * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
  */
@@ -2053,6 +2225,22 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__MALL command.
 	 */
 	struct dmub_rb_cmd_mall mall;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+	/**
+	 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
+	 */
+	struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
+
+	/**
+	 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
+	 */
+	struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
+
+	/**
+	 * Definition of DMUB_CMD__PANEL_CNTL commands.
+	 */
+	struct dmub_rb_cmd_panel_cntl panel_cntl;
+#endif
 	/**
 	 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
 	 */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile
index 4d9387f53c77..80b9fe225208 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/Makefile
+++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile
@@ -24,6 +24,9 @@ DMUB = dmub_srv.o dmub_srv_stat.o dmub_reg.o dmub_dcn20.o dmub_dcn21.o
 DMUB += dmub_dcn30.o dmub_dcn301.o
 DMUB += dmub_dcn302.o
 DMUB += dmub_dcn303.o
+ifdef CONFIG_DRM_AMD_DC_DCN3_1
+DMUB += dmub_dcn31.o
+endif
 
 AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB))
 
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
new file mode 100644
index 000000000000..8c886ece71f6
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "../dmub_srv.h"
+#include "dmub_reg.h"
+#include "dmub_dcn31.h"
+
+#include "yellow_carp_offset.h"
+#include "dcn/dcn_3_1_2_offset.h"
+#include "dcn/dcn_3_1_2_sh_mask.h"
+
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
+#define CTX dmub
+#define REGS dmub->regs_dcn31
+#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
+
+const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
+#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
+	{ DMUB_DCN31_REGS() },
+#undef DMUB_SR
+
+#define DMUB_SF(reg, field) FD_MASK(reg, field),
+	{ DMUB_DCN31_FIELDS() },
+#undef DMUB_SF
+
+#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
+	{ DMUB_DCN31_FIELDS() },
+#undef DMUB_SF
+};
+
+static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
+					  uint64_t *fb_base,
+					  uint64_t *fb_offset)
+{
+	uint32_t tmp;
+
+	if (dmub->fb_base || dmub->fb_offset) {
+		*fb_base = dmub->fb_base;
+		*fb_offset = dmub->fb_offset;
+		return;
+	}
+
+	REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+	*fb_base = (uint64_t)tmp << 24;
+
+	REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+	*fb_offset = (uint64_t)tmp << 24;
+}
+
+static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
+					     uint64_t fb_base,
+					     uint64_t fb_offset,
+					     union dmub_addr *addr_out)
+{
+	addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
+}
+
+void dmub_dcn31_reset(struct dmub_srv *dmub)
+{
+	union dmub_gpint_data_register cmd;
+	const uint32_t timeout = 30;
+	uint32_t in_reset, scratch, i;
+
+	REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
+
+	if (in_reset == 0) {
+		cmd.bits.status = 1;
+		cmd.bits.command_code = DMUB_GPINT__STOP_FW;
+		cmd.bits.param = 0;
+
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/**
+		 * Timeout covers both the ACK and the wait
+		 * for remaining work to finish.
+		 *
+		 * This is mostly bound by the PHY disable sequence.
+		 * Each register check will be greater than 1us, so
+		 * don't bother using udelay.
+		 */
+
+		for (i = 0; i < timeout; ++i) {
+			if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
+				break;
+		}
+
+		for (i = 0; i < timeout; ++i) {
+			scratch = dmub->hw_funcs.get_gpint_response(dmub);
+			if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
+				break;
+		}
+
+		/* Clear the GPINT command manually so we don't reset again. */
+		cmd.all = 0;
+		dmub->hw_funcs.set_gpint(dmub, cmd);
+
+		/* Force reset in case we timed out, DMCUB is likely hung. */
+	}
+
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
+	REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
+	REG_WRITE(DMCUB_INBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_INBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
+	REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
+	REG_WRITE(DMCUB_SCRATCH0, 0);
+}
+
+void dmub_dcn31_reset_release(struct dmub_srv *dmub)
+{
+	REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
+	REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
+	REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
+	REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
+}
+
+void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1)
+{
+	union dmub_addr offset;
+	uint64_t fb_base, fb_offset;
+
+	dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset);
+
+	REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
+
+	dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
+	REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
+		  DMCUB_REGION3_CW0_ENABLE, 1);
+
+	dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
+
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
+	REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
+		  DMCUB_REGION3_CW1_ENABLE, 1);
+
+	REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
+		     0x20);
+}
+
+void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
+			      const struct dmub_window *cw2,
+			      const struct dmub_window *cw3,
+			      const struct dmub_window *cw4,
+			      const struct dmub_window *cw5,
+			      const struct dmub_window *cw6)
+{
+	union dmub_addr offset;
+
+	offset = cw3->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
+	REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
+		  DMCUB_REGION3_CW3_ENABLE, 1);
+
+	offset = cw4->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
+	REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
+		  DMCUB_REGION3_CW4_ENABLE, 1);
+
+	offset = cw5->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
+	REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
+		  DMCUB_REGION3_CW5_ENABLE, 1);
+
+	REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
+	REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
+		  DMCUB_REGION5_TOP_ADDRESS,
+		  cw5->region.top - cw5->region.base - 1,
+		  DMCUB_REGION5_ENABLE, 1);
+
+	offset = cw6->offset;
+
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
+	REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
+	REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
+	REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
+		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
+		  DMCUB_REGION3_CW6_ENABLE, 1);
+}
+
+void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *inbox1)
+{
+	REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
+	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
+}
+
+uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_INBOX1_RPTR);
+}
+
+void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
+{
+	REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
+}
+
+void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox1)
+{
+	REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
+	REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
+}
+
+uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)
+{
+	/**
+	 * outbox1 wptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	return REG_READ(DMCUB_OUTBOX1_WPTR);
+}
+
+void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	/**
+	 * outbox1 rptr register is accessed without locks (dal & dc)
+	 * and to be called only by dmub_srv_stat_get_notification()
+	 */
+	REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
+}
+
+bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)
+{
+	uint32_t is_hw_init;
+
+	REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
+
+	return is_hw_init != 0;
+}
+
+bool dmub_dcn31_is_supported(struct dmub_srv *dmub)
+{
+	uint32_t supported = 0;
+
+	REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
+
+	return supported;
+}
+
+void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
+			  union dmub_gpint_data_register reg)
+{
+	REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
+}
+
+bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
+			       union dmub_gpint_data_register reg)
+{
+	union dmub_gpint_data_register test;
+
+	reg.bits.status = 0;
+	test.all = REG_READ(DMCUB_GPINT_DATAIN1);
+
+	return test.all == reg.all;
+}
+
+uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_SCRATCH7);
+}
+
+union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_status status;
+
+	status.all = REG_READ(DMCUB_SCRATCH0);
+	return status;
+}
+
+void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
+{
+	union dmub_fw_boot_options boot_options = {0};
+
+	boot_options.bits.z10_disable = params->disable_z10;
+
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
+{
+	union dmub_fw_boot_options boot_options;
+	boot_options.all = REG_READ(DMCUB_SCRATCH14);
+	boot_options.bits.skip_phy_init_panel_sequence = skip;
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox0)
+{
+	REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
+
+	REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
+}
+
+uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_OUTBOX0_WPTR);
+}
+
+void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
+{
+	REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
+}
+
+uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)
+{
+	return REG_READ(DMCUB_TIMER_CURRENT);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
new file mode 100644
index 000000000000..2829c3e9a310
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef _DMUB_DCN31_H_
+#define _DMUB_DCN31_H_
+
+#include "dmub_dcn20.h"
+
+struct dmub_srv;
+
+/* DCN31 register definitions. */
+
+#define DMUB_DCN31_REGS() \
+	DMUB_SR(DMCUB_CNTL) \
+	DMUB_SR(DMCUB_CNTL2) \
+	DMUB_SR(DMCUB_SEC_CNTL) \
+	DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_INBOX1_SIZE) \
+	DMUB_SR(DMCUB_INBOX1_RPTR) \
+	DMUB_SR(DMCUB_INBOX1_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX0_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX0_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX0_WPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_OUTBOX1_SIZE) \
+	DMUB_SR(DMCUB_OUTBOX1_RPTR) \
+	DMUB_SR(DMCUB_OUTBOX1_WPTR) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
+	DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION4_OFFSET) \
+	DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_REGION5_OFFSET) \
+	DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
+	DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SR(DMCUB_SCRATCH0) \
+	DMUB_SR(DMCUB_SCRATCH1) \
+	DMUB_SR(DMCUB_SCRATCH2) \
+	DMUB_SR(DMCUB_SCRATCH3) \
+	DMUB_SR(DMCUB_SCRATCH4) \
+	DMUB_SR(DMCUB_SCRATCH5) \
+	DMUB_SR(DMCUB_SCRATCH6) \
+	DMUB_SR(DMCUB_SCRATCH7) \
+	DMUB_SR(DMCUB_SCRATCH8) \
+	DMUB_SR(DMCUB_SCRATCH9) \
+	DMUB_SR(DMCUB_SCRATCH10) \
+	DMUB_SR(DMCUB_SCRATCH11) \
+	DMUB_SR(DMCUB_SCRATCH12) \
+	DMUB_SR(DMCUB_SCRATCH13) \
+	DMUB_SR(DMCUB_SCRATCH14) \
+	DMUB_SR(DMCUB_SCRATCH15) \
+	DMUB_SR(DMCUB_GPINT_DATAIN1) \
+	DMUB_SR(CC_DC_PIPE_DIS) \
+	DMUB_SR(MMHUBBUB_SOFT_RESET) \
+	DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+	DMUB_SR(DCN_VM_FB_OFFSET) \
+	DMUB_SR(DMCUB_TIMER_CURRENT)
+
+#define DMUB_DCN31_FIELDS() \
+	DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
+	DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
+	DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
+	DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
+	DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
+	DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
+	DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+	DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+	DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
+
+struct dmub_srv_dcn31_reg_offset {
+#define DMUB_SR(reg) uint32_t reg;
+	DMUB_DCN31_REGS()
+#undef DMUB_SR
+};
+
+struct dmub_srv_dcn31_reg_shift {
+#define DMUB_SF(reg, field) uint8_t reg##__##field;
+	DMUB_DCN31_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn31_reg_mask {
+#define DMUB_SF(reg, field) uint32_t reg##__##field;
+	DMUB_DCN31_FIELDS()
+#undef DMUB_SF
+};
+
+struct dmub_srv_dcn31_regs {
+	const struct dmub_srv_dcn31_reg_offset offset;
+	const struct dmub_srv_dcn31_reg_mask mask;
+	const struct dmub_srv_dcn31_reg_shift shift;
+};
+
+extern const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs;
+
+/* Hardware functions. */
+
+
+void dmub_dcn31_init(struct dmub_srv *dmub);
+
+void dmub_dcn31_reset(struct dmub_srv *dmub);
+
+void dmub_dcn31_reset_release(struct dmub_srv *dmub);
+
+void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
+			      const struct dmub_window *cw0,
+			      const struct dmub_window *cw1);
+
+void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
+			      const struct dmub_window *cw2,
+			      const struct dmub_window *cw3,
+			      const struct dmub_window *cw4,
+			      const struct dmub_window *cw5,
+			      const struct dmub_window *cw6);
+
+void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *inbox1);
+
+uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
+
+void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox1);
+
+uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);
+
+bool dmub_dcn31_is_supported(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
+			  union dmub_gpint_data_register reg);
+
+bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
+			       union dmub_gpint_data_register reg);
+
+uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);
+
+void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
+
+void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
+
+union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);
+
+void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
+			      const struct dmub_region *outbox0);
+
+uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);
+
+void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
+
+uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);
+
+#endif /* _DMUB_DCN31_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index f3f00d36e973..681500f42c91 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -31,6 +31,9 @@
 #include "dmub_dcn301.h"
 #include "dmub_dcn302.h"
 #include "dmub_dcn303.h"
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+#include "dmub_dcn31.h"
+#endif
 #include "os_types.h"
 /*
  * Note: the DMUB service is standalone. No additional headers should be
@@ -203,6 +206,40 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 			funcs->setup_windows = dmub_dcn30_setup_windows;
 		}
 		break;
+#ifdef CONFIG_DRM_AMD_DC_DCN3_1
+
+	case DMUB_ASIC_DCN31:
+		funcs->reset = dmub_dcn31_reset;
+		funcs->reset_release = dmub_dcn31_reset_release;
+		funcs->backdoor_load = dmub_dcn31_backdoor_load;
+		funcs->setup_windows = dmub_dcn31_setup_windows;
+		funcs->setup_mailbox = dmub_dcn31_setup_mailbox;
+		funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr;
+		funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr;
+		funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox;
+		funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr;
+		funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr;
+		funcs->is_supported = dmub_dcn31_is_supported;
+		funcs->is_hw_init = dmub_dcn31_is_hw_init;
+		funcs->set_gpint = dmub_dcn31_set_gpint;
+		funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked;
+		funcs->get_gpint_response = dmub_dcn31_get_gpint_response;
+		funcs->get_fw_status = dmub_dcn31_get_fw_boot_status;
+		funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options;
+		funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence;
+		//outbox0 call stacks
+		funcs->setup_outbox0 = dmub_dcn31_setup_outbox0;
+		funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr;
+		funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr;
+
+		if (asic == DMUB_ASIC_DCN31) {
+			dmub->regs_dcn31 = &dmub_srv_dcn31_regs;
+		}
+
+		funcs->get_current_time = dmub_dcn31_get_current_time;
+
+		break;
+#endif
 
 	default:
 		return false;
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index cb35eae29ca0..d615a8e00f8c 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -224,6 +224,19 @@ enum {
 #define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
 #endif
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+#define FAMILY_YELLOW_CARP                     146
+
+#define YELLOW_CARP_A0 0x01
+#define YELLOW_CARP_B0 0x02		// TODO: DCN31 - update with correct B0 ID
+#define YELLOW_CARP_UNKNOWN 0xFF
+
+#ifndef ASICREV_IS_YELLOW_CARP
+#define ASICREV_IS_YELLOW_CARP(eChipRev) ((eChipRev >= YELLOW_CARP_A0) && (eChipRev < YELLOW_CARP_UNKNOWN))
+#endif
+#endif
+
+
 /*
  * ASIC chip ID
  */
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 85aed509c01f..59453ced9ece 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -55,6 +55,9 @@ enum dce_version {
 	DCN_VERSION_3_01,
 	DCN_VERSION_3_02,
 	DCN_VERSION_3_03,
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	DCN_VERSION_3_1,
+#endif
 	DCN_VERSION_MAX
 };
 
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
index b0306ed6d6b4..70cb230d8f56 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp2_transition.c
@@ -564,7 +564,7 @@ enum mod_hdcp_status mod_hdcp_hdcp2_dp_transition(struct mod_hdcp *hdcp,
 	case D2_A5_AUTHENTICATED:
 		if (input->rxstatus_read == FAIL ||
 				input->reauth_request_check == FAIL) {
-			fail_and_restart_in_ms(0, &status, output);
+			fail_and_restart_in_ms(100, &status, output);
 			break;
 		} else if (input->link_integrity_check_dp == FAIL) {
 			if (hdcp->connection.hdcp2_retry_count >= 1)
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
index ee5230ccf3c4..62dd89cf70bb 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_log.c
@@ -172,6 +172,10 @@ char *mod_hdcp_status_to_str(int32_t status)
 		return "MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE";
 	case MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE:
 		return "MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE";
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	case MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE:
+		return "MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE";
+#endif
 	default:
 		return "MOD_HDCP_STATUS_UNKNOWN";
 	}
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
index 06910d2fd57a..fc88fe249a50 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
@@ -44,11 +44,16 @@ static void hdcp2_message_init(struct mod_hdcp *hdcp,
 	in->process.msg3_desc.msg_id = TA_HDCP_HDCP2_MSG_ID__NULL_MESSAGE;
 	in->process.msg3_desc.msg_size = 0;
 }
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v2(
+		struct mod_hdcp *hdcp, uint8_t index)
+#else
 enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
 		struct mod_hdcp *hdcp, uint8_t index)
- {
- 	struct psp_context *psp = hdcp->config.psp.handle;
- 	struct ta_dtm_shared_memory *dtm_cmd;
+#endif
+{
+	struct psp_context *psp = hdcp->config.psp.handle;
+	struct ta_dtm_shared_memory *dtm_cmd;
 	struct mod_hdcp_display *display =
 			get_active_display_at_index(hdcp, index);
 	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
@@ -79,8 +84,66 @@ enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
 	mutex_unlock(&psp->dtm_context.mutex);
 	return status;
 }
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+static enum mod_hdcp_status mod_hdcp_remove_display_from_topology_v3(
+		struct mod_hdcp *hdcp, uint8_t index)
+{
+	struct psp_context *psp = hdcp->config.psp.handle;
+	struct ta_dtm_shared_memory *dtm_cmd;
+	struct mod_hdcp_display *display =
+		get_active_display_at_index(hdcp, index);
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
+
+	if (!display || !is_display_active(display))
+		return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
+
+	mutex_lock(&psp->dtm_context.mutex);
+
+	memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
+
+	dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3;
+	dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;
+	dtm_cmd->dtm_in_message.topology_update_v3.is_active = 0;
+	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
+
+	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
+
+	if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
+		status = mod_hdcp_remove_display_from_topology_v2(hdcp, index);
+		if (status != MOD_HDCP_STATUS_SUCCESS)
+			display->state = MOD_HDCP_DISPLAY_INACTIVE;
+	} else {
+		display->state = MOD_HDCP_DISPLAY_ACTIVE;
+		HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index);
+	}
+
+	mutex_unlock(&psp->dtm_context.mutex);
+
+	return status;
+}
+
+enum mod_hdcp_status mod_hdcp_remove_display_from_topology(
+		struct mod_hdcp *hdcp, uint8_t index)
+{
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_UPDATE_TOPOLOGY_FAILURE;
+
+	if (hdcp->config.psp.caps.dtm_v3_supported)
+		status = mod_hdcp_remove_display_from_topology_v3(hdcp, index);
+	else
+		status = mod_hdcp_remove_display_from_topology_v2(hdcp, index);
+
+	return status;
+}
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v2(
+		struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
+#else
 enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
 					       struct mod_hdcp_display *display)
+#endif
 {
 	struct psp_context *psp = hdcp->config.psp.handle;
 	struct ta_dtm_shared_memory *dtm_cmd;
@@ -126,6 +189,72 @@ enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
 	return status;
 }
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+static enum mod_hdcp_status mod_hdcp_add_display_to_topology_v3(
+		struct mod_hdcp *hdcp, struct mod_hdcp_display *display)
+{
+	struct psp_context *psp = hdcp->config.psp.handle;
+	struct ta_dtm_shared_memory *dtm_cmd;
+	struct mod_hdcp_link *link = &hdcp->connection.link;
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+	if (!psp->dtm_context.dtm_initialized) {
+		DRM_INFO("Failed to add display topology, DTM TA is not initialized.");
+		display->state = MOD_HDCP_DISPLAY_INACTIVE;
+		return MOD_HDCP_STATUS_FAILURE;
+	}
+
+	dtm_cmd = (struct ta_dtm_shared_memory *)psp->dtm_context.dtm_shared_buf;
+
+	mutex_lock(&psp->dtm_context.mutex);
+	memset(dtm_cmd, 0, sizeof(struct ta_dtm_shared_memory));
+
+	dtm_cmd->cmd_id = TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3;
+	dtm_cmd->dtm_in_message.topology_update_v3.display_handle = display->index;
+	dtm_cmd->dtm_in_message.topology_update_v3.is_active = 1;
+	dtm_cmd->dtm_in_message.topology_update_v3.controller = display->controller;
+	dtm_cmd->dtm_in_message.topology_update_v3.ddc_line = link->ddc_line;
+	dtm_cmd->dtm_in_message.topology_update_v3.link_enc = link->link_enc_idx;
+	dtm_cmd->dtm_in_message.topology_update_v3.stream_enc = display->stream_enc_idx;
+	if (is_dp_hdcp(hdcp))
+		dtm_cmd->dtm_in_message.topology_update_v3.is_assr = link->dp.assr_enabled;
+
+	dtm_cmd->dtm_in_message.topology_update_v3.dp_mst_vcid = display->vc_id;
+	dtm_cmd->dtm_in_message.topology_update_v3.max_hdcp_supported_version =
+			TA_DTM_HDCP_VERSION_MAX_SUPPORTED__2_3;
+	dtm_cmd->dtm_in_message.topology_update_v3.encoder_type = TA_DTM_ENCODER_TYPE__DIG;
+	dtm_cmd->dtm_status = TA_DTM_STATUS__GENERIC_FAILURE;
+	dtm_cmd->dtm_in_message.topology_update_v3.phy_id = link->phy_idx;
+	dtm_cmd->dtm_in_message.topology_update_v3.link_hdcp_cap = link->hdcp_supported_informational;
+
+	psp_dtm_invoke(psp, dtm_cmd->cmd_id);
+
+	if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) {
+		status = mod_hdcp_add_display_to_topology_v2(hdcp, display);
+		if (status != MOD_HDCP_STATUS_SUCCESS)
+			display->state = MOD_HDCP_DISPLAY_INACTIVE;
+	} else {
+		HDCP_TOP_ADD_DISPLAY_TRACE(hdcp, display->index);
+	}
+
+	mutex_unlock(&psp->dtm_context.mutex);
+
+	return status;
+}
+
+enum mod_hdcp_status mod_hdcp_add_display_to_topology(struct mod_hdcp *hdcp,
+					       struct mod_hdcp_display *display)
+{
+	enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
+	if (hdcp->config.psp.caps.dtm_v3_supported)
+		status = mod_hdcp_add_display_to_topology_v3(hdcp, display);
+	else
+		status = mod_hdcp_add_display_to_topology_v2(hdcp, display);
+
+	return status;
+}
+#endif
 enum mod_hdcp_status mod_hdcp_hdcp1_create_session(struct mod_hdcp *hdcp)
 {
 
diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
index 1a663dbbf810..b0b2544eaa9d 100644
--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
+++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.h
@@ -44,7 +44,12 @@ enum bgd_security_hdcp2_content_type {
 enum ta_dtm_command {
 	TA_DTM_COMMAND__UNUSED_1 = 1,
 	TA_DTM_COMMAND__TOPOLOGY_UPDATE_V2,
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE,
+	TA_DTM_COMMAND__TOPOLOGY_UPDATE_V3
+#else
 	TA_DTM_COMMAND__TOPOLOGY_ASSR_ENABLE
+#endif
 };
 
 /* DTM related enumerations */
@@ -86,6 +91,33 @@ struct ta_dtm_topology_update_input_v2 {
 	uint32_t max_hdcp_supported_version;
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+/* For security reason/HW may change value, these encoder type enum values are not HW register values */
+/* Security code will check real HW register values and these SW enum values */
+enum ta_dtm_encoder_type {
+	TA_DTM_ENCODER_TYPE__INVALID    = 0,
+	TA_DTM_ENCODER_TYPE__DIG        = 0x10
+};
+
+struct ta_dtm_topology_update_input_v3 {
+	/* display handle is unique across the driver and is used to identify a display */
+	/* for all security interfaces which reference displays such as HDCP */
+	/* link_hdcp_cap means link is HDCP-capable for audio HDCP capable property(informational), not for other logic(e.g. Crossbar) */
+	uint32_t display_handle;
+	uint32_t is_active;
+	uint32_t is_miracast;
+	uint32_t controller;
+	uint32_t ddc_line;
+	uint32_t link_enc;
+	uint32_t stream_enc;
+	uint32_t dp_mst_vcid;
+	uint32_t is_assr;
+	uint32_t max_hdcp_supported_version;
+	enum ta_dtm_encoder_type encoder_type;
+	uint32_t phy_id;
+	uint32_t link_hdcp_cap;
+};
+#endif
 struct ta_dtm_topology_assr_enable {
 	uint32_t display_topology_dig_be_index;
 };
@@ -99,6 +131,9 @@ struct ta_dtm_topology_assr_enable {
 union ta_dtm_cmd_input {
 	struct ta_dtm_topology_update_input_v2 topology_update_v2;
 	struct ta_dtm_topology_assr_enable topology_assr_enable;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	struct ta_dtm_topology_update_input_v3 topology_update_v3;
+#endif
 };
 
 union ta_dtm_cmd_output {
@@ -278,6 +313,9 @@ enum ta_hdcp2_version {
 	TA_HDCP2_VERSION_UNKNOWN = 0,
 	TA_HDCP2_VERSION_2_0 = 20,
 	TA_HDCP2_VERSION_2_1 = 21,
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	TA_HDCP2_VERSION_2_3 = 23,
+#endif
 	TA_HDCP2_VERSION_2_2 = 22
 };
 
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
index acbeada5215b..2197c269e0a7 100644
--- a/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_hdcp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 Advanced Micro Devices, Inc.
+ * Copyright 2018 Advanced Micro Devices, Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -97,6 +97,9 @@ enum mod_hdcp_status {
 	MOD_HDCP_STATUS_HDCP2_REAUTH_REQUEST,
 	MOD_HDCP_STATUS_HDCP2_REAUTH_LINK_INTEGRITY_FAILURE,
 	MOD_HDCP_STATUS_HDCP2_DEVICE_COUNT_MISMATCH_FAILURE,
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	MOD_HDCP_STATUS_UNSUPPORTED_PSP_VER_FAILURE,
+#endif
 };
 
 struct mod_hdcp_displayport {
@@ -120,6 +123,13 @@ enum mod_hdcp_display_state {
 	MOD_HDCP_DISPLAY_ENCRYPTION_ENABLED
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+struct mod_hdcp_psp_caps {
+	uint8_t dtm_v3_supported;
+	uint8_t opm_state_query_supported;
+};
+
+#endif
 enum mod_hdcp_display_disable_option {
 	MOD_HDCP_DISPLAY_NOT_DISABLE = 0,
 	MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION,
@@ -152,6 +162,9 @@ struct mod_hdcp_ddc {
 struct mod_hdcp_psp {
 	void *handle;
 	void *funcs;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	struct mod_hdcp_psp_caps caps;
+#endif
 };
 
 struct mod_hdcp_display_adjustment {
@@ -227,6 +240,9 @@ struct mod_hdcp_display {
 	uint8_t index;
 	uint8_t controller;
 	uint8_t dig_fe;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	uint8_t stream_enc_idx;
+#endif
 	union {
 		uint8_t vc_id;
 	};
@@ -239,6 +255,11 @@ struct mod_hdcp_link {
 	enum mod_hdcp_operation_mode mode;
 	uint8_t dig_be;
 	uint8_t ddc_line;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_1)
+	uint8_t link_enc_idx;
+	uint8_t phy_idx;
+	uint8_t hdcp_supported_informational;
+#endif
 	union {
 		struct mod_hdcp_displayport dp;
 		struct mod_hdcp_hdmi hdmi;
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
new file mode 100644
index 000000000000..312c50ea30f3
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
@@ -0,0 +1,15083 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_1_2_OFFSET_HEADER
+#define _dcn_3_1_2_OFFSET_HEADER
+
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x1300000
+#define regAZCONTROLLER0_GLOBAL_CAPABILITIES                                                            0x4b7000
+#define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX                                                   3
+#define regAZCONTROLLER0_MINOR_VERSION                                                                  0x4b7000
+#define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX                                                         3
+#define regAZCONTROLLER0_MAJOR_VERSION                                                                  0x4b7000
+#define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX                                                         3
+#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY                                                      0x4b7001
+#define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                             3
+#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY                                                       0x4b7001
+#define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                              3
+#define regAZCONTROLLER0_GLOBAL_CONTROL                                                                 0x4b7002
+#define regAZCONTROLLER0_GLOBAL_CONTROL_BASE_IDX                                                        3
+#define regAZCONTROLLER0_WAKE_ENABLE                                                                    0x4b7003
+#define regAZCONTROLLER0_WAKE_ENABLE_BASE_IDX                                                           3
+#define regAZCONTROLLER0_STATE_CHANGE_STATUS                                                            0x4b7003
+#define regAZCONTROLLER0_STATE_CHANGE_STATUS_BASE_IDX                                                   3
+#define regAZCONTROLLER0_GLOBAL_STATUS                                                                  0x4b7004
+#define regAZCONTROLLER0_GLOBAL_STATUS_BASE_IDX                                                         3
+#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY                                               0x4b7006
+#define regAZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                      3
+#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY                                                0x4b7006
+#define regAZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX                                       3
+#define regAZCONTROLLER0_INTERRUPT_CONTROL                                                              0x4b7008
+#define regAZCONTROLLER0_INTERRUPT_CONTROL_BASE_IDX                                                     3
+#define regAZCONTROLLER0_INTERRUPT_STATUS                                                               0x4b7009
+#define regAZCONTROLLER0_INTERRUPT_STATUS_BASE_IDX                                                      3
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER                                                             0x4b700c
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_BASE_IDX                                                    3
+#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION                                                         0x4b700e
+#define regAZCONTROLLER0_STREAM_SYNCHRONIZATION_BASE_IDX                                                3
+#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS                                                        0x4b7010
+#define regAZCONTROLLER0_CORB_LOWER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS                                                        0x4b7011
+#define regAZCONTROLLER0_CORB_UPPER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_CORB_WRITE_POINTER                                                             0x4b7012
+#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX                                                    3
+#define regAZCONTROLLER0_CORB_READ_POINTER                                                              0x4b7012
+#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX                                                     3
+#define regAZCONTROLLER0_CORB_CONTROL                                                                   0x4b7013
+#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX                                                          3
+#define regAZCONTROLLER0_CORB_STATUS                                                                    0x4b7013
+#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX                                                           3
+#define regAZCONTROLLER0_CORB_SIZE                                                                      0x4b7013
+#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX                                                             3
+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS                                                        0x4b7014
+#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS                                                        0x4b7015
+#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               3
+#define regAZCONTROLLER0_RIRB_WRITE_POINTER                                                             0x4b7016
+#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX                                                    3
+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT                                                       0x4b7016
+#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              3
+#define regAZCONTROLLER0_RIRB_CONTROL                                                                   0x4b7017
+#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX                                                          3
+#define regAZCONTROLLER0_RIRB_STATUS                                                                    0x4b7017
+#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX                                                           3
+#define regAZCONTROLLER0_RIRB_SIZE                                                                      0x4b7017
+#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX                                                             3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x4b7018
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x4b7018
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x4b7018
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              3
+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x4b7019
+#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    3
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS                                                       0x4b701a
+#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              3
+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x4b701c
+#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       3
+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x4b701d
+#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       3
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS                                                       0x4b780c
+#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              3
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x1300000
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x4b7018
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      3
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x4b7018
+#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     3
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x1300000
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x4b7018
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  3
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x4b7018
+#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 3
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
+// base address: 0x48
+#define regVGA_MEM_WRITE_PAGE_ADDR                                                                      0x0000
+#define regVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX                                                             0
+#define regVGA_MEM_READ_PAGE_ADDR                                                                       0x0001
+#define regVGA_MEM_READ_PAGE_ADDR_BASE_IDX                                                              0
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
+// base address: 0x3b4
+#define regCRTC8_IDX                                                                                    0x002d
+#define regCRTC8_IDX_BASE_IDX                                                                           1
+#define regCRTC8_DATA                                                                                   0x002d
+#define regCRTC8_DATA_BASE_IDX                                                                          1
+#define regGENFC_WT                                                                                     0x002e
+#define regGENFC_WT_BASE_IDX                                                                            1
+#define regGENS1                                                                                        0x002e
+#define regGENS1_BASE_IDX                                                                               1
+#define regATTRDW                                                                                       0x0030
+#define regATTRDW_BASE_IDX                                                                              1
+#define regATTRX                                                                                        0x0030
+#define regATTRX_BASE_IDX                                                                               1
+#define regATTRDR                                                                                       0x0030
+#define regATTRDR_BASE_IDX                                                                              1
+#define regGENMO_WT                                                                                     0x0030
+#define regGENMO_WT_BASE_IDX                                                                            1
+#define regGENS0                                                                                        0x0030
+#define regGENS0_BASE_IDX                                                                               1
+#define regGENENB                                                                                       0x0030
+#define regSEQ8_IDX                                                                                     0x0031
+#define regSEQ8_IDX_BASE_IDX                                                                            1
+#define regSEQ8_DATA                                                                                    0x0031
+#define regSEQ8_DATA_BASE_IDX                                                                           1
+#define regDAC_MASK                                                                                     0x0031
+#define regDAC_MASK_BASE_IDX                                                                            1
+#define regDAC_R_INDEX                                                                                  0x0031
+#define regDAC_R_INDEX_BASE_IDX                                                                         1
+#define regDAC_W_INDEX                                                                                  0x0032
+#define regDAC_W_INDEX_BASE_IDX                                                                         1
+#define regDAC_DATA                                                                                     0x0032
+#define regDAC_DATA_BASE_IDX                                                                            1
+#define regGENFC_RD                                                                                     0x0032
+#define regGENFC_RD_BASE_IDX                                                                            1
+#define regGENMO_RD                                                                                     0x0033
+#define regGENMO_RD_BASE_IDX                                                                            1
+#define regGRPH8_IDX                                                                                    0x0033
+#define regGRPH8_IDX_BASE_IDX                                                                           1
+#define regGRPH8_DATA                                                                                   0x0033
+#define regGRPH8_DATA_BASE_IDX                                                                          1
+#define regCRTC8_IDX_1                                                                                  0x0035
+#define regCRTC8_IDX_1_BASE_IDX                                                                         1
+#define regCRTC8_DATA_1                                                                                 0x0035
+#define regCRTC8_DATA_1_BASE_IDX                                                                        1
+#define regGENFC_WT_1                                                                                   0x0036
+#define regGENFC_WT_1_BASE_IDX                                                                          1
+#define regGENS1_1                                                                                      0x0036
+#define regGENS1_1_BASE_IDX                                                                             1
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+// base address: 0x0
+#define regAZCONTROLLER1_CORB_WRITE_POINTER                                                             0x0000
+#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX                                                    0
+#define regAZCONTROLLER1_CORB_READ_POINTER                                                              0x0000
+#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX                                                     0
+#define regAZCONTROLLER1_CORB_CONTROL                                                                   0x0001
+#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX                                                          0
+#define regAZCONTROLLER1_CORB_STATUS                                                                    0x0001
+#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX                                                           0
+#define regAZCONTROLLER1_CORB_SIZE                                                                      0x0001
+#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX                                                             0
+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS                                                        0x0002
+#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX                                               0
+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS                                                        0x0003
+#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX                                               0
+#define regAZCONTROLLER1_RIRB_WRITE_POINTER                                                             0x0004
+#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX                                                    0
+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT                                                       0x0004
+#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX                                              0
+#define regAZCONTROLLER1_RIRB_CONTROL                                                                   0x0005
+#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX                                                          0
+#define regAZCONTROLLER1_RIRB_STATUS                                                                    0x0005
+#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX                                                           0
+#define regAZCONTROLLER1_RIRB_SIZE                                                                      0x0005
+#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX                                                             0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE                                             0x0006
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX                                    0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                                        0x0006
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                               0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                                       0x0006
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                              0
+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE                                             0x0007
+#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX                                    0
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS                                                       0x0008
+#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX                                              0
+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS                                                0x000a
+#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX                                       0
+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS                                                0x000b
+#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX                                       0
+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS                                                       0x074c
+#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX                                              1
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+// base address: 0x0
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA                               0x0006
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX                      0
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX                              0x0006
+#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX                     0
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+// base address: 0x0
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA                           0x0006
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX                  0
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX                          0x0006
+#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX                 0
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+// base address: 0x0
+#define regDENTIST_DISPCLK_CNTL                                                                         0x0064
+#define regDENTIST_DISPCLK_CNTL_BASE_IDX                                                                1
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+// base address: 0x0
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL                                                                   0x0040
+#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL                                                                   0x0041
+#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL                                                                   0x0042
+#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL                                                                   0x0043
+#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDP_DTO_DBUF_EN                                                                               0x0044
+#define regDP_DTO_DBUF_EN_BASE_IDX                                                                      1
+#define regDPREFCLK_CGTT_BLK_CTRL_REG                                                                   0x0048
+#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                          1
+#define regDCCG_GATE_DISABLE_CNTL4                                                                      0x0049
+#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX                                                             1
+#define regDPSTREAMCLK_CNTL                                                                             0x004a
+#define regDPSTREAMCLK_CNTL_BASE_IDX                                                                    1
+#define regREFCLK_CGTT_BLK_CTRL_REG                                                                     0x004b
+#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL                                                                   0x004c
+#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX                                                          1
+#define regDCCG_PERFMON_CNTL2                                                                           0x004e
+#define regDCCG_PERFMON_CNTL2_BASE_IDX                                                                  1
+#define regDCCG_DS_DTO_INCR                                                                             0x0053
+#define regDCCG_DS_DTO_INCR_BASE_IDX                                                                    1
+#define regDCCG_DS_DTO_MODULO                                                                           0x0054
+#define regDCCG_DS_DTO_MODULO_BASE_IDX                                                                  1
+#define regDCCG_DS_CNTL                                                                                 0x0055
+#define regDCCG_DS_CNTL_BASE_IDX                                                                        1
+#define regDCCG_DS_HW_CAL_INTERVAL                                                                      0x0056
+#define regDCCG_DS_HW_CAL_INTERVAL_BASE_IDX                                                             1
+#define regDPREFCLK_CNTL                                                                                0x0058
+#define regDPREFCLK_CNTL_BASE_IDX                                                                       1
+#define regDCE_VERSION                                                                                  0x005e
+#define regDCE_VERSION_BASE_IDX                                                                         1
+#define regDCCG_GTC_CNTL                                                                                0x0060
+#define regDCCG_GTC_CNTL_BASE_IDX                                                                       1
+#define regDCCG_GTC_DTO_INCR                                                                            0x0061
+#define regDCCG_GTC_DTO_INCR_BASE_IDX                                                                   1
+#define regDCCG_GTC_DTO_MODULO                                                                          0x0062
+#define regDCCG_GTC_DTO_MODULO_BASE_IDX                                                                 1
+#define regDCCG_GTC_CURRENT                                                                             0x0063
+#define regDCCG_GTC_CURRENT_BASE_IDX                                                                    1
+#define regSYMCLK32_SE_CNTL                                                                             0x0065
+#define regSYMCLK32_SE_CNTL_BASE_IDX                                                                    1
+#define regSYMCLK32_LE_CNTL                                                                             0x0066
+#define regSYMCLK32_LE_CNTL_BASE_IDX                                                                    1
+#define regDSCCLK0_DTO_PARAM                                                                            0x006c
+#define regDSCCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK1_DTO_PARAM                                                                            0x006d
+#define regDSCCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDSCCLK2_DTO_PARAM                                                                            0x006e
+#define regDSCCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regMILLISECOND_TIME_BASE_DIV                                                                    0x0070
+#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDISPCLK_FREQ_CHANGE_CNTL                                                                     0x0071
+#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX                                                            1
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL                                                                   0x0072
+#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX                                                          1
+#define regDCCG_PERFMON_CNTL                                                                            0x0073
+#define regDCCG_PERFMON_CNTL_BASE_IDX                                                                   1
+#define regDCCG_GATE_DISABLE_CNTL                                                                       0x0074
+#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX                                                              1
+#define regDISPCLK_CGTT_BLK_CTRL_REG                                                                    0x0075
+#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                           1
+#define regSOCCLK_CGTT_BLK_CTRL_REG                                                                     0x0076
+#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_CAC_STATUS                                                                              0x0077
+#define regDCCG_CAC_STATUS_BASE_IDX                                                                     1
+#define regMICROSECOND_TIME_BASE_DIV                                                                    0x007b
+#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX                                                           1
+#define regDCCG_GATE_DISABLE_CNTL2                                                                      0x007c
+#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX                                                             1
+#define regSYMCLK_CGTT_BLK_CTRL_REG                                                                     0x007d
+#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDCCG_DISP_CNTL_REG                                                                           0x007f
+#define regDCCG_DISP_CNTL_REG_BASE_IDX                                                                  1
+#define regOTG0_PIXEL_RATE_CNTL                                                                         0x0080
+#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO0_PHASE                                                                                0x0081
+#define regDP_DTO0_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO0_MODULO                                                                               0x0082
+#define regDP_DTO0_MODULO_BASE_IDX                                                                      1
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0083
+#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG1_PIXEL_RATE_CNTL                                                                         0x0084
+#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO1_PHASE                                                                                0x0085
+#define regDP_DTO1_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO1_MODULO                                                                               0x0086
+#define regDP_DTO1_MODULO_BASE_IDX                                                                      1
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL                                                                  0x0087
+#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG2_PIXEL_RATE_CNTL                                                                         0x0088
+#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO2_PHASE                                                                                0x0089
+#define regDP_DTO2_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO2_MODULO                                                                               0x008a
+#define regDP_DTO2_MODULO_BASE_IDX                                                                      1
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008b
+#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regOTG3_PIXEL_RATE_CNTL                                                                         0x008c
+#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX                                                                1
+#define regDP_DTO3_PHASE                                                                                0x008d
+#define regDP_DTO3_PHASE_BASE_IDX                                                                       1
+#define regDP_DTO3_MODULO                                                                               0x008e
+#define regDP_DTO3_MODULO_BASE_IDX                                                                      1
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL                                                                  0x008f
+#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX                                                         1
+#define regDPPCLK_CGTT_BLK_CTRL_REG                                                                     0x0098
+#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX                                                            1
+#define regDPPCLK0_DTO_PARAM                                                                            0x0099
+#define regDPPCLK0_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK1_DTO_PARAM                                                                            0x009a
+#define regDPPCLK1_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK2_DTO_PARAM                                                                            0x009b
+#define regDPPCLK2_DTO_PARAM_BASE_IDX                                                                   1
+#define regDPPCLK3_DTO_PARAM                                                                            0x009c
+#define regDPPCLK3_DTO_PARAM_BASE_IDX                                                                   1
+#define regDCCG_CAC_STATUS2                                                                             0x009f
+#define regDCCG_CAC_STATUS2_BASE_IDX                                                                    1
+#define regSYMCLKA_CLOCK_ENABLE                                                                         0x00a0
+#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKB_CLOCK_ENABLE                                                                         0x00a1
+#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKC_CLOCK_ENABLE                                                                         0x00a2
+#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKD_CLOCK_ENABLE                                                                         0x00a3
+#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regSYMCLKE_CLOCK_ENABLE                                                                         0x00a4
+#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX                                                                1
+#define regDCCG_SOFT_RESET                                                                              0x00a6
+#define regDCCG_SOFT_RESET_BASE_IDX                                                                     1
+#define regDSCCLK_DTO_CTRL                                                                              0x00a7
+#define regDSCCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_AUDIO_DTO_SOURCE                                                                        0x00ab
+#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_PHASE                                                                        0x00ac
+#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO0_MODULE                                                                       0x00ad
+#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX                                                              1
+#define regDCCG_AUDIO_DTO1_PHASE                                                                        0x00ae
+#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX                                                               1
+#define regDCCG_AUDIO_DTO1_MODULE                                                                       0x00af
+#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX                                                              1
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE                                                                  0x00b0
+#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE                                                                  0x00b1
+#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE                                                                  0x00b2
+#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE                                                                  0x00b3
+#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE                                                                  0x00b4
+#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX                                                         1
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE                                                                  0x00b5
+#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX                                                         1
+#define regDPPCLK_DTO_CTRL                                                                              0x00b6
+#define regDPPCLK_DTO_CTRL_BASE_IDX                                                                     1
+#define regDCCG_VSYNC_CNT_CTRL                                                                          0x00b8
+#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX                                                                 1
+#define regDCCG_VSYNC_CNT_INT_CTRL                                                                      0x00b9
+#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX                                                             1
+#define regFORCE_SYMCLK_DISABLE                                                                         0x00ba
+#define regFORCE_SYMCLK_DISABLE_BASE_IDX                                                                1
+#define regDTBCLK_DTO0_PHASE                                                                            0x0018
+#define regDTBCLK_DTO0_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO1_PHASE                                                                            0x0019
+#define regDTBCLK_DTO1_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO2_PHASE                                                                            0x001a
+#define regDTBCLK_DTO2_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO3_PHASE                                                                            0x001b
+#define regDTBCLK_DTO3_PHASE_BASE_IDX                                                                   2
+#define regDTBCLK_DTO0_MODULO                                                                           0x001f
+#define regDTBCLK_DTO0_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO1_MODULO                                                                           0x0020
+#define regDTBCLK_DTO1_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO2_MODULO                                                                           0x0021
+#define regDTBCLK_DTO2_MODULO_BASE_IDX                                                                  2
+#define regDTBCLK_DTO3_MODULO                                                                           0x0022
+#define regDTBCLK_DTO3_MODULO_BASE_IDX                                                                  2
+#define regPHYASYMCLK_CLOCK_CNTL                                                                        0x0052
+#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYBSYMCLK_CLOCK_CNTL                                                                        0x0053
+#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYCSYMCLK_CLOCK_CNTL                                                                        0x0054
+#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYDSYMCLK_CLOCK_CNTL                                                                        0x0055
+#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regPHYESYMCLK_CLOCK_CNTL                                                                        0x0056
+#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
+#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
+#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
+#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
+#define regDCCG_AUDIO_DTBCLK_DTO_MODULO_BASE_IDX                                                        2
+#define regDTBCLK_DTO_DBUF_EN                                                                           0x0063
+#define regDTBCLK_DTO_DBUF_EN_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+// base address: 0x0
+#define regDC_PERFMON0_PERFCOUNTER_CNTL                                                                 0x0000
+#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON0_PERFCOUNTER_CNTL2                                                                0x0001
+#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON0_PERFCOUNTER_STATE                                                                0x0002
+#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON0_PERFMON_CNTL                                                                     0x0003
+#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON0_PERFMON_CNTL2                                                                    0x0004
+#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC                                                          0x0005
+#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON0_PERFMON_CVALUE_LOW                                                               0x0006
+#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON0_PERFMON_HI                                                                       0x0007
+#define regDC_PERFMON0_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON0_PERFMON_LOW                                                                      0x0008
+#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+// base address: 0x30
+#define regDC_PERFMON1_PERFCOUNTER_CNTL                                                                 0x000c
+#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON1_PERFCOUNTER_CNTL2                                                                0x000d
+#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON1_PERFCOUNTER_STATE                                                                0x000e
+#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON1_PERFMON_CNTL                                                                     0x000f
+#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON1_PERFMON_CNTL2                                                                    0x0010
+#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC                                                          0x0011
+#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON1_PERFMON_CVALUE_LOW                                                               0x0012
+#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON1_PERFMON_HI                                                                       0x0013
+#define regDC_PERFMON1_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON1_PERFMON_LOW                                                                      0x0014
+#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+// base address: 0x0
+#define regDMCU_CTRL                                                                                    0x00da
+#define regDMCU_CTRL_BASE_IDX                                                                           2
+#define regDMCU_STATUS                                                                                  0x00db
+#define regDMCU_STATUS_BASE_IDX                                                                         2
+#define regDMCU_PC_START_ADDR                                                                           0x00dc
+#define regDMCU_PC_START_ADDR_BASE_IDX                                                                  2
+#define regDMCU_FW_START_ADDR                                                                           0x00dd
+#define regDMCU_FW_START_ADDR_BASE_IDX                                                                  2
+#define regDMCU_FW_END_ADDR                                                                             0x00de
+#define regDMCU_FW_END_ADDR_BASE_IDX                                                                    2
+#define regDMCU_FW_ISR_START_ADDR                                                                       0x00df
+#define regDMCU_FW_ISR_START_ADDR_BASE_IDX                                                              2
+#define regDMCU_FW_CS_HI                                                                                0x00e0
+#define regDMCU_FW_CS_HI_BASE_IDX                                                                       2
+#define regDMCU_FW_CS_LO                                                                                0x00e1
+#define regDMCU_FW_CS_LO_BASE_IDX                                                                       2
+#define regDMCU_RAM_ACCESS_CTRL                                                                         0x00e2
+#define regDMCU_RAM_ACCESS_CTRL_BASE_IDX                                                                2
+#define regDMCU_ERAM_WR_CTRL                                                                            0x00e3
+#define regDMCU_ERAM_WR_CTRL_BASE_IDX                                                                   2
+#define regDMCU_ERAM_WR_DATA                                                                            0x00e4
+#define regDMCU_ERAM_WR_DATA_BASE_IDX                                                                   2
+#define regDMCU_ERAM_RD_CTRL                                                                            0x00e5
+#define regDMCU_ERAM_RD_CTRL_BASE_IDX                                                                   2
+#define regDMCU_ERAM_RD_DATA                                                                            0x00e6
+#define regDMCU_ERAM_RD_DATA_BASE_IDX                                                                   2
+#define regDMCU_IRAM_WR_CTRL                                                                            0x00e7
+#define regDMCU_IRAM_WR_CTRL_BASE_IDX                                                                   2
+#define regDMCU_IRAM_WR_DATA                                                                            0x00e8
+#define regDMCU_IRAM_WR_DATA_BASE_IDX                                                                   2
+#define regDMCU_IRAM_RD_CTRL                                                                            0x00e9
+#define regDMCU_IRAM_RD_CTRL_BASE_IDX                                                                   2
+#define regDMCU_IRAM_RD_DATA                                                                            0x00ea
+#define regDMCU_IRAM_RD_DATA_BASE_IDX                                                                   2
+#define regDMCU_EVENT_TRIGGER                                                                           0x00eb
+#define regDMCU_EVENT_TRIGGER_BASE_IDX                                                                  2
+#define regDMCU_UC_INTERNAL_INT_STATUS                                                                  0x00ec
+#define regDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX                                                         2
+#define regDMCU_SS_INTERRUPT_CNTL_STATUS                                                                0x00ed
+#define regDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX                                                       2
+#define regDMCU_INTERRUPT_STATUS                                                                        0x00ee
+#define regDMCU_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDMCU_INTERRUPT_STATUS_1                                                                      0x00ef
+#define regDMCU_INTERRUPT_STATUS_1_BASE_IDX                                                             2
+#define regDMCU_INTERRUPT_TO_HOST_EN_MASK                                                               0x00f0
+#define regDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX                                                      2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK                                                                 0x00f1
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX                                                        2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1                                                               0x00f2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX                                                      2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL                                                            0x00f3
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX                                                   2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1                                                          0x00f4
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX                                                 2
+#define regDC_DMCU_SCRATCH                                                                              0x00f5
+#define regDC_DMCU_SCRATCH_BASE_IDX                                                                     2
+#define regDMCU_INT_CNT                                                                                 0x00f6
+#define regDMCU_INT_CNT_BASE_IDX                                                                        2
+#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS                                                               0x00f7
+#define regDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX                                                      2
+#define regDMCU_UC_CLK_GATING_CNTL                                                                      0x00f8
+#define regDMCU_UC_CLK_GATING_CNTL_BASE_IDX                                                             2
+#define regMASTER_COMM_DATA_REG1                                                                        0x00f9
+#define regMASTER_COMM_DATA_REG1_BASE_IDX                                                               2
+#define regMASTER_COMM_DATA_REG2                                                                        0x00fa
+#define regMASTER_COMM_DATA_REG2_BASE_IDX                                                               2
+#define regMASTER_COMM_DATA_REG3                                                                        0x00fb
+#define regMASTER_COMM_DATA_REG3_BASE_IDX                                                               2
+#define regMASTER_COMM_CMD_REG                                                                          0x00fc
+#define regMASTER_COMM_CMD_REG_BASE_IDX                                                                 2
+#define regMASTER_COMM_CNTL_REG                                                                         0x00fd
+#define regMASTER_COMM_CNTL_REG_BASE_IDX                                                                2
+#define regSLAVE_COMM_DATA_REG1                                                                         0x00fe
+#define regSLAVE_COMM_DATA_REG1_BASE_IDX                                                                2
+#define regSLAVE_COMM_DATA_REG2                                                                         0x00ff
+#define regSLAVE_COMM_DATA_REG2_BASE_IDX                                                                2
+#define regSLAVE_COMM_DATA_REG3                                                                         0x0100
+#define regSLAVE_COMM_DATA_REG3_BASE_IDX                                                                2
+#define regSLAVE_COMM_CMD_REG                                                                           0x0101
+#define regSLAVE_COMM_CMD_REG_BASE_IDX                                                                  2
+#define regSLAVE_COMM_CNTL_REG                                                                          0x0102
+#define regSLAVE_COMM_CNTL_REG_BASE_IDX                                                                 2
+#define regDMCU_PERFMON_INTERRUPT_STATUS1                                                               0x0105
+#define regDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS2                                                               0x0106
+#define regDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS3                                                               0x0107
+#define regDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS4                                                               0x0108
+#define regDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_STATUS5                                                               0x0109
+#define regDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX                                                      2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1                                                        0x010a
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2                                                        0x010b
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3                                                        0x010c
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4                                                        0x010d
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5                                                        0x010e
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX                                               2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                   0x010f
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2                                                   0x0110
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3                                                   0x0111
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4                                                   0x0112
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX                                          2
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5                                                   0x0113
+#define regDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX                                          2
+#define regDMCU_DPRX_INTERRUPT_STATUS1                                                                  0x0114
+#define regDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX                                                         2
+#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1                                                           0x0115
+#define regDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX                                                  2
+#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1                                                      0x0116
+#define regDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX                                             2
+#define regDMCU_INTERRUPT_STATUS_CONTINUE                                                               0x0119
+#define regDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE                                                        0x011a
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX                                               2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE                                                   0x011b
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX                                          2
+#define regDMCU_INT_CNT_CONTINUE                                                                        0x011c
+#define regDMCU_INT_CNT_CONTINUE_BASE_IDX                                                               2
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2                                                      0x011d
+#define regDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX                                             2
+#define regDMCU_INTERRUPT_STATUS_2                                                                      0x011e
+#define regDMCU_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2                                                               0x011f
+#define regDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX                                                      2
+#define regDMCU_INT_CNT_CONT2                                                                           0x0120
+#define regDMCU_INT_CNT_CONT2_BASE_IDX                                                                  2
+#define regDMCU_INT_CNT_CONT3                                                                           0x0121
+#define regDMCU_INT_CNT_CONT3_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+// base address: 0x0
+#define regDMCUB_RBBMIF_SEC_CNTL                                                                        0x017a
+#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+// base address: 0x0
+#define regRBBMIF_TIMEOUT                                                                               0x017f
+#define regRBBMIF_TIMEOUT_BASE_IDX                                                                      2
+#define regRBBMIF_STATUS                                                                                0x0180
+#define regRBBMIF_STATUS_BASE_IDX                                                                       2
+#define regRBBMIF_STATUS_2                                                                              0x0181
+#define regRBBMIF_STATUS_2_BASE_IDX                                                                     2
+#define regRBBMIF_INT_STATUS                                                                            0x0182
+#define regRBBMIF_INT_STATUS_BASE_IDX                                                                   2
+#define regRBBMIF_TIMEOUT_DIS                                                                           0x0183
+#define regRBBMIF_TIMEOUT_DIS_BASE_IDX                                                                  2
+#define regRBBMIF_TIMEOUT_DIS_2                                                                         0x0184
+#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX                                                                2
+#define regRBBMIF_STATUS_FLAG                                                                           0x0185
+#define regRBBMIF_STATUS_FLAG_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2f8
+#define regDC_PERFMON2_PERFCOUNTER_CNTL                                                                 0x00be
+#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON2_PERFCOUNTER_CNTL2                                                                0x00bf
+#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON2_PERFCOUNTER_STATE                                                                0x00c0
+#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON2_PERFMON_CNTL                                                                     0x00c1
+#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON2_PERFMON_CNTL2                                                                    0x00c2
+#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC                                                          0x00c3
+#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON2_PERFMON_CVALUE_LOW                                                               0x00c4
+#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON2_PERFMON_HI                                                                       0x00c5
+#define regDC_PERFMON2_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON2_PERFMON_LOW                                                                      0x00c6
+#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+// base address: 0x0
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE                                                         0x0126
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX                                                2
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP                                                         0x0127
+#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX                                                2
+#define regDC_GPU_TIMER_READ                                                                            0x0128
+#define regDC_GPU_TIMER_READ_BASE_IDX                                                                   2
+#define regDC_GPU_TIMER_READ_CNTL                                                                       0x0129
+#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX                                                              2
+#define regDISP_INTERRUPT_STATUS                                                                        0x012a
+#define regDISP_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE                                                               0x012b
+#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX                                                      2
+#define regDISP_INTERRUPT_STATUS_CONTINUE2                                                              0x012c
+#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE3                                                              0x012d
+#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE4                                                              0x012e
+#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE5                                                              0x012f
+#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE6                                                              0x0130
+#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE7                                                              0x0131
+#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE8                                                              0x0132
+#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE9                                                              0x0133
+#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX                                                     2
+#define regDISP_INTERRUPT_STATUS_CONTINUE10                                                             0x0134
+#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE11                                                             0x0135
+#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE12                                                             0x0136
+#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE13                                                             0x0137
+#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE14                                                             0x0138
+#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE15                                                             0x0139
+#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE16                                                             0x013a
+#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE17                                                             0x013b
+#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE18                                                             0x013c
+#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE19                                                             0x013d
+#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE20                                                             0x013e
+#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE21                                                             0x013f
+#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE22                                                             0x0140
+#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_VREADY                                                           0x0141
+#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX                                                  2
+#define regDC_GPU_TIMER_START_POSITION_FLIP                                                             0x0142
+#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX                                                    2
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK                                                 0x0143
+#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX                                        2
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY                                                        0x0144
+#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX                                               2
+#define regDISP_INTERRUPT_STATUS_CONTINUE23                                                             0x0145
+#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE24                                                             0x0146
+#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX                                                    2
+#define regDISP_INTERRUPT_STATUS_CONTINUE25                                                             0x0147
+#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX                                                    2
+#define regDCCG_INTERRUPT_DEST                                                                          0x0148
+#define regDCCG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDMU_INTERRUPT_DEST                                                                           0x0149
+#define regDMU_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDMU_INTERRUPT_DEST2                                                                          0x014a
+#define regDMU_INTERRUPT_DEST2_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST                                                                          0x014b
+#define regDCPG_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDCPG_INTERRUPT_DEST2                                                                         0x014c
+#define regDCPG_INTERRUPT_DEST2_BASE_IDX                                                                2
+#define regMMHUBBUB_INTERRUPT_DEST                                                                      0x014d
+#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX                                                             2
+#define regWB_INTERRUPT_DEST                                                                            0x014e
+#define regWB_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regDCHUB_INTERRUPT_DEST                                                                         0x014f
+#define regDCHUB_INTERRUPT_DEST_BASE_IDX                                                                2
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST                                                             0x0150
+#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                    2
+#define regDCHUB_INTERRUPT_DEST2                                                                        0x0151
+#define regDCHUB_INTERRUPT_DEST2_BASE_IDX                                                               2
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST                                                               0x0152
+#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX                                                      2
+#define regMPC_INTERRUPT_DEST                                                                           0x0153
+#define regMPC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPP_INTERRUPT_DEST                                                                           0x0154
+#define regOPP_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regOPTC_INTERRUPT_DEST                                                                          0x0155
+#define regOPTC_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG0_INTERRUPT_DEST                                                                          0x0156
+#define regOTG0_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG1_INTERRUPT_DEST                                                                          0x0157
+#define regOTG1_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG2_INTERRUPT_DEST                                                                          0x0158
+#define regOTG2_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG3_INTERRUPT_DEST                                                                          0x0159
+#define regOTG3_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG4_INTERRUPT_DEST                                                                          0x015a
+#define regOTG4_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regOTG5_INTERRUPT_DEST                                                                          0x015b
+#define regOTG5_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regDIG_INTERRUPT_DEST                                                                           0x015c
+#define regDIG_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regI2C_DDC_HPD_INTERRUPT_DEST                                                                   0x015d
+#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX                                                          2
+#define regDIO_INTERRUPT_DEST                                                                           0x015f
+#define regDIO_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDCIO_INTERRUPT_DEST                                                                          0x0160
+#define regDCIO_INTERRUPT_DEST_BASE_IDX                                                                 2
+#define regHPD_INTERRUPT_DEST                                                                           0x0161
+#define regHPD_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regAZ_INTERRUPT_DEST                                                                            0x0162
+#define regAZ_INTERRUPT_DEST_BASE_IDX                                                                   2
+#define regAUX_INTERRUPT_DEST                                                                           0x0163
+#define regAUX_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regDSC_INTERRUPT_DEST                                                                           0x0164
+#define regDSC_INTERRUPT_DEST_BASE_IDX                                                                  2
+#define regHPO_INTERRUPT_DEST                                                                           0x0165
+#define regHPO_INTERRUPT_DEST_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+// base address: 0x0
+#define regCC_DC_PIPE_DIS                                                                               0x00ca
+#define regCC_DC_PIPE_DIS_BASE_IDX                                                                      2
+#define regDMU_CLK_CNTL                                                                                 0x00cb
+#define regDMU_CLK_CNTL_BASE_IDX                                                                        2
+#define regDMU_MEM_PWR_CNTL                                                                             0x00cc
+#define regDMU_MEM_PWR_CNTL_BASE_IDX                                                                    2
+#define regDMCU_SMU_INTERRUPT_CNTL                                                                      0x00cd
+#define regDMCU_SMU_INTERRUPT_CNTL_BASE_IDX                                                             2
+#define regSMU_INTERRUPT_CONTROL                                                                        0x00ce
+#define regSMU_INTERRUPT_CONTROL_BASE_IDX                                                               2
+#define regZSC_CNTL                                                                                     0x00cf
+#define regZSC_CNTL_BASE_IDX                                                                            2
+#define regZSC_CNTL2                                                                                    0x00d0
+#define regZSC_CNTL2_BASE_IDX                                                                           2
+#define regDMU_MISC_ALLOW_DS_FORCE                                                                      0x00d6
+#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX                                                             2
+#define regZSC_STATUS                                                                                   0x00d7
+#define regZSC_STATUS_BASE_IDX                                                                          2
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+// base address: 0x0
+#define regDOMAIN0_PG_CONFIG                                                                            0x0080
+#define regDOMAIN0_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN0_PG_STATUS                                                                            0x0081
+#define regDOMAIN0_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_CONFIG                                                                            0x0082
+#define regDOMAIN1_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN1_PG_STATUS                                                                            0x0083
+#define regDOMAIN1_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_CONFIG                                                                            0x0084
+#define regDOMAIN2_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN2_PG_STATUS                                                                            0x0085
+#define regDOMAIN2_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_CONFIG                                                                            0x0086
+#define regDOMAIN3_PG_CONFIG_BASE_IDX                                                                   2
+#define regDOMAIN3_PG_STATUS                                                                            0x0087
+#define regDOMAIN3_PG_STATUS_BASE_IDX                                                                   2
+#define regDOMAIN16_PG_CONFIG                                                                           0x0089
+#define regDOMAIN16_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN16_PG_STATUS                                                                           0x008a
+#define regDOMAIN16_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_CONFIG                                                                           0x008b
+#define regDOMAIN17_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN17_PG_STATUS                                                                           0x008c
+#define regDOMAIN17_PG_STATUS_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_CONFIG                                                                           0x008d
+#define regDOMAIN18_PG_CONFIG_BASE_IDX                                                                  2
+#define regDOMAIN18_PG_STATUS                                                                           0x008e
+#define regDOMAIN18_PG_STATUS_BASE_IDX                                                                  2
+#define regDCPG_INTERRUPT_STATUS                                                                        0x008f
+#define regDCPG_INTERRUPT_STATUS_BASE_IDX                                                               2
+#define regDCPG_INTERRUPT_STATUS_2                                                                      0x0090
+#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX                                                             2
+#define regDCPG_INTERRUPT_CONTROL_1                                                                     0x0091
+#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX                                                            2
+#define regDCPG_INTERRUPT_CONTROL_3                                                                     0x0092
+#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX                                                            2
+#define regDC_IP_REQUEST_CNTL                                                                           0x0093
+#define regDC_IP_REQUEST_CNTL_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+// base address: 0x0
+#define regDMCUB_REGION0_OFFSET                                                                         0x018e
+#define regDMCUB_REGION0_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION0_OFFSET_HIGH                                                                    0x018f
+#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION1_OFFSET                                                                         0x0190
+#define regDMCUB_REGION1_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION1_OFFSET_HIGH                                                                    0x0191
+#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION2_OFFSET                                                                         0x0192
+#define regDMCUB_REGION2_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION2_OFFSET_HIGH                                                                    0x0193
+#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION4_OFFSET                                                                         0x0196
+#define regDMCUB_REGION4_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION4_OFFSET_HIGH                                                                    0x0197
+#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION5_OFFSET                                                                         0x0198
+#define regDMCUB_REGION5_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION5_OFFSET_HIGH                                                                    0x0199
+#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION6_OFFSET                                                                         0x019a
+#define regDMCUB_REGION6_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION6_OFFSET_HIGH                                                                    0x019b
+#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION7_OFFSET                                                                         0x019c
+#define regDMCUB_REGION7_OFFSET_BASE_IDX                                                                2
+#define regDMCUB_REGION7_OFFSET_HIGH                                                                    0x019d
+#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX                                                           2
+#define regDMCUB_REGION0_TOP_ADDRESS                                                                    0x019e
+#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION1_TOP_ADDRESS                                                                    0x019f
+#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION2_TOP_ADDRESS                                                                    0x01a0
+#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION4_TOP_ADDRESS                                                                    0x01a1
+#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION5_TOP_ADDRESS                                                                    0x01a2
+#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION6_TOP_ADDRESS                                                                    0x01a3
+#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION7_TOP_ADDRESS                                                                    0x01a4
+#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS                                                               0x01a5
+#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS                                                               0x01a6
+#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS                                                               0x01a7
+#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS                                                               0x01a8
+#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS                                                               0x01a9
+#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS                                                               0x01aa
+#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS                                                               0x01ab
+#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS                                                               0x01ac
+#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX                                                      2
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS                                                                0x01ad
+#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS                                                                0x01ae
+#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS                                                                0x01af
+#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS                                                                0x01b0
+#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS                                                                0x01b1
+#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS                                                                0x01b2
+#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS                                                                0x01b3
+#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS                                                                0x01b4
+#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW0_OFFSET                                                                     0x01b5
+#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH                                                                0x01b6
+#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW1_OFFSET                                                                     0x01b7
+#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH                                                                0x01b8
+#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW2_OFFSET                                                                     0x01b9
+#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH                                                                0x01ba
+#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW3_OFFSET                                                                     0x01bb
+#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH                                                                0x01bc
+#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW4_OFFSET                                                                     0x01bd
+#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH                                                                0x01be
+#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW5_OFFSET                                                                     0x01bf
+#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH                                                                0x01c0
+#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW6_OFFSET                                                                     0x01c1
+#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH                                                                0x01c2
+#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_REGION3_CW7_OFFSET                                                                     0x01c3
+#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX                                                            2
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH                                                                0x01c4
+#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX                                                       2
+#define regDMCUB_INTERRUPT_ENABLE                                                                       0x01c5
+#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_ACK                                                                          0x01c6
+#define regDMCUB_INTERRUPT_ACK_BASE_IDX                                                                 2
+#define regDMCUB_INTERRUPT_STATUS                                                                       0x01c7
+#define regDMCUB_INTERRUPT_STATUS_BASE_IDX                                                              2
+#define regDMCUB_INTERRUPT_TYPE                                                                         0x01c8
+#define regDMCUB_INTERRUPT_TYPE_BASE_IDX                                                                2
+#define regDMCUB_EXT_INTERRUPT_STATUS                                                                   0x01c9
+#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX                                                          2
+#define regDMCUB_EXT_INTERRUPT_CTXID                                                                    0x01ca
+#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX                                                           2
+#define regDMCUB_EXT_INTERRUPT_ACK                                                                      0x01cb
+#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX                                                             2
+#define regDMCUB_INST_FETCH_FAULT_ADDR                                                                  0x01cc
+#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_DATA_WRITE_FAULT_ADDR                                                                  0x01cd
+#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX                                                         2
+#define regDMCUB_SEC_CNTL                                                                               0x01ce
+#define regDMCUB_SEC_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_MEM_CNTL                                                                               0x01cf
+#define regDMCUB_MEM_CNTL_BASE_IDX                                                                      2
+#define regDMCUB_INBOX0_BASE_ADDRESS                                                                    0x01d0
+#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX0_SIZE                                                                            0x01d1
+#define regDMCUB_INBOX0_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_WPTR                                                                            0x01d2
+#define regDMCUB_INBOX0_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX0_RPTR                                                                            0x01d3
+#define regDMCUB_INBOX0_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_BASE_ADDRESS                                                                    0x01d4
+#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX                                                           2
+#define regDMCUB_INBOX1_SIZE                                                                            0x01d5
+#define regDMCUB_INBOX1_SIZE_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_WPTR                                                                            0x01d6
+#define regDMCUB_INBOX1_WPTR_BASE_IDX                                                                   2
+#define regDMCUB_INBOX1_RPTR                                                                            0x01d7
+#define regDMCUB_INBOX1_RPTR_BASE_IDX                                                                   2
+#define regDMCUB_OUTBOX0_BASE_ADDRESS                                                                   0x01d8
+#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX0_SIZE                                                                           0x01d9
+#define regDMCUB_OUTBOX0_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_WPTR                                                                           0x01da
+#define regDMCUB_OUTBOX0_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX0_RPTR                                                                           0x01db
+#define regDMCUB_OUTBOX0_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_BASE_ADDRESS                                                                   0x01dc
+#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX                                                          2
+#define regDMCUB_OUTBOX1_SIZE                                                                           0x01dd
+#define regDMCUB_OUTBOX1_SIZE_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_WPTR                                                                           0x01de
+#define regDMCUB_OUTBOX1_WPTR_BASE_IDX                                                                  2
+#define regDMCUB_OUTBOX1_RPTR                                                                           0x01df
+#define regDMCUB_OUTBOX1_RPTR_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_TRIGGER0                                                                         0x01e0
+#define regDMCUB_TIMER_TRIGGER0_BASE_IDX                                                                2
+#define regDMCUB_TIMER_TRIGGER1                                                                         0x01e1
+#define regDMCUB_TIMER_TRIGGER1_BASE_IDX                                                                2
+#define regDMCUB_TIMER_WINDOW                                                                           0x01e2
+#define regDMCUB_TIMER_WINDOW_BASE_IDX                                                                  2
+#define regDMCUB_SCRATCH0                                                                               0x01e3
+#define regDMCUB_SCRATCH0_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH1                                                                               0x01e4
+#define regDMCUB_SCRATCH1_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH2                                                                               0x01e5
+#define regDMCUB_SCRATCH2_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH3                                                                               0x01e6
+#define regDMCUB_SCRATCH3_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH4                                                                               0x01e7
+#define regDMCUB_SCRATCH4_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH5                                                                               0x01e8
+#define regDMCUB_SCRATCH5_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH6                                                                               0x01e9
+#define regDMCUB_SCRATCH6_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH7                                                                               0x01ea
+#define regDMCUB_SCRATCH7_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH8                                                                               0x01eb
+#define regDMCUB_SCRATCH8_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH9                                                                               0x01ec
+#define regDMCUB_SCRATCH9_BASE_IDX                                                                      2
+#define regDMCUB_SCRATCH10                                                                              0x01ed
+#define regDMCUB_SCRATCH10_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH11                                                                              0x01ee
+#define regDMCUB_SCRATCH11_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH12                                                                              0x01ef
+#define regDMCUB_SCRATCH12_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH13                                                                              0x01f0
+#define regDMCUB_SCRATCH13_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH14                                                                              0x01f1
+#define regDMCUB_SCRATCH14_BASE_IDX                                                                     2
+#define regDMCUB_SCRATCH15                                                                              0x01f2
+#define regDMCUB_SCRATCH15_BASE_IDX                                                                     2
+#define regDMCUB_CNTL                                                                                   0x01f6
+#define regDMCUB_CNTL_BASE_IDX                                                                          2
+#define regDMCUB_GPINT_DATAIN0                                                                          0x01f7
+#define regDMCUB_GPINT_DATAIN0_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAIN1                                                                          0x01f8
+#define regDMCUB_GPINT_DATAIN1_BASE_IDX                                                                 2
+#define regDMCUB_GPINT_DATAOUT                                                                          0x01f9
+#define regDMCUB_GPINT_DATAOUT_BASE_IDX                                                                 2
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR                                                           0x01fa
+#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX                                                  2
+#define regDMCUB_LS_WAKE_INT_ENABLE                                                                     0x01fb
+#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX                                                            2
+#define regDMCUB_MEM_PWR_CNTL                                                                           0x01fc
+#define regDMCUB_MEM_PWR_CNTL_BASE_IDX                                                                  2
+#define regDMCUB_TIMER_CURRENT                                                                          0x01fd
+#define regDMCUB_TIMER_CURRENT_BASE_IDX                                                                 2
+#define regDMCUB_PROC_ID                                                                                0x01ff
+#define regDMCUB_PROC_ID_BASE_IDX                                                                       2
+#define regDMCUB_CNTL2                                                                                  0x0200
+#define regDMCUB_CNTL2_BASE_IDX                                                                         2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+// base address: 0x0
+#define regDWB_ENABLE_CLK_CTRL                                                                          0x3228
+#define regDWB_ENABLE_CLK_CTRL_BASE_IDX                                                                 2
+#define regDWB_MEM_PWR_CTRL                                                                             0x3229
+#define regDWB_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regFC_MODE_CTRL                                                                                 0x322a
+#define regFC_MODE_CTRL_BASE_IDX                                                                        2
+#define regFC_FLOW_CTRL                                                                                 0x322b
+#define regFC_FLOW_CTRL_BASE_IDX                                                                        2
+#define regFC_WINDOW_START                                                                              0x322c
+#define regFC_WINDOW_START_BASE_IDX                                                                     2
+#define regFC_WINDOW_SIZE                                                                               0x322d
+#define regFC_WINDOW_SIZE_BASE_IDX                                                                      2
+#define regFC_SOURCE_SIZE                                                                               0x322e
+#define regFC_SOURCE_SIZE_BASE_IDX                                                                      2
+#define regDWB_UPDATE_CTRL                                                                              0x322f
+#define regDWB_UPDATE_CTRL_BASE_IDX                                                                     2
+#define regDWB_CRC_CTRL                                                                                 0x3230
+#define regDWB_CRC_CTRL_BASE_IDX                                                                        2
+#define regDWB_CRC_MASK_R_G                                                                             0x3231
+#define regDWB_CRC_MASK_R_G_BASE_IDX                                                                    2
+#define regDWB_CRC_MASK_B_A                                                                             0x3232
+#define regDWB_CRC_MASK_B_A_BASE_IDX                                                                    2
+#define regDWB_CRC_VAL_R_G                                                                              0x3233
+#define regDWB_CRC_VAL_R_G_BASE_IDX                                                                     2
+#define regDWB_CRC_VAL_B_A                                                                              0x3234
+#define regDWB_CRC_VAL_B_A_BASE_IDX                                                                     2
+#define regDWB_OUT_CTRL                                                                                 0x3235
+#define regDWB_OUT_CTRL_BASE_IDX                                                                        2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN                                                             0x3236
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX                                                    2
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT                                                                0x3237
+#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX                                                       2
+#define regDWB_HOST_READ_CONTROL                                                                        0x3238
+#define regDWB_HOST_READ_CONTROL_BASE_IDX                                                               2
+#define regDWB_OVERFLOW_STATUS                                                                          0x3239
+#define regDWB_OVERFLOW_STATUS_BASE_IDX                                                                 2
+#define regDWB_OVERFLOW_COUNTER                                                                         0x323a
+#define regDWB_OVERFLOW_COUNTER_BASE_IDX                                                                2
+#define regDWB_SOFT_RESET                                                                               0x323b
+#define regDWB_SOFT_RESET_BASE_IDX                                                                      2
+#define regDWB_DEBUG_CTRL                                                                               0x323c
+#define regDWB_DEBUG_CTRL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+// base address: 0x0
+#define regDWB_HDR_MULT_COEF                                                                            0x3294
+#define regDWB_HDR_MULT_COEF_BASE_IDX                                                                   2
+#define regDWB_GAMUT_REMAP_MODE                                                                         0x3295
+#define regDWB_GAMUT_REMAP_MODE_BASE_IDX                                                                2
+#define regDWB_GAMUT_REMAP_COEF_FORMAT                                                                  0x3296
+#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                                         2
+#define regDWB_GAMUT_REMAPA_C11_C12                                                                     0x3297
+#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C13_C14                                                                     0x3298
+#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C21_C22                                                                     0x3299
+#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C23_C24                                                                     0x329a
+#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C31_C32                                                                     0x329b
+#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPA_C33_C34                                                                     0x329c
+#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C11_C12                                                                     0x329d
+#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C13_C14                                                                     0x329e
+#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C21_C22                                                                     0x329f
+#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C23_C24                                                                     0x32a0
+#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C31_C32                                                                     0x32a1
+#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX                                                            2
+#define regDWB_GAMUT_REMAPB_C33_C34                                                                     0x32a2
+#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX                                                            2
+#define regDWB_OGAM_CONTROL                                                                             0x32a3
+#define regDWB_OGAM_CONTROL_BASE_IDX                                                                    2
+#define regDWB_OGAM_LUT_INDEX                                                                           0x32a4
+#define regDWB_OGAM_LUT_INDEX_BASE_IDX                                                                  2
+#define regDWB_OGAM_LUT_DATA                                                                            0x32a5
+#define regDWB_OGAM_LUT_DATA_BASE_IDX                                                                   2
+#define regDWB_OGAM_LUT_CONTROL                                                                         0x32a6
+#define regDWB_OGAM_LUT_CONTROL_BASE_IDX                                                                2
+#define regDWB_OGAM_RAMA_START_CNTL_B                                                                   0x32a7
+#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_G                                                                   0x32a8
+#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_CNTL_R                                                                   0x32a9
+#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B                                                              0x32aa
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B                                                             0x32ab
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G                                                              0x32ac
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G                                                             0x32ad
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R                                                              0x32ae
+#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R                                                             0x32af
+#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMA_END_CNTL1_B                                                                    0x32b0
+#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_B                                                                    0x32b1
+#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_G                                                                    0x32b2
+#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_G                                                                    0x32b3
+#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL1_R                                                                    0x32b4
+#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_END_CNTL2_R                                                                    0x32b5
+#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMA_OFFSET_B                                                                       0x32b6
+#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_G                                                                       0x32b7
+#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_OFFSET_R                                                                       0x32b8
+#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMA_REGION_0_1                                                                     0x32b9
+#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_2_3                                                                     0x32ba
+#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_4_5                                                                     0x32bb
+#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_6_7                                                                     0x32bc
+#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_8_9                                                                     0x32bd
+#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMA_REGION_10_11                                                                   0x32be
+#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_12_13                                                                   0x32bf
+#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_14_15                                                                   0x32c0
+#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_16_17                                                                   0x32c1
+#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_18_19                                                                   0x32c2
+#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_20_21                                                                   0x32c3
+#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_22_23                                                                   0x32c4
+#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_24_25                                                                   0x32c5
+#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_26_27                                                                   0x32c6
+#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_28_29                                                                   0x32c7
+#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_30_31                                                                   0x32c8
+#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMA_REGION_32_33                                                                   0x32c9
+#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_B                                                                   0x32ca
+#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_G                                                                   0x32cb
+#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_CNTL_R                                                                   0x32cc
+#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B                                                              0x32cd
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B                                                             0x32ce
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G                                                              0x32cf
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G                                                             0x32d0
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R                                                              0x32d1
+#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                                     2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R                                                             0x32d2
+#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                                    2
+#define regDWB_OGAM_RAMB_END_CNTL1_B                                                                    0x32d3
+#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_B                                                                    0x32d4
+#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_G                                                                    0x32d5
+#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_G                                                                    0x32d6
+#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL1_R                                                                    0x32d7
+#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_END_CNTL2_R                                                                    0x32d8
+#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                                           2
+#define regDWB_OGAM_RAMB_OFFSET_B                                                                       0x32d9
+#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_G                                                                       0x32da
+#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_OFFSET_R                                                                       0x32db
+#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX                                                              2
+#define regDWB_OGAM_RAMB_REGION_0_1                                                                     0x32dc
+#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_2_3                                                                     0x32dd
+#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_4_5                                                                     0x32de
+#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_6_7                                                                     0x32df
+#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_8_9                                                                     0x32e0
+#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX                                                            2
+#define regDWB_OGAM_RAMB_REGION_10_11                                                                   0x32e1
+#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_12_13                                                                   0x32e2
+#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_14_15                                                                   0x32e3
+#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_16_17                                                                   0x32e4
+#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_18_19                                                                   0x32e5
+#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_20_21                                                                   0x32e6
+#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_22_23                                                                   0x32e7
+#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_24_25                                                                   0x32e8
+#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_26_27                                                                   0x32e9
+#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_28_29                                                                   0x32ea
+#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_30_31                                                                   0x32eb
+#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX                                                          2
+#define regDWB_OGAM_RAMB_REGION_32_33                                                                   0x32ec
+#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+// base address: 0xca20
+#define regDC_PERFMON3_PERFCOUNTER_CNTL                                                                 0x3288
+#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON3_PERFCOUNTER_CNTL2                                                                0x3289
+#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON3_PERFCOUNTER_STATE                                                                0x328a
+#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON3_PERFMON_CNTL                                                                     0x328b
+#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON3_PERFMON_CNTL2                                                                    0x328c
+#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC                                                          0x328d
+#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON3_PERFMON_CVALUE_LOW                                                               0x328e
+#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON3_PERFMON_HI                                                                       0x328f
+#define regDC_PERFMON3_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON3_PERFMON_LOW                                                                      0x3290
+#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+// base address: 0x0
+#define regVGA_RENDER_CONTROL                                                                           0x0000
+#define regVGA_RENDER_CONTROL_BASE_IDX                                                                  1
+#define regVGA_SEQUENCER_RESET_CONTROL                                                                  0x0001
+#define regVGA_SEQUENCER_RESET_CONTROL_BASE_IDX                                                         1
+#define regVGA_MODE_CONTROL                                                                             0x0002
+#define regVGA_MODE_CONTROL_BASE_IDX                                                                    1
+#define regVGA_SURFACE_PITCH_SELECT                                                                     0x0003
+#define regVGA_SURFACE_PITCH_SELECT_BASE_IDX                                                            1
+#define regVGA_MEMORY_BASE_ADDRESS                                                                      0x0004
+#define regVGA_MEMORY_BASE_ADDRESS_BASE_IDX                                                             1
+#define regVGA_DISPBUF1_SURFACE_ADDR                                                                    0x0006
+#define regVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_DISPBUF2_SURFACE_ADDR                                                                    0x0008
+#define regVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX                                                           1
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH                                                                 0x0009
+#define regVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX                                                        1
+#define regVGA_HDP_CONTROL                                                                              0x000a
+#define regVGA_HDP_CONTROL_BASE_IDX                                                                     1
+#define regVGA_CACHE_CONTROL                                                                            0x000b
+#define regVGA_CACHE_CONTROL_BASE_IDX                                                                   1
+#define regD1VGA_CONTROL                                                                                0x000c
+#define regD1VGA_CONTROL_BASE_IDX                                                                       1
+#define regD2VGA_CONTROL                                                                                0x000e
+#define regD2VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_STATUS                                                                                   0x0010
+#define regVGA_STATUS_BASE_IDX                                                                          1
+#define regVGA_INTERRUPT_CONTROL                                                                        0x0011
+#define regVGA_INTERRUPT_CONTROL_BASE_IDX                                                               1
+#define regVGA_STATUS_CLEAR                                                                             0x0012
+#define regVGA_STATUS_CLEAR_BASE_IDX                                                                    1
+#define regVGA_INTERRUPT_STATUS                                                                         0x0013
+#define regVGA_INTERRUPT_STATUS_BASE_IDX                                                                1
+#define regVGA_MAIN_CONTROL                                                                             0x0014
+#define regVGA_MAIN_CONTROL_BASE_IDX                                                                    1
+#define regVGA_TEST_CONTROL                                                                             0x0015
+#define regVGA_TEST_CONTROL_BASE_IDX                                                                    1
+#define regVGA_QOS_CTRL                                                                                 0x0018
+#define regVGA_QOS_CTRL_BASE_IDX                                                                        1
+#define regD3VGA_CONTROL                                                                                0x0038
+#define regD3VGA_CONTROL_BASE_IDX                                                                       1
+#define regD4VGA_CONTROL                                                                                0x0039
+#define regD4VGA_CONTROL_BASE_IDX                                                                       1
+#define regD5VGA_CONTROL                                                                                0x003a
+#define regD5VGA_CONTROL_BASE_IDX                                                                       1
+#define regD6VGA_CONTROL                                                                                0x003b
+#define regD6VGA_CONTROL_BASE_IDX                                                                       1
+#define regVGA_SOURCE_SELECT                                                                            0x003c
+#define regVGA_SOURCE_SELECT_BASE_IDX                                                                   1
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+// base address: 0x0
+#define regMCIF_CONTROL                                                                                 0x034a
+#define regMCIF_CONTROL_BASE_IDX                                                                        2
+#define regMCIF_WRITE_COMBINE_CONTROL                                                                   0x034b
+#define regMCIF_WRITE_COMBINE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER                                                              0x034e
+#define regMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER                                                              0x034f
+#define regMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER                                                              0x0350
+#define regMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+// base address: 0x0
+#define regMCIF_WB_BUFMGR_SW_CONTROL                                                                    0x0272
+#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_BUFMGR_STATUS                                                                        0x0274
+#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_PITCH                                                                            0x0275
+#define regMCIF_WB_BUF_PITCH_BASE_IDX                                                                   2
+#define regMCIF_WB_BUF_1_STATUS                                                                         0x0276
+#define regMCIF_WB_BUF_1_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_STATUS2                                                                        0x0277
+#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_2_STATUS                                                                         0x0278
+#define regMCIF_WB_BUF_2_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_STATUS2                                                                        0x0279
+#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_3_STATUS                                                                         0x027a
+#define regMCIF_WB_BUF_3_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_STATUS2                                                                        0x027b
+#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_4_STATUS                                                                         0x027c
+#define regMCIF_WB_BUF_4_STATUS_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_STATUS2                                                                        0x027d
+#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX                                                               2
+#define regMCIF_WB_ARBITRATION_CONTROL                                                                  0x027e
+#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SCLK_CHANGE                                                                          0x027f
+#define regMCIF_WB_SCLK_CHANGE_BASE_IDX                                                                 2
+#define regMCIF_WB_TEST_DEBUG_INDEX                                                                     0x0280
+#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX                                                            2
+#define regMCIF_WB_TEST_DEBUG_DATA                                                                      0x0281
+#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y                                                                         0x0282
+#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_1_ADDR_C                                                                         0x0284
+#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_Y                                                                         0x0286
+#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_2_ADDR_C                                                                         0x0288
+#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_Y                                                                         0x028a
+#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_3_ADDR_C                                                                         0x028c
+#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_Y                                                                         0x028e
+#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_4_ADDR_C                                                                         0x0290
+#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX                                                                2
+#define regMCIF_WB_BUFMGR_VCE_CONTROL                                                                   0x0292
+#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX                                                          2
+#define regMCIF_WB_NB_PSTATE_CONTROL                                                                    0x0293
+#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX                                                           2
+#define regMCIF_WB_CLOCK_GATER_CONTROL                                                                  0x0294
+#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX                                                         2
+#define regMCIF_WB_SELF_REFRESH_CONTROL                                                                 0x0296
+#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX                                                        2
+#define regMULTI_LEVEL_QOS_CTRL                                                                         0x0297
+#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX                                                                2
+#define regMCIF_WB_BUF_LUMA_SIZE                                                                        0x0299
+#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX                                                               2
+#define regMCIF_WB_BUF_CHROMA_SIZE                                                                      0x029a
+#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX                                                             2
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH                                                                    0x029b
+#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH                                                                    0x029c
+#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH                                                                    0x029d
+#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH                                                                    0x029e
+#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH                                                                    0x029f
+#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH                                                                    0x02a0
+#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH                                                                    0x02a1
+#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH                                                                    0x02a2
+#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX                                                           2
+#define regMCIF_WB_BUF_1_RESOLUTION                                                                     0x02a3
+#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_2_RESOLUTION                                                                     0x02a4
+#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_3_RESOLUTION                                                                     0x02a5
+#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_BUF_4_RESOLUTION                                                                     0x02a6
+#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX                                                            2
+#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI                                                       0x02a7
+#define regMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX                                              2
+#define regMCIF_WB_VMID_CONTROL                                                                         0x02a8
+#define regMCIF_WB_VMID_CONTROL_BASE_IDX                                                                2
+#define regMCIF_WB_MIN_TTO                                                                              0x02a9
+#define regMCIF_WB_MIN_TTO_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0xd48
+#define regDC_PERFMON4_PERFCOUNTER_CNTL                                                                 0x0352
+#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON4_PERFCOUNTER_CNTL2                                                                0x0353
+#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON4_PERFCOUNTER_STATE                                                                0x0354
+#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON4_PERFMON_CNTL                                                                     0x0355
+#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON4_PERFMON_CNTL2                                                                    0x0356
+#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC                                                          0x0357
+#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON4_PERFMON_CVALUE_LOW                                                               0x0358
+#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON4_PERFMON_HI                                                                       0x0359
+#define regDC_PERFMON4_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON4_PERFMON_LOW                                                                      0x035a
+#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+// base address: 0x0
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK                                                          0x02aa
+#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX                                                 2
+#define regMCIF_WB_WATERMARK                                                                            0x02ab
+#define regMCIF_WB_WATERMARK_BASE_IDX                                                                   2
+#define regMMHUBBUB_WARMUP_CONFIG                                                                       0x02ac
+#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX                                                              2
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS                                                               0x02ad
+#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW                                                                0x02ae
+#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX                                                       2
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH                                                               0x02af
+#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX                                                      2
+#define regMMHUBBUB_WARMUP_ADDR_REGION                                                                  0x02b0
+#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX                                                         2
+#define regMMHUBBUB_MIN_TTO                                                                             0x02b1
+#define regMMHUBBUB_MIN_TTO_BASE_IDX                                                                    2
+#define regMMHUBBUB_CTRL                                                                                0x0333
+#define regMMHUBBUB_CTRL_BASE_IDX                                                                       2
+#define regWBIF_SMU_WM_CONTROL                                                                          0x0334
+#define regWBIF_SMU_WM_CONTROL_BASE_IDX                                                                 2
+#define regWBIF0_MISC_CTRL                                                                              0x0335
+#define regWBIF0_MISC_CTRL_BASE_IDX                                                                     2
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER                                                             0x0336
+#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER                                                             0x0337
+#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX                                                    2
+#define regVGA_SRC_SPLIT_CNTL                                                                           0x033e
+#define regVGA_SRC_SPLIT_CNTL_BASE_IDX                                                                  2
+#define regMMHUBBUB_MEM_PWR_STATUS                                                                      0x033f
+#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regMMHUBBUB_MEM_PWR_CNTL                                                                        0x0340
+#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX                                                               2
+#define regMMHUBBUB_CLOCK_CNTL                                                                          0x0341
+#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regMMHUBBUB_SOFT_RESET                                                                          0x0342
+#define regMMHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDMU_IF_ERR_STATUS                                                                            0x0346
+#define regDMU_IF_ERR_STATUS_BASE_IDX                                                                   2
+#define regMMHUBBUB_CLIENT_UNIT_ID                                                                      0x0347
+#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX                                                             2
+#define regMMHUBBUB_WARMUP_VMID_CONTROL                                                                 0x0349
+#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+// base address: 0x0
+#define regAZALIA_CONTROLLER_CLOCK_GATING                                                               0x03c2
+#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX                                                      2
+#define regAZALIA_AUDIO_DTO                                                                             0x03c3
+#define regAZALIA_AUDIO_DTO_BASE_IDX                                                                    2
+#define regAZALIA_AUDIO_DTO_CONTROL                                                                     0x03c4
+#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX                                                            2
+#define regAZALIA_SOCCLK_CONTROL                                                                        0x03c5
+#define regAZALIA_SOCCLK_CONTROL_BASE_IDX                                                               2
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE                                                               0x03c6
+#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX                                                      2
+#define regAZALIA_DATA_DMA_CONTROL                                                                      0x03c7
+#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_BDL_DMA_CONTROL                                                                       0x03c8
+#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX                                                              2
+#define regAZALIA_RIRB_AND_DP_CONTROL                                                                   0x03c9
+#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX                                                          2
+#define regAZALIA_CORB_DMA_CONTROL                                                                      0x03ca
+#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX                                                             2
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER                                                 0x03d1
+#define regAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX                                        2
+#define regAZALIA_CYCLIC_BUFFER_SYNC                                                                    0x03d2
+#define regAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX                                                           2
+#define regAZALIA_GLOBAL_CAPABILITIES                                                                   0x03d3
+#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX                                                          2
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY                                                             0x03d4
+#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                    2
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL                                                         0x03d5
+#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX                                                2
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY                                                              0x03d6
+#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX                                                     2
+#define regAZALIA_INPUT_CRC0_CONTROL0                                                                   0x03d9
+#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL1                                                                   0x03da
+#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL2                                                                   0x03db
+#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_CONTROL3                                                                   0x03dc
+#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC0_RESULT                                                                     0x03dd
+#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX                                                            2
+#define regAZALIA_INPUT_CRC1_CONTROL0                                                                   0x03de
+#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL1                                                                   0x03df
+#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL2                                                                   0x03e0
+#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_CONTROL3                                                                   0x03e1
+#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX                                                          2
+#define regAZALIA_INPUT_CRC1_RESULT                                                                     0x03e2
+#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX                                                            2
+#define regAZALIA_CRC0_CONTROL0                                                                         0x03e3
+#define regAZALIA_CRC0_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL1                                                                         0x03e4
+#define regAZALIA_CRC0_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL2                                                                         0x03e5
+#define regAZALIA_CRC0_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC0_CONTROL3                                                                         0x03e6
+#define regAZALIA_CRC0_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC0_RESULT                                                                           0x03e7
+#define regAZALIA_CRC0_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_CRC1_CONTROL0                                                                         0x03e8
+#define regAZALIA_CRC1_CONTROL0_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL1                                                                         0x03e9
+#define regAZALIA_CRC1_CONTROL1_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL2                                                                         0x03ea
+#define regAZALIA_CRC1_CONTROL2_BASE_IDX                                                                2
+#define regAZALIA_CRC1_CONTROL3                                                                         0x03eb
+#define regAZALIA_CRC1_CONTROL3_BASE_IDX                                                                2
+#define regAZALIA_CRC1_RESULT                                                                           0x03ec
+#define regAZALIA_CRC1_RESULT_BASE_IDX                                                                  2
+#define regAZALIA_MEM_PWR_CTRL                                                                          0x03ee
+#define regAZALIA_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regAZALIA_MEM_PWR_STATUS                                                                        0x03ef
+#define regAZALIA_MEM_PWR_STATUS_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+// base address: 0x0
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0406
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX                                 2
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0407
+#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX                                          2
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL                                                        0x0408
+#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX                                               2
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL                                                          0x0409
+#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX                                                 2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x040a
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX                                       2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x040b
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX                             2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x040c
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX                                   2
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x040d
+#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX                                     2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x040e
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX                                        2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET                                                       0x040f
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX                                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x0410
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX                              2
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x0411
+#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX                          2
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY                                                            0x0412
+#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                   2
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                      0x0413
+#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                             2
+#define regAZALIA_F0_GTC_GROUP_OFFSET0                                                                  0x0415
+#define regAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET1                                                                  0x0416
+#define regAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET2                                                                  0x0417
+#define regAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET3                                                                  0x0418
+#define regAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET4                                                                  0x0419
+#define regAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET5                                                                  0x041a
+#define regAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX                                                         2
+#define regAZALIA_F0_GTC_GROUP_OFFSET6                                                                  0x041b
+#define regAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX                                                         2
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY                                                               0x041c
+#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX                                                      2
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY                                                         0x041d
+#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX                                                2
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+// base address: 0x0
+#define regAZ_CLOCK_CNTL                                                                                0x0372
+#define regAZ_CLOCK_CNTL_BASE_IDX                                                                       2
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+// base address: 0xde8
+#define regDC_PERFMON5_PERFCOUNTER_CNTL                                                                 0x037a
+#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON5_PERFCOUNTER_CNTL2                                                                0x037b
+#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON5_PERFCOUNTER_STATE                                                                0x037c
+#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON5_PERFMON_CNTL                                                                     0x037d
+#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON5_PERFMON_CNTL2                                                                    0x037e
+#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC                                                          0x037f
+#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON5_PERFMON_CVALUE_LOW                                                               0x0380
+#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON5_PERFMON_HI                                                                       0x0381
+#define regDC_PERFMON5_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON5_PERFMON_LOW                                                                      0x0382
+#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+// base address: 0x0
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX                                                              0x035e
+#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM0_AZALIA_STREAM_DATA                                                               0x035f
+#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+// base address: 0x8
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX                                                              0x0360
+#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM1_AZALIA_STREAM_DATA                                                               0x0361
+#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+// base address: 0x10
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX                                                              0x0362
+#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM2_AZALIA_STREAM_DATA                                                               0x0363
+#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+// base address: 0x18
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX                                                              0x0364
+#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM3_AZALIA_STREAM_DATA                                                               0x0365
+#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+// base address: 0x20
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX                                                              0x0366
+#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM4_AZALIA_STREAM_DATA                                                               0x0367
+#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+// base address: 0x28
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX                                                              0x0368
+#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM5_AZALIA_STREAM_DATA                                                               0x0369
+#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+// base address: 0x30
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX                                                              0x036a
+#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM6_AZALIA_STREAM_DATA                                                               0x036b
+#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+// base address: 0x38
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX                                                              0x036c
+#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM7_AZALIA_STREAM_DATA                                                               0x036d
+#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+// base address: 0x320
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX                                                              0x0426
+#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM8_AZALIA_STREAM_DATA                                                               0x0427
+#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+// base address: 0x328
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX                                                              0x0428
+#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX                                                     2
+#define regAZF0STREAM9_AZALIA_STREAM_DATA                                                               0x0429
+#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+// base address: 0x330
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX                                                             0x042a
+#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM10_AZALIA_STREAM_DATA                                                              0x042b
+#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+// base address: 0x338
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX                                                             0x042c
+#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM11_AZALIA_STREAM_DATA                                                              0x042d
+#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+// base address: 0x340
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX                                                             0x042e
+#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM12_AZALIA_STREAM_DATA                                                              0x042f
+#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+// base address: 0x348
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX                                                             0x0430
+#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM13_AZALIA_STREAM_DATA                                                              0x0431
+#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+// base address: 0x350
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX                                                             0x0432
+#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM14_AZALIA_STREAM_DATA                                                              0x0433
+#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+// base address: 0x358
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX                                                             0x0434
+#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX                                                    2
+#define regAZF0STREAM15_AZALIA_STREAM_DATA                                                              0x0435
+#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+// base address: 0x0
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0386
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0387
+#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+// base address: 0x18
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x038c
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x038d
+#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+// base address: 0x30
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0392
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0393
+#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+// base address: 0x48
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x0398
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x0399
+#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+// base address: 0x60
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x039e
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x039f
+#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+// base address: 0x78
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03a4
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03a5
+#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+// base address: 0x90
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03aa
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03ab
+#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+// base address: 0xa8
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX                                                 0x03b0
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX                                        2
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA                                                  0x03b1
+#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX                                         2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+// base address: 0x0
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043a
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043b
+#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+// base address: 0x10
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x043e
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x043f
+#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+// base address: 0x20
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0442
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0443
+#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+// base address: 0x30
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0446
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0447
+#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+// base address: 0x40
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044a
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044b
+#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+// base address: 0x50
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x044e
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x044f
+#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+// base address: 0x60
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0452
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0453
+#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+// base address: 0x70
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX                                      0x0456
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX                             2
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA                                       0x0457
+#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+// base address: 0x0
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND                                                                 0x04f9
+#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_SAT_LEVEL                                                                       0x04fa
+#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_QOS_FORCE                                                                       0x04fb
+#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX                                                              2
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL                                                                 0x04fc
+#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX                                                        2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A                                                        0x04fd
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A                                                     0x04fe
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A                                                      0x04ff
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A                                                   0x0500
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A                                                       0x0501
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A                                                    0x0502
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A                                               0x0503
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A                                                               0x0504
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A                                                              0x0505
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B                                                        0x0506
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B                                                     0x0507
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B                                                      0x0508
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B                                                   0x0509
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B                                                       0x050a
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B                                                    0x050b
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B                                               0x050c
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B                                                               0x050d
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B                                                              0x050e
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C                                                        0x050f
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C                                                     0x0510
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C                                                      0x0511
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C                                                   0x0512
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C                                                       0x0513
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C                                                    0x0514
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C                                               0x0515
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C                                                               0x0516
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C                                                              0x0517
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D                                                        0x0518
+#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX                                               2
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D                                                     0x0519
+#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX                                            2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D                                                      0x051a
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX                                             2
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D                                                   0x051b
+#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX                                          2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D                                                       0x051c
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX                                              2
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D                                                    0x051d
+#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX                                           2
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D                                               0x051e
+#define regDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D                                                               0x051f
+#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX                                                      2
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D                                                              0x0520
+#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX                                                     2
+#define regDCHUBBUB_ARB_HOSTVM_CNTL                                                                     0x0521
+#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX                                                            2
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL                                                           0x0522
+#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE                                                                  0x0523
+#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX                                                         2
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL                                                                   0x0524
+#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_LSB                                                                   0x0525
+#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK0_ADDRESS_MSB                                                                   0x0526
+#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_LSB                                                                   0x0527
+#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK1_ADDRESS_MSB                                                                   0x0528
+#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_LSB                                                                   0x0529
+#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK2_ADDRESS_MSB                                                                   0x052a
+#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_LSB                                                                   0x052b
+#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX                                                          2
+#define regSURFACE_CHECK3_ADDRESS_MSB                                                                   0x052c
+#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX                                                          2
+#define regVTG0_CONTROL                                                                                 0x052d
+#define regVTG0_CONTROL_BASE_IDX                                                                        2
+#define regVTG1_CONTROL                                                                                 0x052e
+#define regVTG1_CONTROL_BASE_IDX                                                                        2
+#define regVTG2_CONTROL                                                                                 0x052f
+#define regVTG2_CONTROL_BASE_IDX                                                                        2
+#define regVTG3_CONTROL                                                                                 0x0530
+#define regVTG3_CONTROL_BASE_IDX                                                                        2
+#define regDCHUBBUB_SOFT_RESET                                                                          0x0531
+#define regDCHUBBUB_SOFT_RESET_BASE_IDX                                                                 2
+#define regDCHUBBUB_CLOCK_CNTL                                                                          0x0532
+#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX                                                                 2
+#define regDCFCLK_CNTL                                                                                  0x0533
+#define regDCFCLK_CNTL_BASE_IDX                                                                         2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL                                                        0x0534
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX                                               2
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2                                                       0x0535
+#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX                                              2
+#define regDCHUBBUB_VLINE_SNAPSHOT                                                                      0x0536
+#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX                                                             2
+#define regDCHUBBUB_CTRL_STATUS                                                                         0x0537
+#define regDCHUBBUB_CTRL_STATUS_BASE_IDX                                                                2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1                                                             0x053d
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2                                                             0x053e
+#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX                                                    2
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS                                                            0x053f
+#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
+#define regFMON_CTRL                                                                                    0x0540
+#define regFMON_CTRL_BASE_IDX                                                                           2
+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x0541
+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x0542
+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+// base address: 0x0
+#define regDCHUBBUB_SDPIF_CFG0                                                                          0x046f
+#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG1                                                                          0x0470
+#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX                                                                 2
+#define regDCHUBBUB_SDPIF_CFG2                                                                          0x0471
+#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX                                                                 2
+#define regVM_REQUEST_PHYSICAL                                                                          0x0472
+#define regVM_REQUEST_PHYSICAL_BASE_IDX                                                                 2
+#define regDCHUBBUB_FORCE_IO_STATUS_0                                                                   0x0473
+#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX                                                          2
+#define regDCHUBBUB_FORCE_IO_STATUS_1                                                                   0x0474
+#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX                                                          2
+#define regDCN_VM_FB_LOCATION_BASE                                                                      0x0475
+#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX                                                             2
+#define regDCN_VM_FB_LOCATION_TOP                                                                       0x0476
+#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX                                                              2
+#define regDCN_VM_FB_OFFSET                                                                             0x0477
+#define regDCN_VM_FB_OFFSET_BASE_IDX                                                                    2
+#define regDCN_VM_AGP_BOT                                                                               0x0478
+#define regDCN_VM_AGP_BOT_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_TOP                                                                               0x0479
+#define regDCN_VM_AGP_TOP_BASE_IDX                                                                      2
+#define regDCN_VM_AGP_BASE                                                                              0x047a
+#define regDCN_VM_AGP_BASE_BASE_IDX                                                                     2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START                                                               0x047b
+#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                      2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END                                                                 0x047c
+#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                        2
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                           0x047d
+#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                  2
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL                                                                  0x0483
+#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX                                                         2
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS                                                                0x0484
+#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+// base address: 0x0
+#define regDCHUBBUB_RET_PATH_DCC_CFG                                                                    0x04af
+#define regDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX                                                           2
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_0                                                                 0x04b0
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_1                                                                 0x04b1
+#define regDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_0                                                                 0x04b2
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_1                                                                 0x04b3
+#define regDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_0                                                                 0x04b4
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_1                                                                 0x04b5
+#define regDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_0                                                                 0x04b6
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_1                                                                 0x04b7
+#define regDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_0                                                                 0x04b8
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_1                                                                 0x04b9
+#define regDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_0                                                                 0x04ba
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_1                                                                 0x04bb
+#define regDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_0                                                                 0x04bc
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_1                                                                 0x04bd
+#define regDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_0                                                                 0x04be
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_1                                                                 0x04bf
+#define regDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX                                                        2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL                                                               0x04c0
+#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX                                                      2
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS                                                             0x04c1
+#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX                                                    2
+#define regDCHUBBUB_CRC_CTRL                                                                            0x04c2
+#define regDCHUBBUB_CRC_CTRL_BASE_IDX                                                                   2
+#define regDCHUBBUB_CRC0_VAL_R_G                                                                        0x04c3
+#define regDCHUBBUB_CRC0_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC0_VAL_B_A                                                                        0x04c4
+#define regDCHUBBUB_CRC0_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_R_G                                                                        0x04c5
+#define regDCHUBBUB_CRC1_VAL_R_G_BASE_IDX                                                               2
+#define regDCHUBBUB_CRC1_VAL_B_A                                                                        0x04c6
+#define regDCHUBBUB_CRC1_VAL_B_A_BASE_IDX                                                               2
+#define regDCHUBBUB_DCC_STAT_CNTL                                                                       0x04c7
+#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX                                                              2
+#define regDCHUBBUB_DCC_STAT0                                                                           0x04c8
+#define regDCHUBBUB_DCC_STAT0_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT1                                                                           0x04c9
+#define regDCHUBBUB_DCC_STAT1_BASE_IDX                                                                  2
+#define regDCHUBBUB_DCC_STAT2                                                                           0x04ca
+#define regDCHUBBUB_DCC_STAT2_BASE_IDX                                                                  2
+#define regDCHUBBUB_COMPBUF_CTRL                                                                        0x04cb
+#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX                                                               2
+#define regDCHUBBUB_DET0_CTRL                                                                           0x04cc
+#define regDCHUBBUB_DET0_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET1_CTRL                                                                           0x04cd
+#define regDCHUBBUB_DET1_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET2_CTRL                                                                           0x04ce
+#define regDCHUBBUB_DET2_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_DET3_CTRL                                                                           0x04cf
+#define regDCHUBBUB_DET3_CTRL_BASE_IDX                                                                  2
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL                                                                   0x04d1
+#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX                                                          2
+#define regCOMPBUF_MEM_PWR_CTRL_1                                                                       0x04d2
+#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX                                                              2
+#define regCOMPBUF_MEM_PWR_CTRL_2                                                                       0x04d3
+#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX                                                              2
+#define regDCHUBBUB_MEM_PWR_STATUS                                                                      0x04d4
+#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX                                                             2
+#define regCOMPBUF_RESERVED_SPACE                                                                       0x04d5
+#define regCOMPBUF_RESERVED_SPACE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+// base address: 0x0
+#define regDCN_VM_CONTEXT0_CNTL                                                                         0x0559
+#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                    0x055a
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                    0x055b
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                   0x055c
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                   0x055d
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                     0x055e
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                     0x055f
+#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_CNTL                                                                         0x0560
+#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0561
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0562
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                   0x0563
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                   0x0564
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                     0x0565
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                     0x0566
+#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_CNTL                                                                         0x0567
+#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0568
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0569
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                   0x056a
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                   0x056b
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                     0x056c
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                     0x056d
+#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_CNTL                                                                         0x056e
+#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                    0x056f
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0570
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                   0x0571
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                   0x0572
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                     0x0573
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                     0x0574
+#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_CNTL                                                                         0x0575
+#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0576
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0577
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                   0x0578
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                   0x0579
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                     0x057a
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                     0x057b
+#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_CNTL                                                                         0x057c
+#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                    0x057d
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                    0x057e
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                   0x057f
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                   0x0580
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                     0x0581
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                     0x0582
+#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_CNTL                                                                         0x0583
+#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0584
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0585
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                   0x0586
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                   0x0587
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                     0x0588
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                     0x0589
+#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_CNTL                                                                         0x058a
+#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                    0x058b
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                    0x058c
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                   0x058d
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                   0x058e
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                     0x058f
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                     0x0590
+#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_CNTL                                                                         0x0591
+#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0592
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                    0x0593
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                   0x0594
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                   0x0595
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                     0x0596
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                     0x0597
+#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_CNTL                                                                         0x0598
+#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX                                                                2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                    0x0599
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                    0x059a
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                   0x059b
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                   0x059c
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                     0x059d
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                     0x059e
+#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                            2
+#define regDCN_VM_CONTEXT10_CNTL                                                                        0x059f
+#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a0
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a1
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                  0x05a2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                  0x05a3
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                    0x05a4
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                    0x05a5
+#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_CNTL                                                                        0x05a6
+#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05a7
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05a8
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                  0x05a9
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                  0x05aa
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                    0x05ab
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                    0x05ac
+#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_CNTL                                                                        0x05ad
+#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05ae
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05af
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                  0x05b0
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                  0x05b1
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                    0x05b2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                    0x05b3
+#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_CNTL                                                                        0x05b4
+#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05b5
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05b6
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                  0x05b7
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                  0x05b8
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                    0x05b9
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                    0x05ba
+#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_CNTL                                                                        0x05bb
+#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05bc
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05bd
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                  0x05be
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                  0x05bf
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                    0x05c0
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                    0x05c1
+#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_CNTL                                                                        0x05c2
+#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX                                                               2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                   0x05c3
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                   0x05c4
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                          2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                  0x05c5
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                  0x05c6
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                         2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                    0x05c7
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                           2
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                    0x05c8
+#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                           2
+#define regDCN_VM_DEFAULT_ADDR_MSB                                                                      0x05c9
+#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX                                                             2
+#define regDCN_VM_DEFAULT_ADDR_LSB                                                                      0x05ca
+#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX                                                             2
+#define regDCN_VM_FAULT_CNTL                                                                            0x05cb
+#define regDCN_VM_FAULT_CNTL_BASE_IDX                                                                   2
+#define regDCN_VM_FAULT_STATUS                                                                          0x05cc
+#define regDCN_VM_FAULT_STATUS_BASE_IDX                                                                 2
+#define regDCN_VM_FAULT_ADDR_MSB                                                                        0x05cd
+#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX                                                               2
+#define regDCN_VM_FAULT_ADDR_LSB                                                                        0x05ce
+#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1534
+#define regDC_PERFMON6_PERFCOUNTER_CNTL                                                                 0x054d
+#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON6_PERFCOUNTER_CNTL2                                                                0x054e
+#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON6_PERFCOUNTER_STATE                                                                0x054f
+#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON6_PERFMON_CNTL                                                                     0x0550
+#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON6_PERFMON_CNTL2                                                                    0x0551
+#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC                                                          0x0552
+#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON6_PERFMON_CVALUE_LOW                                                               0x0553
+#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON6_PERFMON_HI                                                                       0x0554
+#define regDC_PERFMON6_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON6_PERFMON_LOW                                                                      0x0555
+#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+// base address: 0x0
+#define regHUBP0_DCSURF_SURFACE_CONFIG                                                                  0x05e5
+#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP0_DCSURF_ADDR_CONFIG                                                                     0x05e6
+#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_DCSURF_TILING_CONFIG                                                                   0x05e7
+#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START                                                              0x05e9
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x05ea
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C                                                            0x05eb
+#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x05ec
+#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START                                                              0x05ed
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x05ee
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C                                                            0x05ef
+#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x05f0
+#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG                                                                 0x05f1
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x05f2
+#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP0_DCHUBP_CNTL                                                                            0x05f3
+#define regHUBP0_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP0_HUBP_CLK_CNTL                                                                          0x05f4
+#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP0_DCHUBP_VMPG_CONFIG                                                                     0x05f5
+#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP0_HUBPREQ_DEBUG_DB                                                                       0x05f6
+#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP0_HUBPREQ_DEBUG                                                                          0x05f7
+#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x05fb
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x05fc
+#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+// base address: 0x0
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH                                                                0x0607
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C                                                              0x0608
+#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ0_VMID_SETTINGS_0                                                                     0x0609
+#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x060a
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x060b
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x060c
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x060d
+#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x060e
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x060f
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x0610
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x0611
+#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x0612
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x0613
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x0614
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x0615
+#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x0616
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x0617
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x0618
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x0619
+#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL                                                              0x061a
+#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL                                                                 0x061b
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2                                                                0x061c
+#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x0620
+#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE                                                                0x0621
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH                                                           0x0622
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C                                                              0x0623
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0624
+#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0625
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0626
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0627
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0628
+#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ0_DCN_EXPANSION_MODE                                                                  0x0629
+#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_TTU_QOS_WM                                                                      0x062a
+#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL                                                                 0x062b
+#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0                                                                 0x062c
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1                                                                 0x062d
+#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0                                                                 0x062e
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1                                                                 0x062f
+#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0                                                                  0x0630
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1                                                                  0x0631
+#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0                                                                  0x0632
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1                                                                  0x0633
+#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL                                                                  0x0634
+#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0635
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0636
+#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL                                                               0x0643
+#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ0_BLANK_OFFSET_0                                                                      0x0644
+#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ0_BLANK_OFFSET_1                                                                      0x0645
+#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_DIMENSIONS                                                                      0x0646
+#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ0_DST_AFTER_SCALER                                                                    0x0647
+#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ0_PREFETCH_SETTINGS                                                                   0x0648
+#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ0_PREFETCH_SETTINGS_C                                                                 0x0649
+#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_0                                                                 0x064a
+#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_1                                                                 0x064b
+#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_2                                                                 0x064c
+#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_3                                                                 0x064d
+#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_4                                                                 0x064e
+#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_0                                                                   0x064f
+#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_1                                                                   0x0650
+#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_2                                                                   0x0651
+#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ0_NOM_PARAMETERS_0                                                                    0x0652
+#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_1                                                                    0x0653
+#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_2                                                                    0x0654
+#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_3                                                                    0x0655
+#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_4                                                                    0x0656
+#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_5                                                                    0x0657
+#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_6                                                                    0x0658
+#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ0_NOM_PARAMETERS_7                                                                    0x0659
+#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE                                                               0x065a
+#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ0_PER_LINE_DELIVERY                                                                   0x065b
+#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ0_CURSOR_SETTINGS                                                                     0x065c
+#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ                                                                0x065d
+#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT                                                               0x065e
+#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL                                                                0x065f
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS                                                              0x0660
+#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ0_VBLANK_PARAMETERS_5                                                                 0x0663
+#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ0_VBLANK_PARAMETERS_6                                                                 0x0664
+#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ0_FLIP_PARAMETERS_3                                                                   0x0665
+#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_4                                                                   0x0666
+#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_5                                                                   0x0667
+#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ0_FLIP_PARAMETERS_6                                                                   0x0668
+#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+// base address: 0x0
+#define regHUBPRET0_HUBPRET_CONTROL                                                                     0x066c
+#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL                                                                0x066d
+#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS                                                              0x066e
+#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0                                                             0x066f
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1                                                             0x0670
+#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE0                                                                  0x0671
+#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_READ_LINE1                                                                  0x0672
+#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET0_HUBPRET_INTERRUPT                                                                   0x0673
+#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE                                                             0x0674
+#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS                                                            0x0675
+#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+// base address: 0x0
+#define regCURSOR0_0_CURSOR_CONTROL                                                                     0x0678
+#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS                                                             0x0679
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x067a
+#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_0_CURSOR_SIZE                                                                        0x067b
+#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_0_CURSOR_POSITION                                                                    0x067c
+#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_HOT_SPOT                                                                    0x067d
+#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL                                                              0x067e
+#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_0_CURSOR_DST_OFFSET                                                                  0x067f
+#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL                                                                0x0680
+#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS                                                              0x0681
+#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH                                                                0x0682
+#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW                                                                 0x0683
+#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_0_DMDATA_CNTL                                                                        0x0684
+#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_0_DMDATA_QOS_CNTL                                                                    0x0685
+#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_0_DMDATA_STATUS                                                                      0x0686
+#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_0_DMDATA_SW_CNTL                                                                     0x0687
+#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_0_DMDATA_SW_DATA                                                                     0x0688
+#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a74
+#define regDC_PERFMON7_PERFCOUNTER_CNTL                                                                 0x069d
+#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON7_PERFCOUNTER_CNTL2                                                                0x069e
+#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON7_PERFCOUNTER_STATE                                                                0x069f
+#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON7_PERFMON_CNTL                                                                     0x06a0
+#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON7_PERFMON_CNTL2                                                                    0x06a1
+#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC                                                          0x06a2
+#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON7_PERFMON_CVALUE_LOW                                                               0x06a3
+#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON7_PERFMON_HI                                                                       0x06a4
+#define regDC_PERFMON7_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON7_PERFMON_LOW                                                                      0x06a5
+#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+// base address: 0x370
+#define regHUBP1_DCSURF_SURFACE_CONFIG                                                                  0x06c1
+#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP1_DCSURF_ADDR_CONFIG                                                                     0x06c2
+#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_DCSURF_TILING_CONFIG                                                                   0x06c3
+#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START                                                              0x06c5
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x06c6
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C                                                            0x06c7
+#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x06c8
+#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START                                                              0x06c9
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x06ca
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C                                                            0x06cb
+#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x06cc
+#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG                                                                 0x06cd
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x06ce
+#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP1_DCHUBP_CNTL                                                                            0x06cf
+#define regHUBP1_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP1_HUBP_CLK_CNTL                                                                          0x06d0
+#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP1_DCHUBP_VMPG_CONFIG                                                                     0x06d1
+#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP1_HUBPREQ_DEBUG_DB                                                                       0x06d2
+#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP1_HUBPREQ_DEBUG                                                                          0x06d3
+#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x06d7
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x06d8
+#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+// base address: 0x370
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH                                                                0x06e3
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C                                                              0x06e4
+#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ1_VMID_SETTINGS_0                                                                     0x06e5
+#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x06e6
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x06e7
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x06e8
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x06e9
+#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x06ea
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x06eb
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x06ec
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x06ed
+#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x06ee
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x06ef
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x06f0
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x06f1
+#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x06f2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x06f3
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x06f4
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x06f5
+#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL                                                              0x06f6
+#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL                                                                 0x06f7
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2                                                                0x06f8
+#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x06fc
+#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE                                                                0x06fd
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH                                                           0x06fe
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C                                                              0x06ff
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x0700
+#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x0701
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x0702
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x0703
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x0704
+#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ1_DCN_EXPANSION_MODE                                                                  0x0705
+#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_TTU_QOS_WM                                                                      0x0706
+#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL                                                                 0x0707
+#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0                                                                 0x0708
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1                                                                 0x0709
+#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0                                                                 0x070a
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1                                                                 0x070b
+#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0                                                                  0x070c
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1                                                                  0x070d
+#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0                                                                  0x070e
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1                                                                  0x070f
+#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL                                                                  0x0710
+#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x0711
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x0712
+#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL                                                               0x071f
+#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ1_BLANK_OFFSET_0                                                                      0x0720
+#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ1_BLANK_OFFSET_1                                                                      0x0721
+#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_DIMENSIONS                                                                      0x0722
+#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ1_DST_AFTER_SCALER                                                                    0x0723
+#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ1_PREFETCH_SETTINGS                                                                   0x0724
+#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ1_PREFETCH_SETTINGS_C                                                                 0x0725
+#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_0                                                                 0x0726
+#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_1                                                                 0x0727
+#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_2                                                                 0x0728
+#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_3                                                                 0x0729
+#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_4                                                                 0x072a
+#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_0                                                                   0x072b
+#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_1                                                                   0x072c
+#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_2                                                                   0x072d
+#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ1_NOM_PARAMETERS_0                                                                    0x072e
+#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_1                                                                    0x072f
+#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_2                                                                    0x0730
+#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_3                                                                    0x0731
+#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_4                                                                    0x0732
+#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_5                                                                    0x0733
+#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_6                                                                    0x0734
+#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ1_NOM_PARAMETERS_7                                                                    0x0735
+#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE                                                               0x0736
+#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ1_PER_LINE_DELIVERY                                                                   0x0737
+#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ1_CURSOR_SETTINGS                                                                     0x0738
+#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ                                                                0x0739
+#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT                                                               0x073a
+#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL                                                                0x073b
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS                                                              0x073c
+#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ1_VBLANK_PARAMETERS_5                                                                 0x073f
+#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ1_VBLANK_PARAMETERS_6                                                                 0x0740
+#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ1_FLIP_PARAMETERS_3                                                                   0x0741
+#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_4                                                                   0x0742
+#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_5                                                                   0x0743
+#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ1_FLIP_PARAMETERS_6                                                                   0x0744
+#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+// base address: 0x370
+#define regHUBPRET1_HUBPRET_CONTROL                                                                     0x0748
+#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL                                                                0x0749
+#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS                                                              0x074a
+#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0                                                             0x074b
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1                                                             0x074c
+#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE0                                                                  0x074d
+#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_READ_LINE1                                                                  0x074e
+#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET1_HUBPRET_INTERRUPT                                                                   0x074f
+#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE                                                             0x0750
+#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS                                                            0x0751
+#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+// base address: 0x370
+#define regCURSOR0_1_CURSOR_CONTROL                                                                     0x0754
+#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS                                                             0x0755
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0756
+#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_1_CURSOR_SIZE                                                                        0x0757
+#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_1_CURSOR_POSITION                                                                    0x0758
+#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_HOT_SPOT                                                                    0x0759
+#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL                                                              0x075a
+#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_1_CURSOR_DST_OFFSET                                                                  0x075b
+#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL                                                                0x075c
+#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS                                                              0x075d
+#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH                                                                0x075e
+#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW                                                                 0x075f
+#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_1_DMDATA_CNTL                                                                        0x0760
+#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_1_DMDATA_QOS_CNTL                                                                    0x0761
+#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_1_DMDATA_STATUS                                                                      0x0762
+#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_1_DMDATA_SW_CNTL                                                                     0x0763
+#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_1_DMDATA_SW_DATA                                                                     0x0764
+#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1de4
+#define regDC_PERFMON8_PERFCOUNTER_CNTL                                                                 0x0779
+#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON8_PERFCOUNTER_CNTL2                                                                0x077a
+#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON8_PERFCOUNTER_STATE                                                                0x077b
+#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON8_PERFMON_CNTL                                                                     0x077c
+#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON8_PERFMON_CNTL2                                                                    0x077d
+#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC                                                          0x077e
+#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON8_PERFMON_CVALUE_LOW                                                               0x077f
+#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON8_PERFMON_HI                                                                       0x0780
+#define regDC_PERFMON8_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON8_PERFMON_LOW                                                                      0x0781
+#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+// base address: 0x6e0
+#define regHUBP2_DCSURF_SURFACE_CONFIG                                                                  0x079d
+#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP2_DCSURF_ADDR_CONFIG                                                                     0x079e
+#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_DCSURF_TILING_CONFIG                                                                   0x079f
+#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START                                                              0x07a1
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x07a2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C                                                            0x07a3
+#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x07a4
+#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START                                                              0x07a5
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x07a6
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C                                                            0x07a7
+#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x07a8
+#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG                                                                 0x07a9
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x07aa
+#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP2_DCHUBP_CNTL                                                                            0x07ab
+#define regHUBP2_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP2_HUBP_CLK_CNTL                                                                          0x07ac
+#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP2_DCHUBP_VMPG_CONFIG                                                                     0x07ad
+#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP2_HUBPREQ_DEBUG_DB                                                                       0x07ae
+#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP2_HUBPREQ_DEBUG                                                                          0x07af
+#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x07b3
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x07b4
+#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+// base address: 0x6e0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH                                                                0x07bf
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C                                                              0x07c0
+#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ2_VMID_SETTINGS_0                                                                     0x07c1
+#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x07c2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x07c3
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x07c4
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x07c5
+#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x07c6
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x07c7
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x07c8
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x07c9
+#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x07ca
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x07cb
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x07cc
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x07cd
+#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x07ce
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x07cf
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x07d0
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x07d1
+#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL                                                              0x07d2
+#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL                                                                 0x07d3
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2                                                                0x07d4
+#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x07d8
+#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE                                                                0x07d9
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH                                                           0x07da
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C                                                              0x07db
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x07dc
+#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x07dd
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x07de
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x07df
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x07e0
+#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ2_DCN_EXPANSION_MODE                                                                  0x07e1
+#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_TTU_QOS_WM                                                                      0x07e2
+#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL                                                                 0x07e3
+#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0                                                                 0x07e4
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1                                                                 0x07e5
+#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0                                                                 0x07e6
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1                                                                 0x07e7
+#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0                                                                  0x07e8
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1                                                                  0x07e9
+#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0                                                                  0x07ea
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1                                                                  0x07eb
+#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL                                                                  0x07ec
+#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x07ed
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x07ee
+#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL                                                               0x07fb
+#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ2_BLANK_OFFSET_0                                                                      0x07fc
+#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ2_BLANK_OFFSET_1                                                                      0x07fd
+#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_DIMENSIONS                                                                      0x07fe
+#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ2_DST_AFTER_SCALER                                                                    0x07ff
+#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ2_PREFETCH_SETTINGS                                                                   0x0800
+#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ2_PREFETCH_SETTINGS_C                                                                 0x0801
+#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_0                                                                 0x0802
+#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_1                                                                 0x0803
+#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_2                                                                 0x0804
+#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_3                                                                 0x0805
+#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_4                                                                 0x0806
+#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_0                                                                   0x0807
+#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_1                                                                   0x0808
+#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_2                                                                   0x0809
+#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ2_NOM_PARAMETERS_0                                                                    0x080a
+#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_1                                                                    0x080b
+#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_2                                                                    0x080c
+#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_3                                                                    0x080d
+#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_4                                                                    0x080e
+#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_5                                                                    0x080f
+#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_6                                                                    0x0810
+#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ2_NOM_PARAMETERS_7                                                                    0x0811
+#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE                                                               0x0812
+#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ2_PER_LINE_DELIVERY                                                                   0x0813
+#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ2_CURSOR_SETTINGS                                                                     0x0814
+#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ                                                                0x0815
+#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT                                                               0x0816
+#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL                                                                0x0817
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS                                                              0x0818
+#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ2_VBLANK_PARAMETERS_5                                                                 0x081b
+#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ2_VBLANK_PARAMETERS_6                                                                 0x081c
+#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ2_FLIP_PARAMETERS_3                                                                   0x081d
+#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_4                                                                   0x081e
+#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_5                                                                   0x081f
+#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ2_FLIP_PARAMETERS_6                                                                   0x0820
+#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+// base address: 0x6e0
+#define regHUBPRET2_HUBPRET_CONTROL                                                                     0x0824
+#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL                                                                0x0825
+#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS                                                              0x0826
+#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0                                                             0x0827
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1                                                             0x0828
+#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE0                                                                  0x0829
+#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_READ_LINE1                                                                  0x082a
+#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET2_HUBPRET_INTERRUPT                                                                   0x082b
+#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE                                                             0x082c
+#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS                                                            0x082d
+#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+// base address: 0x6e0
+#define regCURSOR0_2_CURSOR_CONTROL                                                                     0x0830
+#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS                                                             0x0831
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x0832
+#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_2_CURSOR_SIZE                                                                        0x0833
+#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_2_CURSOR_POSITION                                                                    0x0834
+#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_HOT_SPOT                                                                    0x0835
+#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL                                                              0x0836
+#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_2_CURSOR_DST_OFFSET                                                                  0x0837
+#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL                                                                0x0838
+#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS                                                              0x0839
+#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH                                                                0x083a
+#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW                                                                 0x083b
+#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_2_DMDATA_CNTL                                                                        0x083c
+#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_2_DMDATA_QOS_CNTL                                                                    0x083d
+#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_2_DMDATA_STATUS                                                                      0x083e
+#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_2_DMDATA_SW_CNTL                                                                     0x083f
+#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_2_DMDATA_SW_DATA                                                                     0x0840
+#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x2154
+#define regDC_PERFMON9_PERFCOUNTER_CNTL                                                                 0x0855
+#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX                                                        2
+#define regDC_PERFMON9_PERFCOUNTER_CNTL2                                                                0x0856
+#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX                                                       2
+#define regDC_PERFMON9_PERFCOUNTER_STATE                                                                0x0857
+#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX                                                       2
+#define regDC_PERFMON9_PERFMON_CNTL                                                                     0x0858
+#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX                                                            2
+#define regDC_PERFMON9_PERFMON_CNTL2                                                                    0x0859
+#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX                                                           2
+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC                                                          0x085a
+#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                 2
+#define regDC_PERFMON9_PERFMON_CVALUE_LOW                                                               0x085b
+#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX                                                      2
+#define regDC_PERFMON9_PERFMON_HI                                                                       0x085c
+#define regDC_PERFMON9_PERFMON_HI_BASE_IDX                                                              2
+#define regDC_PERFMON9_PERFMON_LOW                                                                      0x085d
+#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+// base address: 0xa50
+#define regHUBP3_DCSURF_SURFACE_CONFIG                                                                  0x0879
+#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX                                                         2
+#define regHUBP3_DCSURF_ADDR_CONFIG                                                                     0x087a
+#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_DCSURF_TILING_CONFIG                                                                   0x087b
+#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX                                                          2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START                                                              0x087d
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x087e
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C                                                            0x087f
+#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C                                                        0x0880
+#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START                                                              0x0881
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX                                                     2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION                                                          0x0882
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX                                                 2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C                                                            0x0883
+#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX                                                   2
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C                                                        0x0884
+#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX                                               2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG                                                                 0x0885
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX                                                        2
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C                                                               0x0886
+#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX                                                      2
+#define regHUBP3_DCHUBP_CNTL                                                                            0x0887
+#define regHUBP3_DCHUBP_CNTL_BASE_IDX                                                                   2
+#define regHUBP3_HUBP_CLK_CNTL                                                                          0x0888
+#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX                                                                 2
+#define regHUBP3_DCHUBP_VMPG_CONFIG                                                                     0x0889
+#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX                                                            2
+#define regHUBP3_HUBPREQ_DEBUG_DB                                                                       0x088a
+#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX                                                              2
+#define regHUBP3_HUBPREQ_DEBUG                                                                          0x088b
+#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX                                                                 2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK                                                           0x088f
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX                                                  2
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK                                                           0x0890
+#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+// base address: 0xa50
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH                                                                0x089b
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C                                                              0x089c
+#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX                                                     2
+#define regHUBPREQ3_VMID_SETTINGS_0                                                                     0x089d
+#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX                                                            2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS                                                      0x089e
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX                                             2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH                                                 0x089f
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C                                                    0x08a0
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C                                               0x08a1
+#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS                                                    0x08a2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX                                           2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH                                               0x08a3
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C                                                  0x08a4
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C                                             0x08a5
+#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS                                                 0x08a6
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX                                        2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH                                            0x08a7
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                   2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C                                               0x08a8
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C                                          0x08a9
+#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS                                               0x08aa
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX                                      2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH                                          0x08ab
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX                                 2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C                                             0x08ac
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX                                    2
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C                                        0x08ad
+#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX                               2
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL                                                              0x08ae
+#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL                                                                 0x08af
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2                                                                0x08b0
+#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT                                                       0x08b4
+#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE                                                                0x08b5
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX                                                       2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH                                                           0x08b6
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX                                                  2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C                                                              0x08b7
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX                                                     2
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C                                                         0x08b8
+#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX                                                2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE                                                       0x08b9
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX                                              2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH                                                  0x08ba
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX                                         2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C                                                     0x08bb
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX                                            2
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C                                                0x08bc
+#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX                                       2
+#define regHUBPREQ3_DCN_EXPANSION_MODE                                                                  0x08bd
+#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_TTU_QOS_WM                                                                      0x08be
+#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX                                                             2
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL                                                                 0x08bf
+#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0                                                                 0x08c0
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1                                                                 0x08c1
+#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0                                                                 0x08c2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1                                                                 0x08c3
+#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX                                                        2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0                                                                  0x08c4
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1                                                                  0x08c5
+#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0                                                                  0x08c6
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1                                                                  0x08c7
+#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL                                                                  0x08c8
+#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX                                                         2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR                                                     0x08c9
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                            2
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR                                                    0x08ca
+#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                           2
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL                                                               0x08d7
+#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX                                                      2
+#define regHUBPREQ3_BLANK_OFFSET_0                                                                      0x08d8
+#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX                                                             2
+#define regHUBPREQ3_BLANK_OFFSET_1                                                                      0x08d9
+#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_DIMENSIONS                                                                      0x08da
+#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX                                                             2
+#define regHUBPREQ3_DST_AFTER_SCALER                                                                    0x08db
+#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX                                                           2
+#define regHUBPREQ3_PREFETCH_SETTINGS                                                                   0x08dc
+#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX                                                          2
+#define regHUBPREQ3_PREFETCH_SETTINGS_C                                                                 0x08dd
+#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_0                                                                 0x08de
+#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_1                                                                 0x08df
+#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_2                                                                 0x08e0
+#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_3                                                                 0x08e1
+#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4                                                                 0x08e2
+#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_0                                                                   0x08e3
+#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_1                                                                   0x08e4
+#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_2                                                                   0x08e5
+#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX                                                          2
+#define regHUBPREQ3_NOM_PARAMETERS_0                                                                    0x08e6
+#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_1                                                                    0x08e7
+#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_2                                                                    0x08e8
+#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_3                                                                    0x08e9
+#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_4                                                                    0x08ea
+#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_5                                                                    0x08eb
+#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_6                                                                    0x08ec
+#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX                                                           2
+#define regHUBPREQ3_NOM_PARAMETERS_7                                                                    0x08ed
+#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX                                                           2
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE                                                               0x08ee
+#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX                                                      2
+#define regHUBPREQ3_PER_LINE_DELIVERY                                                                   0x08ef
+#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX                                                          2
+#define regHUBPREQ3_CURSOR_SETTINGS                                                                     0x08f0
+#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX                                                            2
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ                                                                0x08f1
+#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX                                                       2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT                                                               0x08f2
+#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX                                                      2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL                                                                0x08f3
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS                                                              0x08f4
+#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPREQ3_VBLANK_PARAMETERS_5                                                                 0x08f7
+#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX                                                        2
+#define regHUBPREQ3_VBLANK_PARAMETERS_6                                                                 0x08f8
+#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX                                                        2
+#define regHUBPREQ3_FLIP_PARAMETERS_3                                                                   0x08f9
+#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_4                                                                   0x08fa
+#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_5                                                                   0x08fb
+#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX                                                          2
+#define regHUBPREQ3_FLIP_PARAMETERS_6                                                                   0x08fc
+#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+// base address: 0xa50
+#define regHUBPRET3_HUBPRET_CONTROL                                                                     0x0900
+#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX                                                            2
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL                                                                0x0901
+#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS                                                              0x0902
+#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0                                                             0x0903
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1                                                             0x0904
+#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE0                                                                  0x0905
+#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_READ_LINE1                                                                  0x0906
+#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX                                                         2
+#define regHUBPRET3_HUBPRET_INTERRUPT                                                                   0x0907
+#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX                                                          2
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE                                                             0x0908
+#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX                                                    2
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS                                                            0x0909
+#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+// base address: 0xa50
+#define regCURSOR0_3_CURSOR_CONTROL                                                                     0x090c
+#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX                                                            2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS                                                             0x090d
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX                                                    2
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH                                                        0x090e
+#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX                                               2
+#define regCURSOR0_3_CURSOR_SIZE                                                                        0x090f
+#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX                                                               2
+#define regCURSOR0_3_CURSOR_POSITION                                                                    0x0910
+#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_HOT_SPOT                                                                    0x0911
+#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX                                                           2
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL                                                              0x0912
+#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX                                                     2
+#define regCURSOR0_3_CURSOR_DST_OFFSET                                                                  0x0913
+#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX                                                         2
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL                                                                0x0914
+#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX                                                       2
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS                                                              0x0915
+#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX                                                     2
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH                                                                0x0916
+#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX                                                       2
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW                                                                 0x0917
+#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX                                                        2
+#define regCURSOR0_3_DMDATA_CNTL                                                                        0x0918
+#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX                                                               2
+#define regCURSOR0_3_DMDATA_QOS_CNTL                                                                    0x0919
+#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX                                                           2
+#define regCURSOR0_3_DMDATA_STATUS                                                                      0x091a
+#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX                                                             2
+#define regCURSOR0_3_DMDATA_SW_CNTL                                                                     0x091b
+#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX                                                            2
+#define regCURSOR0_3_DMDATA_SW_DATA                                                                     0x091c
+#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x24c4
+#define regDC_PERFMON10_PERFCOUNTER_CNTL                                                                0x0931
+#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON10_PERFCOUNTER_CNTL2                                                               0x0932
+#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON10_PERFCOUNTER_STATE                                                               0x0933
+#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON10_PERFMON_CNTL                                                                    0x0934
+#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON10_PERFMON_CNTL2                                                                   0x0935
+#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC                                                         0x0936
+#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON10_PERFMON_CVALUE_LOW                                                              0x0937
+#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON10_PERFMON_HI                                                                      0x0938
+#define regDC_PERFMON10_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON10_PERFMON_LOW                                                                     0x0939
+#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+// base address: 0x0
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0ccf
+#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG0_FORMAT_CONTROL                                                                     0x0cd0
+#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_R                                                                     0x0cd1
+#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G                                                                     0x0cd2
+#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_BIAS_B                                                                     0x0cd3
+#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG0_FCNV_FP_SCALE_R                                                                    0x0cd4
+#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_G                                                                    0x0cd5
+#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG0_FCNV_FP_SCALE_B                                                                    0x0cd6
+#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL                                                                0x0cd7
+#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA                                                                  0x0cd8
+#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_RED                                                                    0x0cd9
+#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG0_COLOR_KEYER_GREEN                                                                  0x0cda
+#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG0_COLOR_KEYER_BLUE                                                                   0x0cdb
+#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG0_ALPHA_2BIT_LUT                                                                     0x0cdd
+#define regCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG0_PRE_DEALPHA                                                                        0x0cde
+#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG0_PRE_CSC_MODE                                                                       0x0cdf
+#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG0_PRE_CSC_C11_C12                                                                    0x0ce0
+#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C13_C14                                                                    0x0ce1
+#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C21_C22                                                                    0x0ce2
+#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C23_C24                                                                    0x0ce3
+#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C31_C32                                                                    0x0ce4
+#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_C33_C34                                                                    0x0ce5
+#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12                                                                  0x0ce6
+#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14                                                                  0x0ce7
+#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22                                                                  0x0ce8
+#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24                                                                  0x0ce9
+#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32                                                                  0x0cea
+#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34                                                                  0x0ceb
+#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG0_CNVC_COEF_FORMAT                                                                   0x0cec
+#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG0_PRE_DEGAM                                                                          0x0ced
+#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG0_PRE_REALPHA                                                                        0x0cee
+#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+// base address: 0x0
+#define regCNVC_CUR0_CURSOR0_CONTROL                                                                    0x0cf1
+#define regCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR0_CURSOR0_COLOR0                                                                     0x0cf2
+#define regCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_COLOR1                                                                     0x0cf3
+#define regCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS                                                              0x0cf4
+#define regCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+// base address: 0x0
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT                                                                0x0cf9
+#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA                                                                  0x0cfa
+#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL0_SCL_MODE                                                                               0x0cfb
+#define regDSCL0_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL0_SCL_TAP_CONTROL                                                                        0x0cfc
+#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL0_DSCL_CONTROL                                                                           0x0cfd
+#define regDSCL0_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_2TAP_CONTROL                                                                      0x0cfe
+#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0cff
+#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0d00
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_HORZ_FILTER_INIT                                                                   0x0d01
+#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0d02
+#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C                                                                 0x0d03
+#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0d04
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL0_SCL_VERT_FILTER_INIT                                                                   0x0d05
+#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT                                                               0x0d06
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0d07
+#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL0_SCL_VERT_FILTER_INIT_C                                                                 0x0d08
+#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0d09
+#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL0_SCL_BLACK_COLOR                                                                        0x0d0a
+#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL0_DSCL_UPDATE                                                                            0x0d0b
+#define regDSCL0_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL0_DSCL_AUTOCAL                                                                           0x0d0c
+#define regDSCL0_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0d0d
+#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0d0e
+#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL0_OTG_H_BLANK                                                                            0x0d0f
+#define regDSCL0_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_OTG_V_BLANK                                                                            0x0d10
+#define regDSCL0_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL0_RECOUT_START                                                                           0x0d11
+#define regDSCL0_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL0_RECOUT_SIZE                                                                            0x0d12
+#define regDSCL0_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL0_MPC_SIZE                                                                               0x0d13
+#define regDSCL0_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL0_LB_DATA_FORMAT                                                                         0x0d14
+#define regDSCL0_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL0_LB_MEMORY_CTRL                                                                         0x0d15
+#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL0_LB_V_COUNTER                                                                           0x0d16
+#define regDSCL0_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL0_DSCL_MEM_PWR_CTRL                                                                      0x0d17
+#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL0_DSCL_MEM_PWR_STATUS                                                                    0x0d18
+#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL0_OBUF_CONTROL                                                                           0x0d19
+#define regDSCL0_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL0_OBUF_MEM_PWR_CTRL                                                                      0x0d1a
+#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+// base address: 0x0
+#define regCM0_CM_CONTROL                                                                               0x0d20
+#define regCM0_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM0_CM_POST_CSC_CONTROL                                                                      0x0d21
+#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C11_C12                                                                      0x0d22
+#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C13_C14                                                                      0x0d23
+#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C21_C22                                                                      0x0d24
+#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C23_C24                                                                      0x0d25
+#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C31_C32                                                                      0x0d26
+#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_C33_C34                                                                      0x0d27
+#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM0_CM_POST_CSC_B_C11_C12                                                                    0x0d28
+#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C13_C14                                                                    0x0d29
+#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C21_C22                                                                    0x0d2a
+#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C23_C24                                                                    0x0d2b
+#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C31_C32                                                                    0x0d2c
+#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM0_CM_POST_CSC_B_C33_C34                                                                    0x0d2d
+#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM0_CM_GAMUT_REMAP_CONTROL                                                                   0x0d2e
+#define regCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C11_C12                                                                   0x0d2f
+#define regCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C13_C14                                                                   0x0d30
+#define regCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C21_C22                                                                   0x0d31
+#define regCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C23_C24                                                                   0x0d32
+#define regCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C31_C32                                                                   0x0d33
+#define regCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_C33_C34                                                                   0x0d34
+#define regCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0d35
+#define regCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0d36
+#define regCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0d37
+#define regCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0d38
+#define regCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0d39
+#define regCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0d3a
+#define regCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM0_CM_BIAS_CR_R                                                                             0x0d3b
+#define regCM0_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM0_CM_BIAS_Y_G_CB_B                                                                         0x0d3c
+#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM0_CM_GAMCOR_CONTROL                                                                        0x0d3d
+#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_GAMCOR_LUT_INDEX                                                                      0x0d3e
+#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_GAMCOR_LUT_DATA                                                                       0x0d3f
+#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_GAMCOR_LUT_CONTROL                                                                    0x0d40
+#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0d41
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0d42
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0d43
+#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0d44
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0d45
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0d46
+#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0d47
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0d48
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0d49
+#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0d4a
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0d4b
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0d4c
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0d4d
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0d4e
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0d4f
+#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0d50
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0d51
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0d52
+#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0d53
+#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0d54
+#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0d55
+#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0d56
+#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0d57
+#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0d58
+#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0d59
+#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0d5a
+#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0d5b
+#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0d5c
+#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0d5d
+#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0d5e
+#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0d5f
+#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0d60
+#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0d61
+#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0d62
+#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0d63
+#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0d64
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0d65
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0d66
+#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0d67
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0d68
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0d69
+#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0d6a
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0d6b
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0d6c
+#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0d6d
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0d6e
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0d6f
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0d70
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0d71
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0d72
+#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0d73
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0d74
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0d75
+#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0d76
+#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0d77
+#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0d78
+#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0d79
+#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0d7a
+#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0d7b
+#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0d7c
+#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0d7d
+#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0d7e
+#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0d7f
+#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0d80
+#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0d81
+#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0d82
+#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0d83
+#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0d84
+#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0d85
+#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0d86
+#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_CONTROL                                                                       0x0d87
+#define regCM0_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM0_CM_BLNDGAM_LUT_INDEX                                                                     0x0d88
+#define regCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM0_CM_BLNDGAM_LUT_DATA                                                                      0x0d89
+#define regCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM0_CM_BLNDGAM_LUT_CONTROL                                                                   0x0d8a
+#define regCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0d8b
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0d8c
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0d8d
+#define regCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0d8e
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0d8f
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0d90
+#define regCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0d91
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0d92
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0d93
+#define regCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0d94
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0d95
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0d96
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0d97
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0d98
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0d99
+#define regCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0d9a
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0d9b
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0d9c
+#define regCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0d9d
+#define regCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0d9e
+#define regCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0d9f
+#define regCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0da0
+#define regCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0da1
+#define regCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0da2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0da3
+#define regCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0da4
+#define regCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0da5
+#define regCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0da6
+#define regCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0da7
+#define regCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0da8
+#define regCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0da9
+#define regCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0daa
+#define regCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0dab
+#define regCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0dac
+#define regCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0dad
+#define regCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0dae
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0daf
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0db0
+#define regCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0db1
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0db2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0db3
+#define regCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0db4
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0db5
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0db6
+#define regCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0db7
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0db8
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0db9
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0dba
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0dbb
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0dbc
+#define regCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0dbd
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0dbe
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0dbf
+#define regCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0dc0
+#define regCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0dc1
+#define regCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0dc2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0dc3
+#define regCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0dc4
+#define regCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0dc5
+#define regCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0dc6
+#define regCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0dc7
+#define regCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0dc8
+#define regCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0dc9
+#define regCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0dca
+#define regCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0dcb
+#define regCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0dcc
+#define regCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0dcd
+#define regCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0dce
+#define regCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0dcf
+#define regCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0dd0
+#define regCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM0_CM_HDR_MULT_COEF                                                                         0x0dd1
+#define regCM0_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_CTRL                                                                          0x0dd2
+#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM0_CM_MEM_PWR_STATUS                                                                        0x0dd3
+#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM0_CM_DEALPHA                                                                               0x0dd5
+#define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM0_CM_COEF_FORMAT                                                                           0x0dd6
+#define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM0_CM_SHAPER_CONTROL                                                                        0x0dd7
+#define regCM0_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM0_CM_SHAPER_OFFSET_R                                                                       0x0dd8
+#define regCM0_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_OFFSET_G                                                                       0x0dd9
+#define regCM0_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_OFFSET_B                                                                       0x0dda
+#define regCM0_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_SCALE_R                                                                        0x0ddb
+#define regCM0_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM0_CM_SHAPER_SCALE_G_B                                                                      0x0ddc
+#define regCM0_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM0_CM_SHAPER_LUT_INDEX                                                                      0x0ddd
+#define regCM0_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_SHAPER_LUT_DATA                                                                       0x0dde
+#define regCM0_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0ddf
+#define regCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0de0
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0de1
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0de2
+#define regCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0de3
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0de4
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0de5
+#define regCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_0_1                                                                0x0de6
+#define regCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_2_3                                                                0x0de7
+#define regCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_4_5                                                                0x0de8
+#define regCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_6_7                                                                0x0de9
+#define regCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_8_9                                                                0x0dea
+#define regCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMA_REGION_10_11                                                              0x0deb
+#define regCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_12_13                                                              0x0dec
+#define regCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_14_15                                                              0x0ded
+#define regCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_16_17                                                              0x0dee
+#define regCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_18_19                                                              0x0def
+#define regCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_20_21                                                              0x0df0
+#define regCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_22_23                                                              0x0df1
+#define regCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_24_25                                                              0x0df2
+#define regCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_26_27                                                              0x0df3
+#define regCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_28_29                                                              0x0df4
+#define regCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_30_31                                                              0x0df5
+#define regCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMA_REGION_32_33                                                              0x0df6
+#define regCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0df7
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0df8
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0df9
+#define regCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0dfa
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0dfb
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0dfc
+#define regCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_0_1                                                                0x0dfd
+#define regCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_2_3                                                                0x0dfe
+#define regCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_4_5                                                                0x0dff
+#define regCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_6_7                                                                0x0e00
+#define regCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_8_9                                                                0x0e01
+#define regCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM0_CM_SHAPER_RAMB_REGION_10_11                                                              0x0e02
+#define regCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_12_13                                                              0x0e03
+#define regCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_14_15                                                              0x0e04
+#define regCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_16_17                                                              0x0e05
+#define regCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_18_19                                                              0x0e06
+#define regCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_20_21                                                              0x0e07
+#define regCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_22_23                                                              0x0e08
+#define regCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_24_25                                                              0x0e09
+#define regCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_26_27                                                              0x0e0a
+#define regCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_28_29                                                              0x0e0b
+#define regCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_30_31                                                              0x0e0c
+#define regCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM0_CM_SHAPER_RAMB_REGION_32_33                                                              0x0e0d
+#define regCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM0_CM_MEM_PWR_CTRL2                                                                         0x0e0e
+#define regCM0_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM0_CM_MEM_PWR_STATUS2                                                                       0x0e0f
+#define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM0_CM_3DLUT_MODE                                                                            0x0e10
+#define regCM0_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM0_CM_3DLUT_INDEX                                                                           0x0e11
+#define regCM0_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM0_CM_3DLUT_DATA                                                                            0x0e12
+#define regCM0_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM0_CM_3DLUT_DATA_30BIT                                                                      0x0e13
+#define regCM0_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM0_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0e14
+#define regCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM0_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0e15
+#define regCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM0_CM_3DLUT_OUT_OFFSET_R                                                                    0x0e16
+#define regCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM0_CM_3DLUT_OUT_OFFSET_G                                                                    0x0e17
+#define regCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM0_CM_3DLUT_OUT_OFFSET_B                                                                    0x0e18
+#define regCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0e19
+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0e1a
+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+// base address: 0x0
+#define regDPP_TOP0_DPP_CONTROL                                                                         0x0cc5
+#define regDPP_TOP0_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP0_DPP_SOFT_RESET                                                                      0x0cc6
+#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP0_DPP_CRC_VAL_R_G                                                                     0x0cc7
+#define regDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_VAL_B_A                                                                     0x0cc8
+#define regDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP0_DPP_CRC_CTRL                                                                        0x0cc9
+#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP0_HOST_READ_CONTROL                                                                   0x0cca
+#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3890
+#define regDC_PERFMON11_PERFCOUNTER_CNTL                                                                0x0e24
+#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON11_PERFCOUNTER_CNTL2                                                               0x0e25
+#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON11_PERFCOUNTER_STATE                                                               0x0e26
+#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON11_PERFMON_CNTL                                                                    0x0e27
+#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON11_PERFMON_CNTL2                                                                   0x0e28
+#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC                                                         0x0e29
+#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON11_PERFMON_CVALUE_LOW                                                              0x0e2a
+#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON11_PERFMON_HI                                                                      0x0e2b
+#define regDC_PERFMON11_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON11_PERFMON_LOW                                                                     0x0e2c
+#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+// base address: 0x5ac
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0e3a
+#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG1_FORMAT_CONTROL                                                                     0x0e3b
+#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_R                                                                     0x0e3c
+#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_G                                                                     0x0e3d
+#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_BIAS_B                                                                     0x0e3e
+#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG1_FCNV_FP_SCALE_R                                                                    0x0e3f
+#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_G                                                                    0x0e40
+#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG1_FCNV_FP_SCALE_B                                                                    0x0e41
+#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL                                                                0x0e42
+#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA                                                                  0x0e43
+#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_RED                                                                    0x0e44
+#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG1_COLOR_KEYER_GREEN                                                                  0x0e45
+#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG1_COLOR_KEYER_BLUE                                                                   0x0e46
+#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG1_ALPHA_2BIT_LUT                                                                     0x0e48
+#define regCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG1_PRE_DEALPHA                                                                        0x0e49
+#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG1_PRE_CSC_MODE                                                                       0x0e4a
+#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG1_PRE_CSC_C11_C12                                                                    0x0e4b
+#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C13_C14                                                                    0x0e4c
+#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C21_C22                                                                    0x0e4d
+#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C23_C24                                                                    0x0e4e
+#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C31_C32                                                                    0x0e4f
+#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_C33_C34                                                                    0x0e50
+#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12                                                                  0x0e51
+#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14                                                                  0x0e52
+#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22                                                                  0x0e53
+#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24                                                                  0x0e54
+#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32                                                                  0x0e55
+#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34                                                                  0x0e56
+#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG1_CNVC_COEF_FORMAT                                                                   0x0e57
+#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG1_PRE_DEGAM                                                                          0x0e58
+#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG1_PRE_REALPHA                                                                        0x0e59
+#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+// base address: 0x5ac
+#define regCNVC_CUR1_CURSOR0_CONTROL                                                                    0x0e5c
+#define regCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR1_CURSOR0_COLOR0                                                                     0x0e5d
+#define regCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_COLOR1                                                                     0x0e5e
+#define regCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS                                                              0x0e5f
+#define regCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+// base address: 0x5ac
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT                                                                0x0e64
+#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA                                                                  0x0e65
+#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL1_SCL_MODE                                                                               0x0e66
+#define regDSCL1_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL1_SCL_TAP_CONTROL                                                                        0x0e67
+#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL1_DSCL_CONTROL                                                                           0x0e68
+#define regDSCL1_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_2TAP_CONTROL                                                                      0x0e69
+#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0e6a
+#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0e6b
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_HORZ_FILTER_INIT                                                                   0x0e6c
+#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0e6d
+#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C                                                                 0x0e6e
+#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0e6f
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL1_SCL_VERT_FILTER_INIT                                                                   0x0e70
+#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT                                                               0x0e71
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0e72
+#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL1_SCL_VERT_FILTER_INIT_C                                                                 0x0e73
+#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0e74
+#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL1_SCL_BLACK_COLOR                                                                        0x0e75
+#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL1_DSCL_UPDATE                                                                            0x0e76
+#define regDSCL1_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL1_DSCL_AUTOCAL                                                                           0x0e77
+#define regDSCL1_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0e78
+#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0e79
+#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL1_OTG_H_BLANK                                                                            0x0e7a
+#define regDSCL1_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_OTG_V_BLANK                                                                            0x0e7b
+#define regDSCL1_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL1_RECOUT_START                                                                           0x0e7c
+#define regDSCL1_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL1_RECOUT_SIZE                                                                            0x0e7d
+#define regDSCL1_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL1_MPC_SIZE                                                                               0x0e7e
+#define regDSCL1_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL1_LB_DATA_FORMAT                                                                         0x0e7f
+#define regDSCL1_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL1_LB_MEMORY_CTRL                                                                         0x0e80
+#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL1_LB_V_COUNTER                                                                           0x0e81
+#define regDSCL1_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL1_DSCL_MEM_PWR_CTRL                                                                      0x0e82
+#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL1_DSCL_MEM_PWR_STATUS                                                                    0x0e83
+#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL1_OBUF_CONTROL                                                                           0x0e84
+#define regDSCL1_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL1_OBUF_MEM_PWR_CTRL                                                                      0x0e85
+#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+// base address: 0x5ac
+#define regCM1_CM_CONTROL                                                                               0x0e8b
+#define regCM1_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM1_CM_POST_CSC_CONTROL                                                                      0x0e8c
+#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C11_C12                                                                      0x0e8d
+#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C13_C14                                                                      0x0e8e
+#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C21_C22                                                                      0x0e8f
+#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C23_C24                                                                      0x0e90
+#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C31_C32                                                                      0x0e91
+#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_C33_C34                                                                      0x0e92
+#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM1_CM_POST_CSC_B_C11_C12                                                                    0x0e93
+#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C13_C14                                                                    0x0e94
+#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C21_C22                                                                    0x0e95
+#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C23_C24                                                                    0x0e96
+#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C31_C32                                                                    0x0e97
+#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM1_CM_POST_CSC_B_C33_C34                                                                    0x0e98
+#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM1_CM_GAMUT_REMAP_CONTROL                                                                   0x0e99
+#define regCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C11_C12                                                                   0x0e9a
+#define regCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C13_C14                                                                   0x0e9b
+#define regCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C21_C22                                                                   0x0e9c
+#define regCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C23_C24                                                                   0x0e9d
+#define regCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C31_C32                                                                   0x0e9e
+#define regCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_C33_C34                                                                   0x0e9f
+#define regCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12                                                                 0x0ea0
+#define regCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14                                                                 0x0ea1
+#define regCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22                                                                 0x0ea2
+#define regCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24                                                                 0x0ea3
+#define regCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32                                                                 0x0ea4
+#define regCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34                                                                 0x0ea5
+#define regCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM1_CM_BIAS_CR_R                                                                             0x0ea6
+#define regCM1_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM1_CM_BIAS_Y_G_CB_B                                                                         0x0ea7
+#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM1_CM_GAMCOR_CONTROL                                                                        0x0ea8
+#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_GAMCOR_LUT_INDEX                                                                      0x0ea9
+#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_GAMCOR_LUT_DATA                                                                       0x0eaa
+#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_GAMCOR_LUT_CONTROL                                                                    0x0eab
+#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x0eac
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x0ead
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x0eae
+#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x0eaf
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x0eb0
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x0eb1
+#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x0eb2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x0eb3
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x0eb4
+#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x0eb5
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x0eb6
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x0eb7
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x0eb8
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x0eb9
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x0eba
+#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x0ebb
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x0ebc
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x0ebd
+#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1                                                                0x0ebe
+#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3                                                                0x0ebf
+#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5                                                                0x0ec0
+#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7                                                                0x0ec1
+#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9                                                                0x0ec2
+#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11                                                              0x0ec3
+#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13                                                              0x0ec4
+#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15                                                              0x0ec5
+#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17                                                              0x0ec6
+#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19                                                              0x0ec7
+#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21                                                              0x0ec8
+#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23                                                              0x0ec9
+#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25                                                              0x0eca
+#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27                                                              0x0ecb
+#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29                                                              0x0ecc
+#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31                                                              0x0ecd
+#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33                                                              0x0ece
+#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x0ecf
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x0ed0
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x0ed1
+#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x0ed2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x0ed3
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x0ed4
+#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x0ed5
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x0ed6
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x0ed7
+#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x0ed8
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x0ed9
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x0eda
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x0edb
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x0edc
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x0edd
+#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x0ede
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x0edf
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x0ee0
+#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1                                                                0x0ee1
+#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3                                                                0x0ee2
+#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5                                                                0x0ee3
+#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7                                                                0x0ee4
+#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9                                                                0x0ee5
+#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11                                                              0x0ee6
+#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13                                                              0x0ee7
+#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15                                                              0x0ee8
+#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17                                                              0x0ee9
+#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19                                                              0x0eea
+#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21                                                              0x0eeb
+#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23                                                              0x0eec
+#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25                                                              0x0eed
+#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27                                                              0x0eee
+#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29                                                              0x0eef
+#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31                                                              0x0ef0
+#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33                                                              0x0ef1
+#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_CONTROL                                                                       0x0ef2
+#define regCM1_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM1_CM_BLNDGAM_LUT_INDEX                                                                     0x0ef3
+#define regCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM1_CM_BLNDGAM_LUT_DATA                                                                      0x0ef4
+#define regCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM1_CM_BLNDGAM_LUT_CONTROL                                                                   0x0ef5
+#define regCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x0ef6
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x0ef7
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x0ef8
+#define regCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x0ef9
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x0efa
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x0efb
+#define regCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x0efc
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x0efd
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x0efe
+#define regCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x0eff
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x0f00
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x0f01
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x0f02
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x0f03
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x0f04
+#define regCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x0f05
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x0f06
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x0f07
+#define regCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x0f08
+#define regCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x0f09
+#define regCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x0f0a
+#define regCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x0f0b
+#define regCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x0f0c
+#define regCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x0f0d
+#define regCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x0f0e
+#define regCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x0f0f
+#define regCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x0f10
+#define regCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x0f11
+#define regCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x0f12
+#define regCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x0f13
+#define regCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x0f14
+#define regCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x0f15
+#define regCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x0f16
+#define regCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x0f17
+#define regCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x0f18
+#define regCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x0f19
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x0f1a
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x0f1b
+#define regCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x0f1c
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x0f1d
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x0f1e
+#define regCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x0f1f
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x0f20
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x0f21
+#define regCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x0f22
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x0f23
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x0f24
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x0f25
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x0f26
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x0f27
+#define regCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x0f28
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x0f29
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x0f2a
+#define regCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x0f2b
+#define regCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x0f2c
+#define regCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x0f2d
+#define regCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x0f2e
+#define regCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x0f2f
+#define regCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x0f30
+#define regCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x0f31
+#define regCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x0f32
+#define regCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x0f33
+#define regCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x0f34
+#define regCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x0f35
+#define regCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x0f36
+#define regCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x0f37
+#define regCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x0f38
+#define regCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x0f39
+#define regCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x0f3a
+#define regCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x0f3b
+#define regCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM1_CM_HDR_MULT_COEF                                                                         0x0f3c
+#define regCM1_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_CTRL                                                                          0x0f3d
+#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM1_CM_MEM_PWR_STATUS                                                                        0x0f3e
+#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM1_CM_DEALPHA                                                                               0x0f40
+#define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM1_CM_COEF_FORMAT                                                                           0x0f41
+#define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM1_CM_SHAPER_CONTROL                                                                        0x0f42
+#define regCM1_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM1_CM_SHAPER_OFFSET_R                                                                       0x0f43
+#define regCM1_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_OFFSET_G                                                                       0x0f44
+#define regCM1_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_OFFSET_B                                                                       0x0f45
+#define regCM1_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_SCALE_R                                                                        0x0f46
+#define regCM1_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM1_CM_SHAPER_SCALE_G_B                                                                      0x0f47
+#define regCM1_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM1_CM_SHAPER_LUT_INDEX                                                                      0x0f48
+#define regCM1_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_SHAPER_LUT_DATA                                                                       0x0f49
+#define regCM1_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x0f4a
+#define regCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_B                                                              0x0f4b
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_G                                                              0x0f4c
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_R                                                              0x0f4d
+#define regCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_B                                                                0x0f4e
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_G                                                                0x0f4f
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_R                                                                0x0f50
+#define regCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_0_1                                                                0x0f51
+#define regCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_2_3                                                                0x0f52
+#define regCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_4_5                                                                0x0f53
+#define regCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_6_7                                                                0x0f54
+#define regCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_8_9                                                                0x0f55
+#define regCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMA_REGION_10_11                                                              0x0f56
+#define regCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_12_13                                                              0x0f57
+#define regCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_14_15                                                              0x0f58
+#define regCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_16_17                                                              0x0f59
+#define regCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_18_19                                                              0x0f5a
+#define regCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_20_21                                                              0x0f5b
+#define regCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_22_23                                                              0x0f5c
+#define regCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_24_25                                                              0x0f5d
+#define regCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_26_27                                                              0x0f5e
+#define regCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_28_29                                                              0x0f5f
+#define regCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_30_31                                                              0x0f60
+#define regCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMA_REGION_32_33                                                              0x0f61
+#define regCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_B                                                              0x0f62
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_G                                                              0x0f63
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_R                                                              0x0f64
+#define regCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_B                                                                0x0f65
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_G                                                                0x0f66
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_R                                                                0x0f67
+#define regCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_0_1                                                                0x0f68
+#define regCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_2_3                                                                0x0f69
+#define regCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_4_5                                                                0x0f6a
+#define regCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_6_7                                                                0x0f6b
+#define regCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_8_9                                                                0x0f6c
+#define regCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM1_CM_SHAPER_RAMB_REGION_10_11                                                              0x0f6d
+#define regCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_12_13                                                              0x0f6e
+#define regCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_14_15                                                              0x0f6f
+#define regCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_16_17                                                              0x0f70
+#define regCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_18_19                                                              0x0f71
+#define regCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_20_21                                                              0x0f72
+#define regCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_22_23                                                              0x0f73
+#define regCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_24_25                                                              0x0f74
+#define regCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_26_27                                                              0x0f75
+#define regCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_28_29                                                              0x0f76
+#define regCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_30_31                                                              0x0f77
+#define regCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM1_CM_SHAPER_RAMB_REGION_32_33                                                              0x0f78
+#define regCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM1_CM_MEM_PWR_CTRL2                                                                         0x0f79
+#define regCM1_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM1_CM_MEM_PWR_STATUS2                                                                       0x0f7a
+#define regCM1_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM1_CM_3DLUT_MODE                                                                            0x0f7b
+#define regCM1_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM1_CM_3DLUT_INDEX                                                                           0x0f7c
+#define regCM1_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM1_CM_3DLUT_DATA                                                                            0x0f7d
+#define regCM1_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM1_CM_3DLUT_DATA_30BIT                                                                      0x0f7e
+#define regCM1_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM1_CM_3DLUT_READ_WRITE_CONTROL                                                              0x0f7f
+#define regCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM1_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x0f80
+#define regCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM1_CM_3DLUT_OUT_OFFSET_R                                                                    0x0f81
+#define regCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM1_CM_3DLUT_OUT_OFFSET_G                                                                    0x0f82
+#define regCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM1_CM_3DLUT_OUT_OFFSET_B                                                                    0x0f83
+#define regCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0f84
+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0f85
+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+// base address: 0x5ac
+#define regDPP_TOP1_DPP_CONTROL                                                                         0x0e30
+#define regDPP_TOP1_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP1_DPP_SOFT_RESET                                                                      0x0e31
+#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP1_DPP_CRC_VAL_R_G                                                                     0x0e32
+#define regDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_VAL_B_A                                                                     0x0e33
+#define regDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP1_DPP_CRC_CTRL                                                                        0x0e34
+#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP1_HOST_READ_CONTROL                                                                   0x0e35
+#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x3e3c
+#define regDC_PERFMON12_PERFCOUNTER_CNTL                                                                0x0f8f
+#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON12_PERFCOUNTER_CNTL2                                                               0x0f90
+#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON12_PERFCOUNTER_STATE                                                               0x0f91
+#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON12_PERFMON_CNTL                                                                    0x0f92
+#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON12_PERFMON_CNTL2                                                                   0x0f93
+#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC                                                         0x0f94
+#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON12_PERFMON_CVALUE_LOW                                                              0x0f95
+#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON12_PERFMON_HI                                                                      0x0f96
+#define regDC_PERFMON12_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON12_PERFMON_LOW                                                                     0x0f97
+#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+// base address: 0xb58
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT                                                          0x0fa5
+#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG2_FORMAT_CONTROL                                                                     0x0fa6
+#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_R                                                                     0x0fa7
+#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_G                                                                     0x0fa8
+#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_BIAS_B                                                                     0x0fa9
+#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG2_FCNV_FP_SCALE_R                                                                    0x0faa
+#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_G                                                                    0x0fab
+#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG2_FCNV_FP_SCALE_B                                                                    0x0fac
+#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL                                                                0x0fad
+#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA                                                                  0x0fae
+#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_RED                                                                    0x0faf
+#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG2_COLOR_KEYER_GREEN                                                                  0x0fb0
+#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG2_COLOR_KEYER_BLUE                                                                   0x0fb1
+#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG2_ALPHA_2BIT_LUT                                                                     0x0fb3
+#define regCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG2_PRE_DEALPHA                                                                        0x0fb4
+#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG2_PRE_CSC_MODE                                                                       0x0fb5
+#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG2_PRE_CSC_C11_C12                                                                    0x0fb6
+#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C13_C14                                                                    0x0fb7
+#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C21_C22                                                                    0x0fb8
+#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C23_C24                                                                    0x0fb9
+#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C31_C32                                                                    0x0fba
+#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_C33_C34                                                                    0x0fbb
+#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12                                                                  0x0fbc
+#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14                                                                  0x0fbd
+#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22                                                                  0x0fbe
+#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24                                                                  0x0fbf
+#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32                                                                  0x0fc0
+#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34                                                                  0x0fc1
+#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT                                                                   0x0fc2
+#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG2_PRE_DEGAM                                                                          0x0fc3
+#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG2_PRE_REALPHA                                                                        0x0fc4
+#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+// base address: 0xb58
+#define regCNVC_CUR2_CURSOR0_CONTROL                                                                    0x0fc7
+#define regCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR2_CURSOR0_COLOR0                                                                     0x0fc8
+#define regCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_COLOR1                                                                     0x0fc9
+#define regCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS                                                              0x0fca
+#define regCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+// base address: 0xb58
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT                                                                0x0fcf
+#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA                                                                  0x0fd0
+#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL2_SCL_MODE                                                                               0x0fd1
+#define regDSCL2_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL2_SCL_TAP_CONTROL                                                                        0x0fd2
+#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL2_DSCL_CONTROL                                                                           0x0fd3
+#define regDSCL2_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_2TAP_CONTROL                                                                      0x0fd4
+#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL                                                           0x0fd5
+#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x0fd6
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_HORZ_FILTER_INIT                                                                   0x0fd7
+#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x0fd8
+#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C                                                                 0x0fd9
+#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO                                                            0x0fda
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL2_SCL_VERT_FILTER_INIT                                                                   0x0fdb
+#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT                                                               0x0fdc
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x0fdd
+#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL2_SCL_VERT_FILTER_INIT_C                                                                 0x0fde
+#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C                                                             0x0fdf
+#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL2_SCL_BLACK_COLOR                                                                        0x0fe0
+#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL2_DSCL_UPDATE                                                                            0x0fe1
+#define regDSCL2_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL2_DSCL_AUTOCAL                                                                           0x0fe2
+#define regDSCL2_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x0fe3
+#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x0fe4
+#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL2_OTG_H_BLANK                                                                            0x0fe5
+#define regDSCL2_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_OTG_V_BLANK                                                                            0x0fe6
+#define regDSCL2_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL2_RECOUT_START                                                                           0x0fe7
+#define regDSCL2_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL2_RECOUT_SIZE                                                                            0x0fe8
+#define regDSCL2_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL2_MPC_SIZE                                                                               0x0fe9
+#define regDSCL2_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL2_LB_DATA_FORMAT                                                                         0x0fea
+#define regDSCL2_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL2_LB_MEMORY_CTRL                                                                         0x0feb
+#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL2_LB_V_COUNTER                                                                           0x0fec
+#define regDSCL2_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL2_DSCL_MEM_PWR_CTRL                                                                      0x0fed
+#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL2_DSCL_MEM_PWR_STATUS                                                                    0x0fee
+#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL2_OBUF_CONTROL                                                                           0x0fef
+#define regDSCL2_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL2_OBUF_MEM_PWR_CTRL                                                                      0x0ff0
+#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+// base address: 0xb58
+#define regCM2_CM_CONTROL                                                                               0x0ff6
+#define regCM2_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM2_CM_POST_CSC_CONTROL                                                                      0x0ff7
+#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C11_C12                                                                      0x0ff8
+#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C13_C14                                                                      0x0ff9
+#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C21_C22                                                                      0x0ffa
+#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C23_C24                                                                      0x0ffb
+#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C31_C32                                                                      0x0ffc
+#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_C33_C34                                                                      0x0ffd
+#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM2_CM_POST_CSC_B_C11_C12                                                                    0x0ffe
+#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C13_C14                                                                    0x0fff
+#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C21_C22                                                                    0x1000
+#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C23_C24                                                                    0x1001
+#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C31_C32                                                                    0x1002
+#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM2_CM_POST_CSC_B_C33_C34                                                                    0x1003
+#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM2_CM_GAMUT_REMAP_CONTROL                                                                   0x1004
+#define regCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C11_C12                                                                   0x1005
+#define regCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C13_C14                                                                   0x1006
+#define regCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C21_C22                                                                   0x1007
+#define regCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C23_C24                                                                   0x1008
+#define regCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C31_C32                                                                   0x1009
+#define regCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_C33_C34                                                                   0x100a
+#define regCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12                                                                 0x100b
+#define regCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14                                                                 0x100c
+#define regCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22                                                                 0x100d
+#define regCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24                                                                 0x100e
+#define regCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32                                                                 0x100f
+#define regCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34                                                                 0x1010
+#define regCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM2_CM_BIAS_CR_R                                                                             0x1011
+#define regCM2_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM2_CM_BIAS_Y_G_CB_B                                                                         0x1012
+#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM2_CM_GAMCOR_CONTROL                                                                        0x1013
+#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_GAMCOR_LUT_INDEX                                                                      0x1014
+#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_GAMCOR_LUT_DATA                                                                       0x1015
+#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_GAMCOR_LUT_CONTROL                                                                    0x1016
+#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1017
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1018
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1019
+#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x101a
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x101b
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x101c
+#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x101d
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x101e
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x101f
+#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x1020
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x1021
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x1022
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x1023
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x1024
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1025
+#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1026
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1027
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1028
+#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1029
+#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3                                                                0x102a
+#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5                                                                0x102b
+#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7                                                                0x102c
+#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9                                                                0x102d
+#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11                                                              0x102e
+#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13                                                              0x102f
+#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15                                                              0x1030
+#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17                                                              0x1031
+#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19                                                              0x1032
+#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21                                                              0x1033
+#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23                                                              0x1034
+#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25                                                              0x1035
+#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27                                                              0x1036
+#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29                                                              0x1037
+#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31                                                              0x1038
+#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33                                                              0x1039
+#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x103a
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x103b
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x103c
+#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x103d
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x103e
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x103f
+#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x1040
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x1041
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x1042
+#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x1043
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x1044
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x1045
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x1046
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x1047
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x1048
+#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x1049
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x104a
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x104b
+#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1                                                                0x104c
+#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3                                                                0x104d
+#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5                                                                0x104e
+#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7                                                                0x104f
+#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9                                                                0x1050
+#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11                                                              0x1051
+#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13                                                              0x1052
+#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15                                                              0x1053
+#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17                                                              0x1054
+#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19                                                              0x1055
+#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21                                                              0x1056
+#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23                                                              0x1057
+#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25                                                              0x1058
+#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27                                                              0x1059
+#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29                                                              0x105a
+#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31                                                              0x105b
+#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33                                                              0x105c
+#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_CONTROL                                                                       0x105d
+#define regCM2_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM2_CM_BLNDGAM_LUT_INDEX                                                                     0x105e
+#define regCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM2_CM_BLNDGAM_LUT_DATA                                                                      0x105f
+#define regCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM2_CM_BLNDGAM_LUT_CONTROL                                                                   0x1060
+#define regCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x1061
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x1062
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x1063
+#define regCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x1064
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x1065
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x1066
+#define regCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x1067
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x1068
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x1069
+#define regCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x106a
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x106b
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x106c
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x106d
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x106e
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x106f
+#define regCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x1070
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x1071
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x1072
+#define regCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x1073
+#define regCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x1074
+#define regCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x1075
+#define regCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x1076
+#define regCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x1077
+#define regCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x1078
+#define regCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x1079
+#define regCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x107a
+#define regCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x107b
+#define regCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x107c
+#define regCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x107d
+#define regCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x107e
+#define regCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x107f
+#define regCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x1080
+#define regCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x1081
+#define regCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x1082
+#define regCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x1083
+#define regCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x1084
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x1085
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x1086
+#define regCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x1087
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x1088
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x1089
+#define regCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x108a
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x108b
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x108c
+#define regCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x108d
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x108e
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x108f
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x1090
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x1091
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x1092
+#define regCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x1093
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x1094
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1095
+#define regCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1096
+#define regCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1097
+#define regCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1098
+#define regCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1099
+#define regCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x109a
+#define regCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x109b
+#define regCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x109c
+#define regCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x109d
+#define regCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x109e
+#define regCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x109f
+#define regCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x10a0
+#define regCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x10a1
+#define regCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x10a2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x10a3
+#define regCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x10a4
+#define regCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x10a5
+#define regCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x10a6
+#define regCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM2_CM_HDR_MULT_COEF                                                                         0x10a7
+#define regCM2_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_CTRL                                                                          0x10a8
+#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM2_CM_MEM_PWR_STATUS                                                                        0x10a9
+#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM2_CM_DEALPHA                                                                               0x10ab
+#define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM2_CM_COEF_FORMAT                                                                           0x10ac
+#define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM2_CM_SHAPER_CONTROL                                                                        0x10ad
+#define regCM2_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM2_CM_SHAPER_OFFSET_R                                                                       0x10ae
+#define regCM2_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_OFFSET_G                                                                       0x10af
+#define regCM2_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_OFFSET_B                                                                       0x10b0
+#define regCM2_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_SCALE_R                                                                        0x10b1
+#define regCM2_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM2_CM_SHAPER_SCALE_G_B                                                                      0x10b2
+#define regCM2_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM2_CM_SHAPER_LUT_INDEX                                                                      0x10b3
+#define regCM2_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_SHAPER_LUT_DATA                                                                       0x10b4
+#define regCM2_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x10b5
+#define regCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_B                                                              0x10b6
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_G                                                              0x10b7
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_R                                                              0x10b8
+#define regCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_B                                                                0x10b9
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_G                                                                0x10ba
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_R                                                                0x10bb
+#define regCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_0_1                                                                0x10bc
+#define regCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_2_3                                                                0x10bd
+#define regCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_4_5                                                                0x10be
+#define regCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_6_7                                                                0x10bf
+#define regCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_8_9                                                                0x10c0
+#define regCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMA_REGION_10_11                                                              0x10c1
+#define regCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_12_13                                                              0x10c2
+#define regCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_14_15                                                              0x10c3
+#define regCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_16_17                                                              0x10c4
+#define regCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_18_19                                                              0x10c5
+#define regCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_20_21                                                              0x10c6
+#define regCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_22_23                                                              0x10c7
+#define regCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_24_25                                                              0x10c8
+#define regCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_26_27                                                              0x10c9
+#define regCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_28_29                                                              0x10ca
+#define regCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_30_31                                                              0x10cb
+#define regCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMA_REGION_32_33                                                              0x10cc
+#define regCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_B                                                              0x10cd
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_G                                                              0x10ce
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_R                                                              0x10cf
+#define regCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_B                                                                0x10d0
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_G                                                                0x10d1
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_R                                                                0x10d2
+#define regCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_0_1                                                                0x10d3
+#define regCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_2_3                                                                0x10d4
+#define regCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_4_5                                                                0x10d5
+#define regCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_6_7                                                                0x10d6
+#define regCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_8_9                                                                0x10d7
+#define regCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM2_CM_SHAPER_RAMB_REGION_10_11                                                              0x10d8
+#define regCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_12_13                                                              0x10d9
+#define regCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_14_15                                                              0x10da
+#define regCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_16_17                                                              0x10db
+#define regCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_18_19                                                              0x10dc
+#define regCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_20_21                                                              0x10dd
+#define regCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_22_23                                                              0x10de
+#define regCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_24_25                                                              0x10df
+#define regCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_26_27                                                              0x10e0
+#define regCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_28_29                                                              0x10e1
+#define regCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_30_31                                                              0x10e2
+#define regCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM2_CM_SHAPER_RAMB_REGION_32_33                                                              0x10e3
+#define regCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM2_CM_MEM_PWR_CTRL2                                                                         0x10e4
+#define regCM2_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM2_CM_MEM_PWR_STATUS2                                                                       0x10e5
+#define regCM2_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM2_CM_3DLUT_MODE                                                                            0x10e6
+#define regCM2_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM2_CM_3DLUT_INDEX                                                                           0x10e7
+#define regCM2_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM2_CM_3DLUT_DATA                                                                            0x10e8
+#define regCM2_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM2_CM_3DLUT_DATA_30BIT                                                                      0x10e9
+#define regCM2_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM2_CM_3DLUT_READ_WRITE_CONTROL                                                              0x10ea
+#define regCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM2_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x10eb
+#define regCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM2_CM_3DLUT_OUT_OFFSET_R                                                                    0x10ec
+#define regCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM2_CM_3DLUT_OUT_OFFSET_G                                                                    0x10ed
+#define regCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM2_CM_3DLUT_OUT_OFFSET_B                                                                    0x10ee
+#define regCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x10ef
+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x10f0
+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+// base address: 0xb58
+#define regDPP_TOP2_DPP_CONTROL                                                                         0x0f9b
+#define regDPP_TOP2_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP2_DPP_SOFT_RESET                                                                      0x0f9c
+#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP2_DPP_CRC_VAL_R_G                                                                     0x0f9d
+#define regDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_VAL_B_A                                                                     0x0f9e
+#define regDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP2_DPP_CRC_CTRL                                                                        0x0f9f
+#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP2_HOST_READ_CONTROL                                                                   0x0fa0
+#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x43e8
+#define regDC_PERFMON13_PERFCOUNTER_CNTL                                                                0x10fa
+#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON13_PERFCOUNTER_CNTL2                                                               0x10fb
+#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON13_PERFCOUNTER_STATE                                                               0x10fc
+#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON13_PERFMON_CNTL                                                                    0x10fd
+#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON13_PERFMON_CNTL2                                                                   0x10fe
+#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC                                                         0x10ff
+#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON13_PERFMON_CVALUE_LOW                                                              0x1100
+#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON13_PERFMON_HI                                                                      0x1101
+#define regDC_PERFMON13_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON13_PERFMON_LOW                                                                     0x1102
+#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+// base address: 0x1104
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT                                                          0x1110
+#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX                                                 2
+#define regCNVC_CFG3_FORMAT_CONTROL                                                                     0x1111
+#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_R                                                                     0x1112
+#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_G                                                                     0x1113
+#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_BIAS_B                                                                     0x1114
+#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX                                                            2
+#define regCNVC_CFG3_FCNV_FP_SCALE_R                                                                    0x1115
+#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_G                                                                    0x1116
+#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX                                                           2
+#define regCNVC_CFG3_FCNV_FP_SCALE_B                                                                    0x1117
+#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL                                                                0x1118
+#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX                                                       2
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA                                                                  0x1119
+#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_RED                                                                    0x111a
+#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX                                                           2
+#define regCNVC_CFG3_COLOR_KEYER_GREEN                                                                  0x111b
+#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX                                                         2
+#define regCNVC_CFG3_COLOR_KEYER_BLUE                                                                   0x111c
+#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX                                                          2
+#define regCNVC_CFG3_ALPHA_2BIT_LUT                                                                     0x111e
+#define regCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX                                                            2
+#define regCNVC_CFG3_PRE_DEALPHA                                                                        0x111f
+#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX                                                               2
+#define regCNVC_CFG3_PRE_CSC_MODE                                                                       0x1120
+#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX                                                              2
+#define regCNVC_CFG3_PRE_CSC_C11_C12                                                                    0x1121
+#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C13_C14                                                                    0x1122
+#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C21_C22                                                                    0x1123
+#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C23_C24                                                                    0x1124
+#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C31_C32                                                                    0x1125
+#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_C33_C34                                                                    0x1126
+#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX                                                           2
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12                                                                  0x1127
+#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14                                                                  0x1128
+#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22                                                                  0x1129
+#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24                                                                  0x112a
+#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32                                                                  0x112b
+#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX                                                         2
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34                                                                  0x112c
+#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX                                                         2
+#define regCNVC_CFG3_CNVC_COEF_FORMAT                                                                   0x112d
+#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX                                                          2
+#define regCNVC_CFG3_PRE_DEGAM                                                                          0x112e
+#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX                                                                 2
+#define regCNVC_CFG3_PRE_REALPHA                                                                        0x112f
+#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+// base address: 0x1104
+#define regCNVC_CUR3_CURSOR0_CONTROL                                                                    0x1132
+#define regCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX                                                           2
+#define regCNVC_CUR3_CURSOR0_COLOR0                                                                     0x1133
+#define regCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_COLOR1                                                                     0x1134
+#define regCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX                                                            2
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS                                                              0x1135
+#define regCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+// base address: 0x1104
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT                                                                0x113a
+#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX                                                       2
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA                                                                  0x113b
+#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX                                                         2
+#define regDSCL3_SCL_MODE                                                                               0x113c
+#define regDSCL3_SCL_MODE_BASE_IDX                                                                      2
+#define regDSCL3_SCL_TAP_CONTROL                                                                        0x113d
+#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX                                                               2
+#define regDSCL3_DSCL_CONTROL                                                                           0x113e
+#define regDSCL3_DSCL_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_2TAP_CONTROL                                                                      0x113f
+#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX                                                             2
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL                                                           0x1140
+#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX                                                  2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO                                                            0x1141
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_HORZ_FILTER_INIT                                                                   0x1142
+#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C                                                          0x1143
+#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C                                                                 0x1144
+#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO                                                            0x1145
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX                                                   2
+#define regDSCL3_SCL_VERT_FILTER_INIT                                                                   0x1146
+#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX                                                          2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT                                                               0x1147
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX                                                      2
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C                                                          0x1148
+#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX                                                 2
+#define regDSCL3_SCL_VERT_FILTER_INIT_C                                                                 0x1149
+#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX                                                        2
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C                                                             0x114a
+#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX                                                    2
+#define regDSCL3_SCL_BLACK_COLOR                                                                        0x114b
+#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX                                                               2
+#define regDSCL3_DSCL_UPDATE                                                                            0x114c
+#define regDSCL3_DSCL_UPDATE_BASE_IDX                                                                   2
+#define regDSCL3_DSCL_AUTOCAL                                                                           0x114d
+#define regDSCL3_DSCL_AUTOCAL_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT                                                           0x114e
+#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX                                                  2
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM                                                           0x114f
+#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX                                                  2
+#define regDSCL3_OTG_H_BLANK                                                                            0x1150
+#define regDSCL3_OTG_H_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_OTG_V_BLANK                                                                            0x1151
+#define regDSCL3_OTG_V_BLANK_BASE_IDX                                                                   2
+#define regDSCL3_RECOUT_START                                                                           0x1152
+#define regDSCL3_RECOUT_START_BASE_IDX                                                                  2
+#define regDSCL3_RECOUT_SIZE                                                                            0x1153
+#define regDSCL3_RECOUT_SIZE_BASE_IDX                                                                   2
+#define regDSCL3_MPC_SIZE                                                                               0x1154
+#define regDSCL3_MPC_SIZE_BASE_IDX                                                                      2
+#define regDSCL3_LB_DATA_FORMAT                                                                         0x1155
+#define regDSCL3_LB_DATA_FORMAT_BASE_IDX                                                                2
+#define regDSCL3_LB_MEMORY_CTRL                                                                         0x1156
+#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX                                                                2
+#define regDSCL3_LB_V_COUNTER                                                                           0x1157
+#define regDSCL3_LB_V_COUNTER_BASE_IDX                                                                  2
+#define regDSCL3_DSCL_MEM_PWR_CTRL                                                                      0x1158
+#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX                                                             2
+#define regDSCL3_DSCL_MEM_PWR_STATUS                                                                    0x1159
+#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX                                                           2
+#define regDSCL3_OBUF_CONTROL                                                                           0x115a
+#define regDSCL3_OBUF_CONTROL_BASE_IDX                                                                  2
+#define regDSCL3_OBUF_MEM_PWR_CTRL                                                                      0x115b
+#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+// base address: 0x1104
+#define regCM3_CM_CONTROL                                                                               0x1161
+#define regCM3_CM_CONTROL_BASE_IDX                                                                      2
+#define regCM3_CM_POST_CSC_CONTROL                                                                      0x1162
+#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C11_C12                                                                      0x1163
+#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C13_C14                                                                      0x1164
+#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C21_C22                                                                      0x1165
+#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C23_C24                                                                      0x1166
+#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C31_C32                                                                      0x1167
+#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_C33_C34                                                                      0x1168
+#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX                                                             2
+#define regCM3_CM_POST_CSC_B_C11_C12                                                                    0x1169
+#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C13_C14                                                                    0x116a
+#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C21_C22                                                                    0x116b
+#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C23_C24                                                                    0x116c
+#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C31_C32                                                                    0x116d
+#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX                                                           2
+#define regCM3_CM_POST_CSC_B_C33_C34                                                                    0x116e
+#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX                                                           2
+#define regCM3_CM_GAMUT_REMAP_CONTROL                                                                   0x116f
+#define regCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C11_C12                                                                   0x1170
+#define regCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C13_C14                                                                   0x1171
+#define regCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C21_C22                                                                   0x1172
+#define regCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C23_C24                                                                   0x1173
+#define regCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C31_C32                                                                   0x1174
+#define regCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_C33_C34                                                                   0x1175
+#define regCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX                                                          2
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12                                                                 0x1176
+#define regCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14                                                                 0x1177
+#define regCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22                                                                 0x1178
+#define regCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24                                                                 0x1179
+#define regCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32                                                                 0x117a
+#define regCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX                                                        2
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34                                                                 0x117b
+#define regCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX                                                        2
+#define regCM3_CM_BIAS_CR_R                                                                             0x117c
+#define regCM3_CM_BIAS_CR_R_BASE_IDX                                                                    2
+#define regCM3_CM_BIAS_Y_G_CB_B                                                                         0x117d
+#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX                                                                2
+#define regCM3_CM_GAMCOR_CONTROL                                                                        0x117e
+#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_GAMCOR_LUT_INDEX                                                                      0x117f
+#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_GAMCOR_LUT_DATA                                                                       0x1180
+#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_GAMCOR_LUT_CONTROL                                                                    0x1181
+#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX                                                           2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B                                                              0x1182
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G                                                              0x1183
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R                                                              0x1184
+#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B                                                        0x1185
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G                                                        0x1186
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R                                                        0x1187
+#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B                                                         0x1188
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G                                                         0x1189
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R                                                         0x118a
+#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B                                                               0x118b
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B                                                               0x118c
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G                                                               0x118d
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G                                                               0x118e
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R                                                               0x118f
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R                                                               0x1190
+#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B                                                                  0x1191
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G                                                                  0x1192
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R                                                                  0x1193
+#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1                                                                0x1194
+#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3                                                                0x1195
+#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5                                                                0x1196
+#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7                                                                0x1197
+#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9                                                                0x1198
+#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11                                                              0x1199
+#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13                                                              0x119a
+#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15                                                              0x119b
+#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17                                                              0x119c
+#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19                                                              0x119d
+#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21                                                              0x119e
+#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23                                                              0x119f
+#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25                                                              0x11a0
+#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27                                                              0x11a1
+#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29                                                              0x11a2
+#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31                                                              0x11a3
+#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33                                                              0x11a4
+#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B                                                              0x11a5
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G                                                              0x11a6
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R                                                              0x11a7
+#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B                                                        0x11a8
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G                                                        0x11a9
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R                                                        0x11aa
+#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B                                                         0x11ab
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G                                                         0x11ac
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R                                                         0x11ad
+#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX                                                2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B                                                               0x11ae
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B                                                               0x11af
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G                                                               0x11b0
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G                                                               0x11b1
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R                                                               0x11b2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R                                                               0x11b3
+#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX                                                      2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B                                                                  0x11b4
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G                                                                  0x11b5
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R                                                                  0x11b6
+#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX                                                         2
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1                                                                0x11b7
+#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3                                                                0x11b8
+#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5                                                                0x11b9
+#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7                                                                0x11ba
+#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9                                                                0x11bb
+#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11                                                              0x11bc
+#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13                                                              0x11bd
+#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15                                                              0x11be
+#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17                                                              0x11bf
+#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19                                                              0x11c0
+#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21                                                              0x11c1
+#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23                                                              0x11c2
+#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25                                                              0x11c3
+#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27                                                              0x11c4
+#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29                                                              0x11c5
+#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31                                                              0x11c6
+#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33                                                              0x11c7
+#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_CONTROL                                                                       0x11c8
+#define regCM3_CM_BLNDGAM_CONTROL_BASE_IDX                                                              2
+#define regCM3_CM_BLNDGAM_LUT_INDEX                                                                     0x11c9
+#define regCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX                                                            2
+#define regCM3_CM_BLNDGAM_LUT_DATA                                                                      0x11ca
+#define regCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX                                                             2
+#define regCM3_CM_BLNDGAM_LUT_CONTROL                                                                   0x11cb
+#define regCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX                                                          2
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B                                                             0x11cc
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G                                                             0x11cd
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R                                                             0x11ce
+#define regCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B                                                       0x11cf
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G                                                       0x11d0
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R                                                       0x11d1
+#define regCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B                                                        0x11d2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G                                                        0x11d3
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R                                                        0x11d4
+#define regCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B                                                              0x11d5
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B                                                              0x11d6
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G                                                              0x11d7
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G                                                              0x11d8
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R                                                              0x11d9
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R                                                              0x11da
+#define regCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B                                                                 0x11db
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G                                                                 0x11dc
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R                                                                 0x11dd
+#define regCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1                                                               0x11de
+#define regCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3                                                               0x11df
+#define regCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5                                                               0x11e0
+#define regCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7                                                               0x11e1
+#define regCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9                                                               0x11e2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11                                                             0x11e3
+#define regCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13                                                             0x11e4
+#define regCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15                                                             0x11e5
+#define regCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17                                                             0x11e6
+#define regCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19                                                             0x11e7
+#define regCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21                                                             0x11e8
+#define regCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23                                                             0x11e9
+#define regCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25                                                             0x11ea
+#define regCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27                                                             0x11eb
+#define regCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29                                                             0x11ec
+#define regCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31                                                             0x11ed
+#define regCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33                                                             0x11ee
+#define regCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B                                                             0x11ef
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G                                                             0x11f0
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R                                                             0x11f1
+#define regCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B                                                       0x11f2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G                                                       0x11f3
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R                                                       0x11f4
+#define regCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                              2
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B                                                        0x11f5
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G                                                        0x11f6
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R                                                        0x11f7
+#define regCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                               2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B                                                              0x11f8
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B                                                              0x11f9
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G                                                              0x11fa
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G                                                              0x11fb
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R                                                              0x11fc
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R                                                              0x11fd
+#define regCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX                                                     2
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B                                                                 0x11fe
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G                                                                 0x11ff
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R                                                                 0x1200
+#define regCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX                                                        2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1                                                               0x1201
+#define regCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3                                                               0x1202
+#define regCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5                                                               0x1203
+#define regCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7                                                               0x1204
+#define regCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9                                                               0x1205
+#define regCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX                                                      2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11                                                             0x1206
+#define regCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13                                                             0x1207
+#define regCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15                                                             0x1208
+#define regCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17                                                             0x1209
+#define regCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19                                                             0x120a
+#define regCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21                                                             0x120b
+#define regCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23                                                             0x120c
+#define regCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25                                                             0x120d
+#define regCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27                                                             0x120e
+#define regCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29                                                             0x120f
+#define regCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31                                                             0x1210
+#define regCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX                                                    2
+#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33                                                             0x1211
+#define regCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX                                                    2
+#define regCM3_CM_HDR_MULT_COEF                                                                         0x1212
+#define regCM3_CM_HDR_MULT_COEF_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_CTRL                                                                          0x1213
+#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX                                                                 2
+#define regCM3_CM_MEM_PWR_STATUS                                                                        0x1214
+#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX                                                               2
+#define regCM3_CM_DEALPHA                                                                               0x1216
+#define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
+#define regCM3_CM_COEF_FORMAT                                                                           0x1217
+#define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM3_CM_SHAPER_CONTROL                                                                        0x1218
+#define regCM3_CM_SHAPER_CONTROL_BASE_IDX                                                               2
+#define regCM3_CM_SHAPER_OFFSET_R                                                                       0x1219
+#define regCM3_CM_SHAPER_OFFSET_R_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_OFFSET_G                                                                       0x121a
+#define regCM3_CM_SHAPER_OFFSET_G_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_OFFSET_B                                                                       0x121b
+#define regCM3_CM_SHAPER_OFFSET_B_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_SCALE_R                                                                        0x121c
+#define regCM3_CM_SHAPER_SCALE_R_BASE_IDX                                                               2
+#define regCM3_CM_SHAPER_SCALE_G_B                                                                      0x121d
+#define regCM3_CM_SHAPER_SCALE_G_B_BASE_IDX                                                             2
+#define regCM3_CM_SHAPER_LUT_INDEX                                                                      0x121e
+#define regCM3_CM_SHAPER_LUT_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_SHAPER_LUT_DATA                                                                       0x121f
+#define regCM3_CM_SHAPER_LUT_DATA_BASE_IDX                                                              2
+#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK                                                              0x1220
+#define regCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_B                                                              0x1221
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_G                                                              0x1222
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_R                                                              0x1223
+#define regCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_B                                                                0x1224
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_G                                                                0x1225
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_R                                                                0x1226
+#define regCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_0_1                                                                0x1227
+#define regCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_2_3                                                                0x1228
+#define regCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_4_5                                                                0x1229
+#define regCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_6_7                                                                0x122a
+#define regCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_8_9                                                                0x122b
+#define regCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMA_REGION_10_11                                                              0x122c
+#define regCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_12_13                                                              0x122d
+#define regCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_14_15                                                              0x122e
+#define regCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_16_17                                                              0x122f
+#define regCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_18_19                                                              0x1230
+#define regCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_20_21                                                              0x1231
+#define regCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_22_23                                                              0x1232
+#define regCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_24_25                                                              0x1233
+#define regCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_26_27                                                              0x1234
+#define regCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_28_29                                                              0x1235
+#define regCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_30_31                                                              0x1236
+#define regCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMA_REGION_32_33                                                              0x1237
+#define regCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_B                                                              0x1238
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_G                                                              0x1239
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_R                                                              0x123a
+#define regCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_B                                                                0x123b
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_G                                                                0x123c
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_R                                                                0x123d
+#define regCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_0_1                                                                0x123e
+#define regCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_2_3                                                                0x123f
+#define regCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_4_5                                                                0x1240
+#define regCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_6_7                                                                0x1241
+#define regCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_8_9                                                                0x1242
+#define regCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                       2
+#define regCM3_CM_SHAPER_RAMB_REGION_10_11                                                              0x1243
+#define regCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_12_13                                                              0x1244
+#define regCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_14_15                                                              0x1245
+#define regCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_16_17                                                              0x1246
+#define regCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_18_19                                                              0x1247
+#define regCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_20_21                                                              0x1248
+#define regCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_22_23                                                              0x1249
+#define regCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_24_25                                                              0x124a
+#define regCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_26_27                                                              0x124b
+#define regCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_28_29                                                              0x124c
+#define regCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_30_31                                                              0x124d
+#define regCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                     2
+#define regCM3_CM_SHAPER_RAMB_REGION_32_33                                                              0x124e
+#define regCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                     2
+#define regCM3_CM_MEM_PWR_CTRL2                                                                         0x124f
+#define regCM3_CM_MEM_PWR_CTRL2_BASE_IDX                                                                2
+#define regCM3_CM_MEM_PWR_STATUS2                                                                       0x1250
+#define regCM3_CM_MEM_PWR_STATUS2_BASE_IDX                                                              2
+#define regCM3_CM_3DLUT_MODE                                                                            0x1251
+#define regCM3_CM_3DLUT_MODE_BASE_IDX                                                                   2
+#define regCM3_CM_3DLUT_INDEX                                                                           0x1252
+#define regCM3_CM_3DLUT_INDEX_BASE_IDX                                                                  2
+#define regCM3_CM_3DLUT_DATA                                                                            0x1253
+#define regCM3_CM_3DLUT_DATA_BASE_IDX                                                                   2
+#define regCM3_CM_3DLUT_DATA_30BIT                                                                      0x1254
+#define regCM3_CM_3DLUT_DATA_30BIT_BASE_IDX                                                             2
+#define regCM3_CM_3DLUT_READ_WRITE_CONTROL                                                              0x1255
+#define regCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                     2
+#define regCM3_CM_3DLUT_OUT_NORM_FACTOR                                                                 0x1256
+#define regCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                        2
+#define regCM3_CM_3DLUT_OUT_OFFSET_R                                                                    0x1257
+#define regCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX                                                           2
+#define regCM3_CM_3DLUT_OUT_OFFSET_G                                                                    0x1258
+#define regCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX                                                           2
+#define regCM3_CM_3DLUT_OUT_OFFSET_B                                                                    0x1259
+#define regCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX                                                           2
+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x125a
+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x125b
+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+// base address: 0x1104
+#define regDPP_TOP3_DPP_CONTROL                                                                         0x1106
+#define regDPP_TOP3_DPP_CONTROL_BASE_IDX                                                                2
+#define regDPP_TOP3_DPP_SOFT_RESET                                                                      0x1107
+#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX                                                             2
+#define regDPP_TOP3_DPP_CRC_VAL_R_G                                                                     0x1108
+#define regDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_VAL_B_A                                                                     0x1109
+#define regDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX                                                            2
+#define regDPP_TOP3_DPP_CRC_CTRL                                                                        0x110a
+#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX                                                               2
+#define regDPP_TOP3_HOST_READ_CONTROL                                                                   0x110b
+#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x4994
+#define regDC_PERFMON14_PERFCOUNTER_CNTL                                                                0x1265
+#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON14_PERFCOUNTER_CNTL2                                                               0x1266
+#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON14_PERFCOUNTER_STATE                                                               0x1267
+#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON14_PERFMON_CNTL                                                                    0x1268
+#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON14_PERFMON_CNTL2                                                                   0x1269
+#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC                                                         0x126a
+#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON14_PERFMON_CVALUE_LOW                                                              0x126b
+#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON14_PERFMON_HI                                                                      0x126c
+#define regDC_PERFMON14_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON14_PERFMON_LOW                                                                     0x126d
+#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+// base address: 0x0
+#define regMPCC0_MPCC_TOP_SEL                                                                           0x0000
+#define regMPCC0_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BOT_SEL                                                                           0x0001
+#define regMPCC0_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_OPP_ID                                                                            0x0002
+#define regMPCC0_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_CONTROL                                                                           0x0003
+#define regMPCC0_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_SM_CONTROL                                                                        0x0004
+#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL                                                                   0x0005
+#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC0_MPCC_TOP_GAIN                                                                          0x0006
+#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE                                                                   0x0007
+#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0008
+#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC0_MPCC_BG_R_CR                                                                           0x0009
+#define regMPCC0_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_BG_G_Y                                                                            0x000a
+#define regMPCC0_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC0_MPCC_BG_B_CB                                                                           0x000b
+#define regMPCC0_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC0_MPCC_MEM_PWR_CTRL                                                                      0x000c
+#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC0_MPCC_STATUS                                                                            0x000d
+#define regMPCC0_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+// base address: 0x80
+#define regMPCC1_MPCC_TOP_SEL                                                                           0x0020
+#define regMPCC1_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BOT_SEL                                                                           0x0021
+#define regMPCC1_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_OPP_ID                                                                            0x0022
+#define regMPCC1_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_CONTROL                                                                           0x0023
+#define regMPCC1_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_SM_CONTROL                                                                        0x0024
+#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL                                                                   0x0025
+#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC1_MPCC_TOP_GAIN                                                                          0x0026
+#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE                                                                   0x0027
+#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0028
+#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC1_MPCC_BG_R_CR                                                                           0x0029
+#define regMPCC1_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_BG_G_Y                                                                            0x002a
+#define regMPCC1_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC1_MPCC_BG_B_CB                                                                           0x002b
+#define regMPCC1_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC1_MPCC_MEM_PWR_CTRL                                                                      0x002c
+#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC1_MPCC_STATUS                                                                            0x002d
+#define regMPCC1_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+// base address: 0x100
+#define regMPCC2_MPCC_TOP_SEL                                                                           0x0040
+#define regMPCC2_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BOT_SEL                                                                           0x0041
+#define regMPCC2_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_OPP_ID                                                                            0x0042
+#define regMPCC2_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_CONTROL                                                                           0x0043
+#define regMPCC2_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_SM_CONTROL                                                                        0x0044
+#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL                                                                   0x0045
+#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC2_MPCC_TOP_GAIN                                                                          0x0046
+#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE                                                                   0x0047
+#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0048
+#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC2_MPCC_BG_R_CR                                                                           0x0049
+#define regMPCC2_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_BG_G_Y                                                                            0x004a
+#define regMPCC2_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC2_MPCC_BG_B_CB                                                                           0x004b
+#define regMPCC2_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC2_MPCC_MEM_PWR_CTRL                                                                      0x004c
+#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC2_MPCC_STATUS                                                                            0x004d
+#define regMPCC2_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+// base address: 0x180
+#define regMPCC3_MPCC_TOP_SEL                                                                           0x0060
+#define regMPCC3_MPCC_TOP_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BOT_SEL                                                                           0x0061
+#define regMPCC3_MPCC_BOT_SEL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_OPP_ID                                                                            0x0062
+#define regMPCC3_MPCC_OPP_ID_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_CONTROL                                                                           0x0063
+#define regMPCC3_MPCC_CONTROL_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_SM_CONTROL                                                                        0x0064
+#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX                                                               3
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL                                                                   0x0065
+#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX                                                          3
+#define regMPCC3_MPCC_TOP_GAIN                                                                          0x0066
+#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX                                                                 3
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE                                                                   0x0067
+#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX                                                          3
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE                                                                  0x0068
+#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX                                                         3
+#define regMPCC3_MPCC_BG_R_CR                                                                           0x0069
+#define regMPCC3_MPCC_BG_R_CR_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_BG_G_Y                                                                            0x006a
+#define regMPCC3_MPCC_BG_G_Y_BASE_IDX                                                                   3
+#define regMPCC3_MPCC_BG_B_CB                                                                           0x006b
+#define regMPCC3_MPCC_BG_B_CB_BASE_IDX                                                                  3
+#define regMPCC3_MPCC_MEM_PWR_CTRL                                                                      0x006c
+#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX                                                             3
+#define regMPCC3_MPCC_STATUS                                                                            0x006d
+#define regMPCC3_MPCC_STATUS_BASE_IDX                                                                   3
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+// base address: 0x0
+#define regMPC_CLOCK_CONTROL                                                                            0x0500
+#define regMPC_CLOCK_CONTROL_BASE_IDX                                                                   3
+#define regMPC_SOFT_RESET                                                                               0x0501
+#define regMPC_SOFT_RESET_BASE_IDX                                                                      3
+#define regMPC_CRC_CTRL                                                                                 0x0502
+#define regMPC_CRC_CTRL_BASE_IDX                                                                        3
+#define regMPC_CRC_SEL_CONTROL                                                                          0x0503
+#define regMPC_CRC_SEL_CONTROL_BASE_IDX                                                                 3
+#define regMPC_CRC_RESULT_AR                                                                            0x0504
+#define regMPC_CRC_RESULT_AR_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_GB                                                                            0x0505
+#define regMPC_CRC_RESULT_GB_BASE_IDX                                                                   3
+#define regMPC_CRC_RESULT_C                                                                             0x0506
+#define regMPC_CRC_RESULT_C_BASE_IDX                                                                    3
+#define regMPC_PERFMON_EVENT_CTRL                                                                       0x0509
+#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX                                                              3
+#define regMPC_BYPASS_BG_AR                                                                             0x050a
+#define regMPC_BYPASS_BG_AR_BASE_IDX                                                                    3
+#define regMPC_BYPASS_BG_GB                                                                             0x050b
+#define regMPC_BYPASS_BG_GB_BASE_IDX                                                                    3
+#define regMPC_HOST_READ_CONTROL                                                                        0x050c
+#define regMPC_HOST_READ_CONTROL_BASE_IDX                                                               3
+#define regMPC_DPP_PENDING_STATUS                                                                       0x050d
+#define regMPC_DPP_PENDING_STATUS_BASE_IDX                                                              3
+#define regMPC_PENDING_STATUS_MISC                                                                      0x050e
+#define regMPC_PENDING_STATUS_MISC_BASE_IDX                                                             3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0                                                                0x050f
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET0                                                                    0x0510
+#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET0                                                                        0x0511
+#define regADR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET0                                                                        0x0512
+#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET0                                                                        0x0513
+#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1                                                                0x0514
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET1                                                                    0x0515
+#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET1                                                                        0x0516
+#define regADR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET1                                                                        0x0517
+#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET1                                                                        0x0518
+#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2                                                                0x0519
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET2                                                                    0x051a
+#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET2                                                                        0x051b
+#define regADR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET2                                                                        0x051c
+#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET2                                                                        0x051d
+#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX                                                               3
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3                                                                0x051e
+#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX                                                       3
+#define regADR_CFG_VUPDATE_LOCK_SET3                                                                    0x051f
+#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX                                                           3
+#define regADR_VUPDATE_LOCK_SET3                                                                        0x0520
+#define regADR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCFG_VUPDATE_LOCK_SET3                                                                        0x0521
+#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regCUR_VUPDATE_LOCK_SET3                                                                        0x0522
+#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX                                                               3
+#define regMPC_DWB0_MUX                                                                                 0x055c
+#define regMPC_DWB0_MUX_BASE_IDX                                                                        3
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1901c
+#define regDC_PERFMON15_PERFCOUNTER_CNTL                                                                0x08c7
+#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define regDC_PERFMON15_PERFCOUNTER_CNTL2                                                               0x08c8
+#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define regDC_PERFMON15_PERFCOUNTER_STATE                                                               0x08c9
+#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define regDC_PERFMON15_PERFMON_CNTL                                                                    0x08ca
+#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX                                                           3
+#define regDC_PERFMON15_PERFMON_CNTL2                                                                   0x08cb
+#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX                                                          3
+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC                                                         0x08cc
+#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define regDC_PERFMON15_PERFMON_CVALUE_LOW                                                              0x08cd
+#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define regDC_PERFMON15_PERFMON_HI                                                                      0x08ce
+#define regDC_PERFMON15_PERFMON_HI_BASE_IDX                                                             3
+#define regDC_PERFMON15_PERFMON_LOW                                                                     0x08cf
+#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+// base address: 0x0
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL                                                                 0x0100
+#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX                                                               0x0101
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA                                                                0x0102
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL                                                             0x0103
+#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0104
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0105
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0106
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0107
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0108
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0109
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x010a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x010b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x010c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x010d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x010e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x010f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0110
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0111
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0112
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0113
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0114
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0115
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0116
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0117
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0118
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0119
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9                                                         0x011a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11                                                       0x011b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13                                                       0x011c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15                                                       0x011d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17                                                       0x011e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19                                                       0x011f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0120
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0121
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0122
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0123
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0124
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0125
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0126
+#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0127
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0128
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0129
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x012a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x012b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x012c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x012d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x012e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x012f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0130
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0131
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0132
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0133
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0134
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0135
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0136
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0137
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0138
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0139
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3                                                         0x013a
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5                                                         0x013b
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7                                                         0x013c
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9                                                         0x013d
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11                                                       0x013e
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13                                                       0x013f
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0140
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0141
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0142
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0143
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0144
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0145
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0146
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0147
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0148
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0149
+#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x014a
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE                                                             0x014b
+#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A                                                         0x014c
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A                                                         0x014d
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A                                                         0x014e
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A                                                         0x014f
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0150
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0151
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0152
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0153
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0154
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0155
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0156
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0157
+#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+// base address: 0x200
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL                                                                 0x0180
+#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX                                                               0x0181
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA                                                                0x0182
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL                                                             0x0183
+#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0184
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0185
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0186
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0187
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0188
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0189
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x018a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x018b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x018c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x018d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x018e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x018f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0190
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0191
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0192
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0193
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0194
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0195
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0196
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0197
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0198
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0199
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9                                                         0x019a
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11                                                       0x019b
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13                                                       0x019c
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15                                                       0x019d
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17                                                       0x019e
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19                                                       0x019f
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21                                                       0x01a0
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23                                                       0x01a1
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25                                                       0x01a2
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27                                                       0x01a3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29                                                       0x01a4
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31                                                       0x01a5
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33                                                       0x01a6
+#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x01a7
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x01a8
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x01a9
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x01aa
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x01ab
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x01ac
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x01ad
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x01ae
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x01af
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x01b0
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x01b1
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x01b2
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x01b3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x01b4
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x01b5
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B                                                           0x01b6
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G                                                           0x01b7
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R                                                           0x01b8
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1                                                         0x01b9
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3                                                         0x01ba
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5                                                         0x01bb
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7                                                         0x01bc
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9                                                         0x01bd
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11                                                       0x01be
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13                                                       0x01bf
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15                                                       0x01c0
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17                                                       0x01c1
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19                                                       0x01c2
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21                                                       0x01c3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23                                                       0x01c4
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25                                                       0x01c5
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27                                                       0x01c6
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29                                                       0x01c7
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31                                                       0x01c8
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33                                                       0x01c9
+#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x01ca
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE                                                             0x01cb
+#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A                                                         0x01cc
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A                                                         0x01cd
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A                                                         0x01ce
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A                                                         0x01cf
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A                                                         0x01d0
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A                                                         0x01d1
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B                                                         0x01d2
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B                                                         0x01d3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B                                                         0x01d4
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B                                                         0x01d5
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B                                                         0x01d6
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B                                                         0x01d7
+#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+// base address: 0x400
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL                                                                 0x0200
+#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX                                                               0x0201
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA                                                                0x0202
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL                                                             0x0203
+#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0204
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0205
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0206
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0207
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0208
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0209
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x020a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x020b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x020c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x020d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x020e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x020f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0210
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0211
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0212
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0213
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0214
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0215
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0216
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0217
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0218
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0219
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9                                                         0x021a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11                                                       0x021b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13                                                       0x021c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15                                                       0x021d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17                                                       0x021e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19                                                       0x021f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21                                                       0x0220
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23                                                       0x0221
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25                                                       0x0222
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27                                                       0x0223
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29                                                       0x0224
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31                                                       0x0225
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33                                                       0x0226
+#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x0227
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x0228
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x0229
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x022a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x022b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x022c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x022d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x022e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x022f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x0230
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x0231
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x0232
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x0233
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x0234
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x0235
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B                                                           0x0236
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G                                                           0x0237
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R                                                           0x0238
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1                                                         0x0239
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3                                                         0x023a
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5                                                         0x023b
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7                                                         0x023c
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9                                                         0x023d
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11                                                       0x023e
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13                                                       0x023f
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15                                                       0x0240
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17                                                       0x0241
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19                                                       0x0242
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21                                                       0x0243
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23                                                       0x0244
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25                                                       0x0245
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27                                                       0x0246
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29                                                       0x0247
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31                                                       0x0248
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33                                                       0x0249
+#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x024a
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE                                                             0x024b
+#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A                                                         0x024c
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A                                                         0x024d
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A                                                         0x024e
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A                                                         0x024f
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A                                                         0x0250
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A                                                         0x0251
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B                                                         0x0252
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B                                                         0x0253
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B                                                         0x0254
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B                                                         0x0255
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B                                                         0x0256
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B                                                         0x0257
+#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+// base address: 0x600
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL                                                                 0x0280
+#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX                                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX                                                               0x0281
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX                                                      3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA                                                                0x0282
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX                                                       3
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL                                                             0x0283
+#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B                                                       0x0284
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G                                                       0x0285
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R                                                       0x0286
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B                                                 0x0287
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G                                                 0x0288
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R                                                 0x0289
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B                                                  0x028a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G                                                  0x028b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R                                                  0x028c
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B                                                        0x028d
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B                                                        0x028e
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G                                                        0x028f
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G                                                        0x0290
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R                                                        0x0291
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R                                                        0x0292
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B                                                           0x0293
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G                                                           0x0294
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R                                                           0x0295
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1                                                         0x0296
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3                                                         0x0297
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5                                                         0x0298
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7                                                         0x0299
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9                                                         0x029a
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11                                                       0x029b
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13                                                       0x029c
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15                                                       0x029d
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17                                                       0x029e
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19                                                       0x029f
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21                                                       0x02a0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23                                                       0x02a1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25                                                       0x02a2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27                                                       0x02a3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29                                                       0x02a4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31                                                       0x02a5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33                                                       0x02a6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B                                                       0x02a7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G                                                       0x02a8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R                                                       0x02a9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B                                                 0x02aa
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G                                                 0x02ab
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R                                                 0x02ac
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX                                        3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B                                                  0x02ad
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G                                                  0x02ae
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R                                                  0x02af
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX                                         3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B                                                        0x02b0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B                                                        0x02b1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G                                                        0x02b2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G                                                        0x02b3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R                                                        0x02b4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R                                                        0x02b5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX                                               3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B                                                           0x02b6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G                                                           0x02b7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R                                                           0x02b8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX                                                  3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1                                                         0x02b9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3                                                         0x02ba
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5                                                         0x02bb
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7                                                         0x02bc
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9                                                         0x02bd
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11                                                       0x02be
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13                                                       0x02bf
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15                                                       0x02c0
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17                                                       0x02c1
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19                                                       0x02c2
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21                                                       0x02c3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23                                                       0x02c4
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25                                                       0x02c5
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27                                                       0x02c6
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29                                                       0x02c7
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31                                                       0x02c8
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33                                                       0x02c9
+#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX                                              3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT                                                      0x02ca
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX                                             3
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE                                                             0x02cb
+#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX                                                    3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A                                                         0x02cc
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A                                                         0x02cd
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A                                                         0x02ce
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A                                                         0x02cf
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A                                                         0x02d0
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A                                                         0x02d1
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B                                                         0x02d2
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B                                                         0x02d3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B                                                         0x02d4
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B                                                         0x02d5
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B                                                         0x02d6
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX                                                3
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B                                                         0x02d7
+#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX                                                3
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+// base address: 0x0
+#define regMPC_OUT0_MUX                                                                                 0x0580
+#define regMPC_OUT0_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT0_DENORM_CONTROL                                                                      0x0581
+#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT0_DENORM_CLAMP_G_Y                                                                    0x0582
+#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT0_DENORM_CLAMP_B_CB                                                                   0x0583
+#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT1_MUX                                                                                 0x0584
+#define regMPC_OUT1_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT1_DENORM_CONTROL                                                                      0x0585
+#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT1_DENORM_CLAMP_G_Y                                                                    0x0586
+#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT1_DENORM_CLAMP_B_CB                                                                   0x0587
+#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT2_MUX                                                                                 0x0588
+#define regMPC_OUT2_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT2_DENORM_CONTROL                                                                      0x0589
+#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT2_DENORM_CLAMP_G_Y                                                                    0x058a
+#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT2_DENORM_CLAMP_B_CB                                                                   0x058b
+#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT3_MUX                                                                                 0x058c
+#define regMPC_OUT3_MUX_BASE_IDX                                                                        3
+#define regMPC_OUT3_DENORM_CONTROL                                                                      0x058d
+#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX                                                             3
+#define regMPC_OUT3_DENORM_CLAMP_G_Y                                                                    0x058e
+#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX                                                           3
+#define regMPC_OUT3_DENORM_CLAMP_B_CB                                                                   0x058f
+#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX                                                          3
+#define regMPC_OUT_CSC_COEF_FORMAT                                                                      0x05a0
+#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX                                                             3
+#define regMPC_OUT0_CSC_MODE                                                                            0x05a1
+#define regMPC_OUT0_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT0_CSC_C11_C12_A                                                                       0x05a2
+#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_A                                                                       0x05a3
+#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_A                                                                       0x05a4
+#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_A                                                                       0x05a5
+#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_A                                                                       0x05a6
+#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_A                                                                       0x05a7
+#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C11_C12_B                                                                       0x05a8
+#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C13_C14_B                                                                       0x05a9
+#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C21_C22_B                                                                       0x05aa
+#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C23_C24_B                                                                       0x05ab
+#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C31_C32_B                                                                       0x05ac
+#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT0_CSC_C33_C34_B                                                                       0x05ad
+#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_MODE                                                                            0x05ae
+#define regMPC_OUT1_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT1_CSC_C11_C12_A                                                                       0x05af
+#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_A                                                                       0x05b0
+#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_A                                                                       0x05b1
+#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_A                                                                       0x05b2
+#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_A                                                                       0x05b3
+#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_A                                                                       0x05b4
+#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C11_C12_B                                                                       0x05b5
+#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C13_C14_B                                                                       0x05b6
+#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C21_C22_B                                                                       0x05b7
+#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C23_C24_B                                                                       0x05b8
+#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C31_C32_B                                                                       0x05b9
+#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT1_CSC_C33_C34_B                                                                       0x05ba
+#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_MODE                                                                            0x05bb
+#define regMPC_OUT2_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT2_CSC_C11_C12_A                                                                       0x05bc
+#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_A                                                                       0x05bd
+#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_A                                                                       0x05be
+#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_A                                                                       0x05bf
+#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_A                                                                       0x05c0
+#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_A                                                                       0x05c1
+#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C11_C12_B                                                                       0x05c2
+#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C13_C14_B                                                                       0x05c3
+#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C21_C22_B                                                                       0x05c4
+#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C23_C24_B                                                                       0x05c5
+#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C31_C32_B                                                                       0x05c6
+#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT2_CSC_C33_C34_B                                                                       0x05c7
+#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_MODE                                                                            0x05c8
+#define regMPC_OUT3_CSC_MODE_BASE_IDX                                                                   3
+#define regMPC_OUT3_CSC_C11_C12_A                                                                       0x05c9
+#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_A                                                                       0x05ca
+#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_A                                                                       0x05cb
+#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_A                                                                       0x05cc
+#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_A                                                                       0x05cd
+#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_A                                                                       0x05ce
+#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C11_C12_B                                                                       0x05cf
+#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C13_C14_B                                                                       0x05d0
+#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C21_C22_B                                                                       0x05d1
+#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C23_C24_B                                                                       0x05d2
+#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C31_C32_B                                                                       0x05d3
+#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX                                                              3
+#define regMPC_OUT3_CSC_C33_C34_B                                                                       0x05d4
+#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX                                                              3
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+// base address: 0x0
+#define regMPC_RMU_CONTROL                                                                              0x0680
+#define regMPC_RMU_CONTROL_BASE_IDX                                                                     3
+#define regMPC_RMU_MEM_PWR_CTRL                                                                         0x0681
+#define regMPC_RMU_MEM_PWR_CTRL_BASE_IDX                                                                3
+#define regMPC_RMU0_SHAPER_CONTROL                                                                      0x0682
+#define regMPC_RMU0_SHAPER_CONTROL_BASE_IDX                                                             3
+#define regMPC_RMU0_SHAPER_OFFSET_R                                                                     0x0683
+#define regMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_OFFSET_G                                                                     0x0684
+#define regMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_OFFSET_B                                                                     0x0685
+#define regMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_SCALE_R                                                                      0x0686
+#define regMPC_RMU0_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define regMPC_RMU0_SHAPER_SCALE_G_B                                                                    0x0687
+#define regMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define regMPC_RMU0_SHAPER_LUT_INDEX                                                                    0x0688
+#define regMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define regMPC_RMU0_SHAPER_LUT_DATA                                                                     0x0689
+#define regMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK                                                            0x068a
+#define regMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B                                                            0x068b
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G                                                            0x068c
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R                                                            0x068d
+#define regMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B                                                              0x068e
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G                                                              0x068f
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R                                                              0x0690
+#define regMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1                                                              0x0691
+#define regMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3                                                              0x0692
+#define regMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5                                                              0x0693
+#define regMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7                                                              0x0694
+#define regMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9                                                              0x0695
+#define regMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11                                                            0x0696
+#define regMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13                                                            0x0697
+#define regMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15                                                            0x0698
+#define regMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17                                                            0x0699
+#define regMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19                                                            0x069a
+#define regMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21                                                            0x069b
+#define regMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23                                                            0x069c
+#define regMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25                                                            0x069d
+#define regMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27                                                            0x069e
+#define regMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29                                                            0x069f
+#define regMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31                                                            0x06a0
+#define regMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33                                                            0x06a1
+#define regMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B                                                            0x06a2
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G                                                            0x06a3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R                                                            0x06a4
+#define regMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B                                                              0x06a5
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G                                                              0x06a6
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R                                                              0x06a7
+#define regMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1                                                              0x06a8
+#define regMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3                                                              0x06a9
+#define regMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5                                                              0x06aa
+#define regMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7                                                              0x06ab
+#define regMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9                                                              0x06ac
+#define regMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11                                                            0x06ad
+#define regMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13                                                            0x06ae
+#define regMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15                                                            0x06af
+#define regMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17                                                            0x06b0
+#define regMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19                                                            0x06b1
+#define regMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21                                                            0x06b2
+#define regMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23                                                            0x06b3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25                                                            0x06b4
+#define regMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27                                                            0x06b5
+#define regMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29                                                            0x06b6
+#define regMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31                                                            0x06b7
+#define regMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33                                                            0x06b8
+#define regMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU0_3DLUT_MODE                                                                          0x06b9
+#define regMPC_RMU0_3DLUT_MODE_BASE_IDX                                                                 3
+#define regMPC_RMU0_3DLUT_INDEX                                                                         0x06ba
+#define regMPC_RMU0_3DLUT_INDEX_BASE_IDX                                                                3
+#define regMPC_RMU0_3DLUT_DATA                                                                          0x06bb
+#define regMPC_RMU0_3DLUT_DATA_BASE_IDX                                                                 3
+#define regMPC_RMU0_3DLUT_DATA_30BIT                                                                    0x06bc
+#define regMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL                                                            0x06bd
+#define regMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR                                                               0x06be
+#define regMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_R                                                                  0x06bf
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_G                                                                  0x06c0
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_B                                                                  0x06c1
+#define regMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+#define regMPC_RMU1_SHAPER_CONTROL                                                                      0x06c2
+#define regMPC_RMU1_SHAPER_CONTROL_BASE_IDX                                                             3
+#define regMPC_RMU1_SHAPER_OFFSET_R                                                                     0x06c3
+#define regMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_OFFSET_G                                                                     0x06c4
+#define regMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_OFFSET_B                                                                     0x06c5
+#define regMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_SCALE_R                                                                      0x06c6
+#define regMPC_RMU1_SHAPER_SCALE_R_BASE_IDX                                                             3
+#define regMPC_RMU1_SHAPER_SCALE_G_B                                                                    0x06c7
+#define regMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX                                                           3
+#define regMPC_RMU1_SHAPER_LUT_INDEX                                                                    0x06c8
+#define regMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX                                                           3
+#define regMPC_RMU1_SHAPER_LUT_DATA                                                                     0x06c9
+#define regMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX                                                            3
+#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK                                                            0x06ca
+#define regMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B                                                            0x06cb
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G                                                            0x06cc
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R                                                            0x06cd
+#define regMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B                                                              0x06ce
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G                                                              0x06cf
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R                                                              0x06d0
+#define regMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1                                                              0x06d1
+#define regMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3                                                              0x06d2
+#define regMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5                                                              0x06d3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7                                                              0x06d4
+#define regMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9                                                              0x06d5
+#define regMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11                                                            0x06d6
+#define regMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13                                                            0x06d7
+#define regMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15                                                            0x06d8
+#define regMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17                                                            0x06d9
+#define regMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19                                                            0x06da
+#define regMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21                                                            0x06db
+#define regMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23                                                            0x06dc
+#define regMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25                                                            0x06dd
+#define regMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27                                                            0x06de
+#define regMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29                                                            0x06df
+#define regMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31                                                            0x06e0
+#define regMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33                                                            0x06e1
+#define regMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B                                                            0x06e2
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G                                                            0x06e3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R                                                            0x06e4
+#define regMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B                                                              0x06e5
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G                                                              0x06e6
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R                                                              0x06e7
+#define regMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1                                                              0x06e8
+#define regMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3                                                              0x06e9
+#define regMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5                                                              0x06ea
+#define regMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7                                                              0x06eb
+#define regMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9                                                              0x06ec
+#define regMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX                                                     3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11                                                            0x06ed
+#define regMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13                                                            0x06ee
+#define regMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15                                                            0x06ef
+#define regMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17                                                            0x06f0
+#define regMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19                                                            0x06f1
+#define regMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21                                                            0x06f2
+#define regMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23                                                            0x06f3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25                                                            0x06f4
+#define regMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27                                                            0x06f5
+#define regMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29                                                            0x06f6
+#define regMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31                                                            0x06f7
+#define regMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX                                                   3
+#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33                                                            0x06f8
+#define regMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX                                                   3
+#define regMPC_RMU1_3DLUT_MODE                                                                          0x06f9
+#define regMPC_RMU1_3DLUT_MODE_BASE_IDX                                                                 3
+#define regMPC_RMU1_3DLUT_INDEX                                                                         0x06fa
+#define regMPC_RMU1_3DLUT_INDEX_BASE_IDX                                                                3
+#define regMPC_RMU1_3DLUT_DATA                                                                          0x06fb
+#define regMPC_RMU1_3DLUT_DATA_BASE_IDX                                                                 3
+#define regMPC_RMU1_3DLUT_DATA_30BIT                                                                    0x06fc
+#define regMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX                                                           3
+#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL                                                            0x06fd
+#define regMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX                                                   3
+#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR                                                               0x06fe
+#define regMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX                                                      3
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_R                                                                  0x06ff
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX                                                         3
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_G                                                                  0x0700
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX                                                         3
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_B                                                                  0x0701
+#define regMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+// base address: 0x0
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0e7a
+#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM0_BL1_PWM_USER_LEVEL                                                                      0x0e7b
+#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0e7c
+#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0e7d
+#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0e7e
+#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0e7f
+#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM0_BL1_PWM_ABM_CNTL                                                                        0x0e80
+#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0e81
+#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM0_BL1_PWM_GRP2_REG_LOCK                                                                   0x0e82
+#define regABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_CNTL                                                                            0x0e83
+#define regABM0_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0e84
+#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0e85
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0e86
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0e87
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0e88
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0e89
+#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM0_DC_ABM1_ACE_THRES_12                                                                    0x0e8a
+#define regABM0_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_THRES_34                                                                    0x0e8b
+#define regABM0_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_ACE_CNTL_MISC                                                                   0x0e8c
+#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0e8e
+#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_MISC_CTRL                                                                    0x0e8f
+#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0e90
+#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0e91
+#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0e92
+#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0e93
+#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0e94
+#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0e95
+#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0e96
+#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0e97
+#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0e98
+#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0e99
+#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0e9a
+#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0e9b
+#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0e9c
+#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0e9d
+#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM0_DC_ABM1_HG_RESULT_1                                                                     0x0e9e
+#define regABM0_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_2                                                                     0x0e9f
+#define regABM0_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_3                                                                     0x0ea0
+#define regABM0_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_4                                                                     0x0ea1
+#define regABM0_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_5                                                                     0x0ea2
+#define regABM0_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_6                                                                     0x0ea3
+#define regABM0_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_7                                                                     0x0ea4
+#define regABM0_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_8                                                                     0x0ea5
+#define regABM0_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_9                                                                     0x0ea6
+#define regABM0_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM0_DC_ABM1_HG_RESULT_10                                                                    0x0ea7
+#define regABM0_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_11                                                                    0x0ea8
+#define regABM0_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_12                                                                    0x0ea9
+#define regABM0_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_13                                                                    0x0eaa
+#define regABM0_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_14                                                                    0x0eab
+#define regABM0_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_15                                                                    0x0eac
+#define regABM0_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_16                                                                    0x0ead
+#define regABM0_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_17                                                                    0x0eae
+#define regABM0_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_18                                                                    0x0eaf
+#define regABM0_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_19                                                                    0x0eb0
+#define regABM0_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_20                                                                    0x0eb1
+#define regABM0_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_21                                                                    0x0eb2
+#define regABM0_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_22                                                                    0x0eb3
+#define regABM0_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_23                                                                    0x0eb4
+#define regABM0_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_HG_RESULT_24                                                                    0x0eb5
+#define regABM0_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM0_DC_ABM1_BL_MASTER_LOCK                                                                  0x0eb6
+#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+// base address: 0x104
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0ebb
+#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM1_BL1_PWM_USER_LEVEL                                                                      0x0ebc
+#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0ebd
+#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0ebe
+#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0ebf
+#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0ec0
+#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM1_BL1_PWM_ABM_CNTL                                                                        0x0ec1
+#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0ec2
+#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK                                                                   0x0ec3
+#define regABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_CNTL                                                                            0x0ec4
+#define regABM1_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0ec5
+#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0ec6
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0ec7
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0ec8
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0ec9
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0eca
+#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM1_DC_ABM1_ACE_THRES_12                                                                    0x0ecb
+#define regABM1_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_THRES_34                                                                    0x0ecc
+#define regABM1_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_ACE_CNTL_MISC                                                                   0x0ecd
+#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0ecf
+#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_MISC_CTRL                                                                    0x0ed0
+#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0ed1
+#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0ed2
+#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0ed3
+#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0ed4
+#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0ed5
+#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0ed6
+#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0ed7
+#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0ed8
+#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0ed9
+#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0eda
+#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0edb
+#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0edc
+#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0edd
+#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0ede
+#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM1_DC_ABM1_HG_RESULT_1                                                                     0x0edf
+#define regABM1_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_2                                                                     0x0ee0
+#define regABM1_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_3                                                                     0x0ee1
+#define regABM1_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_4                                                                     0x0ee2
+#define regABM1_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_5                                                                     0x0ee3
+#define regABM1_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_6                                                                     0x0ee4
+#define regABM1_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_7                                                                     0x0ee5
+#define regABM1_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_8                                                                     0x0ee6
+#define regABM1_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_9                                                                     0x0ee7
+#define regABM1_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM1_DC_ABM1_HG_RESULT_10                                                                    0x0ee8
+#define regABM1_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_11                                                                    0x0ee9
+#define regABM1_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_12                                                                    0x0eea
+#define regABM1_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_13                                                                    0x0eeb
+#define regABM1_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_14                                                                    0x0eec
+#define regABM1_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_15                                                                    0x0eed
+#define regABM1_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_16                                                                    0x0eee
+#define regABM1_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_17                                                                    0x0eef
+#define regABM1_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_18                                                                    0x0ef0
+#define regABM1_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_19                                                                    0x0ef1
+#define regABM1_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_20                                                                    0x0ef2
+#define regABM1_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_21                                                                    0x0ef3
+#define regABM1_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_22                                                                    0x0ef4
+#define regABM1_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_23                                                                    0x0ef5
+#define regABM1_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_HG_RESULT_24                                                                    0x0ef6
+#define regABM1_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM1_DC_ABM1_BL_MASTER_LOCK                                                                  0x0ef7
+#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+// base address: 0x208
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0efc
+#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM2_BL1_PWM_USER_LEVEL                                                                      0x0efd
+#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0efe
+#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0eff
+#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f00
+#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f01
+#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM2_BL1_PWM_ABM_CNTL                                                                        0x0f02
+#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f03
+#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM2_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f04
+#define regABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_CNTL                                                                            0x0f05
+#define regABM2_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f06
+#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f07
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f08
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f09
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f0a
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f0b
+#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM2_DC_ABM1_ACE_THRES_12                                                                    0x0f0c
+#define regABM2_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_THRES_34                                                                    0x0f0d
+#define regABM2_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f0e
+#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f10
+#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_MISC_CTRL                                                                    0x0f11
+#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f12
+#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f13
+#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f14
+#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f15
+#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f16
+#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f17
+#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f18
+#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f19
+#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f1a
+#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f1b
+#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f1c
+#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f1d
+#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f1e
+#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f1f
+#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM2_DC_ABM1_HG_RESULT_1                                                                     0x0f20
+#define regABM2_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_2                                                                     0x0f21
+#define regABM2_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_3                                                                     0x0f22
+#define regABM2_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_4                                                                     0x0f23
+#define regABM2_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_5                                                                     0x0f24
+#define regABM2_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_6                                                                     0x0f25
+#define regABM2_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_7                                                                     0x0f26
+#define regABM2_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_8                                                                     0x0f27
+#define regABM2_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_9                                                                     0x0f28
+#define regABM2_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM2_DC_ABM1_HG_RESULT_10                                                                    0x0f29
+#define regABM2_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_11                                                                    0x0f2a
+#define regABM2_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_12                                                                    0x0f2b
+#define regABM2_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_13                                                                    0x0f2c
+#define regABM2_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_14                                                                    0x0f2d
+#define regABM2_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_15                                                                    0x0f2e
+#define regABM2_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_16                                                                    0x0f2f
+#define regABM2_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_17                                                                    0x0f30
+#define regABM2_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_18                                                                    0x0f31
+#define regABM2_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_19                                                                    0x0f32
+#define regABM2_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_20                                                                    0x0f33
+#define regABM2_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_21                                                                    0x0f34
+#define regABM2_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_22                                                                    0x0f35
+#define regABM2_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_23                                                                    0x0f36
+#define regABM2_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_HG_RESULT_24                                                                    0x0f37
+#define regABM2_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM2_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f38
+#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+// base address: 0x30c
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL                                                             0x0f3d
+#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX                                                    3
+#define regABM3_BL1_PWM_USER_LEVEL                                                                      0x0f3e
+#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX                                                             3
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL                                                                0x0f3f
+#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL                                                               0x0f40
+#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX                                                      3
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE                                                                0x0f41
+#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX                                                       3
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE                                                              0x0f42
+#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX                                                     3
+#define regABM3_BL1_PWM_ABM_CNTL                                                                        0x0f43
+#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX                                                               3
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE                                                           0x0f44
+#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX                                                  3
+#define regABM3_BL1_PWM_GRP2_REG_LOCK                                                                   0x0f45
+#define regABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_CNTL                                                                            0x0f46
+#define regABM3_DC_ABM1_CNTL_BASE_IDX                                                                   3
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL                                                                 0x0f47
+#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0                                                              0x0f48
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1                                                              0x0f49
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2                                                              0x0f4a
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3                                                              0x0f4b
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4                                                              0x0f4c
+#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX                                                     3
+#define regABM3_DC_ABM1_ACE_THRES_12                                                                    0x0f4d
+#define regABM3_DC_ABM1_ACE_THRES_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_THRES_34                                                                    0x0f4e
+#define regABM3_DC_ABM1_ACE_THRES_34_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_ACE_CNTL_MISC                                                                   0x0f4f
+#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX                                                          3
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS                                                          0x0f51
+#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_MISC_CTRL                                                                    0x0f52
+#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA                                                                  0x0f53
+#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA                                                                 0x0f54
+#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX                                                        3
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA                                                        0x0f55
+#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT                                                                  0x0f56
+#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES                                                    0x0f57
+#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX                                           3
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT                                                        0x0f58
+#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT                                                        0x0f59
+#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE                                                                  0x0f5a
+#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE                                                                  0x0f5b
+#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX                                                         3
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG                                                          0x0f5c
+#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX                                                          0x0f5d
+#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX                                                 3
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX                                                         0x0f5e
+#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX                                                3
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX                                                        0x0f5f
+#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX                                                        0x0f60
+#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX                                               3
+#define regABM3_DC_ABM1_HG_RESULT_1                                                                     0x0f61
+#define regABM3_DC_ABM1_HG_RESULT_1_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_2                                                                     0x0f62
+#define regABM3_DC_ABM1_HG_RESULT_2_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_3                                                                     0x0f63
+#define regABM3_DC_ABM1_HG_RESULT_3_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_4                                                                     0x0f64
+#define regABM3_DC_ABM1_HG_RESULT_4_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_5                                                                     0x0f65
+#define regABM3_DC_ABM1_HG_RESULT_5_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_6                                                                     0x0f66
+#define regABM3_DC_ABM1_HG_RESULT_6_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_7                                                                     0x0f67
+#define regABM3_DC_ABM1_HG_RESULT_7_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_8                                                                     0x0f68
+#define regABM3_DC_ABM1_HG_RESULT_8_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_9                                                                     0x0f69
+#define regABM3_DC_ABM1_HG_RESULT_9_BASE_IDX                                                            3
+#define regABM3_DC_ABM1_HG_RESULT_10                                                                    0x0f6a
+#define regABM3_DC_ABM1_HG_RESULT_10_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_11                                                                    0x0f6b
+#define regABM3_DC_ABM1_HG_RESULT_11_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_12                                                                    0x0f6c
+#define regABM3_DC_ABM1_HG_RESULT_12_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_13                                                                    0x0f6d
+#define regABM3_DC_ABM1_HG_RESULT_13_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_14                                                                    0x0f6e
+#define regABM3_DC_ABM1_HG_RESULT_14_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_15                                                                    0x0f6f
+#define regABM3_DC_ABM1_HG_RESULT_15_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_16                                                                    0x0f70
+#define regABM3_DC_ABM1_HG_RESULT_16_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_17                                                                    0x0f71
+#define regABM3_DC_ABM1_HG_RESULT_17_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_18                                                                    0x0f72
+#define regABM3_DC_ABM1_HG_RESULT_18_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_19                                                                    0x0f73
+#define regABM3_DC_ABM1_HG_RESULT_19_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_20                                                                    0x0f74
+#define regABM3_DC_ABM1_HG_RESULT_20_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_21                                                                    0x0f75
+#define regABM3_DC_ABM1_HG_RESULT_21_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_22                                                                    0x0f76
+#define regABM3_DC_ABM1_HG_RESULT_22_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_23                                                                    0x0f77
+#define regABM3_DC_ABM1_HG_RESULT_23_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_HG_RESULT_24                                                                    0x0f78
+#define regABM3_DC_ABM1_HG_RESULT_24_BASE_IDX                                                           3
+#define regABM3_DC_ABM1_BL_MASTER_LOCK                                                                  0x0f79
+#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX                                                         3
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+// base address: 0x0
+#define regDPG0_DPG_CONTROL                                                                             0x1854
+#define regDPG0_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG0_DPG_RAMP_CONTROL                                                                        0x1855
+#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG0_DPG_DIMENSIONS                                                                          0x1856
+#define regDPG0_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_R_CR                                                                         0x1857
+#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG0_DPG_COLOUR_G_Y                                                                          0x1858
+#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG0_DPG_COLOUR_B_CB                                                                         0x1859
+#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG0_DPG_OFFSET_SEGMENT                                                                      0x185a
+#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG0_DPG_STATUS                                                                              0x185b
+#define regDPG0_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+// base address: 0x0
+#define regFMT0_FMT_CLAMP_COMPONENT_R                                                                   0x183c
+#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_G                                                                   0x183d
+#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT0_FMT_CLAMP_COMPONENT_B                                                                   0x183e
+#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL                                                                    0x183f
+#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT0_FMT_CONTROL                                                                             0x1840
+#define regFMT0_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT0_FMT_BIT_DEPTH_CONTROL                                                                   0x1841
+#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT0_FMT_DITHER_RAND_R_SEED                                                                  0x1842
+#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_G_SEED                                                                  0x1843
+#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_DITHER_RAND_B_SEED                                                                  0x1844
+#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT0_FMT_CLAMP_CNTL                                                                          0x1845
+#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1846
+#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL                                                               0x1847
+#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT0_FMT_422_CONTROL                                                                         0x1849
+#define regFMT0_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+// base address: 0x0
+#define regOPPBUF0_OPPBUF_CONTROL                                                                       0x1884
+#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0                                                               0x1885
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1                                                               0x1886
+#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF0_OPPBUF_CONTROL1                                                                      0x1889
+#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+// base address: 0x0
+#define regOPP_PIPE0_OPP_PIPE_CONTROL                                                                   0x188c
+#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+// base address: 0x0
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL                                                           0x1891
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK                                                              0x1892
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0                                                           0x1893
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1                                                           0x1894
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2                                                           0x1895
+#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+// base address: 0x168
+#define regDPG1_DPG_CONTROL                                                                             0x18ae
+#define regDPG1_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG1_DPG_RAMP_CONTROL                                                                        0x18af
+#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG1_DPG_DIMENSIONS                                                                          0x18b0
+#define regDPG1_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_R_CR                                                                         0x18b1
+#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG1_DPG_COLOUR_G_Y                                                                          0x18b2
+#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG1_DPG_COLOUR_B_CB                                                                         0x18b3
+#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG1_DPG_OFFSET_SEGMENT                                                                      0x18b4
+#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG1_DPG_STATUS                                                                              0x18b5
+#define regDPG1_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+// base address: 0x168
+#define regFMT1_FMT_CLAMP_COMPONENT_R                                                                   0x1896
+#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_G                                                                   0x1897
+#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT1_FMT_CLAMP_COMPONENT_B                                                                   0x1898
+#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL                                                                    0x1899
+#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT1_FMT_CONTROL                                                                             0x189a
+#define regFMT1_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT1_FMT_BIT_DEPTH_CONTROL                                                                   0x189b
+#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT1_FMT_DITHER_RAND_R_SEED                                                                  0x189c
+#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_G_SEED                                                                  0x189d
+#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_DITHER_RAND_B_SEED                                                                  0x189e
+#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT1_FMT_CLAMP_CNTL                                                                          0x189f
+#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18a0
+#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL                                                               0x18a1
+#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT1_FMT_422_CONTROL                                                                         0x18a3
+#define regFMT1_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+// base address: 0x168
+#define regOPPBUF1_OPPBUF_CONTROL                                                                       0x18de
+#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0                                                               0x18df
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1                                                               0x18e0
+#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF1_OPPBUF_CONTROL1                                                                      0x18e3
+#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+// base address: 0x168
+#define regOPP_PIPE1_OPP_PIPE_CONTROL                                                                   0x18e6
+#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+// base address: 0x168
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL                                                           0x18eb
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK                                                              0x18ec
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0                                                           0x18ed
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1                                                           0x18ee
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2                                                           0x18ef
+#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+// base address: 0x2d0
+#define regDPG2_DPG_CONTROL                                                                             0x1908
+#define regDPG2_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG2_DPG_RAMP_CONTROL                                                                        0x1909
+#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG2_DPG_DIMENSIONS                                                                          0x190a
+#define regDPG2_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_R_CR                                                                         0x190b
+#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG2_DPG_COLOUR_G_Y                                                                          0x190c
+#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG2_DPG_COLOUR_B_CB                                                                         0x190d
+#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG2_DPG_OFFSET_SEGMENT                                                                      0x190e
+#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG2_DPG_STATUS                                                                              0x190f
+#define regDPG2_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+// base address: 0x2d0
+#define regFMT2_FMT_CLAMP_COMPONENT_R                                                                   0x18f0
+#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_G                                                                   0x18f1
+#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT2_FMT_CLAMP_COMPONENT_B                                                                   0x18f2
+#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL                                                                    0x18f3
+#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT2_FMT_CONTROL                                                                             0x18f4
+#define regFMT2_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT2_FMT_BIT_DEPTH_CONTROL                                                                   0x18f5
+#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT2_FMT_DITHER_RAND_R_SEED                                                                  0x18f6
+#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_G_SEED                                                                  0x18f7
+#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_DITHER_RAND_B_SEED                                                                  0x18f8
+#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT2_FMT_CLAMP_CNTL                                                                          0x18f9
+#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x18fa
+#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL                                                               0x18fb
+#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT2_FMT_422_CONTROL                                                                         0x18fd
+#define regFMT2_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+// base address: 0x2d0
+#define regOPPBUF2_OPPBUF_CONTROL                                                                       0x1938
+#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0                                                               0x1939
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1                                                               0x193a
+#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF2_OPPBUF_CONTROL1                                                                      0x193d
+#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE2_OPP_PIPE_CONTROL                                                                   0x1940
+#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+// base address: 0x2d0
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL                                                           0x1945
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK                                                              0x1946
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0                                                           0x1947
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1                                                           0x1948
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2                                                           0x1949
+#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+// base address: 0x438
+#define regDPG3_DPG_CONTROL                                                                             0x1962
+#define regDPG3_DPG_CONTROL_BASE_IDX                                                                    2
+#define regDPG3_DPG_RAMP_CONTROL                                                                        0x1963
+#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX                                                               2
+#define regDPG3_DPG_DIMENSIONS                                                                          0x1964
+#define regDPG3_DPG_DIMENSIONS_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_R_CR                                                                         0x1965
+#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX                                                                2
+#define regDPG3_DPG_COLOUR_G_Y                                                                          0x1966
+#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX                                                                 2
+#define regDPG3_DPG_COLOUR_B_CB                                                                         0x1967
+#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX                                                                2
+#define regDPG3_DPG_OFFSET_SEGMENT                                                                      0x1968
+#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX                                                             2
+#define regDPG3_DPG_STATUS                                                                              0x1969
+#define regDPG3_DPG_STATUS_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+// base address: 0x438
+#define regFMT3_FMT_CLAMP_COMPONENT_R                                                                   0x194a
+#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_G                                                                   0x194b
+#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX                                                          2
+#define regFMT3_FMT_CLAMP_COMPONENT_B                                                                   0x194c
+#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX                                                          2
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL                                                                    0x194d
+#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX                                                           2
+#define regFMT3_FMT_CONTROL                                                                             0x194e
+#define regFMT3_FMT_CONTROL_BASE_IDX                                                                    2
+#define regFMT3_FMT_BIT_DEPTH_CONTROL                                                                   0x194f
+#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX                                                          2
+#define regFMT3_FMT_DITHER_RAND_R_SEED                                                                  0x1950
+#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_G_SEED                                                                  0x1951
+#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_DITHER_RAND_B_SEED                                                                  0x1952
+#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX                                                         2
+#define regFMT3_FMT_CLAMP_CNTL                                                                          0x1953
+#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX                                                                 2
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL                                                         0x1954
+#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX                                                2
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL                                                               0x1955
+#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX                                                      2
+#define regFMT3_FMT_422_CONTROL                                                                         0x1957
+#define regFMT3_FMT_422_CONTROL_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+// base address: 0x438
+#define regOPPBUF3_OPPBUF_CONTROL                                                                       0x1992
+#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX                                                              2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0                                                               0x1993
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1                                                               0x1994
+#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX                                                      2
+#define regOPPBUF3_OPPBUF_CONTROL1                                                                      0x1997
+#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+// base address: 0x438
+#define regOPP_PIPE3_OPP_PIPE_CONTROL                                                                   0x199a
+#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+// base address: 0x438
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL                                                           0x199f
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK                                                              0x19a0
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX                                                     2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0                                                           0x19a1
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1                                                           0x19a2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX                                                  2
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2                                                           0x19a3
+#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+// base address: 0x0
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a64
+#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+// base address: 0x4
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a65
+#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+// base address: 0x8
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG                                                              0x1a66
+#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+// base address: 0x0
+#define regOPP_TOP_CLK_CONTROL                                                                          0x1a5e
+#define regOPP_TOP_CLK_CONTROL_BASE_IDX                                                                 2
+#define regOPP_ABM_CONTROL                                                                              0x1a60
+#define regOPP_ABM_CONTROL_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+// base address: 0x6af8
+#define regDC_PERFMON16_PERFCOUNTER_CNTL                                                                0x1abe
+#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON16_PERFCOUNTER_CNTL2                                                               0x1abf
+#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON16_PERFCOUNTER_STATE                                                               0x1ac0
+#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON16_PERFMON_CNTL                                                                    0x1ac1
+#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON16_PERFMON_CNTL2                                                                   0x1ac2
+#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC                                                         0x1ac3
+#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON16_PERFMON_CVALUE_LOW                                                              0x1ac4
+#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON16_PERFMON_HI                                                                      0x1ac5
+#define regDC_PERFMON16_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON16_PERFMON_LOW                                                                     0x1ac6
+#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+// base address: 0x0
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aca
+#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM0_OPTC_DATA_SOURCE_SELECT                                                                 0x1acb
+#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM0_OPTC_DATA_FORMAT_CONTROL                                                                0x1acc
+#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_BYTES_PER_PIXEL                                                                    0x1acd
+#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM0_OPTC_WIDTH_CONTROL                                                                      0x1ace
+#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL                                                                0x1acf
+#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM0_OPTC_MEMORY_CONFIG                                                                      0x1ad0
+#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM0_OPTC_INPUT_SPARE_REGISTER                                                               0x1ad1
+#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+// base address: 0x40
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1ada
+#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM1_OPTC_DATA_SOURCE_SELECT                                                                 0x1adb
+#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM1_OPTC_DATA_FORMAT_CONTROL                                                                0x1adc
+#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_BYTES_PER_PIXEL                                                                    0x1add
+#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM1_OPTC_WIDTH_CONTROL                                                                      0x1ade
+#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL                                                                0x1adf
+#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM1_OPTC_MEMORY_CONFIG                                                                      0x1ae0
+#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM1_OPTC_INPUT_SPARE_REGISTER                                                               0x1ae1
+#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+// base address: 0x80
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1aea
+#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM2_OPTC_DATA_SOURCE_SELECT                                                                 0x1aeb
+#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM2_OPTC_DATA_FORMAT_CONTROL                                                                0x1aec
+#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_BYTES_PER_PIXEL                                                                    0x1aed
+#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM2_OPTC_WIDTH_CONTROL                                                                      0x1aee
+#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aef
+#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM2_OPTC_MEMORY_CONFIG                                                                      0x1af0
+#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM2_OPTC_INPUT_SPARE_REGISTER                                                               0x1af1
+#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+// base address: 0xc0
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL                                                               0x1afa
+#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX                                                      2
+#define regODM3_OPTC_DATA_SOURCE_SELECT                                                                 0x1afb
+#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX                                                        2
+#define regODM3_OPTC_DATA_FORMAT_CONTROL                                                                0x1afc
+#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_BYTES_PER_PIXEL                                                                    0x1afd
+#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX                                                           2
+#define regODM3_OPTC_WIDTH_CONTROL                                                                      0x1afe
+#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL                                                                0x1aff
+#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX                                                       2
+#define regODM3_OPTC_MEMORY_CONFIG                                                                      0x1b00
+#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX                                                             2
+#define regODM3_OPTC_INPUT_SPARE_REGISTER                                                               0x1b01
+#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+// base address: 0x0
+#define regOTG0_OTG_H_TOTAL                                                                             0x1b2a
+#define regOTG0_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_H_BLANK_START_END                                                                   0x1b2b
+#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_H_SYNC_A                                                                            0x1b2c
+#define regOTG0_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_H_SYNC_A_CNTL                                                                       0x1b2d
+#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_H_TIMING_CNTL                                                                       0x1b2e
+#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_V_TOTAL                                                                             0x1b2f
+#define regOTG0_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG0_OTG_V_TOTAL_MIN                                                                         0x1b30
+#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MAX                                                                         0x1b31
+#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_MID                                                                         0x1b32
+#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG0_OTG_V_TOTAL_CONTROL                                                                     0x1b33
+#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_V_TOTAL_INT_STATUS                                                                  0x1b34
+#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS                                                                0x1b35
+#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG0_OTG_V_BLANK_START_END                                                                   0x1b36
+#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG0_OTG_V_SYNC_A                                                                            0x1b37
+#define regOTG0_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG0_OTG_V_SYNC_A_CNTL                                                                       0x1b38
+#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG0_OTG_TRIGA_CNTL                                                                          0x1b39
+#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG                                                                   0x1b3a
+#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_TRIGB_CNTL                                                                          0x1b3b
+#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG                                                                   0x1b3c
+#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1b3d
+#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG0_OTG_FLOW_CONTROL                                                                        0x1b3e
+#define regOTG0_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1b3f
+#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG0_OTG_CONTROL                                                                             0x1b41
+#define regOTG0_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG0_OTG_INTERLACE_CONTROL                                                                   0x1b44
+#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_INTERLACE_STATUS                                                                    0x1b45
+#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG0_OTG_PIXEL_DATA_READBACK0                                                                0x1b47
+#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG0_OTG_PIXEL_DATA_READBACK1                                                                0x1b48
+#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG0_OTG_STATUS                                                                              0x1b49
+#define regOTG0_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG0_OTG_STATUS_POSITION                                                                     0x1b4a
+#define regOTG0_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG0_OTG_NOM_VERT_POSITION                                                                   0x1b4b
+#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_STATUS_FRAME_COUNT                                                                  0x1b4c
+#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG0_OTG_STATUS_VF_COUNT                                                                     0x1b4d
+#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_STATUS_HV_COUNT                                                                     0x1b4e
+#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG0_OTG_COUNT_CONTROL                                                                       0x1b4f
+#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_COUNT_RESET                                                                         0x1b50
+#define regOTG0_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1b51
+#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG0_OTG_VERT_SYNC_CONTROL                                                                   0x1b52
+#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_STEREO_STATUS                                                                       0x1b53
+#define regOTG0_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG0_OTG_STEREO_CONTROL                                                                      0x1b54
+#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG0_OTG_SNAPSHOT_STATUS                                                                     0x1b55
+#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG0_OTG_SNAPSHOT_CONTROL                                                                    0x1b56
+#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG0_OTG_SNAPSHOT_POSITION                                                                   0x1b57
+#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG0_OTG_SNAPSHOT_FRAME                                                                      0x1b58
+#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG0_OTG_INTERRUPT_CONTROL                                                                   0x1b59
+#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG0_OTG_UPDATE_LOCK                                                                         0x1b5a
+#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1b5b
+#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_MASTER_EN                                                                           0x1b5c
+#define regOTG0_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1b62
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1b63
+#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1b64
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1b65
+#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1b66
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1b67
+#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG0_OTG_CRC_CNTL                                                                            0x1b68
+#define regOTG0_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG0_OTG_CRC_CNTL2                                                                           0x1b69
+#define regOTG0_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1b6a
+#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1b6b
+#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1b6c
+#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1b6d
+#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC0_DATA_RG                                                                        0x1b6e
+#define regOTG0_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC0_DATA_B                                                                         0x1b6f
+#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1b70
+#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1b71
+#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1b72
+#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1b73
+#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC1_DATA_RG                                                                        0x1b74
+#define regOTG0_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC1_DATA_B                                                                         0x1b75
+#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC2_DATA_RG                                                                        0x1b76
+#define regOTG0_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC2_DATA_B                                                                         0x1b77
+#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC3_DATA_RG                                                                        0x1b78
+#define regOTG0_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG0_OTG_CRC3_DATA_B                                                                         0x1b79
+#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1b7a
+#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1b7b
+#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL                                                               0x1b82
+#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL                                                                0x1b83
+#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG0_OTG_GSL_VSYNC_GAP                                                                       0x1b84
+#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG0_OTG_MASTER_UPDATE_MODE                                                                  0x1b85
+#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG0_OTG_CLOCK_CONTROL                                                                       0x1b86
+#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG0_OTG_VSTARTUP_PARAM                                                                      0x1b87
+#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG0_OTG_VUPDATE_PARAM                                                                       0x1b88
+#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG0_OTG_VREADY_PARAM                                                                        0x1b89
+#define regOTG0_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS                                                                  0x1b8a
+#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_MASTER_UPDATE_LOCK                                                                  0x1b8b
+#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG0_OTG_GSL_CONTROL                                                                         0x1b8c
+#define regOTG0_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_GSL_WINDOW_X                                                                        0x1b8d
+#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG0_OTG_GSL_WINDOW_Y                                                                        0x1b8e
+#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG0_OTG_VUPDATE_KEEPOUT                                                                     0x1b8f
+#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL0                                                                     0x1b90
+#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL1                                                                     0x1b91
+#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL2                                                                     0x1b92
+#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL3                                                                     0x1b93
+#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG0_OTG_GLOBAL_CONTROL4                                                                     0x1b94
+#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL                                                                 0x1b95
+#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL                                                                 0x1b96
+#define regOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS                                                               0x1b97
+#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1b98
+#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1b99
+#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW                                                                  0x1b9a
+#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG0_OTG_DRR_CONTROL                                                                         0x1b9b
+#define regOTG0_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG0_OTG_M_CONST_DTO0                                                                        0x1b9c
+#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG0_OTG_M_CONST_DTO1                                                                        0x1b9d
+#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG0_OTG_REQUEST_CONTROL                                                                     0x1b9e
+#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG0_OTG_DSC_START_POSITION                                                                  0x1b9f
+#define regOTG0_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG0_OTG_PIPE_UPDATE_STATUS                                                                  0x1ba0
+#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG0_OTG_SPARE_REGISTER                                                                      0x1ba2
+#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+// base address: 0x200
+#define regOTG1_OTG_H_TOTAL                                                                             0x1baa
+#define regOTG1_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_H_BLANK_START_END                                                                   0x1bab
+#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_H_SYNC_A                                                                            0x1bac
+#define regOTG1_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_H_SYNC_A_CNTL                                                                       0x1bad
+#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_H_TIMING_CNTL                                                                       0x1bae
+#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_V_TOTAL                                                                             0x1baf
+#define regOTG1_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG1_OTG_V_TOTAL_MIN                                                                         0x1bb0
+#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MAX                                                                         0x1bb1
+#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_MID                                                                         0x1bb2
+#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG1_OTG_V_TOTAL_CONTROL                                                                     0x1bb3
+#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_V_TOTAL_INT_STATUS                                                                  0x1bb4
+#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS                                                                0x1bb5
+#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG1_OTG_V_BLANK_START_END                                                                   0x1bb6
+#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG1_OTG_V_SYNC_A                                                                            0x1bb7
+#define regOTG1_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG1_OTG_V_SYNC_A_CNTL                                                                       0x1bb8
+#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG1_OTG_TRIGA_CNTL                                                                          0x1bb9
+#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG                                                                   0x1bba
+#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_TRIGB_CNTL                                                                          0x1bbb
+#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG                                                                   0x1bbc
+#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1bbd
+#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG1_OTG_FLOW_CONTROL                                                                        0x1bbe
+#define regOTG1_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1bbf
+#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG1_OTG_CONTROL                                                                             0x1bc1
+#define regOTG1_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG1_OTG_INTERLACE_CONTROL                                                                   0x1bc4
+#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_INTERLACE_STATUS                                                                    0x1bc5
+#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG1_OTG_PIXEL_DATA_READBACK0                                                                0x1bc7
+#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG1_OTG_PIXEL_DATA_READBACK1                                                                0x1bc8
+#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG1_OTG_STATUS                                                                              0x1bc9
+#define regOTG1_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG1_OTG_STATUS_POSITION                                                                     0x1bca
+#define regOTG1_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG1_OTG_NOM_VERT_POSITION                                                                   0x1bcb
+#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_STATUS_FRAME_COUNT                                                                  0x1bcc
+#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG1_OTG_STATUS_VF_COUNT                                                                     0x1bcd
+#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_STATUS_HV_COUNT                                                                     0x1bce
+#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG1_OTG_COUNT_CONTROL                                                                       0x1bcf
+#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_COUNT_RESET                                                                         0x1bd0
+#define regOTG1_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1bd1
+#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG1_OTG_VERT_SYNC_CONTROL                                                                   0x1bd2
+#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_STEREO_STATUS                                                                       0x1bd3
+#define regOTG1_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG1_OTG_STEREO_CONTROL                                                                      0x1bd4
+#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG1_OTG_SNAPSHOT_STATUS                                                                     0x1bd5
+#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG1_OTG_SNAPSHOT_CONTROL                                                                    0x1bd6
+#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG1_OTG_SNAPSHOT_POSITION                                                                   0x1bd7
+#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG1_OTG_SNAPSHOT_FRAME                                                                      0x1bd8
+#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG1_OTG_INTERRUPT_CONTROL                                                                   0x1bd9
+#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG1_OTG_UPDATE_LOCK                                                                         0x1bda
+#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1bdb
+#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_MASTER_EN                                                                           0x1bdc
+#define regOTG1_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1be2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1be3
+#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1be4
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1be5
+#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1be6
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1be7
+#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG1_OTG_CRC_CNTL                                                                            0x1be8
+#define regOTG1_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG1_OTG_CRC_CNTL2                                                                           0x1be9
+#define regOTG1_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1bea
+#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1beb
+#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1bec
+#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1bed
+#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC0_DATA_RG                                                                        0x1bee
+#define regOTG1_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC0_DATA_B                                                                         0x1bef
+#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1bf0
+#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1bf1
+#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1bf2
+#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1bf3
+#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC1_DATA_RG                                                                        0x1bf4
+#define regOTG1_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC1_DATA_B                                                                         0x1bf5
+#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC2_DATA_RG                                                                        0x1bf6
+#define regOTG1_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC2_DATA_B                                                                         0x1bf7
+#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC3_DATA_RG                                                                        0x1bf8
+#define regOTG1_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG1_OTG_CRC3_DATA_B                                                                         0x1bf9
+#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1bfa
+#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1bfb
+#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL                                                               0x1c02
+#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL                                                                0x1c03
+#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG1_OTG_GSL_VSYNC_GAP                                                                       0x1c04
+#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG1_OTG_MASTER_UPDATE_MODE                                                                  0x1c05
+#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG1_OTG_CLOCK_CONTROL                                                                       0x1c06
+#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG1_OTG_VSTARTUP_PARAM                                                                      0x1c07
+#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG1_OTG_VUPDATE_PARAM                                                                       0x1c08
+#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG1_OTG_VREADY_PARAM                                                                        0x1c09
+#define regOTG1_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c0a
+#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_MASTER_UPDATE_LOCK                                                                  0x1c0b
+#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG1_OTG_GSL_CONTROL                                                                         0x1c0c
+#define regOTG1_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_GSL_WINDOW_X                                                                        0x1c0d
+#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG1_OTG_GSL_WINDOW_Y                                                                        0x1c0e
+#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG1_OTG_VUPDATE_KEEPOUT                                                                     0x1c0f
+#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL0                                                                     0x1c10
+#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL1                                                                     0x1c11
+#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL2                                                                     0x1c12
+#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL3                                                                     0x1c13
+#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG1_OTG_GLOBAL_CONTROL4                                                                     0x1c14
+#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c15
+#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c16
+#define regOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS                                                               0x1c17
+#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c18
+#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c19
+#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c1a
+#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG1_OTG_DRR_CONTROL                                                                         0x1c1b
+#define regOTG1_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG1_OTG_M_CONST_DTO0                                                                        0x1c1c
+#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG1_OTG_M_CONST_DTO1                                                                        0x1c1d
+#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG1_OTG_REQUEST_CONTROL                                                                     0x1c1e
+#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG1_OTG_DSC_START_POSITION                                                                  0x1c1f
+#define regOTG1_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG1_OTG_PIPE_UPDATE_STATUS                                                                  0x1c20
+#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG1_OTG_SPARE_REGISTER                                                                      0x1c22
+#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+// base address: 0x400
+#define regOTG2_OTG_H_TOTAL                                                                             0x1c2a
+#define regOTG2_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_H_BLANK_START_END                                                                   0x1c2b
+#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_H_SYNC_A                                                                            0x1c2c
+#define regOTG2_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_H_SYNC_A_CNTL                                                                       0x1c2d
+#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_H_TIMING_CNTL                                                                       0x1c2e
+#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_V_TOTAL                                                                             0x1c2f
+#define regOTG2_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG2_OTG_V_TOTAL_MIN                                                                         0x1c30
+#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MAX                                                                         0x1c31
+#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_MID                                                                         0x1c32
+#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG2_OTG_V_TOTAL_CONTROL                                                                     0x1c33
+#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_V_TOTAL_INT_STATUS                                                                  0x1c34
+#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS                                                                0x1c35
+#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG2_OTG_V_BLANK_START_END                                                                   0x1c36
+#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG2_OTG_V_SYNC_A                                                                            0x1c37
+#define regOTG2_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG2_OTG_V_SYNC_A_CNTL                                                                       0x1c38
+#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG2_OTG_TRIGA_CNTL                                                                          0x1c39
+#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG                                                                   0x1c3a
+#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_TRIGB_CNTL                                                                          0x1c3b
+#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG                                                                   0x1c3c
+#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1c3d
+#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG2_OTG_FLOW_CONTROL                                                                        0x1c3e
+#define regOTG2_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1c3f
+#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG2_OTG_CONTROL                                                                             0x1c41
+#define regOTG2_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG2_OTG_INTERLACE_CONTROL                                                                   0x1c44
+#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_INTERLACE_STATUS                                                                    0x1c45
+#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG2_OTG_PIXEL_DATA_READBACK0                                                                0x1c47
+#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG2_OTG_PIXEL_DATA_READBACK1                                                                0x1c48
+#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG2_OTG_STATUS                                                                              0x1c49
+#define regOTG2_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG2_OTG_STATUS_POSITION                                                                     0x1c4a
+#define regOTG2_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG2_OTG_NOM_VERT_POSITION                                                                   0x1c4b
+#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_STATUS_FRAME_COUNT                                                                  0x1c4c
+#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG2_OTG_STATUS_VF_COUNT                                                                     0x1c4d
+#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_STATUS_HV_COUNT                                                                     0x1c4e
+#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG2_OTG_COUNT_CONTROL                                                                       0x1c4f
+#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_COUNT_RESET                                                                         0x1c50
+#define regOTG2_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1c51
+#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG2_OTG_VERT_SYNC_CONTROL                                                                   0x1c52
+#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_STEREO_STATUS                                                                       0x1c53
+#define regOTG2_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG2_OTG_STEREO_CONTROL                                                                      0x1c54
+#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG2_OTG_SNAPSHOT_STATUS                                                                     0x1c55
+#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG2_OTG_SNAPSHOT_CONTROL                                                                    0x1c56
+#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG2_OTG_SNAPSHOT_POSITION                                                                   0x1c57
+#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG2_OTG_SNAPSHOT_FRAME                                                                      0x1c58
+#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG2_OTG_INTERRUPT_CONTROL                                                                   0x1c59
+#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG2_OTG_UPDATE_LOCK                                                                         0x1c5a
+#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1c5b
+#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_MASTER_EN                                                                           0x1c5c
+#define regOTG2_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1c62
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1c63
+#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1c64
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1c65
+#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1c66
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1c67
+#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG2_OTG_CRC_CNTL                                                                            0x1c68
+#define regOTG2_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG2_OTG_CRC_CNTL2                                                                           0x1c69
+#define regOTG2_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1c6a
+#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1c6b
+#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1c6c
+#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1c6d
+#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC0_DATA_RG                                                                        0x1c6e
+#define regOTG2_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC0_DATA_B                                                                         0x1c6f
+#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1c70
+#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1c71
+#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1c72
+#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1c73
+#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC1_DATA_RG                                                                        0x1c74
+#define regOTG2_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC1_DATA_B                                                                         0x1c75
+#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC2_DATA_RG                                                                        0x1c76
+#define regOTG2_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC2_DATA_B                                                                         0x1c77
+#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC3_DATA_RG                                                                        0x1c78
+#define regOTG2_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG2_OTG_CRC3_DATA_B                                                                         0x1c79
+#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1c7a
+#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1c7b
+#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL                                                               0x1c82
+#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL                                                                0x1c83
+#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG2_OTG_GSL_VSYNC_GAP                                                                       0x1c84
+#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG2_OTG_MASTER_UPDATE_MODE                                                                  0x1c85
+#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG2_OTG_CLOCK_CONTROL                                                                       0x1c86
+#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG2_OTG_VSTARTUP_PARAM                                                                      0x1c87
+#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG2_OTG_VUPDATE_PARAM                                                                       0x1c88
+#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG2_OTG_VREADY_PARAM                                                                        0x1c89
+#define regOTG2_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS                                                                  0x1c8a
+#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_MASTER_UPDATE_LOCK                                                                  0x1c8b
+#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG2_OTG_GSL_CONTROL                                                                         0x1c8c
+#define regOTG2_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_GSL_WINDOW_X                                                                        0x1c8d
+#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG2_OTG_GSL_WINDOW_Y                                                                        0x1c8e
+#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG2_OTG_VUPDATE_KEEPOUT                                                                     0x1c8f
+#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL0                                                                     0x1c90
+#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL1                                                                     0x1c91
+#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL2                                                                     0x1c92
+#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL3                                                                     0x1c93
+#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG2_OTG_GLOBAL_CONTROL4                                                                     0x1c94
+#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL                                                                 0x1c95
+#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL                                                                 0x1c96
+#define regOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS                                                               0x1c97
+#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1c98
+#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1c99
+#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW                                                                  0x1c9a
+#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG2_OTG_DRR_CONTROL                                                                         0x1c9b
+#define regOTG2_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG2_OTG_M_CONST_DTO0                                                                        0x1c9c
+#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG2_OTG_M_CONST_DTO1                                                                        0x1c9d
+#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG2_OTG_REQUEST_CONTROL                                                                     0x1c9e
+#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG2_OTG_DSC_START_POSITION                                                                  0x1c9f
+#define regOTG2_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG2_OTG_PIPE_UPDATE_STATUS                                                                  0x1ca0
+#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG2_OTG_SPARE_REGISTER                                                                      0x1ca2
+#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+// base address: 0x600
+#define regOTG3_OTG_H_TOTAL                                                                             0x1caa
+#define regOTG3_OTG_H_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_H_BLANK_START_END                                                                   0x1cab
+#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_H_SYNC_A                                                                            0x1cac
+#define regOTG3_OTG_H_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_H_SYNC_A_CNTL                                                                       0x1cad
+#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_H_TIMING_CNTL                                                                       0x1cae
+#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_V_TOTAL                                                                             0x1caf
+#define regOTG3_OTG_V_TOTAL_BASE_IDX                                                                    2
+#define regOTG3_OTG_V_TOTAL_MIN                                                                         0x1cb0
+#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MAX                                                                         0x1cb1
+#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_MID                                                                         0x1cb2
+#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX                                                                2
+#define regOTG3_OTG_V_TOTAL_CONTROL                                                                     0x1cb3
+#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_V_TOTAL_INT_STATUS                                                                  0x1cb4
+#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS                                                                0x1cb5
+#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX                                                       2
+#define regOTG3_OTG_V_BLANK_START_END                                                                   0x1cb6
+#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX                                                          2
+#define regOTG3_OTG_V_SYNC_A                                                                            0x1cb7
+#define regOTG3_OTG_V_SYNC_A_BASE_IDX                                                                   2
+#define regOTG3_OTG_V_SYNC_A_CNTL                                                                       0x1cb8
+#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX                                                              2
+#define regOTG3_OTG_TRIGA_CNTL                                                                          0x1cb9
+#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG                                                                   0x1cba
+#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_TRIGB_CNTL                                                                          0x1cbb
+#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX                                                                 2
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG                                                                   0x1cbc
+#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX                                                          2
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL                                                                0x1cbd
+#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX                                                       2
+#define regOTG3_OTG_FLOW_CONTROL                                                                        0x1cbe
+#define regOTG3_OTG_FLOW_CONTROL_BASE_IDX                                                               2
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE                                                               0x1cbf
+#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX                                                      2
+#define regOTG3_OTG_CONTROL                                                                             0x1cc1
+#define regOTG3_OTG_CONTROL_BASE_IDX                                                                    2
+#define regOTG3_OTG_INTERLACE_CONTROL                                                                   0x1cc4
+#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_INTERLACE_STATUS                                                                    0x1cc5
+#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX                                                           2
+#define regOTG3_OTG_PIXEL_DATA_READBACK0                                                                0x1cc7
+#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX                                                       2
+#define regOTG3_OTG_PIXEL_DATA_READBACK1                                                                0x1cc8
+#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX                                                       2
+#define regOTG3_OTG_STATUS                                                                              0x1cc9
+#define regOTG3_OTG_STATUS_BASE_IDX                                                                     2
+#define regOTG3_OTG_STATUS_POSITION                                                                     0x1cca
+#define regOTG3_OTG_STATUS_POSITION_BASE_IDX                                                            2
+#define regOTG3_OTG_NOM_VERT_POSITION                                                                   0x1ccb
+#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_STATUS_FRAME_COUNT                                                                  0x1ccc
+#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX                                                         2
+#define regOTG3_OTG_STATUS_VF_COUNT                                                                     0x1ccd
+#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_STATUS_HV_COUNT                                                                     0x1cce
+#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX                                                            2
+#define regOTG3_OTG_COUNT_CONTROL                                                                       0x1ccf
+#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_COUNT_RESET                                                                         0x1cd0
+#define regOTG3_OTG_COUNT_RESET_BASE_IDX                                                                2
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE                                                        0x1cd1
+#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX                                               2
+#define regOTG3_OTG_VERT_SYNC_CONTROL                                                                   0x1cd2
+#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_STEREO_STATUS                                                                       0x1cd3
+#define regOTG3_OTG_STEREO_STATUS_BASE_IDX                                                              2
+#define regOTG3_OTG_STEREO_CONTROL                                                                      0x1cd4
+#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX                                                             2
+#define regOTG3_OTG_SNAPSHOT_STATUS                                                                     0x1cd5
+#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX                                                            2
+#define regOTG3_OTG_SNAPSHOT_CONTROL                                                                    0x1cd6
+#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX                                                           2
+#define regOTG3_OTG_SNAPSHOT_POSITION                                                                   0x1cd7
+#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX                                                          2
+#define regOTG3_OTG_SNAPSHOT_FRAME                                                                      0x1cd8
+#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX                                                             2
+#define regOTG3_OTG_INTERRUPT_CONTROL                                                                   0x1cd9
+#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX                                                          2
+#define regOTG3_OTG_UPDATE_LOCK                                                                         0x1cda
+#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX                                                                2
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL                                                               0x1cdb
+#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_MASTER_EN                                                                           0x1cdc
+#define regOTG3_OTG_MASTER_EN_BASE_IDX                                                                  2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION                                                        0x1ce2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL                                                         0x1ce3
+#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION                                                        0x1ce4
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL                                                         0x1ce5
+#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION                                                        0x1ce6
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX                                               2
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL                                                         0x1ce7
+#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX                                                2
+#define regOTG3_OTG_CRC_CNTL                                                                            0x1ce8
+#define regOTG3_OTG_CRC_CNTL_BASE_IDX                                                                   2
+#define regOTG3_OTG_CRC_CNTL2                                                                           0x1ce9
+#define regOTG3_OTG_CRC_CNTL2_BASE_IDX                                                                  2
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL                                                              0x1cea
+#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL                                                              0x1ceb
+#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL                                                              0x1cec
+#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL                                                              0x1ced
+#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC0_DATA_RG                                                                        0x1cee
+#define regOTG3_OTG_CRC0_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC0_DATA_B                                                                         0x1cef
+#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL                                                              0x1cf0
+#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL                                                              0x1cf1
+#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL                                                              0x1cf2
+#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL                                                              0x1cf3
+#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC1_DATA_RG                                                                        0x1cf4
+#define regOTG3_OTG_CRC1_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC1_DATA_B                                                                         0x1cf5
+#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC2_DATA_RG                                                                        0x1cf6
+#define regOTG3_OTG_CRC2_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC2_DATA_B                                                                         0x1cf7
+#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC3_DATA_RG                                                                        0x1cf8
+#define regOTG3_OTG_CRC3_DATA_RG_BASE_IDX                                                               2
+#define regOTG3_OTG_CRC3_DATA_B                                                                         0x1cf9
+#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX                                                                2
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK                                                              0x1cfa
+#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX                                                     2
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK                                                           0x1cfb
+#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX                                                  2
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL                                                               0x1d02
+#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX                                                      2
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL                                                                0x1d03
+#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX                                                       2
+#define regOTG3_OTG_GSL_VSYNC_GAP                                                                       0x1d04
+#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX                                                              2
+#define regOTG3_OTG_MASTER_UPDATE_MODE                                                                  0x1d05
+#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX                                                         2
+#define regOTG3_OTG_CLOCK_CONTROL                                                                       0x1d06
+#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX                                                              2
+#define regOTG3_OTG_VSTARTUP_PARAM                                                                      0x1d07
+#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX                                                             2
+#define regOTG3_OTG_VUPDATE_PARAM                                                                       0x1d08
+#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX                                                              2
+#define regOTG3_OTG_VREADY_PARAM                                                                        0x1d09
+#define regOTG3_OTG_VREADY_PARAM_BASE_IDX                                                               2
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS                                                                  0x1d0a
+#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_MASTER_UPDATE_LOCK                                                                  0x1d0b
+#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX                                                         2
+#define regOTG3_OTG_GSL_CONTROL                                                                         0x1d0c
+#define regOTG3_OTG_GSL_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_GSL_WINDOW_X                                                                        0x1d0d
+#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX                                                               2
+#define regOTG3_OTG_GSL_WINDOW_Y                                                                        0x1d0e
+#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX                                                               2
+#define regOTG3_OTG_VUPDATE_KEEPOUT                                                                     0x1d0f
+#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL0                                                                     0x1d10
+#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL1                                                                     0x1d11
+#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL2                                                                     0x1d12
+#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL3                                                                     0x1d13
+#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX                                                            2
+#define regOTG3_OTG_GLOBAL_CONTROL4                                                                     0x1d14
+#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX                                                            2
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL                                                                 0x1d15
+#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL                                                                 0x1d16
+#define regOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX                                                        2
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS                                                               0x1d17
+#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX                                                      2
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE                                                             0x1d18
+#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX                                                    2
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE                                                                  0x1d19
+#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW                                                                  0x1d1a
+#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX                                                         2
+#define regOTG3_OTG_DRR_CONTROL                                                                         0x1d1b
+#define regOTG3_OTG_DRR_CONTROL_BASE_IDX                                                                2
+#define regOTG3_OTG_M_CONST_DTO0                                                                        0x1d1c
+#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX                                                               2
+#define regOTG3_OTG_M_CONST_DTO1                                                                        0x1d1d
+#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX                                                               2
+#define regOTG3_OTG_REQUEST_CONTROL                                                                     0x1d1e
+#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX                                                            2
+#define regOTG3_OTG_DSC_START_POSITION                                                                  0x1d1f
+#define regOTG3_OTG_DSC_START_POSITION_BASE_IDX                                                         2
+#define regOTG3_OTG_PIPE_UPDATE_STATUS                                                                  0x1d20
+#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX                                                         2
+#define regOTG3_OTG_SPARE_REGISTER                                                                      0x1d22
+#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+// base address: 0x0
+#define regDWB_SOURCE_SELECT                                                                            0x1e2a
+#define regDWB_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regGSL_SOURCE_SELECT                                                                            0x1e2b
+#define regGSL_SOURCE_SELECT_BASE_IDX                                                                   2
+#define regOPTC_CLOCK_CONTROL                                                                           0x1e2c
+#define regOPTC_CLOCK_CONTROL_BASE_IDX                                                                  2
+#define regODM_MEM_PWR_CTRL                                                                             0x1e2d
+#define regODM_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regODM_MEM_PWR_CTRL3                                                                            0x1e2f
+#define regODM_MEM_PWR_CTRL3_BASE_IDX                                                                   2
+#define regODM_MEM_PWR_STATUS                                                                           0x1e30
+#define regODM_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regOPTC_MISC_SPARE_REGISTER                                                                     0x1e31
+#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+// base address: 0x79a8
+#define regDC_PERFMON17_PERFCOUNTER_CNTL                                                                0x1e6a
+#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON17_PERFCOUNTER_CNTL2                                                               0x1e6b
+#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON17_PERFCOUNTER_STATE                                                               0x1e6c
+#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON17_PERFMON_CNTL                                                                    0x1e6d
+#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON17_PERFMON_CNTL2                                                                   0x1e6e
+#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC                                                         0x1e6f
+#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON17_PERFMON_CVALUE_LOW                                                              0x1e70
+#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON17_PERFMON_HI                                                                      0x1e71
+#define regDC_PERFMON17_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON17_PERFMON_LOW                                                                     0x1e72
+#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+// base address: 0x0
+#define regHPD0_DC_HPD_INT_STATUS                                                                       0x1f14
+#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD0_DC_HPD_INT_CONTROL                                                                      0x1f15
+#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD0_DC_HPD_CONTROL                                                                          0x1f16
+#define regHPD0_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f17
+#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f18
+#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+// base address: 0x20
+#define regHPD1_DC_HPD_INT_STATUS                                                                       0x1f1c
+#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD1_DC_HPD_INT_CONTROL                                                                      0x1f1d
+#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD1_DC_HPD_CONTROL                                                                          0x1f1e
+#define regHPD1_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f1f
+#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f20
+#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+// base address: 0x40
+#define regHPD2_DC_HPD_INT_STATUS                                                                       0x1f24
+#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD2_DC_HPD_INT_CONTROL                                                                      0x1f25
+#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD2_DC_HPD_CONTROL                                                                          0x1f26
+#define regHPD2_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f27
+#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f28
+#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+// base address: 0x60
+#define regHPD3_DC_HPD_INT_STATUS                                                                       0x1f2c
+#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD3_DC_HPD_INT_CONTROL                                                                      0x1f2d
+#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD3_DC_HPD_CONTROL                                                                          0x1f2e
+#define regHPD3_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f2f
+#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f30
+#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+// base address: 0x80
+#define regHPD4_DC_HPD_INT_STATUS                                                                       0x1f34
+#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX                                                              2
+#define regHPD4_DC_HPD_INT_CONTROL                                                                      0x1f35
+#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX                                                             2
+#define regHPD4_DC_HPD_CONTROL                                                                          0x1f36
+#define regHPD4_DC_HPD_CONTROL_BASE_IDX                                                                 2
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL                                                                  0x1f37
+#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX                                                         2
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL                                                                 0x1f38
+#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX                                                        2
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+// base address: 0x0
+#define regDP0_DP_LINK_CNTL                                                                             0x2108
+#define regDP0_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_PIXEL_FORMAT                                                                          0x2109
+#define regDP0_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP0_DP_MSA_COLORIMETRY                                                                       0x210a
+#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP0_DP_CONFIG                                                                                0x210b
+#define regDP0_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP0_DP_VID_STREAM_CNTL                                                                       0x210c
+#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_STEER_FIFO                                                                            0x210d
+#define regDP0_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP0_DP_MSA_MISC                                                                              0x210e
+#define regDP0_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP0_DP_DPHY_INTERNAL_CTRL                                                                    0x210f
+#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP0_DP_VID_TIMING                                                                            0x2110
+#define regDP0_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP0_DP_VID_N                                                                                 0x2111
+#define regDP0_DP_VID_N_BASE_IDX                                                                        2
+#define regDP0_DP_VID_M                                                                                 0x2112
+#define regDP0_DP_VID_M_BASE_IDX                                                                        2
+#define regDP0_DP_LINK_FRAMING_CNTL                                                                     0x2113
+#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_HBR2_EYE_PATTERN                                                                      0x2114
+#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP0_DP_VID_MSA_VBID                                                                          0x2115
+#define regDP0_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP0_DP_VID_INTERRUPT_CNTL                                                                    0x2116
+#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_CNTL                                                                             0x2117
+#define regDP0_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2118
+#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP0_DP_DPHY_SYM0                                                                             0x2119
+#define regDP0_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM1                                                                             0x211a
+#define regDP0_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_SYM2                                                                             0x211b
+#define regDP0_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP0_DP_DPHY_8B10B_CNTL                                                                       0x211c
+#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_PRBS_CNTL                                                                        0x211d
+#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP0_DP_DPHY_SCRAM_CNTL                                                                       0x211e
+#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_EN                                                                           0x211f
+#define regDP0_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP0_DP_DPHY_CRC_CNTL                                                                         0x2120
+#define regDP0_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_CRC_RESULT                                                                       0x2121
+#define regDP0_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP0_DP_DPHY_CRC_MST_CNTL                                                                     0x2122
+#define regDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP0_DP_DPHY_CRC_MST_STATUS                                                                   0x2123
+#define regDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP0_DP_DPHY_FAST_TRAINING                                                                    0x2124
+#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2125
+#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP0_DP_SEC_CNTL                                                                              0x212b
+#define regDP0_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL1                                                                             0x212c
+#define regDP0_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_FRAMING1                                                                          0x212d
+#define regDP0_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING2                                                                          0x212e
+#define regDP0_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING3                                                                          0x212f
+#define regDP0_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_FRAMING4                                                                          0x2130
+#define regDP0_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP0_DP_SEC_AUD_N                                                                             0x2131
+#define regDP0_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_N_READBACK                                                                    0x2132
+#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_AUD_M                                                                             0x2133
+#define regDP0_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_AUD_M_READBACK                                                                    0x2134
+#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP0_DP_SEC_TIMESTAMP                                                                         0x2135
+#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP0_DP_SEC_PACKET_CNTL                                                                       0x2136
+#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP0_DP_MSE_RATE_CNTL                                                                         0x2137
+#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_MSE_RATE_UPDATE                                                                       0x2139
+#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT0                                                                              0x213a
+#define regDP0_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT1                                                                              0x213b
+#define regDP0_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT2                                                                              0x213c
+#define regDP0_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP0_DP_MSE_SAT_UPDATE                                                                        0x213d
+#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP0_DP_MSE_LINK_TIMING                                                                       0x213e
+#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP0_DP_MSE_MISC_CNTL                                                                         0x213f
+#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2144
+#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2145
+#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP0_DP_MSE_SAT0_STATUS                                                                       0x2147
+#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT1_STATUS                                                                       0x2148
+#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSE_SAT2_STATUS                                                                       0x2149
+#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP0_DP_MSA_TIMING_PARAM1                                                                     0x214c
+#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM2                                                                     0x214d
+#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM3                                                                     0x214e
+#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP0_DP_MSA_TIMING_PARAM4                                                                     0x214f
+#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP0_DP_MSO_CNTL                                                                              0x2150
+#define regDP0_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_MSO_CNTL1                                                                             0x2151
+#define regDP0_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP0_DP_DSC_CNTL                                                                              0x2152
+#define regDP0_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP0_DP_SEC_CNTL2                                                                             0x2153
+#define regDP0_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL3                                                                             0x2154
+#define regDP0_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL4                                                                             0x2155
+#define regDP0_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL5                                                                             0x2156
+#define regDP0_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL6                                                                             0x2157
+#define regDP0_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP0_DP_SEC_CNTL7                                                                             0x2158
+#define regDP0_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP0_DP_DB_CNTL                                                                               0x2159
+#define regDP0_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP0_DP_MSA_VBID_MISC                                                                         0x215a
+#define regDP0_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP0_DP_SEC_METADATA_TRANSMISSION                                                             0x215b
+#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP0_DP_DSC_BYTES_PER_PIXEL                                                                   0x215c
+#define regDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP0_DP_ALPM_CNTL                                                                             0x215d
+#define regDP0_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP8_CNTL                                                                             0x215e
+#define regDP0_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP9_CNTL                                                                             0x215f
+#define regDP0_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP0_DP_GSP10_CNTL                                                                            0x2160
+#define regDP0_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP11_CNTL                                                                            0x2161
+#define regDP0_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP0_DP_GSP_EN_DB_STATUS                                                                      0x2162
+#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+// base address: 0x0
+#define regDIG0_DIG_FE_CNTL                                                                             0x208b
+#define regDIG0_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_OUTPUT_CRC_CNTL                                                                     0x208c
+#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG0_DIG_OUTPUT_CRC_RESULT                                                                   0x208d
+#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG0_DIG_CLOCK_PATTERN                                                                       0x208e
+#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG0_DIG_TEST_PATTERN                                                                        0x208f
+#define regDIG0_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG0_DIG_RANDOM_PATTERN_SEED                                                                 0x2090
+#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG0_DIG_FIFO_STATUS                                                                         0x2091
+#define regDIG0_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL                                                            0x2092
+#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG0_HDMI_CONTROL                                                                            0x2093
+#define regDIG0_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG0_HDMI_STATUS                                                                             0x2094
+#define regDIG0_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL                                                               0x2095
+#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG0_HDMI_ACR_PACKET_CONTROL                                                                 0x2096
+#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_VBI_PACKET_CONTROL                                                                 0x2097
+#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL0                                                                 0x2098
+#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG0_HDMI_INFOFRAME_CONTROL1                                                                 0x2099
+#define regDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0                                                            0x209a
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6                                                            0x209b
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5                                                            0x209c
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG0_HDMI_GC                                                                                 0x209d
+#define regDIG0_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1                                                            0x209e
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2                                                            0x209f
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3                                                            0x20a0
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4                                                            0x20a1
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7                                                            0x20a2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8                                                            0x20a3
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9                                                            0x20a4
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10                                                           0x20a5
+#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG0_HDMI_DB_CONTROL                                                                         0x20a6
+#define regDIG0_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG0_HDMI_ACR_32_0                                                                           0x20a7
+#define regDIG0_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_32_1                                                                           0x20a8
+#define regDIG0_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_0                                                                           0x20a9
+#define regDIG0_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_44_1                                                                           0x20aa
+#define regDIG0_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_0                                                                           0x20ab
+#define regDIG0_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_48_1                                                                           0x20ac
+#define regDIG0_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG0_HDMI_ACR_STATUS_0                                                                       0x20ad
+#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG0_HDMI_ACR_STATUS_1                                                                       0x20ae
+#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG0_AFMT_CNTL                                                                               0x20af
+#define regDIG0_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG0_DIG_BE_CNTL                                                                             0x20b0
+#define regDIG0_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG0_DIG_BE_EN_CNTL                                                                          0x20b1
+#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG0_TMDS_CNTL                                                                               0x20d7
+#define regDIG0_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG0_TMDS_CONTROL_CHAR                                                                       0x20d8
+#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG0_TMDS_CONTROL0_FEEDBACK                                                                  0x20d9
+#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL                                                                 0x20da
+#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x20db
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x20dc
+#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG0_TMDS_CTL_BITS                                                                           0x20de
+#define regDIG0_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG0_TMDS_DCBALANCER_CONTROL                                                                 0x20df
+#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR                                                                0x20e0
+#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL                                                                    0x20e1
+#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL                                                                    0x20e2
+#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG0_DIG_VERSION                                                                             0x20e4
+#define regDIG0_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG0_FORCE_DIG_DISABLE                                                                       0x20e5
+#define regDIG0_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+// base address: 0x400
+#define regDP1_DP_LINK_CNTL                                                                             0x2208
+#define regDP1_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_PIXEL_FORMAT                                                                          0x2209
+#define regDP1_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP1_DP_MSA_COLORIMETRY                                                                       0x220a
+#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP1_DP_CONFIG                                                                                0x220b
+#define regDP1_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP1_DP_VID_STREAM_CNTL                                                                       0x220c
+#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_STEER_FIFO                                                                            0x220d
+#define regDP1_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP1_DP_MSA_MISC                                                                              0x220e
+#define regDP1_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP1_DP_DPHY_INTERNAL_CTRL                                                                    0x220f
+#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP1_DP_VID_TIMING                                                                            0x2210
+#define regDP1_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP1_DP_VID_N                                                                                 0x2211
+#define regDP1_DP_VID_N_BASE_IDX                                                                        2
+#define regDP1_DP_VID_M                                                                                 0x2212
+#define regDP1_DP_VID_M_BASE_IDX                                                                        2
+#define regDP1_DP_LINK_FRAMING_CNTL                                                                     0x2213
+#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_HBR2_EYE_PATTERN                                                                      0x2214
+#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP1_DP_VID_MSA_VBID                                                                          0x2215
+#define regDP1_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP1_DP_VID_INTERRUPT_CNTL                                                                    0x2216
+#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_CNTL                                                                             0x2217
+#define regDP1_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2218
+#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP1_DP_DPHY_SYM0                                                                             0x2219
+#define regDP1_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM1                                                                             0x221a
+#define regDP1_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_SYM2                                                                             0x221b
+#define regDP1_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP1_DP_DPHY_8B10B_CNTL                                                                       0x221c
+#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_PRBS_CNTL                                                                        0x221d
+#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP1_DP_DPHY_SCRAM_CNTL                                                                       0x221e
+#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_EN                                                                           0x221f
+#define regDP1_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP1_DP_DPHY_CRC_CNTL                                                                         0x2220
+#define regDP1_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_CRC_RESULT                                                                       0x2221
+#define regDP1_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP1_DP_DPHY_CRC_MST_CNTL                                                                     0x2222
+#define regDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP1_DP_DPHY_CRC_MST_STATUS                                                                   0x2223
+#define regDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP1_DP_DPHY_FAST_TRAINING                                                                    0x2224
+#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2225
+#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP1_DP_SEC_CNTL                                                                              0x222b
+#define regDP1_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL1                                                                             0x222c
+#define regDP1_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_FRAMING1                                                                          0x222d
+#define regDP1_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING2                                                                          0x222e
+#define regDP1_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING3                                                                          0x222f
+#define regDP1_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_FRAMING4                                                                          0x2230
+#define regDP1_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP1_DP_SEC_AUD_N                                                                             0x2231
+#define regDP1_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_N_READBACK                                                                    0x2232
+#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_AUD_M                                                                             0x2233
+#define regDP1_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_AUD_M_READBACK                                                                    0x2234
+#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP1_DP_SEC_TIMESTAMP                                                                         0x2235
+#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP1_DP_SEC_PACKET_CNTL                                                                       0x2236
+#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP1_DP_MSE_RATE_CNTL                                                                         0x2237
+#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_MSE_RATE_UPDATE                                                                       0x2239
+#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT0                                                                              0x223a
+#define regDP1_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT1                                                                              0x223b
+#define regDP1_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT2                                                                              0x223c
+#define regDP1_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP1_DP_MSE_SAT_UPDATE                                                                        0x223d
+#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP1_DP_MSE_LINK_TIMING                                                                       0x223e
+#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP1_DP_MSE_MISC_CNTL                                                                         0x223f
+#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2244
+#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2245
+#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP1_DP_MSE_SAT0_STATUS                                                                       0x2247
+#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT1_STATUS                                                                       0x2248
+#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSE_SAT2_STATUS                                                                       0x2249
+#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP1_DP_MSA_TIMING_PARAM1                                                                     0x224c
+#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM2                                                                     0x224d
+#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM3                                                                     0x224e
+#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP1_DP_MSA_TIMING_PARAM4                                                                     0x224f
+#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP1_DP_MSO_CNTL                                                                              0x2250
+#define regDP1_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_MSO_CNTL1                                                                             0x2251
+#define regDP1_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP1_DP_DSC_CNTL                                                                              0x2252
+#define regDP1_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP1_DP_SEC_CNTL2                                                                             0x2253
+#define regDP1_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL3                                                                             0x2254
+#define regDP1_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL4                                                                             0x2255
+#define regDP1_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL5                                                                             0x2256
+#define regDP1_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL6                                                                             0x2257
+#define regDP1_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP1_DP_SEC_CNTL7                                                                             0x2258
+#define regDP1_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP1_DP_DB_CNTL                                                                               0x2259
+#define regDP1_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP1_DP_MSA_VBID_MISC                                                                         0x225a
+#define regDP1_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP1_DP_SEC_METADATA_TRANSMISSION                                                             0x225b
+#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP1_DP_DSC_BYTES_PER_PIXEL                                                                   0x225c
+#define regDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP1_DP_ALPM_CNTL                                                                             0x225d
+#define regDP1_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP8_CNTL                                                                             0x225e
+#define regDP1_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP9_CNTL                                                                             0x225f
+#define regDP1_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP1_DP_GSP10_CNTL                                                                            0x2260
+#define regDP1_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP11_CNTL                                                                            0x2261
+#define regDP1_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP1_DP_GSP_EN_DB_STATUS                                                                      0x2262
+#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+// base address: 0x400
+#define regDIG1_DIG_FE_CNTL                                                                             0x218b
+#define regDIG1_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_OUTPUT_CRC_CNTL                                                                     0x218c
+#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG1_DIG_OUTPUT_CRC_RESULT                                                                   0x218d
+#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG1_DIG_CLOCK_PATTERN                                                                       0x218e
+#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG1_DIG_TEST_PATTERN                                                                        0x218f
+#define regDIG1_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG1_DIG_RANDOM_PATTERN_SEED                                                                 0x2190
+#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG1_DIG_FIFO_STATUS                                                                         0x2191
+#define regDIG1_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL                                                            0x2192
+#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG1_HDMI_CONTROL                                                                            0x2193
+#define regDIG1_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG1_HDMI_STATUS                                                                             0x2194
+#define regDIG1_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL                                                               0x2195
+#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG1_HDMI_ACR_PACKET_CONTROL                                                                 0x2196
+#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_VBI_PACKET_CONTROL                                                                 0x2197
+#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL0                                                                 0x2198
+#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG1_HDMI_INFOFRAME_CONTROL1                                                                 0x2199
+#define regDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0                                                            0x219a
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6                                                            0x219b
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5                                                            0x219c
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG1_HDMI_GC                                                                                 0x219d
+#define regDIG1_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1                                                            0x219e
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2                                                            0x219f
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3                                                            0x21a0
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4                                                            0x21a1
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7                                                            0x21a2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8                                                            0x21a3
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9                                                            0x21a4
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10                                                           0x21a5
+#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG1_HDMI_DB_CONTROL                                                                         0x21a6
+#define regDIG1_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG1_HDMI_ACR_32_0                                                                           0x21a7
+#define regDIG1_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_32_1                                                                           0x21a8
+#define regDIG1_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_0                                                                           0x21a9
+#define regDIG1_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_44_1                                                                           0x21aa
+#define regDIG1_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_0                                                                           0x21ab
+#define regDIG1_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_48_1                                                                           0x21ac
+#define regDIG1_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG1_HDMI_ACR_STATUS_0                                                                       0x21ad
+#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG1_HDMI_ACR_STATUS_1                                                                       0x21ae
+#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG1_AFMT_CNTL                                                                               0x21af
+#define regDIG1_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG1_DIG_BE_CNTL                                                                             0x21b0
+#define regDIG1_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG1_DIG_BE_EN_CNTL                                                                          0x21b1
+#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG1_TMDS_CNTL                                                                               0x21d7
+#define regDIG1_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG1_TMDS_CONTROL_CHAR                                                                       0x21d8
+#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG1_TMDS_CONTROL0_FEEDBACK                                                                  0x21d9
+#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL                                                                 0x21da
+#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x21db
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x21dc
+#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG1_TMDS_CTL_BITS                                                                           0x21de
+#define regDIG1_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG1_TMDS_DCBALANCER_CONTROL                                                                 0x21df
+#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR                                                                0x21e0
+#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL                                                                    0x21e1
+#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL                                                                    0x21e2
+#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG1_DIG_VERSION                                                                             0x21e4
+#define regDIG1_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG1_FORCE_DIG_DISABLE                                                                       0x21e5
+#define regDIG1_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+// base address: 0x800
+#define regDP2_DP_LINK_CNTL                                                                             0x2308
+#define regDP2_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_PIXEL_FORMAT                                                                          0x2309
+#define regDP2_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP2_DP_MSA_COLORIMETRY                                                                       0x230a
+#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP2_DP_CONFIG                                                                                0x230b
+#define regDP2_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP2_DP_VID_STREAM_CNTL                                                                       0x230c
+#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_STEER_FIFO                                                                            0x230d
+#define regDP2_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP2_DP_MSA_MISC                                                                              0x230e
+#define regDP2_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP2_DP_DPHY_INTERNAL_CTRL                                                                    0x230f
+#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP2_DP_VID_TIMING                                                                            0x2310
+#define regDP2_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP2_DP_VID_N                                                                                 0x2311
+#define regDP2_DP_VID_N_BASE_IDX                                                                        2
+#define regDP2_DP_VID_M                                                                                 0x2312
+#define regDP2_DP_VID_M_BASE_IDX                                                                        2
+#define regDP2_DP_LINK_FRAMING_CNTL                                                                     0x2313
+#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_HBR2_EYE_PATTERN                                                                      0x2314
+#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP2_DP_VID_MSA_VBID                                                                          0x2315
+#define regDP2_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP2_DP_VID_INTERRUPT_CNTL                                                                    0x2316
+#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_CNTL                                                                             0x2317
+#define regDP2_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2318
+#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP2_DP_DPHY_SYM0                                                                             0x2319
+#define regDP2_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM1                                                                             0x231a
+#define regDP2_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_SYM2                                                                             0x231b
+#define regDP2_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP2_DP_DPHY_8B10B_CNTL                                                                       0x231c
+#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_PRBS_CNTL                                                                        0x231d
+#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP2_DP_DPHY_SCRAM_CNTL                                                                       0x231e
+#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_EN                                                                           0x231f
+#define regDP2_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP2_DP_DPHY_CRC_CNTL                                                                         0x2320
+#define regDP2_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_CRC_RESULT                                                                       0x2321
+#define regDP2_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP2_DP_DPHY_CRC_MST_CNTL                                                                     0x2322
+#define regDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP2_DP_DPHY_CRC_MST_STATUS                                                                   0x2323
+#define regDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP2_DP_DPHY_FAST_TRAINING                                                                    0x2324
+#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2325
+#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP2_DP_SEC_CNTL                                                                              0x232b
+#define regDP2_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL1                                                                             0x232c
+#define regDP2_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_FRAMING1                                                                          0x232d
+#define regDP2_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING2                                                                          0x232e
+#define regDP2_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING3                                                                          0x232f
+#define regDP2_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_FRAMING4                                                                          0x2330
+#define regDP2_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP2_DP_SEC_AUD_N                                                                             0x2331
+#define regDP2_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_N_READBACK                                                                    0x2332
+#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_AUD_M                                                                             0x2333
+#define regDP2_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_AUD_M_READBACK                                                                    0x2334
+#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP2_DP_SEC_TIMESTAMP                                                                         0x2335
+#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP2_DP_SEC_PACKET_CNTL                                                                       0x2336
+#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP2_DP_MSE_RATE_CNTL                                                                         0x2337
+#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_MSE_RATE_UPDATE                                                                       0x2339
+#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT0                                                                              0x233a
+#define regDP2_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT1                                                                              0x233b
+#define regDP2_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT2                                                                              0x233c
+#define regDP2_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP2_DP_MSE_SAT_UPDATE                                                                        0x233d
+#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP2_DP_MSE_LINK_TIMING                                                                       0x233e
+#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP2_DP_MSE_MISC_CNTL                                                                         0x233f
+#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2344
+#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2345
+#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP2_DP_MSE_SAT0_STATUS                                                                       0x2347
+#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT1_STATUS                                                                       0x2348
+#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSE_SAT2_STATUS                                                                       0x2349
+#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP2_DP_MSA_TIMING_PARAM1                                                                     0x234c
+#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM2                                                                     0x234d
+#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM3                                                                     0x234e
+#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP2_DP_MSA_TIMING_PARAM4                                                                     0x234f
+#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP2_DP_MSO_CNTL                                                                              0x2350
+#define regDP2_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_MSO_CNTL1                                                                             0x2351
+#define regDP2_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP2_DP_DSC_CNTL                                                                              0x2352
+#define regDP2_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP2_DP_SEC_CNTL2                                                                             0x2353
+#define regDP2_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL3                                                                             0x2354
+#define regDP2_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL4                                                                             0x2355
+#define regDP2_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL5                                                                             0x2356
+#define regDP2_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL6                                                                             0x2357
+#define regDP2_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP2_DP_SEC_CNTL7                                                                             0x2358
+#define regDP2_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP2_DP_DB_CNTL                                                                               0x2359
+#define regDP2_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP2_DP_MSA_VBID_MISC                                                                         0x235a
+#define regDP2_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP2_DP_SEC_METADATA_TRANSMISSION                                                             0x235b
+#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP2_DP_DSC_BYTES_PER_PIXEL                                                                   0x235c
+#define regDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP2_DP_ALPM_CNTL                                                                             0x235d
+#define regDP2_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP8_CNTL                                                                             0x235e
+#define regDP2_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP9_CNTL                                                                             0x235f
+#define regDP2_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP2_DP_GSP10_CNTL                                                                            0x2360
+#define regDP2_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP11_CNTL                                                                            0x2361
+#define regDP2_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP2_DP_GSP_EN_DB_STATUS                                                                      0x2362
+#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+// base address: 0x800
+#define regDIG2_DIG_FE_CNTL                                                                             0x228b
+#define regDIG2_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_OUTPUT_CRC_CNTL                                                                     0x228c
+#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG2_DIG_OUTPUT_CRC_RESULT                                                                   0x228d
+#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG2_DIG_CLOCK_PATTERN                                                                       0x228e
+#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG2_DIG_TEST_PATTERN                                                                        0x228f
+#define regDIG2_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG2_DIG_RANDOM_PATTERN_SEED                                                                 0x2290
+#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG2_DIG_FIFO_STATUS                                                                         0x2291
+#define regDIG2_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL                                                            0x2292
+#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG2_HDMI_CONTROL                                                                            0x2293
+#define regDIG2_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG2_HDMI_STATUS                                                                             0x2294
+#define regDIG2_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL                                                               0x2295
+#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG2_HDMI_ACR_PACKET_CONTROL                                                                 0x2296
+#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_VBI_PACKET_CONTROL                                                                 0x2297
+#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL0                                                                 0x2298
+#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG2_HDMI_INFOFRAME_CONTROL1                                                                 0x2299
+#define regDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0                                                            0x229a
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6                                                            0x229b
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5                                                            0x229c
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG2_HDMI_GC                                                                                 0x229d
+#define regDIG2_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1                                                            0x229e
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2                                                            0x229f
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3                                                            0x22a0
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4                                                            0x22a1
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7                                                            0x22a2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8                                                            0x22a3
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9                                                            0x22a4
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10                                                           0x22a5
+#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG2_HDMI_DB_CONTROL                                                                         0x22a6
+#define regDIG2_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG2_HDMI_ACR_32_0                                                                           0x22a7
+#define regDIG2_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_32_1                                                                           0x22a8
+#define regDIG2_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_0                                                                           0x22a9
+#define regDIG2_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_44_1                                                                           0x22aa
+#define regDIG2_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_0                                                                           0x22ab
+#define regDIG2_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_48_1                                                                           0x22ac
+#define regDIG2_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG2_HDMI_ACR_STATUS_0                                                                       0x22ad
+#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG2_HDMI_ACR_STATUS_1                                                                       0x22ae
+#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG2_AFMT_CNTL                                                                               0x22af
+#define regDIG2_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG2_DIG_BE_CNTL                                                                             0x22b0
+#define regDIG2_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG2_DIG_BE_EN_CNTL                                                                          0x22b1
+#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG2_TMDS_CNTL                                                                               0x22d7
+#define regDIG2_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG2_TMDS_CONTROL_CHAR                                                                       0x22d8
+#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG2_TMDS_CONTROL0_FEEDBACK                                                                  0x22d9
+#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL                                                                 0x22da
+#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x22db
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x22dc
+#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG2_TMDS_CTL_BITS                                                                           0x22de
+#define regDIG2_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG2_TMDS_DCBALANCER_CONTROL                                                                 0x22df
+#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR                                                                0x22e0
+#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL                                                                    0x22e1
+#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL                                                                    0x22e2
+#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG2_DIG_VERSION                                                                             0x22e4
+#define regDIG2_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG2_FORCE_DIG_DISABLE                                                                       0x22e5
+#define regDIG2_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+// base address: 0xc00
+#define regDP3_DP_LINK_CNTL                                                                             0x2408
+#define regDP3_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_PIXEL_FORMAT                                                                          0x2409
+#define regDP3_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP3_DP_MSA_COLORIMETRY                                                                       0x240a
+#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP3_DP_CONFIG                                                                                0x240b
+#define regDP3_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP3_DP_VID_STREAM_CNTL                                                                       0x240c
+#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_STEER_FIFO                                                                            0x240d
+#define regDP3_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP3_DP_MSA_MISC                                                                              0x240e
+#define regDP3_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP3_DP_DPHY_INTERNAL_CTRL                                                                    0x240f
+#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP3_DP_VID_TIMING                                                                            0x2410
+#define regDP3_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP3_DP_VID_N                                                                                 0x2411
+#define regDP3_DP_VID_N_BASE_IDX                                                                        2
+#define regDP3_DP_VID_M                                                                                 0x2412
+#define regDP3_DP_VID_M_BASE_IDX                                                                        2
+#define regDP3_DP_LINK_FRAMING_CNTL                                                                     0x2413
+#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_HBR2_EYE_PATTERN                                                                      0x2414
+#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP3_DP_VID_MSA_VBID                                                                          0x2415
+#define regDP3_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP3_DP_VID_INTERRUPT_CNTL                                                                    0x2416
+#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_CNTL                                                                             0x2417
+#define regDP3_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2418
+#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP3_DP_DPHY_SYM0                                                                             0x2419
+#define regDP3_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM1                                                                             0x241a
+#define regDP3_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_SYM2                                                                             0x241b
+#define regDP3_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP3_DP_DPHY_8B10B_CNTL                                                                       0x241c
+#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_PRBS_CNTL                                                                        0x241d
+#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP3_DP_DPHY_SCRAM_CNTL                                                                       0x241e
+#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_EN                                                                           0x241f
+#define regDP3_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP3_DP_DPHY_CRC_CNTL                                                                         0x2420
+#define regDP3_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_CRC_RESULT                                                                       0x2421
+#define regDP3_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP3_DP_DPHY_CRC_MST_CNTL                                                                     0x2422
+#define regDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP3_DP_DPHY_CRC_MST_STATUS                                                                   0x2423
+#define regDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP3_DP_DPHY_FAST_TRAINING                                                                    0x2424
+#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2425
+#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP3_DP_SEC_CNTL                                                                              0x242b
+#define regDP3_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL1                                                                             0x242c
+#define regDP3_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_FRAMING1                                                                          0x242d
+#define regDP3_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING2                                                                          0x242e
+#define regDP3_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING3                                                                          0x242f
+#define regDP3_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_FRAMING4                                                                          0x2430
+#define regDP3_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP3_DP_SEC_AUD_N                                                                             0x2431
+#define regDP3_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_N_READBACK                                                                    0x2432
+#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_AUD_M                                                                             0x2433
+#define regDP3_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_AUD_M_READBACK                                                                    0x2434
+#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP3_DP_SEC_TIMESTAMP                                                                         0x2435
+#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP3_DP_SEC_PACKET_CNTL                                                                       0x2436
+#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP3_DP_MSE_RATE_CNTL                                                                         0x2437
+#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_MSE_RATE_UPDATE                                                                       0x2439
+#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT0                                                                              0x243a
+#define regDP3_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT1                                                                              0x243b
+#define regDP3_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT2                                                                              0x243c
+#define regDP3_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP3_DP_MSE_SAT_UPDATE                                                                        0x243d
+#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP3_DP_MSE_LINK_TIMING                                                                       0x243e
+#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP3_DP_MSE_MISC_CNTL                                                                         0x243f
+#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2444
+#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2445
+#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP3_DP_MSE_SAT0_STATUS                                                                       0x2447
+#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT1_STATUS                                                                       0x2448
+#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSE_SAT2_STATUS                                                                       0x2449
+#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP3_DP_MSA_TIMING_PARAM1                                                                     0x244c
+#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM2                                                                     0x244d
+#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM3                                                                     0x244e
+#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP3_DP_MSA_TIMING_PARAM4                                                                     0x244f
+#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP3_DP_MSO_CNTL                                                                              0x2450
+#define regDP3_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_MSO_CNTL1                                                                             0x2451
+#define regDP3_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP3_DP_DSC_CNTL                                                                              0x2452
+#define regDP3_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP3_DP_SEC_CNTL2                                                                             0x2453
+#define regDP3_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL3                                                                             0x2454
+#define regDP3_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL4                                                                             0x2455
+#define regDP3_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL5                                                                             0x2456
+#define regDP3_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL6                                                                             0x2457
+#define regDP3_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP3_DP_SEC_CNTL7                                                                             0x2458
+#define regDP3_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP3_DP_DB_CNTL                                                                               0x2459
+#define regDP3_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP3_DP_MSA_VBID_MISC                                                                         0x245a
+#define regDP3_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP3_DP_SEC_METADATA_TRANSMISSION                                                             0x245b
+#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP3_DP_DSC_BYTES_PER_PIXEL                                                                   0x245c
+#define regDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP3_DP_ALPM_CNTL                                                                             0x245d
+#define regDP3_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP8_CNTL                                                                             0x245e
+#define regDP3_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP9_CNTL                                                                             0x245f
+#define regDP3_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP3_DP_GSP10_CNTL                                                                            0x2460
+#define regDP3_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP11_CNTL                                                                            0x2461
+#define regDP3_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP3_DP_GSP_EN_DB_STATUS                                                                      0x2462
+#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+// base address: 0xc00
+#define regDIG3_DIG_FE_CNTL                                                                             0x238b
+#define regDIG3_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_OUTPUT_CRC_CNTL                                                                     0x238c
+#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG3_DIG_OUTPUT_CRC_RESULT                                                                   0x238d
+#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG3_DIG_CLOCK_PATTERN                                                                       0x238e
+#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG3_DIG_TEST_PATTERN                                                                        0x238f
+#define regDIG3_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG3_DIG_RANDOM_PATTERN_SEED                                                                 0x2390
+#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG3_DIG_FIFO_STATUS                                                                         0x2391
+#define regDIG3_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL                                                            0x2392
+#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG3_HDMI_CONTROL                                                                            0x2393
+#define regDIG3_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG3_HDMI_STATUS                                                                             0x2394
+#define regDIG3_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL                                                               0x2395
+#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG3_HDMI_ACR_PACKET_CONTROL                                                                 0x2396
+#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_VBI_PACKET_CONTROL                                                                 0x2397
+#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL0                                                                 0x2398
+#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG3_HDMI_INFOFRAME_CONTROL1                                                                 0x2399
+#define regDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0                                                            0x239a
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6                                                            0x239b
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5                                                            0x239c
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG3_HDMI_GC                                                                                 0x239d
+#define regDIG3_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1                                                            0x239e
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2                                                            0x239f
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3                                                            0x23a0
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4                                                            0x23a1
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7                                                            0x23a2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8                                                            0x23a3
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9                                                            0x23a4
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10                                                           0x23a5
+#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG3_HDMI_DB_CONTROL                                                                         0x23a6
+#define regDIG3_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG3_HDMI_ACR_32_0                                                                           0x23a7
+#define regDIG3_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_32_1                                                                           0x23a8
+#define regDIG3_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_0                                                                           0x23a9
+#define regDIG3_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_44_1                                                                           0x23aa
+#define regDIG3_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_0                                                                           0x23ab
+#define regDIG3_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_48_1                                                                           0x23ac
+#define regDIG3_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG3_HDMI_ACR_STATUS_0                                                                       0x23ad
+#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG3_HDMI_ACR_STATUS_1                                                                       0x23ae
+#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG3_AFMT_CNTL                                                                               0x23af
+#define regDIG3_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG3_DIG_BE_CNTL                                                                             0x23b0
+#define regDIG3_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG3_DIG_BE_EN_CNTL                                                                          0x23b1
+#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG3_TMDS_CNTL                                                                               0x23d7
+#define regDIG3_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG3_TMDS_CONTROL_CHAR                                                                       0x23d8
+#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG3_TMDS_CONTROL0_FEEDBACK                                                                  0x23d9
+#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL                                                                 0x23da
+#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x23db
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x23dc
+#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG3_TMDS_CTL_BITS                                                                           0x23de
+#define regDIG3_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG3_TMDS_DCBALANCER_CONTROL                                                                 0x23df
+#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR                                                                0x23e0
+#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL                                                                    0x23e1
+#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL                                                                    0x23e2
+#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG3_DIG_VERSION                                                                             0x23e4
+#define regDIG3_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG3_FORCE_DIG_DISABLE                                                                       0x23e5
+#define regDIG3_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+// base address: 0x1000
+#define regDP4_DP_LINK_CNTL                                                                             0x2508
+#define regDP4_DP_LINK_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_PIXEL_FORMAT                                                                          0x2509
+#define regDP4_DP_PIXEL_FORMAT_BASE_IDX                                                                 2
+#define regDP4_DP_MSA_COLORIMETRY                                                                       0x250a
+#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX                                                              2
+#define regDP4_DP_CONFIG                                                                                0x250b
+#define regDP4_DP_CONFIG_BASE_IDX                                                                       2
+#define regDP4_DP_VID_STREAM_CNTL                                                                       0x250c
+#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_STEER_FIFO                                                                            0x250d
+#define regDP4_DP_STEER_FIFO_BASE_IDX                                                                   2
+#define regDP4_DP_MSA_MISC                                                                              0x250e
+#define regDP4_DP_MSA_MISC_BASE_IDX                                                                     2
+#define regDP4_DP_DPHY_INTERNAL_CTRL                                                                    0x250f
+#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX                                                           2
+#define regDP4_DP_VID_TIMING                                                                            0x2510
+#define regDP4_DP_VID_TIMING_BASE_IDX                                                                   2
+#define regDP4_DP_VID_N                                                                                 0x2511
+#define regDP4_DP_VID_N_BASE_IDX                                                                        2
+#define regDP4_DP_VID_M                                                                                 0x2512
+#define regDP4_DP_VID_M_BASE_IDX                                                                        2
+#define regDP4_DP_LINK_FRAMING_CNTL                                                                     0x2513
+#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_HBR2_EYE_PATTERN                                                                      0x2514
+#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX                                                             2
+#define regDP4_DP_VID_MSA_VBID                                                                          0x2515
+#define regDP4_DP_VID_MSA_VBID_BASE_IDX                                                                 2
+#define regDP4_DP_VID_INTERRUPT_CNTL                                                                    0x2516
+#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_CNTL                                                                             0x2517
+#define regDP4_DP_DPHY_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL                                                             0x2518
+#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX                                                    2
+#define regDP4_DP_DPHY_SYM0                                                                             0x2519
+#define regDP4_DP_DPHY_SYM0_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM1                                                                             0x251a
+#define regDP4_DP_DPHY_SYM1_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_SYM2                                                                             0x251b
+#define regDP4_DP_DPHY_SYM2_BASE_IDX                                                                    2
+#define regDP4_DP_DPHY_8B10B_CNTL                                                                       0x251c
+#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_PRBS_CNTL                                                                        0x251d
+#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX                                                               2
+#define regDP4_DP_DPHY_SCRAM_CNTL                                                                       0x251e
+#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_EN                                                                           0x251f
+#define regDP4_DP_DPHY_CRC_EN_BASE_IDX                                                                  2
+#define regDP4_DP_DPHY_CRC_CNTL                                                                         0x2520
+#define regDP4_DP_DPHY_CRC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_CRC_RESULT                                                                       0x2521
+#define regDP4_DP_DPHY_CRC_RESULT_BASE_IDX                                                              2
+#define regDP4_DP_DPHY_CRC_MST_CNTL                                                                     0x2522
+#define regDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX                                                            2
+#define regDP4_DP_DPHY_CRC_MST_STATUS                                                                   0x2523
+#define regDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX                                                          2
+#define regDP4_DP_DPHY_FAST_TRAINING                                                                    0x2524
+#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX                                                           2
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS                                                             0x2525
+#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX                                                    2
+#define regDP4_DP_SEC_CNTL                                                                              0x252b
+#define regDP4_DP_SEC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL1                                                                             0x252c
+#define regDP4_DP_SEC_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_FRAMING1                                                                          0x252d
+#define regDP4_DP_SEC_FRAMING1_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING2                                                                          0x252e
+#define regDP4_DP_SEC_FRAMING2_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING3                                                                          0x252f
+#define regDP4_DP_SEC_FRAMING3_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_FRAMING4                                                                          0x2530
+#define regDP4_DP_SEC_FRAMING4_BASE_IDX                                                                 2
+#define regDP4_DP_SEC_AUD_N                                                                             0x2531
+#define regDP4_DP_SEC_AUD_N_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_N_READBACK                                                                    0x2532
+#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_AUD_M                                                                             0x2533
+#define regDP4_DP_SEC_AUD_M_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_AUD_M_READBACK                                                                    0x2534
+#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX                                                           2
+#define regDP4_DP_SEC_TIMESTAMP                                                                         0x2535
+#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX                                                                2
+#define regDP4_DP_SEC_PACKET_CNTL                                                                       0x2536
+#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX                                                              2
+#define regDP4_DP_MSE_RATE_CNTL                                                                         0x2537
+#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_MSE_RATE_UPDATE                                                                       0x2539
+#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT0                                                                              0x253a
+#define regDP4_DP_MSE_SAT0_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT1                                                                              0x253b
+#define regDP4_DP_MSE_SAT1_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT2                                                                              0x253c
+#define regDP4_DP_MSE_SAT2_BASE_IDX                                                                     2
+#define regDP4_DP_MSE_SAT_UPDATE                                                                        0x253d
+#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX                                                               2
+#define regDP4_DP_MSE_LINK_TIMING                                                                       0x253e
+#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX                                                              2
+#define regDP4_DP_MSE_MISC_CNTL                                                                         0x253f
+#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX                                                                2
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL                                                                  0x2544
+#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX                                                         2
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL                                                             0x2545
+#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX                                                    2
+#define regDP4_DP_MSE_SAT0_STATUS                                                                       0x2547
+#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT1_STATUS                                                                       0x2548
+#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSE_SAT2_STATUS                                                                       0x2549
+#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX                                                              2
+#define regDP4_DP_MSA_TIMING_PARAM1                                                                     0x254c
+#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM2                                                                     0x254d
+#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM3                                                                     0x254e
+#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX                                                            2
+#define regDP4_DP_MSA_TIMING_PARAM4                                                                     0x254f
+#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX                                                            2
+#define regDP4_DP_MSO_CNTL                                                                              0x2550
+#define regDP4_DP_MSO_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_MSO_CNTL1                                                                             0x2551
+#define regDP4_DP_MSO_CNTL1_BASE_IDX                                                                    2
+#define regDP4_DP_DSC_CNTL                                                                              0x2552
+#define regDP4_DP_DSC_CNTL_BASE_IDX                                                                     2
+#define regDP4_DP_SEC_CNTL2                                                                             0x2553
+#define regDP4_DP_SEC_CNTL2_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL3                                                                             0x2554
+#define regDP4_DP_SEC_CNTL3_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL4                                                                             0x2555
+#define regDP4_DP_SEC_CNTL4_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL5                                                                             0x2556
+#define regDP4_DP_SEC_CNTL5_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL6                                                                             0x2557
+#define regDP4_DP_SEC_CNTL6_BASE_IDX                                                                    2
+#define regDP4_DP_SEC_CNTL7                                                                             0x2558
+#define regDP4_DP_SEC_CNTL7_BASE_IDX                                                                    2
+#define regDP4_DP_DB_CNTL                                                                               0x2559
+#define regDP4_DP_DB_CNTL_BASE_IDX                                                                      2
+#define regDP4_DP_MSA_VBID_MISC                                                                         0x255a
+#define regDP4_DP_MSA_VBID_MISC_BASE_IDX                                                                2
+#define regDP4_DP_SEC_METADATA_TRANSMISSION                                                             0x255b
+#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX                                                    2
+#define regDP4_DP_DSC_BYTES_PER_PIXEL                                                                   0x255c
+#define regDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX                                                          2
+#define regDP4_DP_ALPM_CNTL                                                                             0x255d
+#define regDP4_DP_ALPM_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP8_CNTL                                                                             0x255e
+#define regDP4_DP_GSP8_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP9_CNTL                                                                             0x255f
+#define regDP4_DP_GSP9_CNTL_BASE_IDX                                                                    2
+#define regDP4_DP_GSP10_CNTL                                                                            0x2560
+#define regDP4_DP_GSP10_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP11_CNTL                                                                            0x2561
+#define regDP4_DP_GSP11_CNTL_BASE_IDX                                                                   2
+#define regDP4_DP_GSP_EN_DB_STATUS                                                                      0x2562
+#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+// base address: 0x1000
+#define regDIG4_DIG_FE_CNTL                                                                             0x248b
+#define regDIG4_DIG_FE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_OUTPUT_CRC_CNTL                                                                     0x248c
+#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX                                                            2
+#define regDIG4_DIG_OUTPUT_CRC_RESULT                                                                   0x248d
+#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX                                                          2
+#define regDIG4_DIG_CLOCK_PATTERN                                                                       0x248e
+#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX                                                              2
+#define regDIG4_DIG_TEST_PATTERN                                                                        0x248f
+#define regDIG4_DIG_TEST_PATTERN_BASE_IDX                                                               2
+#define regDIG4_DIG_RANDOM_PATTERN_SEED                                                                 0x2490
+#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX                                                        2
+#define regDIG4_DIG_FIFO_STATUS                                                                         0x2491
+#define regDIG4_DIG_FIFO_STATUS_BASE_IDX                                                                2
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL                                                            0x2492
+#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX                                                   2
+#define regDIG4_HDMI_CONTROL                                                                            0x2493
+#define regDIG4_HDMI_CONTROL_BASE_IDX                                                                   2
+#define regDIG4_HDMI_STATUS                                                                             0x2494
+#define regDIG4_HDMI_STATUS_BASE_IDX                                                                    2
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL                                                               0x2495
+#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX                                                      2
+#define regDIG4_HDMI_ACR_PACKET_CONTROL                                                                 0x2496
+#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_VBI_PACKET_CONTROL                                                                 0x2497
+#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL0                                                                 0x2498
+#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX                                                        2
+#define regDIG4_HDMI_INFOFRAME_CONTROL1                                                                 0x2499
+#define regDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0                                                            0x249a
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6                                                            0x249b
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5                                                            0x249c
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX                                                   2
+#define regDIG4_HDMI_GC                                                                                 0x249d
+#define regDIG4_HDMI_GC_BASE_IDX                                                                        2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1                                                            0x249e
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2                                                            0x249f
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3                                                            0x24a0
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4                                                            0x24a1
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7                                                            0x24a2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8                                                            0x24a3
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9                                                            0x24a4
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX                                                   2
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10                                                           0x24a5
+#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX                                                  2
+#define regDIG4_HDMI_DB_CONTROL                                                                         0x24a6
+#define regDIG4_HDMI_DB_CONTROL_BASE_IDX                                                                2
+#define regDIG4_HDMI_ACR_32_0                                                                           0x24a7
+#define regDIG4_HDMI_ACR_32_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_32_1                                                                           0x24a8
+#define regDIG4_HDMI_ACR_32_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_0                                                                           0x24a9
+#define regDIG4_HDMI_ACR_44_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_44_1                                                                           0x24aa
+#define regDIG4_HDMI_ACR_44_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_0                                                                           0x24ab
+#define regDIG4_HDMI_ACR_48_0_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_48_1                                                                           0x24ac
+#define regDIG4_HDMI_ACR_48_1_BASE_IDX                                                                  2
+#define regDIG4_HDMI_ACR_STATUS_0                                                                       0x24ad
+#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX                                                              2
+#define regDIG4_HDMI_ACR_STATUS_1                                                                       0x24ae
+#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX                                                              2
+#define regDIG4_AFMT_CNTL                                                                               0x24af
+#define regDIG4_AFMT_CNTL_BASE_IDX                                                                      2
+#define regDIG4_DIG_BE_CNTL                                                                             0x24b0
+#define regDIG4_DIG_BE_CNTL_BASE_IDX                                                                    2
+#define regDIG4_DIG_BE_EN_CNTL                                                                          0x24b1
+#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX                                                                 2
+#define regDIG4_TMDS_CNTL                                                                               0x24d7
+#define regDIG4_TMDS_CNTL_BASE_IDX                                                                      2
+#define regDIG4_TMDS_CONTROL_CHAR                                                                       0x24d8
+#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX                                                              2
+#define regDIG4_TMDS_CONTROL0_FEEDBACK                                                                  0x24d9
+#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX                                                         2
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL                                                                 0x24da
+#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1                                                              0x24db
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX                                                     2
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3                                                              0x24dc
+#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX                                                     2
+#define regDIG4_TMDS_CTL_BITS                                                                           0x24de
+#define regDIG4_TMDS_CTL_BITS_BASE_IDX                                                                  2
+#define regDIG4_TMDS_DCBALANCER_CONTROL                                                                 0x24df
+#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX                                                        2
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR                                                                0x24e0
+#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX                                                       2
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL                                                                    0x24e1
+#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL                                                                    0x24e2
+#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX                                                           2
+#define regDIG4_DIG_VERSION                                                                             0x24e4
+#define regDIG4_DIG_VERSION_BASE_IDX                                                                    2
+#define regDIG4_FORCE_DIG_DISABLE                                                                       0x24e5
+#define regDIG4_FORCE_DIG_DISABLE_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+// base address: 0x154cc
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL                                                                0x2074
+#define regAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2075
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT0_AFMT_AUDIO_INFO0                                                                       0x2076
+#define regAFMT0_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT0_AFMT_AUDIO_INFO1                                                                       0x2077
+#define regAFMT0_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT0_AFMT_60958_0                                                                           0x2078
+#define regAFMT0_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_60958_1                                                                           0x2079
+#define regAFMT0_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL                                                                 0x207a
+#define regAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_RAMP_CONTROL0                                                                     0x207b
+#define regAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL1                                                                     0x207c
+#define regAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL2                                                                     0x207d
+#define regAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT0_AFMT_RAMP_CONTROL3                                                                     0x207e
+#define regAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT0_AFMT_60958_2                                                                           0x207f
+#define regAFMT0_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT                                                                  0x2080
+#define regAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT0_AFMT_STATUS                                                                            0x2081
+#define regAFMT0_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL                                                              0x2082
+#define regAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0                                                                0x2083
+#define regAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT0_AFMT_INTERRUPT_STATUS                                                                  0x2084
+#define regAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL                                                                 0x2085
+#define regAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT0_AFMT_MEM_PWR                                                                           0x2087
+#define regAFMT0_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+// base address: 0x158cc
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL                                                                0x2174
+#define regAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2175
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT1_AFMT_AUDIO_INFO0                                                                       0x2176
+#define regAFMT1_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT1_AFMT_AUDIO_INFO1                                                                       0x2177
+#define regAFMT1_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT1_AFMT_60958_0                                                                           0x2178
+#define regAFMT1_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_60958_1                                                                           0x2179
+#define regAFMT1_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL                                                                 0x217a
+#define regAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_RAMP_CONTROL0                                                                     0x217b
+#define regAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL1                                                                     0x217c
+#define regAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL2                                                                     0x217d
+#define regAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT1_AFMT_RAMP_CONTROL3                                                                     0x217e
+#define regAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT1_AFMT_60958_2                                                                           0x217f
+#define regAFMT1_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT                                                                  0x2180
+#define regAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT1_AFMT_STATUS                                                                            0x2181
+#define regAFMT1_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL                                                              0x2182
+#define regAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0                                                                0x2183
+#define regAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT1_AFMT_INTERRUPT_STATUS                                                                  0x2184
+#define regAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL                                                                 0x2185
+#define regAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT1_AFMT_MEM_PWR                                                                           0x2187
+#define regAFMT1_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+// base address: 0x15ccc
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL                                                                0x2274
+#define regAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2275
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT2_AFMT_AUDIO_INFO0                                                                       0x2276
+#define regAFMT2_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT2_AFMT_AUDIO_INFO1                                                                       0x2277
+#define regAFMT2_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT2_AFMT_60958_0                                                                           0x2278
+#define regAFMT2_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_60958_1                                                                           0x2279
+#define regAFMT2_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL                                                                 0x227a
+#define regAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_RAMP_CONTROL0                                                                     0x227b
+#define regAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL1                                                                     0x227c
+#define regAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL2                                                                     0x227d
+#define regAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT2_AFMT_RAMP_CONTROL3                                                                     0x227e
+#define regAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT2_AFMT_60958_2                                                                           0x227f
+#define regAFMT2_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT                                                                  0x2280
+#define regAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT2_AFMT_STATUS                                                                            0x2281
+#define regAFMT2_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL                                                              0x2282
+#define regAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0                                                                0x2283
+#define regAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT2_AFMT_INTERRUPT_STATUS                                                                  0x2284
+#define regAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL                                                                 0x2285
+#define regAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT2_AFMT_MEM_PWR                                                                           0x2287
+#define regAFMT2_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+// base address: 0x160cc
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL                                                                0x2374
+#define regAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2375
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT3_AFMT_AUDIO_INFO0                                                                       0x2376
+#define regAFMT3_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT3_AFMT_AUDIO_INFO1                                                                       0x2377
+#define regAFMT3_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT3_AFMT_60958_0                                                                           0x2378
+#define regAFMT3_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_60958_1                                                                           0x2379
+#define regAFMT3_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL                                                                 0x237a
+#define regAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_RAMP_CONTROL0                                                                     0x237b
+#define regAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL1                                                                     0x237c
+#define regAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL2                                                                     0x237d
+#define regAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT3_AFMT_RAMP_CONTROL3                                                                     0x237e
+#define regAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT3_AFMT_60958_2                                                                           0x237f
+#define regAFMT3_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT                                                                  0x2380
+#define regAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT3_AFMT_STATUS                                                                            0x2381
+#define regAFMT3_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL                                                              0x2382
+#define regAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0                                                                0x2383
+#define regAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT3_AFMT_INTERRUPT_STATUS                                                                  0x2384
+#define regAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL                                                                 0x2385
+#define regAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT3_AFMT_MEM_PWR                                                                           0x2387
+#define regAFMT3_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+// base address: 0x164cc
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL                                                                0x2474
+#define regAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2                                                             0x2475
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    2
+#define regAFMT4_AFMT_AUDIO_INFO0                                                                       0x2476
+#define regAFMT4_AFMT_AUDIO_INFO0_BASE_IDX                                                              2
+#define regAFMT4_AFMT_AUDIO_INFO1                                                                       0x2477
+#define regAFMT4_AFMT_AUDIO_INFO1_BASE_IDX                                                              2
+#define regAFMT4_AFMT_60958_0                                                                           0x2478
+#define regAFMT4_AFMT_60958_0_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_60958_1                                                                           0x2479
+#define regAFMT4_AFMT_60958_1_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL                                                                 0x247a
+#define regAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_RAMP_CONTROL0                                                                     0x247b
+#define regAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL1                                                                     0x247c
+#define regAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL2                                                                     0x247d
+#define regAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX                                                            2
+#define regAFMT4_AFMT_RAMP_CONTROL3                                                                     0x247e
+#define regAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX                                                            2
+#define regAFMT4_AFMT_60958_2                                                                           0x247f
+#define regAFMT4_AFMT_60958_2_BASE_IDX                                                                  2
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT                                                                  0x2480
+#define regAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         2
+#define regAFMT4_AFMT_STATUS                                                                            0x2481
+#define regAFMT4_AFMT_STATUS_BASE_IDX                                                                   2
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL                                                              0x2482
+#define regAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     2
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0                                                                0x2483
+#define regAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       2
+#define regAFMT4_AFMT_INTERRUPT_STATUS                                                                  0x2484
+#define regAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         2
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL                                                                 0x2485
+#define regAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        2
+#define regAFMT4_AFMT_MEM_PWR                                                                           0x2487
+#define regAFMT4_AFMT_MEM_PWR_BASE_IDX                                                                  2
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+// base address: 0x15524
+#define regDME0_DME_CONTROL                                                                             0x2089
+#define regDME0_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME0_DME_MEMORY_CONTROL                                                                      0x208a
+#define regDME0_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+// base address: 0x154a0
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2068
+#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG0_VPG_GENERIC_PACKET_DATA                                                                 0x2069
+#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x206a
+#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x206b
+#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG0_VPG_GENERIC_STATUS                                                                      0x206c
+#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG0_VPG_MEM_PWR                                                                             0x206d
+#define regVPG0_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x206e
+#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG0_VPG_ISRC1_2_DATA                                                                        0x206f
+#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG0_VPG_MPEG_INFO0                                                                          0x2070
+#define regVPG0_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG0_VPG_MPEG_INFO1                                                                          0x2071
+#define regVPG0_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+// base address: 0x15924
+#define regDME1_DME_CONTROL                                                                             0x2189
+#define regDME1_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME1_DME_MEMORY_CONTROL                                                                      0x218a
+#define regDME1_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+// base address: 0x158a0
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2168
+#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG1_VPG_GENERIC_PACKET_DATA                                                                 0x2169
+#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x216a
+#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x216b
+#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG1_VPG_GENERIC_STATUS                                                                      0x216c
+#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG1_VPG_MEM_PWR                                                                             0x216d
+#define regVPG1_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x216e
+#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG1_VPG_ISRC1_2_DATA                                                                        0x216f
+#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG1_VPG_MPEG_INFO0                                                                          0x2170
+#define regVPG1_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG1_VPG_MPEG_INFO1                                                                          0x2171
+#define regVPG1_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+// base address: 0x15d24
+#define regDME2_DME_CONTROL                                                                             0x2289
+#define regDME2_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME2_DME_MEMORY_CONTROL                                                                      0x228a
+#define regDME2_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+// base address: 0x15ca0
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2268
+#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG2_VPG_GENERIC_PACKET_DATA                                                                 0x2269
+#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x226a
+#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x226b
+#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG2_VPG_GENERIC_STATUS                                                                      0x226c
+#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG2_VPG_MEM_PWR                                                                             0x226d
+#define regVPG2_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x226e
+#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG2_VPG_ISRC1_2_DATA                                                                        0x226f
+#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG2_VPG_MPEG_INFO0                                                                          0x2270
+#define regVPG2_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG2_VPG_MPEG_INFO1                                                                          0x2271
+#define regVPG2_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+// base address: 0x16124
+#define regDME3_DME_CONTROL                                                                             0x2389
+#define regDME3_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME3_DME_MEMORY_CONTROL                                                                      0x238a
+#define regDME3_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+// base address: 0x160a0
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2368
+#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG3_VPG_GENERIC_PACKET_DATA                                                                 0x2369
+#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x236a
+#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x236b
+#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG3_VPG_GENERIC_STATUS                                                                      0x236c
+#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG3_VPG_MEM_PWR                                                                             0x236d
+#define regVPG3_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x236e
+#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG3_VPG_ISRC1_2_DATA                                                                        0x236f
+#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG3_VPG_MPEG_INFO0                                                                          0x2370
+#define regVPG3_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG3_VPG_MPEG_INFO1                                                                          0x2371
+#define regVPG3_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+// base address: 0x16524
+#define regDME4_DME_CONTROL                                                                             0x2489
+#define regDME4_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME4_DME_MEMORY_CONTROL                                                                      0x248a
+#define regDME4_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+// base address: 0x164a0
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x2468
+#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG4_VPG_GENERIC_PACKET_DATA                                                                 0x2469
+#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x246a
+#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x246b
+#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG4_VPG_GENERIC_STATUS                                                                      0x246c
+#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG4_VPG_MEM_PWR                                                                             0x246d
+#define regVPG4_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x246e
+#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG4_VPG_ISRC1_2_DATA                                                                        0x246f
+#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG4_VPG_MPEG_INFO0                                                                          0x2470
+#define regVPG4_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG4_VPG_MPEG_INFO1                                                                          0x2471
+#define regVPG4_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+// base address: 0x0
+#define regDP_AUX0_AUX_CONTROL                                                                          0x1f50
+#define regDP_AUX0_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_SW_CONTROL                                                                       0x1f51
+#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX0_AUX_ARB_CONTROL                                                                      0x1f52
+#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL                                                                0x1f53
+#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX0_AUX_SW_STATUS                                                                        0x1f54
+#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_LS_STATUS                                                                        0x1f55
+#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX0_AUX_SW_DATA                                                                          0x1f56
+#define regDP_AUX0_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_LS_DATA                                                                          0x1f57
+#define regDP_AUX0_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL                                                              0x1f58
+#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL                                                                  0x1f59
+#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0                                                                 0x1f5a
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1                                                                 0x1f5b
+#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_DPHY_TX_STATUS                                                                   0x1f5c
+#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_DPHY_RX_STATUS                                                                   0x1f5d
+#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL                                                                 0x1f5e
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f5f
+#define regDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f60
+#define regDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS                                                                  0x1f61
+#define regDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL                                                                    0x1f66
+#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+// base address: 0x70
+#define regDP_AUX1_AUX_CONTROL                                                                          0x1f6c
+#define regDP_AUX1_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_SW_CONTROL                                                                       0x1f6d
+#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX1_AUX_ARB_CONTROL                                                                      0x1f6e
+#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL                                                                0x1f6f
+#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX1_AUX_SW_STATUS                                                                        0x1f70
+#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_LS_STATUS                                                                        0x1f71
+#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX1_AUX_SW_DATA                                                                          0x1f72
+#define regDP_AUX1_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_LS_DATA                                                                          0x1f73
+#define regDP_AUX1_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL                                                              0x1f74
+#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL                                                                  0x1f75
+#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0                                                                 0x1f76
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1                                                                 0x1f77
+#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_DPHY_TX_STATUS                                                                   0x1f78
+#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_DPHY_RX_STATUS                                                                   0x1f79
+#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL                                                                 0x1f7a
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f7b
+#define regDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f7c
+#define regDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS                                                                  0x1f7d
+#define regDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL                                                                    0x1f82
+#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+// base address: 0xe0
+#define regDP_AUX2_AUX_CONTROL                                                                          0x1f88
+#define regDP_AUX2_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_SW_CONTROL                                                                       0x1f89
+#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX2_AUX_ARB_CONTROL                                                                      0x1f8a
+#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL                                                                0x1f8b
+#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX2_AUX_SW_STATUS                                                                        0x1f8c
+#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_LS_STATUS                                                                        0x1f8d
+#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX2_AUX_SW_DATA                                                                          0x1f8e
+#define regDP_AUX2_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_LS_DATA                                                                          0x1f8f
+#define regDP_AUX2_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL                                                              0x1f90
+#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL                                                                  0x1f91
+#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0                                                                 0x1f92
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1                                                                 0x1f93
+#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_DPHY_TX_STATUS                                                                   0x1f94
+#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_DPHY_RX_STATUS                                                                   0x1f95
+#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL                                                                 0x1f96
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1f97
+#define regDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1f98
+#define regDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS                                                                  0x1f99
+#define regDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL                                                                    0x1f9e
+#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+// base address: 0x150
+#define regDP_AUX3_AUX_CONTROL                                                                          0x1fa4
+#define regDP_AUX3_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_SW_CONTROL                                                                       0x1fa5
+#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX3_AUX_ARB_CONTROL                                                                      0x1fa6
+#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL                                                                0x1fa7
+#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX3_AUX_SW_STATUS                                                                        0x1fa8
+#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_LS_STATUS                                                                        0x1fa9
+#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX3_AUX_SW_DATA                                                                          0x1faa
+#define regDP_AUX3_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_LS_DATA                                                                          0x1fab
+#define regDP_AUX3_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL                                                              0x1fac
+#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL                                                                  0x1fad
+#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0                                                                 0x1fae
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1                                                                 0x1faf
+#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_DPHY_TX_STATUS                                                                   0x1fb0
+#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_DPHY_RX_STATUS                                                                   0x1fb1
+#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL                                                                 0x1fb2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fb3
+#define regDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fb4
+#define regDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS                                                                  0x1fb5
+#define regDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL                                                                    0x1fba
+#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+// base address: 0x1c0
+#define regDP_AUX4_AUX_CONTROL                                                                          0x1fc0
+#define regDP_AUX4_AUX_CONTROL_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_SW_CONTROL                                                                       0x1fc1
+#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX                                                              2
+#define regDP_AUX4_AUX_ARB_CONTROL                                                                      0x1fc2
+#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX                                                             2
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL                                                                0x1fc3
+#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX                                                       2
+#define regDP_AUX4_AUX_SW_STATUS                                                                        0x1fc4
+#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_LS_STATUS                                                                        0x1fc5
+#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX                                                               2
+#define regDP_AUX4_AUX_SW_DATA                                                                          0x1fc6
+#define regDP_AUX4_AUX_SW_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_LS_DATA                                                                          0x1fc7
+#define regDP_AUX4_AUX_LS_DATA_BASE_IDX                                                                 2
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL                                                              0x1fc8
+#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX                                                     2
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL                                                                  0x1fc9
+#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0                                                                 0x1fca
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1                                                                 0x1fcb
+#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_DPHY_TX_STATUS                                                                   0x1fcc
+#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_DPHY_RX_STATUS                                                                   0x1fcd
+#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX                                                          2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL                                                                 0x1fce
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX                                                        2
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL                                                           0x1fcf
+#define regDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX                                                  2
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS                                                       0x1fd0
+#define regDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX                                              2
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS                                                                  0x1fd1
+#define regDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX                                                         2
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL                                                                    0x1fd6
+#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX                                                           2
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+// base address: 0x0
+#define regDC_I2C_CONTROL                                                                               0x1e98
+#define regDC_I2C_CONTROL_BASE_IDX                                                                      2
+#define regDC_I2C_ARBITRATION                                                                           0x1e99
+#define regDC_I2C_ARBITRATION_BASE_IDX                                                                  2
+#define regDC_I2C_INTERRUPT_CONTROL                                                                     0x1e9a
+#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX                                                            2
+#define regDC_I2C_SW_STATUS                                                                             0x1e9b
+#define regDC_I2C_SW_STATUS_BASE_IDX                                                                    2
+#define regDC_I2C_DDC1_HW_STATUS                                                                        0x1e9c
+#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC2_HW_STATUS                                                                        0x1e9d
+#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC3_HW_STATUS                                                                        0x1e9e
+#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC4_HW_STATUS                                                                        0x1e9f
+#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC5_HW_STATUS                                                                        0x1ea0
+#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX                                                               2
+#define regDC_I2C_DDC1_SPEED                                                                            0x1ea2
+#define regDC_I2C_DDC1_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC1_SETUP                                                                            0x1ea3
+#define regDC_I2C_DDC1_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SPEED                                                                            0x1ea4
+#define regDC_I2C_DDC2_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC2_SETUP                                                                            0x1ea5
+#define regDC_I2C_DDC2_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SPEED                                                                            0x1ea6
+#define regDC_I2C_DDC3_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC3_SETUP                                                                            0x1ea7
+#define regDC_I2C_DDC3_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SPEED                                                                            0x1ea8
+#define regDC_I2C_DDC4_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC4_SETUP                                                                            0x1ea9
+#define regDC_I2C_DDC4_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SPEED                                                                            0x1eaa
+#define regDC_I2C_DDC5_SPEED_BASE_IDX                                                                   2
+#define regDC_I2C_DDC5_SETUP                                                                            0x1eab
+#define regDC_I2C_DDC5_SETUP_BASE_IDX                                                                   2
+#define regDC_I2C_TRANSACTION0                                                                          0x1eae
+#define regDC_I2C_TRANSACTION0_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION1                                                                          0x1eaf
+#define regDC_I2C_TRANSACTION1_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION2                                                                          0x1eb0
+#define regDC_I2C_TRANSACTION2_BASE_IDX                                                                 2
+#define regDC_I2C_TRANSACTION3                                                                          0x1eb1
+#define regDC_I2C_TRANSACTION3_BASE_IDX                                                                 2
+#define regDC_I2C_DATA                                                                                  0x1eb2
+#define regDC_I2C_DATA_BASE_IDX                                                                         2
+#define regDC_I2C_EDID_DETECT_CTRL                                                                      0x1eb6
+#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX                                                             2
+#define regDC_I2C_READ_REQUEST_INTERRUPT                                                                0x1eb7
+#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX                                                       2
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+// base address: 0x0
+#define regDIO_SCRATCH0                                                                                 0x1eca
+#define regDIO_SCRATCH0_BASE_IDX                                                                        2
+#define regDIO_SCRATCH1                                                                                 0x1ecb
+#define regDIO_SCRATCH1_BASE_IDX                                                                        2
+#define regDIO_SCRATCH2                                                                                 0x1ecc
+#define regDIO_SCRATCH2_BASE_IDX                                                                        2
+#define regDIO_SCRATCH3                                                                                 0x1ecd
+#define regDIO_SCRATCH3_BASE_IDX                                                                        2
+#define regDIO_SCRATCH4                                                                                 0x1ece
+#define regDIO_SCRATCH4_BASE_IDX                                                                        2
+#define regDIO_SCRATCH5                                                                                 0x1ecf
+#define regDIO_SCRATCH5_BASE_IDX                                                                        2
+#define regDIO_SCRATCH6                                                                                 0x1ed0
+#define regDIO_SCRATCH6_BASE_IDX                                                                        2
+#define regDIO_SCRATCH7                                                                                 0x1ed1
+#define regDIO_SCRATCH7_BASE_IDX                                                                        2
+#define regDIO_MEM_PWR_STATUS                                                                           0x1edd
+#define regDIO_MEM_PWR_STATUS_BASE_IDX                                                                  2
+#define regDIO_MEM_PWR_CTRL                                                                             0x1ede
+#define regDIO_MEM_PWR_CTRL_BASE_IDX                                                                    2
+#define regDIO_MEM_PWR_CTRL2                                                                            0x1edf
+#define regDIO_MEM_PWR_CTRL2_BASE_IDX                                                                   2
+#define regDIO_CLK_CNTL                                                                                 0x1ee0
+#define regDIO_CLK_CNTL_BASE_IDX                                                                        2
+#define regDIO_POWER_MANAGEMENT_CNTL                                                                    0x1ee4
+#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX                                                           2
+#define regDIG_SOFT_RESET                                                                               0x1eee
+#define regDIG_SOFT_RESET_BASE_IDX                                                                      2
+#define regDIO_CLK_CNTL2                                                                                0x1ef2
+#define regDIO_CLK_CNTL2_BASE_IDX                                                                       2
+#define regDIO_CLK_CNTL3                                                                                0x1ef3
+#define regDIO_CLK_CNTL3_BASE_IDX                                                                       2
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL                                                              0x1eff
+#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX                                                     2
+#define regDIO_GENERIC_INTERRUPT_MESSAGE                                                                0x1f02
+#define regDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX                                                       2
+#define regDIO_GENERIC_INTERRUPT_CLEAR                                                                  0x1f03
+#define regDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX                                                         2
+#define regDIO_LINKA_CNTL                                                                               0x1f04
+#define regDIO_LINKA_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKB_CNTL                                                                               0x1f05
+#define regDIO_LINKB_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKC_CNTL                                                                               0x1f06
+#define regDIO_LINKC_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKD_CNTL                                                                               0x1f07
+#define regDIO_LINKD_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKE_CNTL                                                                               0x1f08
+#define regDIO_LINKE_CNTL_BASE_IDX                                                                      2
+#define regDIO_LINKF_CNTL                                                                               0x1f09
+#define regDIO_LINKF_CNTL_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+// base address: 0x7d10
+#define regDC_PERFMON18_PERFCOUNTER_CNTL                                                                0x1f44
+#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON18_PERFCOUNTER_CNTL2                                                               0x1f45
+#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON18_PERFCOUNTER_STATE                                                               0x1f46
+#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON18_PERFMON_CNTL                                                                    0x1f47
+#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON18_PERFMON_CNTL2                                                                   0x1f48
+#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC                                                         0x1f49
+#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON18_PERFMON_CVALUE_LOW                                                              0x1f4a
+#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON18_PERFMON_HI                                                                      0x1f4b
+#define regDC_PERFMON18_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON18_PERFMON_LOW                                                                     0x1f4c
+#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_LINK_CNTL                                                                            0x2873
+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_LINK_CNTL                                                                            0x2875
+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902
+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19
+#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a
+#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21
+#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec
+// base address: 0x1b0
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85
+#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86
+#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d
+#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+// base address: 0x0
+#define regDSCC0_DSCC_CONFIG0                                                                           0x300a
+#define regDSCC0_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_CONFIG1                                                                           0x300b
+#define regDSCC0_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC0_DSCC_STATUS                                                                            0x300c
+#define regDSCC0_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x300d
+#define regDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC0_DSCC_PPS_CONFIG0                                                                       0x300e
+#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG1                                                                       0x300f
+#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG2                                                                       0x3010
+#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG3                                                                       0x3011
+#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG4                                                                       0x3012
+#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG5                                                                       0x3013
+#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG6                                                                       0x3014
+#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG7                                                                       0x3015
+#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG8                                                                       0x3016
+#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG9                                                                       0x3017
+#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC0_DSCC_PPS_CONFIG10                                                                      0x3018
+#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG11                                                                      0x3019
+#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG12                                                                      0x301a
+#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG13                                                                      0x301b
+#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG14                                                                      0x301c
+#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG15                                                                      0x301d
+#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG16                                                                      0x301e
+#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG17                                                                      0x301f
+#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG18                                                                      0x3020
+#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG19                                                                      0x3021
+#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG20                                                                      0x3022
+#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG21                                                                      0x3023
+#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC0_DSCC_PPS_CONFIG22                                                                      0x3024
+#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC0_DSCC_MEM_POWER_CONTROL                                                                 0x3025
+#define regDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3026
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3027
+#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3028
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3029
+#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x302a
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x302b
+#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC0_DSCC_MAX_ABS_ERROR0                                                                    0x302c
+#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC0_DSCC_MAX_ABS_ERROR1                                                                    0x302d
+#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x302e
+#define regDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x302f
+#define regDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x3030
+#define regDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x3031
+#define regDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x3032
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x3033
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3034
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
+#define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+// base address: 0x0
+#define regDSCCIF0_DSCCIF_CONFIG0                                                                       0x3005
+#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF0_DSCCIF_CONFIG1                                                                       0x3006
+#define regDSCCIF0_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+// base address: 0x0
+#define regDSC_TOP0_DSC_TOP_CONTROL                                                                     0x3000
+#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP0_DSC_DEBUG_CONTROL                                                                   0x3001
+#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc140
+#define regDC_PERFMON19_PERFCOUNTER_CNTL                                                                0x3050
+#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON19_PERFCOUNTER_CNTL2                                                               0x3051
+#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON19_PERFCOUNTER_STATE                                                               0x3052
+#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON19_PERFMON_CNTL                                                                    0x3053
+#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON19_PERFMON_CNTL2                                                                   0x3054
+#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC                                                         0x3055
+#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON19_PERFMON_CVALUE_LOW                                                              0x3056
+#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON19_PERFMON_HI                                                                      0x3057
+#define regDC_PERFMON19_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON19_PERFMON_LOW                                                                     0x3058
+#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+// base address: 0x170
+#define regDSCC1_DSCC_CONFIG0                                                                           0x3066
+#define regDSCC1_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_CONFIG1                                                                           0x3067
+#define regDSCC1_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC1_DSCC_STATUS                                                                            0x3068
+#define regDSCC1_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x3069
+#define regDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC1_DSCC_PPS_CONFIG0                                                                       0x306a
+#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG1                                                                       0x306b
+#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG2                                                                       0x306c
+#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG3                                                                       0x306d
+#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG4                                                                       0x306e
+#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG5                                                                       0x306f
+#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG6                                                                       0x3070
+#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG7                                                                       0x3071
+#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG8                                                                       0x3072
+#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG9                                                                       0x3073
+#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC1_DSCC_PPS_CONFIG10                                                                      0x3074
+#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG11                                                                      0x3075
+#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG12                                                                      0x3076
+#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG13                                                                      0x3077
+#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG14                                                                      0x3078
+#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG15                                                                      0x3079
+#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG16                                                                      0x307a
+#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG17                                                                      0x307b
+#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG18                                                                      0x307c
+#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG19                                                                      0x307d
+#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG20                                                                      0x307e
+#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG21                                                                      0x307f
+#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC1_DSCC_PPS_CONFIG22                                                                      0x3080
+#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC1_DSCC_MEM_POWER_CONTROL                                                                 0x3081
+#define regDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x3082
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x3083
+#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x3084
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x3085
+#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x3086
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x3087
+#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC1_DSCC_MAX_ABS_ERROR0                                                                    0x3088
+#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC1_DSCC_MAX_ABS_ERROR1                                                                    0x3089
+#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x308a
+#define regDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x308b
+#define regDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x308c
+#define regDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x308d
+#define regDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x308e
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x308f
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x3090
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
+#define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+// base address: 0x170
+#define regDSCCIF1_DSCCIF_CONFIG0                                                                       0x3061
+#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF1_DSCCIF_CONFIG1                                                                       0x3062
+#define regDSCCIF1_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+// base address: 0x170
+#define regDSC_TOP1_DSC_TOP_CONTROL                                                                     0x305c
+#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP1_DSC_DEBUG_CONTROL                                                                   0x305d
+#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc2b0
+#define regDC_PERFMON20_PERFCOUNTER_CNTL                                                                0x30ac
+#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON20_PERFCOUNTER_CNTL2                                                               0x30ad
+#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON20_PERFCOUNTER_STATE                                                               0x30ae
+#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON20_PERFMON_CNTL                                                                    0x30af
+#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON20_PERFMON_CNTL2                                                                   0x30b0
+#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC                                                         0x30b1
+#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON20_PERFMON_CVALUE_LOW                                                              0x30b2
+#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON20_PERFMON_HI                                                                      0x30b3
+#define regDC_PERFMON20_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON20_PERFMON_LOW                                                                     0x30b4
+#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+// base address: 0x2e0
+#define regDSCC2_DSCC_CONFIG0                                                                           0x30c2
+#define regDSCC2_DSCC_CONFIG0_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_CONFIG1                                                                           0x30c3
+#define regDSCC2_DSCC_CONFIG1_BASE_IDX                                                                  2
+#define regDSCC2_DSCC_STATUS                                                                            0x30c4
+#define regDSCC2_DSCC_STATUS_BASE_IDX                                                                   2
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS                                                          0x30c5
+#define regDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX                                                 2
+#define regDSCC2_DSCC_PPS_CONFIG0                                                                       0x30c6
+#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG1                                                                       0x30c7
+#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG2                                                                       0x30c8
+#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG3                                                                       0x30c9
+#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG4                                                                       0x30ca
+#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG5                                                                       0x30cb
+#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG6                                                                       0x30cc
+#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG7                                                                       0x30cd
+#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG8                                                                       0x30ce
+#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG9                                                                       0x30cf
+#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX                                                              2
+#define regDSCC2_DSCC_PPS_CONFIG10                                                                      0x30d0
+#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG11                                                                      0x30d1
+#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG12                                                                      0x30d2
+#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG13                                                                      0x30d3
+#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG14                                                                      0x30d4
+#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG15                                                                      0x30d5
+#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG16                                                                      0x30d6
+#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG17                                                                      0x30d7
+#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG18                                                                      0x30d8
+#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG19                                                                      0x30d9
+#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG20                                                                      0x30da
+#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG21                                                                      0x30db
+#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX                                                             2
+#define regDSCC2_DSCC_PPS_CONFIG22                                                                      0x30dc
+#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX                                                             2
+#define regDSCC2_DSCC_MEM_POWER_CONTROL                                                                 0x30dd
+#define regDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX                                                        2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER                                                           0x30de
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER                                                           0x30df
+#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX                                                  2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER                                                          0x30e0
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER                                                          0x30e1
+#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER                                                          0x30e2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER                                                          0x30e3
+#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX                                                 2
+#define regDSCC2_DSCC_MAX_ABS_ERROR0                                                                    0x30e4
+#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX                                                           2
+#define regDSCC2_DSCC_MAX_ABS_ERROR1                                                                    0x30e5
+#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX                                                           2
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL                                                   0x30e6
+#define regDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL                                                   0x30e7
+#define regDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL                                                   0x30e8
+#define regDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL                                                   0x30e9
+#define regDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                          2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL                                           0x30ea
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL                                           0x30eb
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL                                           0x30ec
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
+#define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+// base address: 0x2e0
+#define regDSCCIF2_DSCCIF_CONFIG0                                                                       0x30bd
+#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX                                                              2
+#define regDSCCIF2_DSCCIF_CONFIG1                                                                       0x30be
+#define regDSCCIF2_DSCCIF_CONFIG1_BASE_IDX                                                              2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+// base address: 0x2e0
+#define regDSC_TOP2_DSC_TOP_CONTROL                                                                     0x30b8
+#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX                                                            2
+#define regDSC_TOP2_DSC_DEBUG_CONTROL                                                                   0x30b9
+#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX                                                          2
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+// base address: 0xc420
+#define regDC_PERFMON21_PERFCOUNTER_CNTL                                                                0x3108
+#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX                                                       2
+#define regDC_PERFMON21_PERFCOUNTER_CNTL2                                                               0x3109
+#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX                                                      2
+#define regDC_PERFMON21_PERFCOUNTER_STATE                                                               0x310a
+#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX                                                      2
+#define regDC_PERFMON21_PERFMON_CNTL                                                                    0x310b
+#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX                                                           2
+#define regDC_PERFMON21_PERFMON_CNTL2                                                                   0x310c
+#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX                                                          2
+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC                                                         0x310d
+#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                2
+#define regDC_PERFMON21_PERFMON_CVALUE_LOW                                                              0x310e
+#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX                                                     2
+#define regDC_PERFMON21_PERFMON_HI                                                                      0x310f
+#define regDC_PERFMON21_PERFMON_HI_BASE_IDX                                                             2
+#define regDC_PERFMON21_PERFMON_LOW                                                                     0x3110
+#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX                                                            2
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+// base address: 0x2790c
+#define regHPO_TOP_CLOCK_CONTROL                                                                        0x0e43
+#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX                                                               3
+#define regHPO_TOP_HW_CONTROL                                                                           0x0e4a
+#define regHPO_TOP_HW_CONTROL_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+// base address: 0x27958
+#define regDP_STREAM_MAPPER_CONTROL0                                                                    0x0e56
+#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL1                                                                    0x0e57
+#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL2                                                                    0x0e58
+#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX                                                           3
+#define regDP_STREAM_MAPPER_CONTROL3                                                                    0x0e59
+#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX                                                           3
+
+
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
+// base address: 0x1a698
+#define regDC_PERFMON22_PERFCOUNTER_CNTL                                                                0x0e66
+#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX                                                       3
+#define regDC_PERFMON22_PERFCOUNTER_CNTL2                                                               0x0e67
+#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX                                                      3
+#define regDC_PERFMON22_PERFCOUNTER_STATE                                                               0x0e68
+#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX                                                      3
+#define regDC_PERFMON22_PERFMON_CNTL                                                                    0x0e69
+#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX                                                           3
+#define regDC_PERFMON22_PERFMON_CNTL2                                                                   0x0e6a
+#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX                                                          3
+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC                                                         0x0e6b
+#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX                                                3
+#define regDC_PERFMON22_PERFMON_CVALUE_LOW                                                              0x0e6c
+#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX                                                     3
+#define regDC_PERFMON22_PERFMON_HI                                                                      0x0e6d
+#define regDC_PERFMON22_PERFMON_HI_BASE_IDX                                                             3
+#define regDC_PERFMON22_PERFMON_LOW                                                                     0x0e6e
+#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX                                                            3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+// base address: 0x2646c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL                                                                0x091c
+#define regAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX                                                       3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2                                                             0x091d
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX                                                    3
+#define regAFMT5_AFMT_AUDIO_INFO0                                                                       0x091e
+#define regAFMT5_AFMT_AUDIO_INFO0_BASE_IDX                                                              3
+#define regAFMT5_AFMT_AUDIO_INFO1                                                                       0x091f
+#define regAFMT5_AFMT_AUDIO_INFO1_BASE_IDX                                                              3
+#define regAFMT5_AFMT_60958_0                                                                           0x0920
+#define regAFMT5_AFMT_60958_0_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_60958_1                                                                           0x0921
+#define regAFMT5_AFMT_60958_1_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL                                                                 0x0922
+#define regAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_RAMP_CONTROL0                                                                     0x0923
+#define regAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL1                                                                     0x0924
+#define regAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL2                                                                     0x0925
+#define regAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX                                                            3
+#define regAFMT5_AFMT_RAMP_CONTROL3                                                                     0x0926
+#define regAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX                                                            3
+#define regAFMT5_AFMT_60958_2                                                                           0x0927
+#define regAFMT5_AFMT_60958_2_BASE_IDX                                                                  3
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT                                                                  0x0928
+#define regAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX                                                         3
+#define regAFMT5_AFMT_STATUS                                                                            0x0929
+#define regAFMT5_AFMT_STATUS_BASE_IDX                                                                   3
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL                                                              0x092a
+#define regAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX                                                     3
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0                                                                0x092b
+#define regAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX                                                       3
+#define regAFMT5_AFMT_INTERRUPT_STATUS                                                                  0x092c
+#define regAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX                                                         3
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL                                                                 0x092d
+#define regAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX                                                        3
+#define regAFMT5_AFMT_MEM_PWR                                                                           0x092f
+#define regAFMT5_AFMT_MEM_PWR_BASE_IDX                                                                  3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+// base address: 0x264f0
+#define regDME5_DME_CONTROL                                                                             0x093c
+#define regDME5_DME_CONTROL_BASE_IDX                                                                    3
+#define regDME5_DME_MEMORY_CONTROL                                                                      0x093d
+#define regDME5_DME_MEMORY_CONTROL_BASE_IDX                                                             3
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+// base address: 0x264c4
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x0931
+#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 3
+#define regVPG5_VPG_GENERIC_PACKET_DATA                                                                 0x0932
+#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        3
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x0933
+#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      3
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x0934
+#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  3
+#define regVPG5_VPG_GENERIC_STATUS                                                                      0x0935
+#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX                                                             3
+#define regVPG5_VPG_MEM_PWR                                                                             0x0936
+#define regVPG5_VPG_MEM_PWR_BASE_IDX                                                                    3
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x0937
+#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        3
+#define regVPG5_VPG_ISRC1_2_DATA                                                                        0x0938
+#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX                                                               3
+#define regVPG5_VPG_MPEG_INFO0                                                                          0x0939
+#define regVPG5_VPG_MPEG_INFO0_BASE_IDX                                                                 3
+#define regVPG5_VPG_MPEG_INFO1                                                                          0x093a
+#define regVPG5_VPG_MPEG_INFO1_BASE_IDX                                                                 3
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+// base address: 0x1ab8c
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x3623
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x3624
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x3625
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x3626
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x3627
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE                                                           0x3628
+#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+// base address: 0x1abc0
+#define regAPG0_APG_CONTROL                                                                             0x3630
+#define regAPG0_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG0_APG_CONTROL2                                                                            0x3631
+#define regAPG0_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG0_APG_DBG_GEN_CONTROL                                                                     0x3632
+#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG0_APG_PACKET_CONTROL                                                                      0x3633
+#define regAPG0_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG0_APG_AUDIO_CRC_CONTROL                                                                   0x363a
+#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG0_APG_AUDIO_CRC_CONTROL2                                                                  0x363b
+#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG0_APG_AUDIO_CRC_RESULT                                                                    0x363c
+#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG0_APG_STATUS                                                                              0x3641
+#define regAPG0_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG0_APG_STATUS2                                                                             0x3642
+#define regAPG0_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG0_APG_MEM_PWR                                                                             0x3644
+#define regAPG0_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG0_APG_SPARE                                                                               0x3646
+#define regAPG0_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+// base address: 0x1ac38
+#define regDME6_DME_CONTROL                                                                             0x364e
+#define regDME6_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME6_DME_MEMORY_CONTROL                                                                      0x364f
+#define regDME6_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+// base address: 0x1ac44
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3651
+#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG6_VPG_GENERIC_PACKET_DATA                                                                 0x3652
+#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3653
+#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3654
+#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG6_VPG_GENERIC_STATUS                                                                      0x3655
+#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG6_VPG_MEM_PWR                                                                             0x3656
+#define regVPG6_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x3657
+#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG6_VPG_ISRC1_2_DATA                                                                        0x3658
+#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG6_VPG_MPEG_INFO0                                                                          0x3659
+#define regVPG6_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG6_VPG_MPEG_INFO1                                                                          0x365a
+#define regVPG6_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+// base address: 0x1ac74
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL                                                           0x365d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x365e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x365f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3660
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3661
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0                                                          0x3662
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1                                                          0x3663
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2                                                          0x3664
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3                                                          0x3665
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4                                                          0x3666
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5                                                          0x3667
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6                                                          0x3668
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7                                                          0x3669
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8                                                          0x366a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x366b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x366c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x366d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x366e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x366f
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3670
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3671
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3672
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3673
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3674
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3675
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x3676
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x3677
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3678
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3679
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x367a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL                                                       0x367b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x367c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x367d
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x367e
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3683
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3684
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3685
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3686
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3687
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3688
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3689
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x368a
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x368b
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE                                                             0x368c
+#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+// base address: 0x1aedc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x36f7
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x36f8
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x36f9
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x36fa
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x36fb
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE                                                           0x36fc
+#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+// base address: 0x1af10
+#define regAPG1_APG_CONTROL                                                                             0x3704
+#define regAPG1_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG1_APG_CONTROL2                                                                            0x3705
+#define regAPG1_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG1_APG_DBG_GEN_CONTROL                                                                     0x3706
+#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG1_APG_PACKET_CONTROL                                                                      0x3707
+#define regAPG1_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG1_APG_AUDIO_CRC_CONTROL                                                                   0x370e
+#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG1_APG_AUDIO_CRC_CONTROL2                                                                  0x370f
+#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG1_APG_AUDIO_CRC_RESULT                                                                    0x3710
+#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG1_APG_STATUS                                                                              0x3715
+#define regAPG1_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG1_APG_STATUS2                                                                             0x3716
+#define regAPG1_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG1_APG_MEM_PWR                                                                             0x3718
+#define regAPG1_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG1_APG_SPARE                                                                               0x371a
+#define regAPG1_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+// base address: 0x1af88
+#define regDME7_DME_CONTROL                                                                             0x3722
+#define regDME7_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME7_DME_MEMORY_CONTROL                                                                      0x3723
+#define regDME7_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+// base address: 0x1af94
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x3725
+#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG7_VPG_GENERIC_PACKET_DATA                                                                 0x3726
+#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x3727
+#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x3728
+#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG7_VPG_GENERIC_STATUS                                                                      0x3729
+#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG7_VPG_MEM_PWR                                                                             0x372a
+#define regVPG7_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x372b
+#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG7_VPG_ISRC1_2_DATA                                                                        0x372c
+#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG7_VPG_MPEG_INFO0                                                                          0x372d
+#define regVPG7_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG7_VPG_MPEG_INFO1                                                                          0x372e
+#define regVPG7_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+// base address: 0x1afc4
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL                                                           0x3731
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3732
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3733
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3734
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3735
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0                                                          0x3736
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1                                                          0x3737
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2                                                          0x3738
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3                                                          0x3739
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4                                                          0x373a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5                                                          0x373b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6                                                          0x373c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7                                                          0x373d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8                                                          0x373e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x373f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3740
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3741
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3742
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3743
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3744
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3745
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x3746
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x3747
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x3748
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x3749
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x374a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x374b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x374c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x374d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x374e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL                                                       0x374f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3750
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3751
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3752
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x3757
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3758
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3759
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x375a
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x375b
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x375c
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x375d
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x375e
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x375f
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE                                                             0x3760
+#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+// base address: 0x1b22c
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x37cb
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x37cc
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x37cd
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x37ce
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x37cf
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE                                                           0x37d0
+#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+// base address: 0x1b260
+#define regAPG2_APG_CONTROL                                                                             0x37d8
+#define regAPG2_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG2_APG_CONTROL2                                                                            0x37d9
+#define regAPG2_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG2_APG_DBG_GEN_CONTROL                                                                     0x37da
+#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG2_APG_PACKET_CONTROL                                                                      0x37db
+#define regAPG2_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG2_APG_AUDIO_CRC_CONTROL                                                                   0x37e2
+#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG2_APG_AUDIO_CRC_CONTROL2                                                                  0x37e3
+#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG2_APG_AUDIO_CRC_RESULT                                                                    0x37e4
+#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG2_APG_STATUS                                                                              0x37e9
+#define regAPG2_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG2_APG_STATUS2                                                                             0x37ea
+#define regAPG2_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG2_APG_MEM_PWR                                                                             0x37ec
+#define regAPG2_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG2_APG_SPARE                                                                               0x37ee
+#define regAPG2_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+// base address: 0x1b2d8
+#define regDME8_DME_CONTROL                                                                             0x37f6
+#define regDME8_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME8_DME_MEMORY_CONTROL                                                                      0x37f7
+#define regDME8_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+// base address: 0x1b2e4
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x37f9
+#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG8_VPG_GENERIC_PACKET_DATA                                                                 0x37fa
+#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x37fb
+#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x37fc
+#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG8_VPG_GENERIC_STATUS                                                                      0x37fd
+#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG8_VPG_MEM_PWR                                                                             0x37fe
+#define regVPG8_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x37ff
+#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG8_VPG_ISRC1_2_DATA                                                                        0x3800
+#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG8_VPG_MPEG_INFO0                                                                          0x3801
+#define regVPG8_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG8_VPG_MPEG_INFO1                                                                          0x3802
+#define regVPG8_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+// base address: 0x1b314
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL                                                           0x3805
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x3806
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x3807
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x3808
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x3809
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0                                                          0x380a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1                                                          0x380b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2                                                          0x380c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3                                                          0x380d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4                                                          0x380e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5                                                          0x380f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6                                                          0x3810
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7                                                          0x3811
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8                                                          0x3812
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x3813
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x3814
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x3815
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x3816
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x3817
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x3818
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x3819
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x381a
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x381b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x381c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x381d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x381e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x381f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x3820
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x3821
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x3822
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL                                                       0x3823
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x3824
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x3825
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x3826
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x382b
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x382c
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x382d
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x382e
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x382f
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3830
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3831
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3832
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3833
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE                                                             0x3834
+#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+// base address: 0x1b57c
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL                                                   0x389f
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL                                               0x38a0
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX                                      2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL                                                   0x38a1
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX                                          2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0                        0x38a2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1                        0x38a3
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX               2
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE                                                           0x38a4
+#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX                                                  2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+// base address: 0x1b5b0
+#define regAPG3_APG_CONTROL                                                                             0x38ac
+#define regAPG3_APG_CONTROL_BASE_IDX                                                                    2
+#define regAPG3_APG_CONTROL2                                                                            0x38ad
+#define regAPG3_APG_CONTROL2_BASE_IDX                                                                   2
+#define regAPG3_APG_DBG_GEN_CONTROL                                                                     0x38ae
+#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX                                                            2
+#define regAPG3_APG_PACKET_CONTROL                                                                      0x38af
+#define regAPG3_APG_PACKET_CONTROL_BASE_IDX                                                             2
+#define regAPG3_APG_AUDIO_CRC_CONTROL                                                                   0x38b6
+#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX                                                          2
+#define regAPG3_APG_AUDIO_CRC_CONTROL2                                                                  0x38b7
+#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX                                                         2
+#define regAPG3_APG_AUDIO_CRC_RESULT                                                                    0x38b8
+#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX                                                           2
+#define regAPG3_APG_STATUS                                                                              0x38bd
+#define regAPG3_APG_STATUS_BASE_IDX                                                                     2
+#define regAPG3_APG_STATUS2                                                                             0x38be
+#define regAPG3_APG_STATUS2_BASE_IDX                                                                    2
+#define regAPG3_APG_MEM_PWR                                                                             0x38c0
+#define regAPG3_APG_MEM_PWR_BASE_IDX                                                                    2
+#define regAPG3_APG_SPARE                                                                               0x38c2
+#define regAPG3_APG_SPARE_BASE_IDX                                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+// base address: 0x1b628
+#define regDME9_DME_CONTROL                                                                             0x38ca
+#define regDME9_DME_CONTROL_BASE_IDX                                                                    2
+#define regDME9_DME_MEMORY_CONTROL                                                                      0x38cb
+#define regDME9_DME_MEMORY_CONTROL_BASE_IDX                                                             2
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+// base address: 0x1b634
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL                                                          0x38cd
+#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX                                                 2
+#define regVPG9_VPG_GENERIC_PACKET_DATA                                                                 0x38ce
+#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX                                                        2
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL                                                               0x38cf
+#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX                                                      2
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL                                                           0x38d0
+#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX                                                  2
+#define regVPG9_VPG_GENERIC_STATUS                                                                      0x38d1
+#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX                                                             2
+#define regVPG9_VPG_MEM_PWR                                                                             0x38d2
+#define regVPG9_VPG_MEM_PWR_BASE_IDX                                                                    2
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL                                                                 0x38d3
+#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX                                                        2
+#define regVPG9_VPG_ISRC1_2_DATA                                                                        0x38d4
+#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX                                                               2
+#define regVPG9_VPG_MPEG_INFO0                                                                          0x38d5
+#define regVPG9_VPG_MPEG_INFO0_BASE_IDX                                                                 2
+#define regVPG9_VPG_MPEG_INFO1                                                                          0x38d6
+#define regVPG9_VPG_MPEG_INFO1_BASE_IDX                                                                 2
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+// base address: 0x1b664
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL                                                           0x38d9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX                                                  2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL                                                  0x38da
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL                                     0x38db
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX                            2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL                            0x38dc
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX                   2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT                                                  0x38dd
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0                                                          0x38de
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1                                                          0x38df
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2                                                          0x38e0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3                                                          0x38e1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4                                                          0x38e2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5                                                          0x38e3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6                                                          0x38e4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7                                                          0x38e5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8                                                          0x38e6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX                                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL                                                    0x38e7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0                                                  0x38e8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1                                                  0x38e9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2                                                  0x38ea
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3                                                  0x38eb
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4                                                  0x38ec
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5                                                  0x38ed
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6                                                  0x38ee
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7                                                  0x38ef
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8                                                  0x38f0
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9                                                  0x38f1
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10                                                 0x38f2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11                                                 0x38f3
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12                                                 0x38f4
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13                                                 0x38f5
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14                                                 0x38f6
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL                                                       0x38f7
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX                                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0                                                0x38f8
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1                                                0x38f9
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL                                       0x38fa
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX                              2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL                                                   0x38ff
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL                                                  0x3900
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX                                         2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL                                                0x3901
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX                                       2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL                                          0x3902
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX                                 2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL                                                   0x3903
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0                                                   0x3904
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1                                                   0x3905
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX                                          2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS                                                    0x3906
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX                                           2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL                                                 0x3907
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX                                        2
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE                                                             0x3908
+#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX                                                    2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+// base address: 0x1ad5c
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL                                                       0x3697
+#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE                                                               0x3698
+#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+// base address: 0x1ae00
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL                                                         0x36c0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS                                                          0x36c1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE                                                      0x36c4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x36c5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x36c6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x36c7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x36c8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0                                                         0x36cb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1                                                         0x36cc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2                                                         0x36cd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3                                                         0x36ce
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x36d1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x36d2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x36d3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x36d4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG                                                       0x36d7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x36d8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x36d9
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x36da
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x36db
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x36dc
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x36dd
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x36de
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x36df
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x36e0
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x36e1
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x36e2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x36e3
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x36e4
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x36e5
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x36e6
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x36e7
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS                                                    0x36e8
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x36ea
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x36eb
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x36ec
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS                                                      0x36ed
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT                                                       0x36ee
+#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+// base address: 0x1b0ac
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL                                                       0x376b
+#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX                                              2
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE                                                               0x376c
+#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX                                                      2
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+// base address: 0x1b150
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL                                                         0x3794
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS                                                          0x3795
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX                                                 2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE                                                      0x3798
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0                                                   0x3799
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1                                                   0x379a
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2                                                   0x379b
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3                                                   0x379c
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0                                                         0x379f
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1                                                         0x37a0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2                                                         0x37a1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3                                                         0x37a2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX                                                2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0                                                  0x37a5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1                                                  0x37a6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2                                                  0x37a7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3                                                  0x37a8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX                                         2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG                                                       0x37ab
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX                                              2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0                                                   0x37ac
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1                                                   0x37ad
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2                                                   0x37ae
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3                                                   0x37af
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX                                          2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE                                                     0x37b0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0                                                      0x37b1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1                                                      0x37b2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2                                                      0x37b3
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3                                                      0x37b4
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4                                                      0x37b5
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5                                                      0x37b6
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6                                                      0x37b7
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7                                                      0x37b8
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8                                                      0x37b9
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9                                                      0x37ba
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10                                                     0x37bb
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS                                                    0x37bc
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX                                           2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE                                                 0x37be
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE_BASE_IDX                                        2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0                                                     0x37bf
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1                                                     0x37c0
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1_BASE_IDX                                            2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS                                                      0x37c1
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS_BASE_IDX                                             2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT                                                       0x37c2
+#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT_BASE_IDX                                              2
+
+
+// addressBlock: dce_dc_dchvm_hvm_dispdec
+// base address: 0x0
+#define regDCHVM_CTRL0                                                                                  0x3603
+#define regDCHVM_CTRL0_BASE_IDX                                                                         2
+#define regDCHVM_CTRL1                                                                                  0x3604
+#define regDCHVM_CTRL1_BASE_IDX                                                                         2
+#define regDCHVM_CLK_CTRL                                                                               0x3605
+#define regDCHVM_CLK_CTRL_BASE_IDX                                                                      2
+#define regDCHVM_MEM_CTRL                                                                               0x3606
+#define regDCHVM_MEM_CTRL_BASE_IDX                                                                      2
+#define regDCHVM_RIOMMU_CTRL0                                                                           0x3607
+#define regDCHVM_RIOMMU_CTRL0_BASE_IDX                                                                  2
+#define regDCHVM_RIOMMU_STAT0                                                                           0x3608
+#define regDCHVM_RIOMMU_STAT0_BASE_IDX                                                                  2
+
+// addressBlock: vga_vgaseqind
+// base address: 0x0
+#define ixSEQ00                                                                                        0x0000
+#define ixSEQ01                                                                                        0x0001
+#define ixSEQ02                                                                                        0x0002
+#define ixSEQ03                                                                                        0x0003
+#define ixSEQ04                                                                                        0x0004
+
+
+// addressBlock: vga_vgacrtind
+// base address: 0x0
+#define ixCRT00                                                                                        0x0000
+#define ixCRT01                                                                                        0x0001
+#define ixCRT02                                                                                        0x0002
+#define ixCRT03                                                                                        0x0003
+#define ixCRT04                                                                                        0x0004
+#define ixCRT05                                                                                        0x0005
+#define ixCRT06                                                                                        0x0006
+#define ixCRT07                                                                                        0x0007
+#define ixCRT08                                                                                        0x0008
+#define ixCRT09                                                                                        0x0009
+#define ixCRT0A                                                                                        0x000a
+#define ixCRT0B                                                                                        0x000b
+#define ixCRT0C                                                                                        0x000c
+#define ixCRT0D                                                                                        0x000d
+#define ixCRT0E                                                                                        0x000e
+#define ixCRT0F                                                                                        0x000f
+#define ixCRT10                                                                                        0x0010
+#define ixCRT11                                                                                        0x0011
+#define ixCRT12                                                                                        0x0012
+#define ixCRT13                                                                                        0x0013
+#define ixCRT14                                                                                        0x0014
+#define ixCRT15                                                                                        0x0015
+#define ixCRT16                                                                                        0x0016
+#define ixCRT17                                                                                        0x0017
+#define ixCRT18                                                                                        0x0018
+#define ixCRT1E                                                                                        0x001e
+#define ixCRT1F                                                                                        0x001f
+#define ixCRT22                                                                                        0x0022
+
+
+// addressBlock: vga_vgagrphind
+// base address: 0x0
+#define ixGRA00                                                                                        0x0000
+#define ixGRA01                                                                                        0x0001
+#define ixGRA02                                                                                        0x0002
+#define ixGRA03                                                                                        0x0003
+#define ixGRA04                                                                                        0x0004
+#define ixGRA05                                                                                        0x0005
+#define ixGRA06                                                                                        0x0006
+#define ixGRA07                                                                                        0x0007
+#define ixGRA08                                                                                        0x0008
+
+
+// addressBlock: vga_vgaattrind
+// base address: 0x0
+#define ixATTR00                                                                                       0x0000
+#define ixATTR01                                                                                       0x0001
+#define ixATTR02                                                                                       0x0002
+#define ixATTR03                                                                                       0x0003
+#define ixATTR04                                                                                       0x0004
+#define ixATTR05                                                                                       0x0005
+#define ixATTR06                                                                                       0x0006
+#define ixATTR07                                                                                       0x0007
+#define ixATTR08                                                                                       0x0008
+#define ixATTR09                                                                                       0x0009
+#define ixATTR0A                                                                                       0x000a
+#define ixATTR0B                                                                                       0x000b
+#define ixATTR0C                                                                                       0x000c
+#define ixATTR0D                                                                                       0x000d
+#define ixATTR0E                                                                                       0x000e
+#define ixATTR0F                                                                                       0x000f
+#define ixATTR10                                                                                       0x0010
+#define ixATTR11                                                                                       0x0011
+#define ixATTR12                                                                                       0x0012
+#define ixATTR13                                                                                       0x0013
+#define ixATTR14                                                                                       0x0014
+
+
+// addressBlock: azendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                                           0x2200
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                          0x2706
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                                          0x270d
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2                                        0x270e
+#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL                                                     0x2724
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3                                        0x273e
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE                                                  0x2770
+#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                              0x2771
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x2f09
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                                     0x2f0a
+#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                                           0x2f0b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY                                   0x3702
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL                                                   0x3707
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                                             0x3708
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                               0x3709
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                                   0x371c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                                 0x371d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                                 0x371e
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                                 0x371f
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION                                      0x3770
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION                                               0x3771
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO                                                    0x3772
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR                                                 0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA                                            0x3776
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE                                            0x3777
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE                                            0x3778
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE                                            0x3779
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE                                            0x377a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC                                                          0x377b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR                                                              0x377c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX                                            0x3780
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA                                             0x3781
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE                                             0x3785
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE                                             0x3786
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE                                             0x3787
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE                                             0x3788
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                                0x3789
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                                    0x378a
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                                    0x378b
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                                    0x378c
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                                    0x378d
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                                    0x378e
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                                    0x378f
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                                    0x3790
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                                    0x3791
+#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                                    0x3792
+#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO                                                         0x3793
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                                            0x3797
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                            0x3798
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB                                                             0x3799
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                              0x379a
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE                                                      0x379b
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED                                                   0x379c
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                                  0x379d
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                                 0x379e
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                      0x3f09
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES                                                   0x3f0c
+#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH                                         0x3f0e
+
+
+// addressBlock: azendpoint_descriptorind
+// base address: 0x0
+#define ixAUDIO_DESCRIPTOR0                                                                            0x0001
+#define ixAUDIO_DESCRIPTOR1                                                                            0x0002
+#define ixAUDIO_DESCRIPTOR2                                                                            0x0003
+#define ixAUDIO_DESCRIPTOR3                                                                            0x0004
+#define ixAUDIO_DESCRIPTOR4                                                                            0x0005
+#define ixAUDIO_DESCRIPTOR5                                                                            0x0006
+#define ixAUDIO_DESCRIPTOR6                                                                            0x0007
+#define ixAUDIO_DESCRIPTOR7                                                                            0x0008
+#define ixAUDIO_DESCRIPTOR8                                                                            0x0009
+#define ixAUDIO_DESCRIPTOR9                                                                            0x000a
+#define ixAUDIO_DESCRIPTOR10                                                                           0x000b
+#define ixAUDIO_DESCRIPTOR11                                                                           0x000c
+#define ixAUDIO_DESCRIPTOR12                                                                           0x000d
+#define ixAUDIO_DESCRIPTOR13                                                                           0x000e
+
+
+// addressBlock: azendpoint_sinkinfoind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID                                                  0x0000
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID                                                       0x0001
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN                                             0x0002
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0                                                          0x0003
+#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1                                                          0x0004
+#define ixSINK_DESCRIPTION0                                                                            0x0005
+#define ixSINK_DESCRIPTION1                                                                            0x0006
+#define ixSINK_DESCRIPTION2                                                                            0x0007
+#define ixSINK_DESCRIPTION3                                                                            0x0008
+#define ixSINK_DESCRIPTION4                                                                            0x0009
+#define ixSINK_DESCRIPTION5                                                                            0x000a
+#define ixSINK_DESCRIPTION6                                                                            0x000b
+#define ixSINK_DESCRIPTION7                                                                            0x000c
+#define ixSINK_DESCRIPTION8                                                                            0x000d
+#define ixSINK_DESCRIPTION9                                                                            0x000e
+#define ixSINK_DESCRIPTION10                                                                           0x000f
+#define ixSINK_DESCRIPTION11                                                                           0x0010
+#define ixSINK_DESCRIPTION12                                                                           0x0011
+#define ixSINK_DESCRIPTION13                                                                           0x0012
+#define ixSINK_DESCRIPTION14                                                                           0x0013
+#define ixSINK_DESCRIPTION15                                                                           0x0014
+#define ixSINK_DESCRIPTION16                                                                           0x0015
+#define ixSINK_DESCRIPTION17                                                                           0x0016
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC0_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC0_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC0_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC0_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC0_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC0_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC0_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC0_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+// base address: 0x0
+#define ixAZALIA_INPUT_CRC1_CHANNEL0                                                                   0x0000
+#define ixAZALIA_INPUT_CRC1_CHANNEL1                                                                   0x0001
+#define ixAZALIA_INPUT_CRC1_CHANNEL2                                                                   0x0002
+#define ixAZALIA_INPUT_CRC1_CHANNEL3                                                                   0x0003
+#define ixAZALIA_INPUT_CRC1_CHANNEL4                                                                   0x0004
+#define ixAZALIA_INPUT_CRC1_CHANNEL5                                                                   0x0005
+#define ixAZALIA_INPUT_CRC1_CHANNEL6                                                                   0x0006
+#define ixAZALIA_INPUT_CRC1_CHANNEL7                                                                   0x0007
+
+
+// addressBlock: azf0controller_azcrc0resultind
+// base address: 0x0
+#define ixAZALIA_CRC0_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC0_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC0_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC0_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC0_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC0_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC0_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC0_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azf0controller_azcrc1resultind
+// base address: 0x0
+#define ixAZALIA_CRC1_CHANNEL0                                                                         0x0000
+#define ixAZALIA_CRC1_CHANNEL1                                                                         0x0001
+#define ixAZALIA_CRC1_CHANNEL2                                                                         0x0002
+#define ixAZALIA_CRC1_CHANNEL3                                                                         0x0003
+#define ixAZALIA_CRC1_CHANNEL4                                                                         0x0004
+#define ixAZALIA_CRC1_CHANNEL5                                                                         0x0005
+#define ixAZALIA_CRC1_CHANNEL6                                                                         0x0006
+#define ixAZALIA_CRC1_CHANNEL7                                                                         0x0007
+
+
+// addressBlock: azinputendpoint_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                                     0x6200
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                                    0x6706
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                                    0x670d
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                          0x6f09
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                               0x6f0a
+#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                                     0x6f0b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                                             0x7707
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                                       0x7708
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE                                         0x7709
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                             0x771c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2                           0x771d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3                           0x771e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4                           0x771f
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                                         0x7771
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE                                       0x7777
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE                                       0x7778
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE                                       0x7779
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE                                       0x777a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR                                                        0x777c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE                                       0x7785
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE                                       0x7786
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE                                       0x7787
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE                                       0x7788
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                                      0x7798
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB                                                       0x7799
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                        0x779a
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                                       0x779b
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME                                                  0x779c
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L                                           0x779d
+#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H                                           0x779e
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                                0x7f09
+#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                                             0x7f0c
+
+
+// addressBlock: azroot_f2codecind
+// base address: 0x0
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID                                          0x0f00
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID                                                   0x0f02
+#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT                                        0x0f04
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE                                                 0x1705
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID                                       0x1720
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2                                     0x1721
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3                                     0x1722
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4                                     0x1723
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION                                   0x1770
+#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET                                                       0x17ff
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT                                    0x1f04
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE                                                0x1f05
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES                                      0x1f0a
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS                                            0x1f0b
+#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES                                              0x1f0f
+
+
+// addressBlock: azf0stream0_streamind
+// base address: 0x0
+#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream1_streamind
+// base address: 0x0
+#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream2_streamind
+// base address: 0x0
+#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream3_streamind
+// base address: 0x0
+#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream4_streamind
+// base address: 0x0
+#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream5_streamind
+// base address: 0x0
+#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream6_streamind
+// base address: 0x0
+#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream7_streamind
+// base address: 0x0
+#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream8_streamind
+// base address: 0x0
+#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream9_streamind
+// base address: 0x0
+#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL                                                         0x0000
+#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL                                                   0x0001
+#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT                                                   0x0002
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT                                                  0x0003
+#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT                                                  0x0004
+
+
+// addressBlock: azf0stream10_streamind
+// base address: 0x0
+#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream11_streamind
+// base address: 0x0
+#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream12_streamind
+// base address: 0x0
+#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream13_streamind
+// base address: 0x0
+#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream14_streamind
+// base address: 0x0
+#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0stream15_streamind
+// base address: 0x0
+#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL                                                        0x0000
+#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL                                                  0x0001
+#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT                                                  0x0002
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT                                                 0x0003
+#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT                                                 0x0004
+
+
+// addressBlock: azf0endpoint0_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint1_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint2_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint3_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint4_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint5_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint6_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0endpoint7_endpointind
+// base address: 0x0
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES                  0x0001
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT                             0x0002
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID                            0x0003
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER                            0x0004
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS                             0x0005
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES                       0x0006
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL                                       0x0007
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE                                    0x0008
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING                                0x0009
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA                                    0x000c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN                                0x000d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX                                0x000e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES                        0x0020
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES                                     0x0021
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE                               0x0022
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE                                 0x0023
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL                                     0x0024
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER                                    0x0025
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0                                  0x0028
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1                                  0x0029
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2                                  0x002a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3                                  0x002b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4                                  0x002c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5                                  0x002d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6                                  0x002e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7                                  0x002f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8                                  0x0030
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9                                  0x0031
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10                                 0x0032
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11                                 0x0033
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12                                 0x0034
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13                                 0x0035
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE                                0x0036
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC                                   0x0037
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR                                       0x0038
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0                                         0x003a
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1                                         0x003b
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2                                         0x003c
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3                                         0x003d
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4                                         0x003e
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5                                         0x003f
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6                                         0x0040
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7                                         0x0041
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8                                         0x0042
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL                                   0x0054
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE                         0x0055
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT                     0x0056
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2                               0x0057
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE                                  0x0058
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0                                      0x0059
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1                                      0x005a
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2                                      0x005b
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3                                      0x005c
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4                                      0x005d
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5                                      0x005e
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6                                      0x005f
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7                                      0x0060
+#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8                                      0x0061
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO                                           0x0062
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS                              0x0063
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                              0x0064
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB                                               0x0065
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                                0x0066
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE                                        0x0067
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED                                     0x0068
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION                    0x0069
+#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE                                   0x006a
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS                                                  0x006b
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS                                             0x006c
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS                                            0x006d
+#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS                                      0x006e
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+// base address: 0x0
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES       0x0001
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT                  0x0002
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID                 0x0003
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER                 0x0004
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS                  0x0005
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES            0x0006
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES             0x0020
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES                          0x0021
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE                    0x0022
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE                0x0023
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL                          0x0024
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE                     0x0036
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2                    0x0037
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR                            0x0038
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION                      0x0053
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL                        0x0054
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE              0x0055
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT          0x0056
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL                   0x0064
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB                                    0x0065
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT                     0x0066
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL                    0x0067
+#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME                               0x0068
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
new file mode 100644
index 000000000000..7b2e5833e345
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
@@ -0,0 +1,60747 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dcn_3_1_2_SH_MASK_HEADER
+#define _dcn_3_1_2_SH_MASK_HEADER
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//AZCONTROLLER0_GLOBAL_CAPABILITIES
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT                            0x0
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                        0x1
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT                   0x3
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT                           0x8
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT                          0xc
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK                              0x0001L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                          0x0006L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK                     0x00F8L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK                             0x0F00L
+#define AZCONTROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK                            0xF000L
+//AZCONTROLLER0_MINOR_VERSION
+#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION__SHIFT                                                     0x0
+#define AZCONTROLLER0_MINOR_VERSION__MINOR_VERSION_MASK                                                       0xFFL
+//AZCONTROLLER0_MAJOR_VERSION
+#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION__SHIFT                                                     0x0
+#define AZCONTROLLER0_MAJOR_VERSION__MAJOR_VERSION_MASK                                                       0xFFL
+//AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                             0x0
+#define AZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                               0xFFFFL
+//AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                               0x0
+#define AZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                 0xFFFFL
+//AZCONTROLLER0_GLOBAL_CONTROL
+#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT                                                 0x0
+#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT                                                    0x1
+#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT                               0x8
+#define AZCONTROLLER0_GLOBAL_CONTROL__CONTROLLER_RESET_MASK                                                   0x00000001L
+#define AZCONTROLLER0_GLOBAL_CONTROL__FLUSH_CONTROL_MASK                                                      0x00000002L
+#define AZCONTROLLER0_GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK                                 0x00000100L
+//AZCONTROLLER0_WAKE_ENABLE
+#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT                                               0x0
+#define AZCONTROLLER0_WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK                                                 0x0001L
+//AZCONTROLLER0_STATE_CHANGE_STATUS
+#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT                                         0x0
+#define AZCONTROLLER0_STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK                                           0x0001L
+//AZCONTROLLER0_GLOBAL_STATUS
+#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS__SHIFT                                                      0x1
+#define AZCONTROLLER0_GLOBAL_STATUS__FLUSH_STATUS_MASK                                                        0x00000002L
+//AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                     0x0
+#define AZCONTROLLER0_OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                       0xFFFFL
+//AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY
+#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                       0x0
+#define AZCONTROLLER0_INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                         0xFFFFL
+//AZCONTROLLER0_INTERRUPT_CONTROL
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT                                     0x0
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT                                     0x1
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT                                     0x2
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT                                     0x3
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT                                     0x4
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT                                     0x5
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT                                     0x6
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT                                     0x7
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT                                     0x8
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT                                     0x9
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT                                    0xa
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT                                    0xb
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT                                    0xc
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT                                    0xd
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT                                    0xe
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT                                    0xf
+#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT                                   0x1e
+#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT                                       0x1f
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK                                       0x00000001L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK                                       0x00000002L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK                                       0x00000004L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK                                       0x00000008L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK                                       0x00000010L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK                                       0x00000020L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK                                       0x00000040L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK                                       0x00000080L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK                                       0x00000100L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK                                       0x00000200L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK                                      0x00000400L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK                                      0x00000800L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK                                      0x00001000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK                                      0x00002000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK                                      0x00004000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK                                      0x00008000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK                                     0x40000000L
+#define AZCONTROLLER0_INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK                                         0x80000000L
+//AZCONTROLLER0_INTERRUPT_STATUS
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT                                      0x0
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT                                      0x1
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT                                      0x2
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT                                      0x3
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT                                      0x4
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT                                      0x5
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT                                      0x6
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT                                      0x7
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT                                      0x8
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT                                      0x9
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT                                     0xa
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT                                     0xb
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT                                     0xc
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT                                     0xd
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT                                     0xe
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT                                     0xf
+#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT                                    0x1e
+#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT                                        0x1f
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK                                        0x00000001L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK                                        0x00000004L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK                                        0x00000008L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK                                        0x00000010L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK                                        0x00000020L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK                                        0x00000040L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK                                        0x00000080L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK                                        0x00000100L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK                                        0x00000200L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK                                       0x00000400L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK                                       0x00000800L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK                                       0x00001000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK                                       0x00002000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK                                       0x00004000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK                                       0x00008000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK                                      0x40000000L
+#define AZCONTROLLER0_INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK                                          0x80000000L
+//AZCONTROLLER0_WALL_CLOCK_COUNTER
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT                                           0x0
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK                                             0xFFFFFFFFL
+//AZCONTROLLER0_STREAM_SYNCHRONIZATION
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT                                 0x0
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT                                 0x1
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT                                 0x2
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT                                 0x3
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT                                 0x4
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT                                 0x5
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT                                 0x6
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT                                 0x7
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT                                 0x8
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT                                 0x9
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT                                0xa
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT                                0xb
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT                                0xc
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT                                0xd
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT                                0xe
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT                                0xf
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK                                   0x00000001L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK                                   0x00000002L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK                                   0x00000004L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK                                   0x00000008L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK                                   0x00000010L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK                                   0x00000020L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK                                   0x00000040L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK                                   0x00000080L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK                                   0x00000100L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK                                   0x00000200L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK                                  0x00000400L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK                                  0x00000800L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK                                  0x00001000L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK                                  0x00002000L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK                                  0x00004000L
+#define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK                                  0x00008000L
+//AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT                                 0x7
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL
+#define AZCONTROLLER0_CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L
+//AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS
+#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT                                 0x0
+#define AZCONTROLLER0_CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL
+//AZCONTROLLER0_CORB_WRITE_POINTER
+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL
+//AZCONTROLLER0_CORB_READ_POINTER
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL
+#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L
+//AZCONTROLLER0_CORB_CONTROL
+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0
+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1
+#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L
+#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L
+//AZCONTROLLER0_CORB_STATUS
+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0
+#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L
+//AZCONTROLLER0_CORB_SIZE
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL
+#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L
+//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS
+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0
+#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL
+//AZCONTROLLER0_RIRB_WRITE_POINTER
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL
+#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L
+//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT
+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0
+#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL
+//AZCONTROLLER0_RIRB_CONTROL
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0
+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L
+#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L
+#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L
+//AZCONTROLLER0_RIRB_STATUS
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L
+#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L
+//AZCONTROLLER0_RIRB_SIZE
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L
+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL
+//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL
+//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0
+#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL
+//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L
+#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L
+//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL
+#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L
+//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS
+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0
+#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL
+//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0
+#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL
+//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0
+#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL
+//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0
+#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
+//VGA_MEM_WRITE_PAGE_ADDR
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT                                              0x0
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT                                              0x10
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK                                                0x000003FFL
+#define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK                                                0x03FF0000L
+//VGA_MEM_READ_PAGE_ADDR
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT                                                0x0
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT                                                0x10
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK                                                  0x000003FFL
+#define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK                                                  0x03FF0000L
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
+//CRTC8_IDX
+#define CRTC8_IDX__VCRTC_IDX__SHIFT                                                                           0x0
+#define CRTC8_IDX__VCRTC_IDX_MASK                                                                             0x3FL
+//CRTC8_DATA
+#define CRTC8_DATA__VCRTC_DATA__SHIFT                                                                         0x0
+#define CRTC8_DATA__VCRTC_DATA_MASK                                                                           0xFFL
+//GENFC_WT
+#define GENFC_WT__VSYNC_SEL_W__SHIFT                                                                          0x3
+#define GENFC_WT__VSYNC_SEL_W_MASK                                                                            0x08L
+//GENS1
+#define GENS1__NO_DISPLAY__SHIFT                                                                              0x0
+#define GENS1__VGA_VSTATUS__SHIFT                                                                             0x3
+#define GENS1__PIXEL_READ_BACK__SHIFT                                                                         0x4
+#define GENS1__NO_DISPLAY_MASK                                                                                0x01L
+#define GENS1__VGA_VSTATUS_MASK                                                                               0x08L
+#define GENS1__PIXEL_READ_BACK_MASK                                                                           0x30L
+//ATTRDW
+#define ATTRDW__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDW__ATTR_DATA_MASK                                                                                0xFFL
+//ATTRX
+#define ATTRX__ATTR_IDX__SHIFT                                                                                0x0
+#define ATTRX__ATTR_IDX_MASK                                                                                  0x1FL
+//ATTRDR
+#define ATTRDR__ATTR_DATA__SHIFT                                                                              0x0
+#define ATTRDR__ATTR_DATA_MASK                                                                                0xFFL
+//GENMO_WT
+#define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_WT__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_WT__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_WT__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_WT__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_WT__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_WT__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_WT__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_WT__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GENS0
+#define GENS0__SENSE_SWITCH__SHIFT                                                                            0x4
+#define GENS0__CRT_INTR__SHIFT                                                                                0x7
+#define GENS0__SENSE_SWITCH_MASK                                                                              0x10L
+#define GENS0__CRT_INTR_MASK                                                                                  0x80L
+//GENENB
+//SEQ8_IDX
+#define SEQ8_IDX__SEQ_IDX__SHIFT                                                                              0x0
+#define SEQ8_IDX__SEQ_IDX_MASK                                                                                0x07L
+//SEQ8_DATA
+#define SEQ8_DATA__SEQ_DATA__SHIFT                                                                            0x0
+#define SEQ8_DATA__SEQ_DATA_MASK                                                                              0xFFL
+//DAC_MASK
+#define DAC_MASK__DAC_MASK__SHIFT                                                                             0x0
+#define DAC_MASK__DAC_MASK_MASK                                                                               0xFFL
+//DAC_R_INDEX
+#define DAC_R_INDEX__DAC_R_INDEX__SHIFT                                                                       0x0
+#define DAC_R_INDEX__DAC_R_INDEX_MASK                                                                         0xFFL
+//DAC_W_INDEX
+#define DAC_W_INDEX__DAC_W_INDEX__SHIFT                                                                       0x0
+#define DAC_W_INDEX__DAC_W_INDEX_MASK                                                                         0xFFL
+//DAC_DATA
+#define DAC_DATA__DAC_DATA__SHIFT                                                                             0x0
+#define DAC_DATA__DAC_DATA_MASK                                                                               0x3FL
+//GENFC_RD
+#define GENFC_RD__VSYNC_SEL_R__SHIFT                                                                          0x3
+#define GENFC_RD__VSYNC_SEL_R_MASK                                                                            0x08L
+//GENMO_RD
+#define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT                                                                 0x0
+#define GENMO_RD__VGA_RAM_EN__SHIFT                                                                           0x1
+#define GENMO_RD__VGA_CKSEL__SHIFT                                                                            0x2
+#define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT                                                                    0x5
+#define GENMO_RD__VGA_HSYNC_POL__SHIFT                                                                        0x6
+#define GENMO_RD__VGA_VSYNC_POL__SHIFT                                                                        0x7
+#define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK                                                                   0x01L
+#define GENMO_RD__VGA_RAM_EN_MASK                                                                             0x02L
+#define GENMO_RD__VGA_CKSEL_MASK                                                                              0x0CL
+#define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK                                                                      0x20L
+#define GENMO_RD__VGA_HSYNC_POL_MASK                                                                          0x40L
+#define GENMO_RD__VGA_VSYNC_POL_MASK                                                                          0x80L
+//GRPH8_IDX
+#define GRPH8_IDX__GRPH_IDX__SHIFT                                                                            0x0
+#define GRPH8_IDX__GRPH_IDX_MASK                                                                              0x0FL
+//GRPH8_DATA
+#define GRPH8_DATA__GRPH_DATA__SHIFT                                                                          0x0
+#define GRPH8_DATA__GRPH_DATA_MASK                                                                            0xFFL
+//CRTC8_IDX_1
+#define CRTC8_IDX_1__VCRTC_IDX__SHIFT                                                                         0x0
+#define CRTC8_IDX_1__VCRTC_IDX_MASK                                                                           0x3FL
+//CRTC8_DATA_1
+#define CRTC8_DATA_1__VCRTC_DATA__SHIFT                                                                       0x0
+#define CRTC8_DATA_1__VCRTC_DATA_MASK                                                                         0xFFL
+//GENFC_WT_1
+#define GENFC_WT_1__VSYNC_SEL_W__SHIFT                                                                        0x3
+#define GENFC_WT_1__VSYNC_SEL_W_MASK                                                                          0x08L
+//GENS1_1
+#define GENS1_1__NO_DISPLAY__SHIFT                                                                            0x0
+#define GENS1_1__VGA_VSTATUS__SHIFT                                                                           0x3
+#define GENS1_1__PIXEL_READ_BACK__SHIFT                                                                       0x4
+#define GENS1_1__NO_DISPLAY_MASK                                                                              0x01L
+#define GENS1_1__VGA_VSTATUS_MASK                                                                             0x08L
+#define GENS1_1__PIXEL_READ_BACK_MASK                                                                         0x30L
+
+
+// addressBlock: dce_dc_hda_azcontroller_azdec
+//AZCONTROLLER1_CORB_WRITE_POINTER
+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK                                             0x00FFL
+//AZCONTROLLER1_CORB_READ_POINTER
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT                                             0x0
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT                                       0xf
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK                                               0x00FFL
+#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK                                         0x8000L
+//AZCONTROLLER1_CORB_CONTROL
+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT                                 0x0
+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT                                             0x1
+#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK                                   0x01L
+#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK                                               0x02L
+//AZCONTROLLER1_CORB_STATUS
+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT                                        0x0
+#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK                                          0x01L
+//AZCONTROLLER1_CORB_SIZE
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT                      0x0
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT                                 0x7
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK                        0x0000007FL
+#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK                                   0xFFFFFF80L
+//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS
+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT                                 0x0
+#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK                                   0xFFFFFFFFL
+//AZCONTROLLER1_RIRB_WRITE_POINTER
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT                                           0x0
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT                                     0xf
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK                                             0x00FFL
+#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK                                       0x8000L
+//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT
+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT                             0x0
+#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK                               0x00FFL
+//AZCONTROLLER1_RIRB_CONTROL
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT                                         0x0
+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                    0x1
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT                                 0x2
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK                                           0x01L
+#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                      0x02L
+#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK                                   0x04L
+//AZCONTROLLER1_RIRB_STATUS
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                  0x0
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT                                   0x2
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK                                                    0x01L
+#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK                                     0x04L
+//AZCONTROLLER1_RIRB_SIZE
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT                                                             0x0
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                  0x4
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK                                                               0x0003L
+#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                    0x00F0L
+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT     0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT        0x1c
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK       0x0FFFFFFFL
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK          0xF0000000L
+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT                 0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK                   0xFFFFFFFFL
+//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT                0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK                  0x0000FFFFL
+//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE
+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT                      0x0
+#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK                        0xFFFFFFFFL
+//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT                                 0x0
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT                                 0x1
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK                                   0x00000001L
+#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK                                   0x00000002L
+//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT                      0x0
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT      0x1
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT                 0x7
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK                        0x00000001L
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK        0x0000007EL
+#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK                   0xFFFFFF80L
+//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS
+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT                 0x0
+#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK                   0xFFFFFFFFL
+//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS
+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT                               0x0
+#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK                                 0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azendpoint_azdec
+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT        0x0
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK          0xFFFFFFFFL
+//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT       0x0
+#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK         0x0001FFFFL
+
+
+// addressBlock: dce_dc_hda_azinputendpoint_azdec
+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT    0x0
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK      0xFFFFFFFFL
+//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT   0x0
+#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK     0x0001FFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
+//DENTIST_DISPCLK_CNTL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT                                                 0x0
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT                                                 0x8
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT                                                 0xf
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT                                                   0x11
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT                                                  0x12
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT                                                 0x13
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT                                                  0x14
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT                                                    0x15
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT                                                   0x16
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT                                                  0x18
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK                                                   0x0000007FL
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK                                                   0x00007F00L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK                                                   0x00018000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK                                                     0x00020000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK                                                    0x00040000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK                                                   0x00080000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK                                                    0x00100000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK                                                      0x00200000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK                                                     0x00400000L
+#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK                                                    0x7F000000L
+
+
+// addressBlock: dce_dc_dccg_dccg_dispdec
+//PHYPLLA_PIXCLK_RESYNC_CNTL
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLB_PIXCLK_RESYNC_CNTL
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLC_PIXCLK_RESYNC_CNTL
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//PHYPLLD_PIXCLK_RESYNC_CNTL
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//DP_DTO_DBUF_EN
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT                                                                0x0
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT                                                                0x1
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT                                                                0x2
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT                                                                0x3
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT                                                                0x4
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT                                                                0x5
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT                                                                0x6
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT                                                                0x7
+#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK                                                                  0x00000001L
+#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK                                                                  0x00000002L
+#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK                                                                  0x00000004L
+#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK                                                                  0x00000008L
+#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK                                                                  0x00000010L
+#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK                                                                  0x00000020L
+#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK                                                                  0x00000040L
+#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK                                                                  0x00000080L
+//DPREFCLK_CGTT_BLK_CTRL_REG
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT                                             0x0
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT                                            0x4
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK                                               0x0000000FL
+#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK                                              0x00000FF0L
+//DCCG_GATE_DISABLE_CNTL4
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x0
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x1
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x2
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11
+#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L
+#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L
+#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L
+#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L
+#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L
+#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L
+//DPSTREAMCLK_CNTL
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE0_EN__SHIFT                                                         0x1
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE1_EN__SHIFT                                                         0x2
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE2_EN__SHIFT                                                         0x3
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE3_EN__SHIFT                                                         0x4
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE0_EN_MASK                                                           0x00000002L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE1_EN_MASK                                                           0x00000004L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE2_EN_MASK                                                           0x00000008L
+#define DPSTREAMCLK_CNTL__DPSTREAMCLK_PIPE3_EN_MASK                                                           0x00000010L
+//REFCLK_CGTT_BLK_CTRL_REG
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//PHYPLLE_PIXCLK_RESYNC_CNTL
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT                                       0x0
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT                               0x1
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT                                       0x4
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT                                              0x8
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT                                  0x9
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK                                         0x00000001L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK                                 0x00000002L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK                                         0x00000030L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK                                                0x00000100L
+#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE_MASK                                    0x00000200L
+//DCCG_PERFMON_CNTL2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT                                                    0x1
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT                                                   0x2
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT                                                   0x3
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT                                            0x4
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT                                            0x5
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT                                            0x6
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT                                            0x7
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT                                            0x8
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT                                                   0x9
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK                                                      0x00000002L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK                                                     0x00000004L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK                                                     0x00000008L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK                                              0x00000010L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK                                              0x00000020L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK                                              0x00000040L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK                                              0x00000080L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK                                              0x00000100L
+#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK                                                     0x00000200L
+//DCCG_DS_DTO_INCR
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR__SHIFT                                                             0x0
+#define DCCG_DS_DTO_INCR__DCCG_DS_DTO_INCR_MASK                                                               0xFFFFFFFFL
+//DCCG_DS_DTO_MODULO
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO__SHIFT                                                         0x0
+#define DCCG_DS_DTO_MODULO__DCCG_DS_DTO_MODULO_MASK                                                           0xFFFFFFFFL
+//DCCG_DS_CNTL
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE__SHIFT                                                                   0x0
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC__SHIFT                                                                  0x4
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE__SHIFT                                                            0x8
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS__SHIFT                                                           0x9
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV__SHIFT                                                          0x10
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS__SHIFT                                                        0x18
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL__SHIFT                                                           0x19
+#define DCCG_DS_CNTL__DCCG_DS_ENABLE_MASK                                                                     0x00000001L
+#define DCCG_DS_CNTL__DCCG_DS_REF_SRC_MASK                                                                    0x00000030L
+#define DCCG_DS_CNTL__DCCG_DS_HW_CAL_ENABLE_MASK                                                              0x00000100L
+#define DCCG_DS_CNTL__DCCG_DS_ENABLED_STATUS_MASK                                                             0x00000200L
+#define DCCG_DS_CNTL__DCCG_DS_XTALIN_RATE_DIV_MASK                                                            0x00030000L
+#define DCCG_DS_CNTL__DCCG_DS_JITTER_REMOVE_DIS_MASK                                                          0x01000000L
+#define DCCG_DS_CNTL__DCCG_DS_DELAY_XTAL_SEL_MASK                                                             0x02000000L
+//DCCG_DS_HW_CAL_INTERVAL
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL__SHIFT                                               0x0
+#define DCCG_DS_HW_CAL_INTERVAL__DCCG_DS_HW_CAL_INTERVAL_MASK                                                 0xFFFFFFFFL
+//DPREFCLK_CNTL
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT                                                                0x0
+#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK                                                                  0x00000007L
+//DCE_VERSION
+#define DCE_VERSION__MAJOR_VERSION__SHIFT                                                                     0x0
+#define DCE_VERSION__MINOR_VERSION__SHIFT                                                                     0x8
+#define DCE_VERSION__MAJOR_VERSION_MASK                                                                       0x000000FFL
+#define DCE_VERSION__MINOR_VERSION_MASK                                                                       0x0000FF00L
+//DCCG_GTC_CNTL
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT                                                                 0x0
+#define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK                                                                   0x00000001L
+//DCCG_GTC_DTO_INCR
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR__SHIFT                                                           0x0
+#define DCCG_GTC_DTO_INCR__DCCG_GTC_DTO_INCR_MASK                                                             0xFFFFFFFFL
+//DCCG_GTC_DTO_MODULO
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT                                                       0x0
+#define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK                                                         0xFFFFFFFFL
+//DCCG_GTC_CURRENT
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT                                                             0x0
+#define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK                                                               0xFFFFFFFFL
+//SYMCLK32_SE_CNTL
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT                                                         0x8
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT                                                              0xb
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT                                                         0xc
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT                                                              0xf
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK                                                                0x00000080L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK                                                           0x00000700L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK                                                                0x00000800L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK                                                           0x00007000L
+#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK                                                                0x00008000L
+//SYMCLK32_LE_CNTL
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT                                                         0x0
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT                                                              0x3
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT                                                         0x4
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT                                                              0x7
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK                                                           0x00000007L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK                                                                0x00000008L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK                                                           0x00000070L
+#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK                                                                0x00000080L
+//DSCCLK0_DTO_PARAM
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK1_DTO_PARAM
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DSCCLK2_DTO_PARAM
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//MILLISECOND_TIME_BASE_DIV
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK                                             0x0001FFFFL
+#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DISPCLK_FREQ_CHANGE_CNTL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT                                                   0x0
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT                                                    0x10
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT                                               0x14
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT                                            0x19
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT                                               0x1c
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT                                               0x1d
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT                                              0x1e
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT                                         0x1f
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK                                                     0x00003FFFL
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK                                                      0x000F0000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK                                                 0x00100000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK                                              0x0E000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK                                                 0x10000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK                                                 0x20000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK                                                0x40000000L
+#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK                                           0x80000000L
+//DC_MEM_GLOBAL_PWR_REQ_CNTL
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT                                          0x0
+#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK                                            0x00000001L
+//DCCG_PERFMON_CNTL
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT                                                    0x0
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT                                                   0x1
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT                                             0x2
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT                                             0x3
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT                                                    0x4
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT                                                               0x5
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT                                                        0x6
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT                                                        0x7
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT                                                           0x8
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV__SHIFT                                                  0xb
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK                                                      0x00000001L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK                                                     0x00000002L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK                                               0x00000004L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK                                               0x00000008L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK                                                      0x00000010L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK                                                                 0x00000020L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK                                                          0x00000040L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK                                                          0x00000080L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK                                                             0x00000700L
+#define DCCG_PERFMON_CNTL__DCCG_PERF_XTALIN_PULSE_DIV_MASK                                                    0xFFFFF800L
+//DCCG_GATE_DISABLE_CNTL
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT                                              0x0
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT                                            0x1
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT                                                    0x2
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT                                                  0x3
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT                                                   0x4
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT                                                   0x6
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT                                           0x8
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT                                                    0x9
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT                                                    0xb
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE__SHIFT                                                  0xc
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT                                                   0x11
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT                                                   0x12
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT                                                   0x13
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE__SHIFT                                              0x16
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT                                                    0x1a
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT                                              0x1b
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT                                                    0x1c
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT                                                   0x1d
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT                                                    0x1e
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK                                                0x00000001L
+#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK                                              0x00000002L
+#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK                                                      0x00000004L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK                                                    0x00000008L
+#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK                                                     0x00000010L
+#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK                                                     0x00000040L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK                                             0x00000100L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK                                                      0x00000200L
+#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK                                                      0x00000800L
+#define DCCG_GATE_DISABLE_CNTL__DMCUBCLK_GATE_DISABLE_MASK                                                    0x00001000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK                                                     0x00020000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK                                                     0x00040000L
+#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK                                                     0x00080000L
+#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GTC_GATE_DISABLE_MASK                                                0x00400000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK                                                      0x04000000L
+#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK                                                0x08000000L
+#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK                                                      0x10000000L
+#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK                                                     0x20000000L
+#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK                                                      0x40000000L
+//DISPCLK_CGTT_BLK_CTRL_REG
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT                                               0x0
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT                                              0x4
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK                                                 0x0000000FL
+#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK                                                0x00000FF0L
+//SOCCLK_CGTT_BLK_CTRL_REG
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_CAC_STATUS
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT                                                             0x0
+#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK                                                               0xFFFFFFFFL
+//MICROSECOND_TIME_BASE_DIV
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT                                           0x0
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT                                                        0x8
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT                                                        0x10
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT                                           0x11
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT                              0x14
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK                                             0x0000007FL
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK                                                          0x00007F00L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK                                                          0x00010000L
+#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK                                             0x00020000L
+#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK                                0x00100000L
+//DCCG_GATE_DISABLE_CNTL2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT                                               0x0
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT                                               0x1
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT                                               0x2
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT                                               0x3
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT                                               0x4
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT                                               0x5
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT                                               0x6
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT                                             0x8
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT                                             0xa
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT                                             0xc
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT                                                  0x10
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT                                                  0x11
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT                                                  0x12
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT                                                  0x13
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT                                                  0x14
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT                                                  0x15
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT                                                  0x16
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE__SHIFT                                               0x18
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE__SHIFT                                               0x19
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE__SHIFT                                               0x1a
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE__SHIFT                                               0x1b
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE__SHIFT                                               0x1c
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE__SHIFT                                               0x1d
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK                                                 0x00000001L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK                                                 0x00000002L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK                                                 0x00000004L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK                                                 0x00000008L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK                                                 0x00000010L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK                                                 0x00000020L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK                                                 0x00000040L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK                                               0x00000100L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK                                               0x00000400L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK                                               0x00001000L
+#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK                                                    0x00010000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK                                                    0x00020000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK                                                    0x00040000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK                                                    0x00080000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK                                                    0x00100000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK                                                    0x00200000L
+#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK                                                    0x00400000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_GATE_DISABLE_MASK                                                 0x01000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_GATE_DISABLE_MASK                                                 0x02000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_GATE_DISABLE_MASK                                                 0x04000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_GATE_DISABLE_MASK                                                 0x08000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_GATE_DISABLE_MASK                                                 0x10000000L
+#define DCCG_GATE_DISABLE_CNTL2__PHYFSYMCLK_GATE_DISABLE_MASK                                                 0x20000000L
+//SYMCLK_CGTT_BLK_CTRL_REG
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DCCG_DISP_CNTL_REG
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT                                                      0x8
+#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK                                                        0x00000100L
+//OTG0_PIXEL_RATE_CNTL
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE__SHIFT                                                       0x3
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT                                                           0x4
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT                                                       0x5
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_DIV__SHIFT                                                          0x1c
+#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_ENABLE_MASK                                                         0x00000008L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK                                                             0x00000010L
+#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLKDTO0_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG0_PIXEL_RATE_CNTL__DTBCLK_DTO0_DIV_MASK                                                            0xF0000000L
+//DP_DTO0_PHASE
+#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT                                                                   0x0
+#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO0_MODULO
+#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT                                                                 0x0
+#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG0_PHYPLL_PIXEL_RATE_CNTL
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG1_PIXEL_RATE_CNTL
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE__SHIFT                                                       0x3
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT                                                           0x4
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT                                                       0x5
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_DIV__SHIFT                                                          0x1c
+#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_ENABLE_MASK                                                         0x00000008L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK                                                             0x00000010L
+#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLKDTO1_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG1_PIXEL_RATE_CNTL__DTBCLK_DTO1_DIV_MASK                                                            0xF0000000L
+//DP_DTO1_PHASE
+#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT                                                                   0x0
+#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO1_MODULO
+#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT                                                                 0x0
+#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG1_PHYPLL_PIXEL_RATE_CNTL
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG2_PIXEL_RATE_CNTL
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE__SHIFT                                                       0x3
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT                                                           0x4
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT                                                       0x5
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_DIV__SHIFT                                                          0x1c
+#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_ENABLE_MASK                                                         0x00000008L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK                                                             0x00000010L
+#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLKDTO2_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG2_PIXEL_RATE_CNTL__DTBCLK_DTO2_DIV_MASK                                                            0xF0000000L
+//DP_DTO2_PHASE
+#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT                                                                   0x0
+#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO2_MODULO
+#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT                                                                 0x0
+#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG2_PHYPLL_PIXEL_RATE_CNTL
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//OTG3_PIXEL_RATE_CNTL
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT                                                   0x0
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE__SHIFT                                                       0x3
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT                                                           0x4
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT                                                       0x5
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS__SHIFT                                                 0x6
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT                                                     0x7
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL__SHIFT                                                           0x8
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL__SHIFT                                                          0x9
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN__SHIFT                                                0xb
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT                                                        0xc
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT                                                      0xe
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT                                                     0x10
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_DIV__SHIFT                                                          0x1c
+#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK                                                     0x00000003L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_ENABLE_MASK                                                         0x00000008L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK                                                             0x00000010L
+#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK                                                         0x00000020L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLKDTO3_ENABLE_STATUS_MASK                                                   0x00000040L
+#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK                                                       0x00000080L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_ADD_PIXEL_MASK                                                             0x00000100L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DROP_PIXEL_MASK                                                            0x00000200L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DISPOUT_HALF_RATE_EN_MASK                                                  0x00000800L
+#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK                                                          0x00001000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK                                                        0x0000C000L
+#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK                                                       0x0FFF0000L
+#define OTG3_PIXEL_RATE_CNTL__DTBCLK_DTO3_DIV_MASK                                                            0xF0000000L
+//DP_DTO3_PHASE
+#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT                                                                   0x0
+#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK                                                                     0xFFFFFFFFL
+//DP_DTO3_MODULO
+#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT                                                                 0x0
+#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK                                                                   0xFFFFFFFFL
+//OTG3_PHYPLL_PIXEL_RATE_CNTL
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT                                     0x0
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT                                        0x4
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK                                       0x00000007L
+#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK                                          0x00000010L
+//DPPCLK_CGTT_BLK_CTRL_REG
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT                                                 0x0
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT                                                0x4
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK                                                   0x0000000FL
+#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK                                                  0x00000FF0L
+//DPPCLK0_DTO_PARAM
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK1_DTO_PARAM
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK2_DTO_PARAM
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK                                                            0x00FF0000L
+//DPPCLK3_DTO_PARAM
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT                                                           0x0
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT                                                          0x10
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK                                                             0x000000FFL
+#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK                                                            0x00FF0000L
+//DCCG_CAC_STATUS2
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT                                                           0x0
+#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK                                                             0x0007FFFFL
+//SYMCLKA_CLOCK_ENABLE
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKB_CLOCK_ENABLE
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKC_CLOCK_ENABLE
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKD_CLOCK_ENABLE
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK                                                       0x00000700L
+//SYMCLKE_CLOCK_ENABLE
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT                                                     0x0
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT                                                      0x4
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT                                                     0x8
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK                                                       0x00000001L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK                                                        0x00000010L
+#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK                                                       0x00000700L
+//DCCG_SOFT_RESET
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT                                                             0x0
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT                                                                0x2
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT                                                                0x3
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT                                                     0x4
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT                                                           0x8
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT                                                             0xc
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT                                                             0xd
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xe
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0xf
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x10
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x11
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x12
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x13
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x14
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT                                                       0x15
+#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK                                                               0x00000001L
+#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK                                                                  0x00000004L
+#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK                                                                  0x00000008L
+#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK                                                       0x00000010L
+#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK                                                             0x00000100L
+#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK                                                               0x00001000L
+#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK                                                               0x00002000L
+#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00004000L
+#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00008000L
+#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00010000L
+#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00020000L
+#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00040000L
+#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00080000L
+#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00100000L
+#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK                                                         0x00200000L
+//DSCCLK_DTO_CTRL
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE__SHIFT                                                            0x1
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE__SHIFT                                                            0x2
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE__SHIFT                                                            0x3
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE__SHIFT                                                            0x4
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE__SHIFT                                                            0x5
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT                                                             0x8
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT                                                             0x9
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT                                                             0xa
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT                                                             0xb
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT                                                             0xc
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT                                                             0xd
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_ENABLE_MASK                                                              0x00000002L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_ENABLE_MASK                                                              0x00000004L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_ENABLE_MASK                                                              0x00000008L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_ENABLE_MASK                                                              0x00000010L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_ENABLE_MASK                                                              0x00000020L
+#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK                                                               0x00000100L
+#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK                                                               0x00000200L
+#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK                                                               0x00000400L
+#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK                                                               0x00000800L
+#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK                                                               0x00001000L
+#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK                                                               0x00002000L
+//DCCG_AUDIO_DTO_SOURCE
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT                                              0x0
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT                                                      0x4
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT                                          0x14
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT                                          0x18
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT                                          0x1c
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO__SHIFT                                    0x1d
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK                                                0x00000007L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK                                                        0x00000070L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK                                            0x00100000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK                                            0x01000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK                                            0x10000000L
+#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTBCLK_DTO_USE_512FBR_DTO_MASK                                      0x20000000L
+//DCCG_AUDIO_DTO0_PHASE
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO0_MODULE
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_PHASE
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT                                                   0x0
+#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK                                                     0xFFFFFFFFL
+//DCCG_AUDIO_DTO1_MODULE
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT                                                 0x0
+#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK                                                   0xFFFFFFFFL
+//DCCG_VSYNC_OTG0_LATCH_VALUE
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG1_LATCH_VALUE
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG2_LATCH_VALUE
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG3_LATCH_VALUE
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG4_LATCH_VALUE
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DCCG_VSYNC_OTG5_LATCH_VALUE
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT                                   0x0
+#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK                                     0xFFFFFFFFL
+//DPPCLK_DTO_CTRL
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE__SHIFT                                                            0x0
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT                                                             0x1
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE__SHIFT                                                            0x4
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT                                                             0x5
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE__SHIFT                                                            0x8
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT                                                             0x9
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE__SHIFT                                                            0xc
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT                                                             0xd
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE__SHIFT                                                            0x10
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT                                                             0x11
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE__SHIFT                                                            0x14
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT                                                             0x15
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_ENABLE_MASK                                                              0x00000001L
+#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK                                                               0x00000002L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_ENABLE_MASK                                                              0x00000010L
+#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK                                                               0x00000020L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_ENABLE_MASK                                                              0x00000100L
+#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK                                                               0x00000200L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_ENABLE_MASK                                                              0x00001000L
+#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK                                                               0x00002000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_ENABLE_MASK                                                              0x00010000L
+#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK                                                               0x00020000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_ENABLE_MASK                                                              0x00100000L
+#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK                                                               0x00200000L
+//DCCG_VSYNC_CNT_CTRL
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT                                                     0x0
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT                                                   0x2
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT                                                  0x3
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT                                               0x4
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT                                                  0x8
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT                                                  0x10
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT                                                  0x11
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT                                                  0x12
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT                                                  0x13
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT                                                  0x14
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT                                                  0x15
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT                                            0x18
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT                                            0x19
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT                                            0x1a
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT                                            0x1b
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT                                            0x1c
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT                                            0x1d
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK                                                       0x00000001L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK                                                     0x00000004L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK                                                    0x00000008L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK                                                 0x000000F0L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK                                                    0x00000F00L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK                                                    0x00010000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK                                                    0x00020000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK                                                    0x00040000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK                                                    0x00080000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK                                                    0x00100000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK                                                    0x00200000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK                                              0x01000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK                                              0x02000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK                                              0x04000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK                                              0x08000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK                                              0x10000000L
+#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK                                              0x20000000L
+//DCCG_VSYNC_CNT_INT_CTRL
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT                                   0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT                             0x0
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT                                   0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT                             0x1
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT                                   0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT                             0x2
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT                                   0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT                             0x3
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT                                   0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT                             0x4
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT                                   0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT                             0x5
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT                                        0x8
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT                                        0x9
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT                                        0xa
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT                                        0xb
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT                                        0xc
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT                                        0xd
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK                                     0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK                               0x00000001L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK                                     0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK                               0x00000002L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK                                     0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK                               0x00000004L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK                                     0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK                               0x00000008L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK                                     0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK                               0x00000010L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK                                     0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK                               0x00000020L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK                                          0x00000100L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK                                          0x00000200L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK                                          0x00000400L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK                                          0x00000800L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK                                          0x00001000L
+#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK                                          0x00002000L
+//FORCE_SYMCLK_DISABLE
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT                                                    0x0
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT                                                    0x1
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT                                                    0x2
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT                                                    0x3
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT                                                    0x4
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT                                                    0x5
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT                                                    0x6
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK                                                      0x00000001L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK                                                      0x00000002L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK                                                      0x00000004L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK                                                      0x00000008L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK                                                      0x00000010L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK                                                      0x00000020L
+#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK                                                      0x00000040L
+//DTBCLK_DTO0_PHASE
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO0_PHASE__DTBCLK_DTO0_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO1_PHASE
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO1_PHASE__DTBCLK_DTO1_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO2_PHASE
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO2_PHASE__DTBCLK_DTO2_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO3_PHASE
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE__SHIFT                                                           0x0
+#define DTBCLK_DTO3_PHASE__DTBCLK_DTO3_PHASE_MASK                                                             0xFFFFFFFFL
+//DTBCLK_DTO0_MODULO
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO0_MODULO__DTBCLK_DTO0_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO1_MODULO
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO1_MODULO__DTBCLK_DTO1_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO2_MODULO
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO2_MODULO__DTBCLK_DTO2_MODULO_MASK                                                           0xFFFFFFFFL
+//DTBCLK_DTO3_MODULO
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO__SHIFT                                                         0x0
+#define DTBCLK_DTO3_MODULO__DTBCLK_DTO3_MODULO_MASK                                                           0xFFFFFFFFL
+//PHYASYMCLK_CLOCK_CNTL
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYBSYMCLK_CLOCK_CNTL
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYCSYMCLK_CLOCK_CNTL
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYDSYMCLK_CLOCK_CNTL
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//PHYESYMCLK_CLOCK_CNTL
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN__SHIFT                                                     0x0
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL__SHIFT                                                0x4
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_EN_MASK                                                       0x00000001L
+#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_FORCE_SRC_SEL_MASK                                                  0x00000030L
+//DCCG_GATE_DISABLE_CNTL3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT                                           0x0
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT                                           0x1
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT                                           0x2
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT                                           0x3
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT                                           0x4
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT                                           0x5
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_ROOT_GATE_DISABLE__SHIFT                                         0x6
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_GATE_DISABLE__SHIFT                                              0x7
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT                                        0x8
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT                                             0x9
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT                                        0xa
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT                                             0xb
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT                                        0xc
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT                                             0xd
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT                                        0xe
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT                                             0xf
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT                                        0x14
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT                                             0x15
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT                                        0x16
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT                                             0x17
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK                                             0x00000001L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK                                             0x00000002L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK                                             0x00000004L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK                                             0x00000008L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK                                             0x00000010L
+#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK                                             0x00000020L
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_ROOT_GATE_DISABLE_MASK                                           0x00000040L
+#define DCCG_GATE_DISABLE_CNTL3__DPSTREAMCLK_GATE_DISABLE_MASK                                                0x00000080L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK                                          0x00000100L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK                                               0x00000200L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK                                          0x00000400L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK                                               0x00000800L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK                                          0x00001000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK                                               0x00002000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK                                          0x00004000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK                                               0x00008000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK                                          0x00100000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L
+#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L
+//DCCG_AUDIO_DTBCLK_DTO_PHASE
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0
+#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL
+//DCCG_AUDIO_DTBCLK_DTO_MODULO
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO__SHIFT                                     0x0
+#define DCCG_AUDIO_DTBCLK_DTO_MODULO__DCCG_AUDIO_DTBCLK_DTO_MODULO_MASK                                       0xFFFFFFFFL
+//DTBCLK_DTO_DBUF_EN
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN__SHIFT                                                        0x0
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN__SHIFT                                                        0x1
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN__SHIFT                                                        0x2
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN__SHIFT                                                        0x3
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO0_DBUF_EN_MASK                                                          0x00000001L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO1_DBUF_EN_MASK                                                          0x00000002L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO2_DBUF_EN_MASK                                                          0x00000004L
+#define DTBCLK_DTO_DBUF_EN__DTBCLK_DTO3_DBUF_EN_MASK                                                          0x00000008L
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
+//DC_PERFMON0_PERFCOUNTER_CNTL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_CNTL2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON0_PERFCOUNTER_STATE
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON0_PERFMON_CNTL
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON0_PERFMON_CNTL2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON0_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON0_PERFMON_CVALUE_LOW
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON0_PERFMON_HI
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON0_PERFMON_LOW
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
+//DC_PERFMON1_PERFCOUNTER_CNTL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_CNTL2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON1_PERFCOUNTER_STATE
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON1_PERFMON_CNTL
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON1_PERFMON_CNTL2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON1_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON1_PERFMON_CVALUE_LOW
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON1_PERFMON_HI
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON1_PERFMON_LOW
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_dmcu_dispdec
+//DMCU_CTRL
+#define DMCU_CTRL__RESET_UC__SHIFT                                                                            0x0
+#define DMCU_CTRL__IGNORE_PWRMGT__SHIFT                                                                       0x1
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT                                                                   0x2
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT                                                                  0x3
+#define DMCU_CTRL__DMCU_ENABLE__SHIFT                                                                         0x4
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN__SHIFT                                                              0x8
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT                                                                   0x10
+#define DMCU_CTRL__RESET_UC_MASK                                                                              0x00000001L
+#define DMCU_CTRL__IGNORE_PWRMGT_MASK                                                                         0x00000002L
+#define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK                                                                     0x00000004L
+#define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK                                                                    0x00000008L
+#define DMCU_CTRL__DMCU_ENABLE_MASK                                                                           0x00000010L
+#define DMCU_CTRL__DMCU_DYN_CLK_GATING_EN_MASK                                                                0x00000100L
+#define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK                                                                     0xFFFF0000L
+//DMCU_STATUS
+#define DMCU_STATUS__UC_IN_RESET__SHIFT                                                                       0x0
+#define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT                                                                   0x1
+#define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT                                                                   0x2
+#define DMCU_STATUS__UC_IN_RESET_MASK                                                                         0x00000001L
+#define DMCU_STATUS__UC_IN_WAIT_MODE_MASK                                                                     0x00000002L
+#define DMCU_STATUS__UC_IN_STOP_MODE_MASK                                                                     0x00000004L
+//DMCU_PC_START_ADDR
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_START_ADDR
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT                                                          0x0
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT                                                          0x8
+#define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK                                                            0x000000FFL
+#define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK                                                            0x0000FF00L
+//DMCU_FW_END_ADDR
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT                                                              0x0
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT                                                              0x8
+#define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK                                                                0x000000FFL
+#define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK                                                                0x0000FF00L
+//DMCU_FW_ISR_START_ADDR
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT                                                  0x0
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT                                                  0x8
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK                                                    0x000000FFL
+#define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK                                                    0x0000FF00L
+//DMCU_FW_CS_HI
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT                                                                  0x0
+#define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK                                                                    0xFFFFFFFFL
+//DMCU_FW_CS_LO
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT                                                                  0x0
+#define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK                                                                    0xFFFFFFFFL
+//DMCU_RAM_ACCESS_CTRL
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x0
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x1
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT                                                    0x2
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT                                                    0x3
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT                                                      0x4
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT                                                      0x5
+#define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000001L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000002L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK                                                      0x00000004L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK                                                      0x00000008L
+#define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK                                                        0x00000010L
+#define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK                                                        0x00000020L
+//DMCU_ERAM_WR_CTRL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_WR_DATA
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_ERAM_RD_CTRL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT                                                                  0x10
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT                                                           0x14
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK                                                                  0x0000FFFFL
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK                                                                    0x000F0000L
+#define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK                                                             0x00100000L
+//DMCU_ERAM_RD_DATA
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK                                                                  0xFFFFFFFFL
+//DMCU_IRAM_WR_CTRL
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_WR_DATA
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK                                                                  0x000000FFL
+//DMCU_IRAM_RD_CTRL
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK                                                                  0x000003FFL
+//DMCU_IRAM_RD_DATA
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT                                                                0x0
+#define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK                                                                  0x000000FFL
+//DMCU_EVENT_TRIGGER
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT                                                           0x0
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT                                                       0x10
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT                                                0x17
+#define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK                                                             0x00000001L
+#define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK                                                         0x007F0000L
+#define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK                                                  0x00800000L
+//DMCU_UC_INTERNAL_INT_STATUS
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT                                                  0x0
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT                                                 0x1
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT                                         0x2
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT                                        0x3
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT                                     0x4
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT                                     0x5
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT                                     0x6
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT                                     0x7
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT                                             0x8
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT                                        0x9
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT                     0xa
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT                                      0xb
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT                                      0xc
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT                                      0xd
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT                               0xe
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT                                 0xf
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK                                                    0x00000001L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK                                                   0x00000002L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK                                           0x00000004L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK                                          0x00000008L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK                                       0x00000010L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK                                       0x00000020L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK                                       0x00000040L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK                                       0x00000080L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK                                               0x00000100L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK                                          0x00000200L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK                       0x00000400L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK                                        0x00000800L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK                                        0x00001000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK                                        0x00002000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK                                 0x00004000L
+#define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK                                   0x00008000L
+//DMCU_SS_INTERRUPT_CNTL_STATUS
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS__SHIFT                                       0xd
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED__SHIFT                                     0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR__SHIFT                                        0xe
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS__SHIFT                                       0xf
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED__SHIFT                                     0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR__SHIFT                                        0x10
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS__SHIFT                                       0x11
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED__SHIFT                                     0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR__SHIFT                                        0x12
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS__SHIFT                                       0x13
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED__SHIFT                                     0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR__SHIFT                                        0x14
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS__SHIFT                                       0x15
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED__SHIFT                                     0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR__SHIFT                                        0x16
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS__SHIFT                                       0x17
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED__SHIFT                                     0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR__SHIFT                                        0x18
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_STATUS_MASK                                         0x00002000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_OCCURRED_MASK                                       0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN1_INT_CLEAR_MASK                                          0x00004000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_STATUS_MASK                                         0x00008000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_OCCURRED_MASK                                       0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN2_INT_CLEAR_MASK                                          0x00010000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_STATUS_MASK                                         0x00020000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_OCCURRED_MASK                                       0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN3_INT_CLEAR_MASK                                          0x00040000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_STATUS_MASK                                         0x00080000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_OCCURRED_MASK                                       0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN4_INT_CLEAR_MASK                                          0x00100000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_STATUS_MASK                                         0x00200000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_OCCURRED_MASK                                       0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN5_INT_CLEAR_MASK                                          0x00400000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_STATUS_MASK                                         0x00800000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_OCCURRED_MASK                                       0x01000000L
+#define DMCU_SS_INTERRUPT_CNTL_STATUS__STATIC_SCREEN6_INT_CLEAR_MASK                                          0x01000000L
+//DMCU_INTERRUPT_STATUS
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT                                              0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT                                                 0x0
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT                                              0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT                                                 0x1
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT                                             0x2
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT                                                0x2
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT                                                        0x3
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT                                                0x8
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT                                                   0x8
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT                                                        0x9
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT                                                0xa
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT                                                   0xa
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT                                          0xb
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT                                             0xb
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                  0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                     0xc
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                  0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                     0xd
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                  0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                     0xe
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                  0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                     0xf
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED__SHIFT                                  0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR__SHIFT                                     0x10
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED__SHIFT                                  0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR__SHIFT                                     0x11
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                   0x12
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                   0x13
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                   0x14
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                   0x15
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED__SHIFT                                0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR__SHIFT                                   0x16
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED__SHIFT                                0x17
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR__SHIFT                                   0x17
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT                                                    0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT                                                       0x18
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT                                                    0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT                                                       0x19
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT                                                    0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT                                                       0x1a
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT                                                    0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT                                                       0x1b
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT                                                    0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT                                                       0x1c
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT                                                    0x1d
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT                                                       0x1d
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK                                                0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK                                                   0x00000001L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK                                                0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK                                                   0x00000002L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK                                               0x00000004L
+#define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK                                                  0x00000004L
+#define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK                                                          0x00000008L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK                                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK                                                     0x00000100L
+#define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK                                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK                                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK                                                     0x00000400L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK                                            0x00000800L
+#define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK                                               0x00000800L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                    0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_UP_INT_CLEAR_MASK                                       0x00001000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                    0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_UP_INT_CLEAR_MASK                                       0x00002000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                    0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_UP_INT_CLEAR_MASK                                       0x00004000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                    0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_UP_INT_CLEAR_MASK                                       0x00008000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_OCCURRED_MASK                                    0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_UP_INT_CLEAR_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_OCCURRED_MASK                                    0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_UP_INT_CLEAR_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                  0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                     0x00040000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                  0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                     0x00080000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                  0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                     0x00100000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                  0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                     0x00200000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_OCCURRED_MASK                                  0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_CLEAR_MASK                                     0x00400000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_OCCURRED_MASK                                  0x00800000L
+#define DMCU_INTERRUPT_STATUS__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_CLEAR_MASK                                     0x00800000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK                                                      0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK                                                         0x01000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK                                                      0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK                                                         0x02000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK                                                      0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK                                                         0x04000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK                                                      0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK                                                         0x08000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK                                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK                                                         0x10000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK                                                      0x20000000L
+#define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK                                                         0x20000000L
+//DMCU_INTERRUPT_STATUS_1
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x6
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x7
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x8
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0x9
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xa
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED__SHIFT                                     0xb
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR__SHIFT                                        0xb
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED__SHIFT                                       0xd
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR__SHIFT                                          0xd
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED__SHIFT                                            0xe
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR__SHIFT                                               0xe
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED__SHIFT                                            0xf
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR__SHIFT                                               0xf
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED__SHIFT                                           0x10
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR__SHIFT                                              0x10
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED__SHIFT                                           0x13
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR__SHIFT                                              0x13
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG0_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG1_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG2_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG3_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG4_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000400L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_OCCURRED_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__OTG5_RANGE_TIMING_UPDATE_CLEAR_MASK                                          0x00000800L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_OCCURRED_MASK                                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__DMCU_GENERIC_INTERRUPT_CLEAR_MASK                                            0x00002000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_OCCURRED_MASK                                              0x00004000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_HG_READY_INT_CLEAR_MASK                                                 0x00004000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_OCCURRED_MASK                                              0x00008000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_LS_READY_INT_CLEAR_MASK                                                 0x00008000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_OCCURRED_MASK                                             0x00010000L
+#define DMCU_INTERRUPT_STATUS_1__ABM2_BL_UPDATE_INT_CLEAR_MASK                                                0x00010000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_HG_READY_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_LS_READY_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_OCCURRED_MASK                                             0x00080000L
+#define DMCU_INTERRUPT_STATUS_1__ABM3_BL_UPDATE_INT_CLEAR_MASK                                                0x00080000L
+//DMCU_INTERRUPT_TO_HOST_EN_MASK
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK__SHIFT                                         0x0
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK__SHIFT                                         0x1
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK__SHIFT                                        0x2
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT                                         0x3
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT                                         0x4
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT                                        0x5
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT                                                   0x9
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT                                           0xa
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT                                     0xb
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK__SHIFT                                         0xc
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK__SHIFT                                         0xd
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK__SHIFT                                        0xe
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK__SHIFT                                         0xf
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK__SHIFT                                         0x10
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK__SHIFT                                        0x11
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_HG_READY_INT_MASK_MASK                                           0x00000001L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_LS_READY_INT_MASK_MASK                                           0x00000002L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM0_BL_UPDATE_INT_MASK_MASK                                          0x00000004L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK                                           0x00000008L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK                                           0x00000010L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK                                          0x00000020L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK                                                     0x00000200L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK                                             0x00000400L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK                                       0x00000800L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_HG_READY_INT_MASK_MASK                                           0x00001000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_LS_READY_INT_MASK_MASK                                           0x00002000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM2_BL_UPDATE_INT_MASK_MASK                                          0x00004000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_HG_READY_INT_MASK_MASK                                           0x00008000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_LS_READY_INT_MASK_MASK                                           0x00010000L
+#define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM3_BL_UPDATE_INT_MASK_MASK                                          0x00020000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT                                       0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT                                       0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT                                      0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT                                                 0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN__SHIFT                                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN__SHIFT                                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT                                         0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN__SHIFT                                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN__SHIFT                                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN__SHIFT                                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN__SHIFT                           0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN__SHIFT                           0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN__SHIFT                           0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN__SHIFT                           0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN__SHIFT                           0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN__SHIFT                           0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN__SHIFT                         0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT                                             0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT                                             0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT                                             0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT                                             0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT                                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT                                             0x1d
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN__SHIFT                                      0x1e
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK                                         0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK                                         0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK                                        0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK                                                   0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN1_INT_TO_UC_EN_MASK                                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN2_INT_TO_UC_EN_MASK                                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK                                           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN3_INT_TO_UC_EN_MASK                                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN4_INT_TO_UC_EN_MASK                                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN5_INT_TO_UC_EN_MASK                                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_UP_INT_TO_UC_EN_MASK                             0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_UP_INT_TO_UC_EN_MASK                             0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_UP_INT_TO_UC_EN_MASK                             0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_UP_INT_TO_UC_EN_MASK                             0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_UP_INT_TO_UC_EN_MASK                             0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_UP_INT_TO_UC_EN_MASK                             0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_TO_UC_EN_MASK                           0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK                                               0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK                                               0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK                                               0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK                                               0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK                                               0x10000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK                                               0x20000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK__STATIC_SCREEN6_INT_TO_UC_EN_MASK                                        0x40000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN__SHIFT                          0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN__SHIFT                                      0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN__SHIFT                                     0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN__SHIFT                                     0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN__SHIFT                                    0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN__SHIFT                                    0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG0_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG1_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG2_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG3_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG4_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__OTG5_RANGE_TIMING_UPDATE_INT_TO_UC_EN_MASK                            0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__DMCU_GENERIC_INT_TO_UC_EN_MASK                                        0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_HG_READY_INT_TO_UC_EN_MASK                                       0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_LS_READY_INT_TO_UC_EN_MASK                                       0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM2_BL_UPDATE_INT_TO_UC_EN_MASK                                      0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_HG_READY_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_LS_READY_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_1__ABM3_BL_UPDATE_INT_TO_UC_EN_MASK                                      0x00080000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                              0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                             0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT                                        0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL__SHIFT                             0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL__SHIFT                             0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT                                0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL__SHIFT                             0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL__SHIFT                             0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL__SHIFT                             0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT                  0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT                0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT                                    0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT                                    0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT                                    0x1d
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL__SHIFT                             0x1e
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK                                0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                               0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK                                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN1_INT_XIRQ_IRQ_SEL_MASK                               0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN2_INT_XIRQ_IRQ_SEL_MASK                               0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN3_INT_XIRQ_IRQ_SEL_MASK                               0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN4_INT_XIRQ_IRQ_SEL_MASK                               0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN5_INT_XIRQ_IRQ_SEL_MASK                               0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK                    0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DOMAIN5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK                  0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK                                      0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK                                      0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK                                      0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK                                      0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK                                      0x20000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__STATIC_SCREEN6_INT_XIRQ_IRQ_SEL_MASK                               0x40000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                 0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL__SHIFT                             0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                           0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                            0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                           0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG0_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG1_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG2_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG3_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG4_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__OTG5_RANGE_TIMING_UPDATE_INT_XIRQ_IRQ_SEL_MASK                   0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__DMCU_GENERIC_INT_XIRQ_IRQ_SEL_MASK                               0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_HG_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_LS_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM2_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                             0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_HG_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_LS_READY_INT_XIRQ_IRQ_SEL_MASK                              0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1__ABM3_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                             0x00080000L
+//DC_DMCU_SCRATCH
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT                                                                  0x0
+#define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK                                                                    0xFFFFFFFFL
+//DMCU_INT_CNT
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT                                                       0x0
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT                                                       0x8
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT                                                      0x10
+#define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK                                                         0x000000FFL
+#define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK                                                         0x0000FF00L
+#define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK                                                        0x00FF0000L
+//DMCU_FW_CHECKSUM_SMPL_BYTE_POS
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT                              0x0
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT                              0x2
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK                                0x00000003L
+#define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK                                0x0000000CL
+//DMCU_UC_CLK_GATING_CNTL
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT                                                      0x0
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT                                                      0x8
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT                                              0x10
+#define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK                                                        0x00000007L
+#define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK                                                        0x00000700L
+#define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK                                                0x00010000L
+//MASTER_COMM_DATA_REG1
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG2
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_DATA_REG3
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT                                             0x0
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT                                             0x8
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT                                             0x10
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT                                             0x18
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK                                               0x000000FFL
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK                                               0x0000FF00L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK                                               0x00FF0000L
+#define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK                                               0xFF000000L
+//MASTER_COMM_CMD_REG
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT                                                 0x0
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT                                                 0x8
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT                                                 0x10
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT                                                 0x18
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK                                                   0x000000FFL
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK                                                   0x0000FF00L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK                                                   0x00FF0000L
+#define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK                                                   0xFF000000L
+//MASTER_COMM_CNTL_REG
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT                                                    0x0
+#define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK                                                      0x00000001L
+//SLAVE_COMM_DATA_REG1
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG2
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_DATA_REG3
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT                                               0x0
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT                                               0x8
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT                                               0x10
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT                                               0x18
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK                                                 0x000000FFL
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK                                                 0x0000FF00L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK                                                 0x00FF0000L
+#define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK                                                 0xFF000000L
+//SLAVE_COMM_CMD_REG
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT                                                   0x0
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT                                                   0x8
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT                                                   0x10
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT                                                   0x18
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK                                                     0x000000FFL
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK                                                     0x0000FF00L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK                                                     0x00FF0000L
+#define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK                                                     0xFF000000L
+//SLAVE_COMM_CNTL_REG
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT                                                      0x0
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT                                         0x8
+#define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK                                                        0x00000001L
+#define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK                                           0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DMU_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DIO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__DCCG_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS1__HPO_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
+//DMCU_PERFMON_INTERRUPT_STATUS2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                            0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                               0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP0_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP1_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP2_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP3_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP4_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP5_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP6_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBP7_PERFMON_COUNTER_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                              0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS2__HUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                                 0x00000100L
+//DMCU_PERFMON_INTERRUPT_STATUS3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP6_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS3__DPP7_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+//DMCU_PERFMON_INTERRUPT_STATUS4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED__SHIFT                             0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR__SHIFT                                0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED__SHIFT                          0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR__SHIFT                             0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB0_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB1_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_OCCURRED_MASK                               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__DCCG_PERFMON2_COUNTER_INT_CLEAR_MASK                                  0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_OCCURRED_MASK                            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__MMHUBBUB_PERFMON_COUNTER_INT_CLEAR_MASK                               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS4__WB2_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000010L
+//DMCU_PERFMON_INTERRUPT_STATUS5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x2
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x6
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x7
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x8
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__MPC_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPP_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__OPTC_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000004L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__HDA_PERFMON_COUNTER_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC0_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC1_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC2_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000040L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC3_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000080L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC4_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000100L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_PERFMON_INTERRUPT_STATUS5__DSC5_PERFMON_COUNTER_INT_CLEAR_MASK                                   0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__HPO_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DMU_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DIO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__DCCG_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1__HPO_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                     0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2__HUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                       0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP6_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3__DPP7_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN__SHIFT                      0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                   0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__DCCG_PERFMON2_COUNTER_INT_TO_UC_EN_MASK                        0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__MMHUBBUB_PERFMON_COUNTER_INT_TO_UC_EN_MASK                     0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4__WB2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__MPC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPP_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__OPTC_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__HDA_PERFMON_COUNTER_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC0_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC1_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC2_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC3_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC4_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5__DSC5_PERFMON_COUNTER_INT_TO_UC_EN_MASK                         0x00000200L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DMU_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DIO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DCCG_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__HPO_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT            0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2__HUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK              0x00000100L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP6_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3__DPP7_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT             0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT          0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__DCCG_PERFMON2_COUNTER_INT_XIRQ_IRQ_SEL_MASK               0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__MMHUBBUB_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK            0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4__WB2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000010L
+//DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x0
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x1
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x2
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT               0x3
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x6
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x7
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x8
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__MPC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000001L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPTC_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000002L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__OPP_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000004L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__HDA_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                 0x00000008L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC0_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC1_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC2_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000040L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC3_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000080L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC4_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000100L
+#define DMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5__DSC5_PERFMON_COUNTER_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+//DMCU_DPRX_INTERRUPT_STATUS1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x0
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x1
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x2
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x3
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x4
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED__SHIFT                              0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR__SHIFT                                 0x5
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED__SHIFT            0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR__SHIFT               0x6
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED__SHIFT                                 0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR__SHIFT                                    0x7
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED__SHIFT                                 0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR__SHIFT                                    0x8
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED__SHIFT                              0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR__SHIFT                                 0x9
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xa
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT       0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT          0xb
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT            0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT               0xc
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT         0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT            0xd
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT          0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT             0xe
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT      0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT         0xf
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED__SHIFT               0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR__SHIFT                  0x10
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED__SHIFT                          0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR__SHIFT                             0x11
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED__SHIFT                           0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR__SHIFT                              0x12
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED__SHIFT                          0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR__SHIFT                             0x13
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED__SHIFT                         0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR__SHIFT                            0x14
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED__SHIFT                    0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR__SHIFT                       0x15
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED__SHIFT                                      0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR__SHIFT                                         0x16
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED__SHIFT                                      0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR__SHIFT                                         0x17
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED__SHIFT                                      0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR__SHIFT                                         0x18
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED__SHIFT                             0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR__SHIFT                                0x19
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED__SHIFT                             0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR__SHIFT                                0x1a
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED__SHIFT                             0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR__SHIFT                                0x1b
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED__SHIFT                             0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR__SHIFT                                0x1c
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000001L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000002L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000004L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000008L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000010L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED_MASK                                0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR_MASK                                   0x00000020L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED_MASK              0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR_MASK                 0x00000040L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_OCCURRED_MASK                                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT0_CLEAR_MASK                                      0x00000080L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_OCCURRED_MASK                                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_VERTICAL_INT1_CLEAR_MASK                                      0x00000100L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED_MASK                                0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR_MASK                                   0x00000200L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000400L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK         0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK            0x00000800L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK              0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                 0x00001000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK           0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK              0x00002000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK            0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK               0x00004000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK        0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK           0x00008000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED_MASK                 0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR_MASK                    0x00010000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED_MASK                            0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR_MASK                               0x00020000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED_MASK                             0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR_MASK                                0x00040000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED_MASK                            0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR_MASK                               0x00080000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED_MASK                           0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR_MASK                              0x00100000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED_MASK                      0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR_MASK                         0x00200000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_OCCURRED_MASK                                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_AUX_INT_CLEAR_MASK                                           0x00400000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_OCCURRED_MASK                                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_I2C_INT_CLEAR_MASK                                           0x00800000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_OCCURRED_MASK                                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_CPU_INT_CLEAR_MASK                                           0x01000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED_MASK                               0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR_MASK                                  0x02000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED_MASK                               0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR_MASK                                  0x04000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED_MASK                               0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR_MASK                                  0x08000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED_MASK                               0x10000000L
+#define DMCU_DPRX_INTERRUPT_STATUS1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR_MASK                                  0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN__SHIFT                       0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN__SHIFT     0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN__SHIFT                          0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN__SHIFT                          0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN__SHIFT                       0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT     0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT   0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN__SHIFT        0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN__SHIFT                   0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN__SHIFT                    0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN__SHIFT                   0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN__SHIFT                  0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN__SHIFT             0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN__SHIFT                               0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN__SHIFT                               0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN__SHIFT                               0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN__SHIFT                      0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN_MASK                         0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN_MASK       0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN_MASK                            0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN_MASK                            0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN_MASK                         0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK       0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK    0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK     0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN_MASK          0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN_MASK                     0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN_MASK                      0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN_MASK                     0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN_MASK                    0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN_MASK               0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_AUX_INT_TO_UC_EN_MASK                                 0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_I2C_INT_TO_UC_EN_MASK                                 0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_CPU_INT_TO_UC_EN_MASK                                 0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN_MASK                        0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN_MASK                        0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN_MASK                        0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN_MASK                        0x10000000L
+//DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x0
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x1
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x2
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x3
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x4
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x5
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL__SHIFT  0x6
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL__SHIFT                 0x7
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL__SHIFT                 0x8
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL__SHIFT              0x9
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xa
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xb
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xc
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xd
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xe
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0xf
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL__SHIFT  0x10
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL__SHIFT          0x11
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL__SHIFT           0x12
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL__SHIFT          0x13
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL__SHIFT         0x14
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL__SHIFT    0x15
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL__SHIFT                      0x16
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL__SHIFT                      0x17
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL__SHIFT                      0x18
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x19
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1a
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1b
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL__SHIFT             0x1c
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000001L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000002L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000004L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000008L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000010L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000020L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL_MASK  0x00000040L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL_MASK                   0x00000080L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL_MASK                   0x00000100L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL_MASK                0x00000200L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000400L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00000800L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00001000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00002000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00004000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00008000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL_MASK  0x00010000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL_MASK            0x00020000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL_MASK             0x00040000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL_MASK            0x00080000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL_MASK           0x00100000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL_MASK      0x00200000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL_MASK                        0x00400000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL_MASK                        0x00800000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL_MASK                        0x01000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x02000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x04000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x08000000L
+#define DMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1__DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL_MASK               0x10000000L
+//DMCU_INTERRUPT_STATUS_CONTINUE
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED__SHIFT                         0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR__SHIFT                            0x0
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED__SHIFT                         0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR__SHIFT                            0x1
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED__SHIFT                         0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR__SHIFT                            0x2
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED__SHIFT                         0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR__SHIFT                            0x3
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED__SHIFT                        0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR__SHIFT                           0x4
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED__SHIFT                        0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR__SHIFT                           0x5
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED__SHIFT                        0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR__SHIFT                           0x6
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED__SHIFT                        0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR__SHIFT                           0x7
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED__SHIFT                        0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR__SHIFT                           0x8
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED__SHIFT                        0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR__SHIFT                           0x9
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED__SHIFT                       0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR__SHIFT                          0xa
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED__SHIFT                       0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR__SHIFT                          0xb
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED__SHIFT                       0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR__SHIFT                          0xc
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED__SHIFT                       0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR__SHIFT                          0xd
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED__SHIFT                      0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR__SHIFT                         0xe
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED__SHIFT                      0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR__SHIFT                         0xf
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED__SHIFT                      0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR__SHIFT                         0x10
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED__SHIFT                      0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR__SHIFT                         0x11
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED__SHIFT                      0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR__SHIFT                         0x12
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED__SHIFT                      0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR__SHIFT                         0x13
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED__SHIFT                          0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR__SHIFT                             0x14
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED__SHIFT                          0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR__SHIFT                             0x15
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED__SHIFT                          0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR__SHIFT                             0x16
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED__SHIFT                          0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR__SHIFT                             0x17
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED__SHIFT                          0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR__SHIFT                             0x18
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED__SHIFT                          0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR__SHIFT                             0x19
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED__SHIFT                                     0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR__SHIFT                                        0x1a
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED__SHIFT                                     0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR__SHIFT                                        0x1b
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED__SHIFT                                    0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR__SHIFT                                       0x1c
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_OCCURRED_MASK                           0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_CLEAR_MASK                              0x00000001L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_OCCURRED_MASK                           0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_CLEAR_MASK                              0x00000002L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_OCCURRED_MASK                           0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_CLEAR_MASK                              0x00000004L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_OCCURRED_MASK                           0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_CLEAR_MASK                              0x00000008L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_OCCURRED_MASK                          0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_CLEAR_MASK                             0x00000010L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_OCCURRED_MASK                          0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_CLEAR_MASK                             0x00000020L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_OCCURRED_MASK                          0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_CLEAR_MASK                             0x00000040L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_OCCURRED_MASK                          0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_CLEAR_MASK                             0x00000080L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_OCCURRED_MASK                          0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_CLEAR_MASK                             0x00000100L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_OCCURRED_MASK                          0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_CLEAR_MASK                             0x00000200L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_OCCURRED_MASK                         0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_CLEAR_MASK                            0x00000400L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_OCCURRED_MASK                         0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_CLEAR_MASK                            0x00000800L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_OCCURRED_MASK                         0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_CLEAR_MASK                            0x00001000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_OCCURRED_MASK                         0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_CLEAR_MASK                            0x00002000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_OCCURRED_MASK                        0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_CLEAR_MASK                           0x00004000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_OCCURRED_MASK                        0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_CLEAR_MASK                           0x00008000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_OCCURRED_MASK                        0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_CLEAR_MASK                           0x00010000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_OCCURRED_MASK                        0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_CLEAR_MASK                           0x00020000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_OCCURRED_MASK                        0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_CLEAR_MASK                           0x00040000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_OCCURRED_MASK                        0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_CLEAR_MASK                           0x00080000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_OCCURRED_MASK                            0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_CLEAR_MASK                               0x00100000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_OCCURRED_MASK                            0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_CLEAR_MASK                               0x00200000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_OCCURRED_MASK                            0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_CLEAR_MASK                               0x00400000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_OCCURRED_MASK                            0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_CLEAR_MASK                               0x00800000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_OCCURRED_MASK                            0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_CLEAR_MASK                               0x01000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_OCCURRED_MASK                            0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_CLEAR_MASK                               0x02000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_OCCURRED_MASK                                       0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_HG_READY_INT_CLEAR_MASK                                          0x04000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_OCCURRED_MASK                                       0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_LS_READY_INT_CLEAR_MASK                                          0x08000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_OCCURRED_MASK                                      0x10000000L
+#define DMCU_INTERRUPT_STATUS_CONTINUE__ABM0_BL_UPDATE_INT_CLEAR_MASK                                         0x10000000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN__SHIFT                  0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN__SHIFT                  0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN__SHIFT                  0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN__SHIFT                  0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN__SHIFT                 0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN__SHIFT                 0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN__SHIFT                 0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN__SHIFT                 0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN__SHIFT                 0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN__SHIFT                 0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xc
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN__SHIFT                0xd
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xe
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN__SHIFT               0xf
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN__SHIFT               0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN__SHIFT                   0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN__SHIFT                   0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN__SHIFT                   0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN__SHIFT                   0x17
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN__SHIFT                   0x18
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN__SHIFT                   0x19
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN__SHIFT                              0x1a
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN__SHIFT                              0x1b
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN__SHIFT                             0x1c
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_TO_UC_EN_MASK                    0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_TO_UC_EN_MASK                    0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_TO_UC_EN_MASK                    0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_TO_UC_EN_MASK                    0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_TO_UC_EN_MASK                   0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_TO_UC_EN_MASK                   0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_TO_UC_EN_MASK                   0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_TO_UC_EN_MASK                   0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_TO_UC_EN_MASK                   0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_TO_UC_EN_MASK                   0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00001000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_TO_UC_EN_MASK                  0x00002000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00004000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00008000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_TO_UC_EN_MASK                 0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_TO_UC_EN_MASK                     0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_TO_UC_EN_MASK                     0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_TO_UC_EN_MASK                     0x00400000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_TO_UC_EN_MASK                     0x00800000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_TO_UC_EN_MASK                     0x01000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_TO_UC_EN_MASK                     0x02000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_HG_READY_INT_TO_UC_EN_MASK                                0x04000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_LS_READY_INT_TO_UC_EN_MASK                                0x08000000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE__ABM0_BL_UPDATE_INT_TO_UC_EN_MASK                               0x10000000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT         0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT        0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xc
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT       0xd
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xe
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0xf
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT      0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL__SHIFT          0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL__SHIFT          0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL__SHIFT          0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL__SHIFT          0x17
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL__SHIFT          0x18
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL__SHIFT          0x19
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1a
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT                     0x1b
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT                    0x1c
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_UP_INT_XIRQ_IRQ_SEL_MASK           0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_UP_INT_XIRQ_IRQ_SEL_MASK          0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN6_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN7_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN8_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00001000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN9_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK         0x00002000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN10_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00004000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN11_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00008000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN12_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN13_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN14_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCPG_IHC_DOMAIN15_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK        0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG0_XIRQ_IRQ_SEL_MASK            0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG1_XIRQ_IRQ_SEL_MASK            0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG2_XIRQ_IRQ_SEL_MASK            0x00400000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG3_XIRQ_IRQ_SEL_MASK            0x00800000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG4_XIRQ_IRQ_SEL_MASK            0x01000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__DCCG_DMCU_INT_VSYNC_CNT_OTG5_XIRQ_IRQ_SEL_MASK            0x02000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_HG_READY_INT_XIRQ_IRQ_SEL_MASK                       0x04000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_LS_READY_INT_XIRQ_IRQ_SEL_MASK                       0x08000000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE__ABM0_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK                      0x10000000L
+//DMCU_INT_CNT_CONTINUE
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT__SHIFT                                              0x0
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT__SHIFT                                              0x8
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT__SHIFT                                             0x10
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_HG_READY_INT_CNT_MASK                                                0x000000FFL
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_LS_READY_INT_CNT_MASK                                                0x0000FF00L
+#define DMCU_INT_CNT_CONTINUE__DMCU_ABM0_BL_UPDATE_INT_CNT_MASK                                               0x00FF0000L
+//DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x0
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x1
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x2
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x3
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x4
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT           0x5
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x6
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x7
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x8
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0x9
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xa
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT         0xb
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL__SHIFT                        0x10
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL__SHIFT                        0x11
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL__SHIFT                        0x12
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL__SHIFT                        0x13
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL__SHIFT                        0x14
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL__SHIFT                        0x15
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL__SHIFT                        0x16
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000001L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000002L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000004L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000008L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000010L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_UP_INT_XIRQ_IRQ_SEL_MASK             0x00000020L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000040L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000080L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000100L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000200L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000400L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK           0x00000800L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXA_INT_XIRQ_IRQ_SEL_MASK                          0x00010000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXB_INT_XIRQ_IRQ_SEL_MASK                          0x00020000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXC_INT_XIRQ_IRQ_SEL_MASK                          0x00040000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXD_INT_XIRQ_IRQ_SEL_MASK                          0x00080000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXE_INT_XIRQ_IRQ_SEL_MASK                          0x00100000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXF_INT_XIRQ_IRQ_SEL_MASK                          0x00200000L
+#define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2__DCIO_DPCS_TXG_INT_XIRQ_IRQ_SEL_MASK                          0x00400000L
+//DMCU_INTERRUPT_STATUS_2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                               0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                  0x0
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                               0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                  0x1
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                               0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                  0x2
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT                               0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR__SHIFT                                  0x3
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED__SHIFT                               0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR__SHIFT                                  0x4
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED__SHIFT                               0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR__SHIFT                                  0x5
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                             0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                0x6
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                             0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                0x7
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                             0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                0x8
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT                             0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT                                0x9
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED__SHIFT                             0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR__SHIFT                                0xa
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED__SHIFT                             0xb
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR__SHIFT                                0xb
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED__SHIFT                                            0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR__SHIFT                                               0x10
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED__SHIFT                                            0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR__SHIFT                                               0x11
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED__SHIFT                                            0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR__SHIFT                                               0x12
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED__SHIFT                                            0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR__SHIFT                                               0x13
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED__SHIFT                                            0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR__SHIFT                                               0x14
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED__SHIFT                                            0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR__SHIFT                                               0x15
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED__SHIFT                                            0x16
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR__SHIFT                                               0x16
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                 0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_CLEAR_MASK                                    0x00000001L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                 0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_CLEAR_MASK                                    0x00000002L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                 0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_CLEAR_MASK                                    0x00000004L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_OCCURRED_MASK                                 0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_CLEAR_MASK                                    0x00000008L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_OCCURRED_MASK                                 0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_CLEAR_MASK                                    0x00000010L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_OCCURRED_MASK                                 0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_CLEAR_MASK                                    0x00000020L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                               0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                  0x00000040L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                               0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                  0x00000080L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                               0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                  0x00000100L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK                               0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_CLEAR_MASK                                  0x00000200L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_OCCURRED_MASK                               0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_CLEAR_MASK                                  0x00000400L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_OCCURRED_MASK                               0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_CLEAR_MASK                                  0x00000800L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_OCCURRED_MASK                                              0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXA_INT_CLEAR_MASK                                                 0x00010000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_OCCURRED_MASK                                              0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXB_INT_CLEAR_MASK                                                 0x00020000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_OCCURRED_MASK                                              0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXC_INT_CLEAR_MASK                                                 0x00040000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_OCCURRED_MASK                                              0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXD_INT_CLEAR_MASK                                                 0x00080000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_OCCURRED_MASK                                              0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXE_INT_CLEAR_MASK                                                 0x00100000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_OCCURRED_MASK                                              0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXF_INT_CLEAR_MASK                                                 0x00200000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_OCCURRED_MASK                                              0x00400000L
+#define DMCU_INTERRUPT_STATUS_2__DCIO_DPCS_TXG_INT_CLEAR_MASK                                                 0x00400000L
+//DMCU_INTERRUPT_TO_UC_EN_MASK_2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN__SHIFT                        0x0
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN__SHIFT                        0x1
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN__SHIFT                        0x2
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN__SHIFT                        0x3
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN__SHIFT                        0x4
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN__SHIFT                        0x5
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x6
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x7
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x8
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0x9
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xa
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN__SHIFT                      0xb
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN__SHIFT                                     0x10
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN__SHIFT                                     0x11
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN__SHIFT                                     0x12
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN__SHIFT                                     0x13
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN__SHIFT                                     0x14
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN__SHIFT                                     0x15
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN__SHIFT                                     0x16
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_UP_INT_TO_UC_EN_MASK                          0x00000001L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_UP_INT_TO_UC_EN_MASK                          0x00000002L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_UP_INT_TO_UC_EN_MASK                          0x00000004L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_UP_INT_TO_UC_EN_MASK                          0x00000008L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_UP_INT_TO_UC_EN_MASK                          0x00000010L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_UP_INT_TO_UC_EN_MASK                          0x00000020L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN16_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000040L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN17_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000080L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN18_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000100L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN19_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000200L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN20_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000400L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCPG_IHC_DOMAIN21_POWER_DOWN_INT_TO_UC_EN_MASK                        0x00000800L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXA_INT_TO_UC_EN_MASK                                       0x00010000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXB_INT_TO_UC_EN_MASK                                       0x00020000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXC_INT_TO_UC_EN_MASK                                       0x00040000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXD_INT_TO_UC_EN_MASK                                       0x00080000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXE_INT_TO_UC_EN_MASK                                       0x00100000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXF_INT_TO_UC_EN_MASK                                       0x00200000L
+#define DMCU_INTERRUPT_TO_UC_EN_MASK_2__DCIO_DPCS_TXG_INT_TO_UC_EN_MASK                                       0x00400000L
+//DMCU_INT_CNT_CONT2
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT__SHIFT                                                 0x0
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT__SHIFT                                                 0x8
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT__SHIFT                                                0x10
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_HG_READY_INT_CNT_MASK                                                   0x000000FFL
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_LS_READY_INT_CNT_MASK                                                   0x0000FF00L
+#define DMCU_INT_CNT_CONT2__DMCU_ABM2_BL_UPDATE_INT_CNT_MASK                                                  0x00FF0000L
+//DMCU_INT_CNT_CONT3
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT__SHIFT                                                 0x0
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT__SHIFT                                                 0x8
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT__SHIFT                                                0x10
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_HG_READY_INT_CNT_MASK                                                   0x000000FFL
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_LS_READY_INT_CNT_MASK                                                   0x0000FF00L
+#define DMCU_INT_CNT_CONT3__DMCU_ABM3_BL_UPDATE_INT_CNT_MASK                                                  0x00FF0000L
+
+
+// addressBlock: dce_dc_dmu_fgsec_dispdec
+//DMCUB_RBBMIF_SEC_CNTL
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT                                                  0x4
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT                                                  0x8
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK                                                    0x00000070L
+#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK                                                    0x01FFFF00L
+
+
+// addressBlock: dce_dc_dmu_rbbmif_dispdec
+//RBBMIF_TIMEOUT
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT                                                           0x0
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT                                                     0x14
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK                                                             0x000FFFFFL
+#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK                                                       0xFFF00000L
+//RBBMIF_STATUS
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT                                                      0x0
+#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK                                                        0xFFFFFFFFL
+//RBBMIF_STATUS_2
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT                                                  0x0
+#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK                                                    0x0000007FL
+//RBBMIF_INT_STATUS
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT                                                         0x2
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT                                                           0x1c
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT                                                  0x1d
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT                                                          0x1e
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT                                                         0x1f
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK                                                           0x0003FFFCL
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK                                                             0x10000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK                                                    0x20000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK                                                            0x40000000L
+#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK                                                           0x80000000L
+//RBBMIF_TIMEOUT_DIS
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT                                                        0x0
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT                                                        0x1
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT                                                        0x2
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT                                                        0x3
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT                                                        0x4
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT                                                        0x5
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT                                                        0x6
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT                                                        0x7
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT                                                        0x8
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT                                                        0x9
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT                                                       0xa
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT                                                       0xb
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT                                                       0xc
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT                                                       0xd
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT                                                       0xe
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT                                                       0xf
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT                                                       0x10
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT                                                       0x11
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT                                                       0x12
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT                                                       0x13
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT                                                       0x14
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT                                                       0x15
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT                                                       0x16
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT                                                       0x17
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT                                                       0x18
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT                                                       0x19
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT                                                       0x1a
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT                                                       0x1b
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT                                                       0x1c
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT                                                       0x1d
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT                                                       0x1e
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT                                                       0x1f
+#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK                                                          0x00000001L
+#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK                                                          0x00000002L
+#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK                                                          0x00000004L
+#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK                                                          0x00000008L
+#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK                                                          0x00000010L
+#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK                                                          0x00000020L
+#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK                                                          0x00000040L
+#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK                                                          0x00000080L
+#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK                                                          0x00000100L
+#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK                                                          0x00000200L
+#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK                                                         0x00000400L
+#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK                                                         0x00000800L
+#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK                                                         0x00001000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK                                                         0x00002000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK                                                         0x00004000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK                                                         0x00008000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK                                                         0x00010000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK                                                         0x00020000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK                                                         0x00040000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK                                                         0x00080000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK                                                         0x00100000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK                                                         0x00200000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK                                                         0x00400000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK                                                         0x00800000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK                                                         0x01000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK                                                         0x02000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK                                                         0x04000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK                                                         0x08000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK                                                         0x10000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK                                                         0x20000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK                                                         0x40000000L
+#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK                                                         0x80000000L
+//RBBMIF_TIMEOUT_DIS_2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT                                                     0x0
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT                                                     0x1
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT                                                     0x2
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT                                                     0x3
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT                                                     0x4
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT                                                     0x5
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT                                                     0x6
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK                                                       0x00000001L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK                                                       0x00000002L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK                                                       0x00000004L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK                                                       0x00000008L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK                                                       0x00000010L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK                                                       0x00000020L
+#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK                                                       0x00000040L
+//RBBMIF_STATUS_FLAG
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT                                                               0x0
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT                                                        0x4
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT                                                          0x5
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT                                                           0x6
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT                                                 0x8
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT                                                 0x9
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT                                                 0x10
+#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK                                                                 0x00000003L
+#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK                                                          0x00000010L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK                                                            0x00000020L
+#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK                                                             0x00000040L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK                                                   0x00000100L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK                                                   0x00000E00L
+#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK                                                   0xFFFF0000L
+
+
+// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON2_PERFCOUNTER_CNTL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_CNTL2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON2_PERFCOUNTER_STATE
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON2_PERFMON_CNTL
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON2_PERFMON_CNTL2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON2_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON2_PERFMON_CVALUE_LOW
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON2_PERFMON_HI
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON2_PERFMON_LOW
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dmu_ihc_dispdec
+//DC_GPU_TIMER_START_POSITION_V_UPDATE
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK                    0x00700000L
+//DC_GPU_TIMER_START_POSITION_VSTARTUP
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT                  0x0
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT                  0x4
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT                  0x8
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT                  0xc
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT                  0x10
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT                  0x14
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK                    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK                    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK                    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK                    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK                    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK                    0x00700000L
+//DC_GPU_TIMER_READ
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT                                                           0x0
+#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK                                                             0xFFFFFFFFL
+//DC_GPU_TIMER_READ_CNTL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT                                               0x0
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT                               0x8
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT                               0xb
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT                               0xe
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT                               0x11
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT                               0x14
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT                               0x17
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK                                                 0x0000007FL
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK                                 0x00000700L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK                                 0x00003800L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK                                 0x0001C000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK                                 0x000E0000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK                                 0x00700000L
+#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK                                 0x03800000L
+//DISP_INTERRUPT_STATUS
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT                                          0x1
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT                                             0x4
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                                      0x6
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT                                                0x7
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT                                                0x8
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                                0xf
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT                                                       0x11
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT                                                    0x12
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT                                                  0x13
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT                                                  0x14
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT                                            0x17
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT                                                0x18
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT                                                    0x1a
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT                                                            0x1b
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT                                                       0x1c
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT                                                       0x1d
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT                                                      0x1e
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT                                          0x1f
+#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK                                            0x00000002L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK                                               0x00000010L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                                        0x00000040L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK                                                  0x00000080L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK                                                  0x00000100L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                                  0x00008000L
+#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK                                                         0x00020000L
+#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK                                                      0x00040000L
+#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK                                                    0x00080000L
+#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK                                                    0x00100000L
+#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK                                              0x00800000L
+#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK                                                  0x01000000L
+#define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK                                                      0x04000000L
+#define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK                                                              0x08000000L
+#define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK                                                         0x10000000L
+#define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK                                                         0x20000000L
+#define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK                                                        0x40000000L
+#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK                                            0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT                                 0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                       0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                             0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT                                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT                                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                     0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                       0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT                                              0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT                                         0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT                                         0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT                                   0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT                                   0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT                                0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK                                   0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                         0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                               0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK                                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK                                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                       0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                         0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK                                                0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK                                           0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK                                           0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK                                     0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK                                     0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK                                  0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE2
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE3
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT                                   0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT                      0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT                                      0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT                                      0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                      0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT                                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT                                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT                                  0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK                                     0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK                        0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK                                        0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK                                        0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                        0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK                                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK                                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK                                    0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE6
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT                                      0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT                                      0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT                                      0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT                                      0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT                                      0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT__SHIFT                                 0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK                                        0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK                                        0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK                                        0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK                                        0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK                                        0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX1_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX2_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX3_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX4_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX5_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__AUX6_GTC_SYNC_ERROR_INTERRUPT_MASK                                   0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE7
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE8
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT                               0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK                                 0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT                                0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT                              0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK                                  0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK                                  0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK                                0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE10
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT                                0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT                                0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT                                0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK                                  0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK                                  0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK                                  0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK                                     0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK                                     0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK                                     0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK                                     0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT                                        0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT                                        0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT                                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT                                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT                                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT                                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT                                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT                                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT__SHIFT                                    0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK                                          0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK                                          0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK                                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK                                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK                                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK                                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK                                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK                                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__VGA_IHC_VGA_CRT_INTERRUPT_MASK                                      0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT                                0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT                                 0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT                          0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT                          0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT                          0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT                          0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT                          0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT                          0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK                                  0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK                                   0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK                            0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK                            0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK                            0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK                            0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK                            0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK                            0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE14
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE15
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT                                   0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT                                   0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK                                     0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK                                     0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK                                    0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT                             0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT                             0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT                                   0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT                                    0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT                                   0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT                                   0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT                                    0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT                                   0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT                                   0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT                                    0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT                                   0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT                                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT                                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT                                   0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT                                   0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT                                    0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT                                   0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT                                  0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK                               0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK                               0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK                                     0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK                                      0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK                                     0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK                                     0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK                                      0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK                                     0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK                                     0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK                                      0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK                                     0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK                                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK                                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK                                     0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK                                     0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK                                      0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK                                     0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK                                    0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK                                    0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK                                    0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK                                    0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK                                    0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT                                     0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT                                     0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT                                     0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT                                     0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT                                     0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT                                     0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT                                     0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT                                     0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK                                       0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK                                       0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK                                       0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK                                       0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK                                       0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK                                       0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK                                       0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK                                       0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT                                0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT                                0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT                            0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT                            0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT                            0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT                            0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT                        0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT                        0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT                        0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT                        0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT                        0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT                        0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT                        0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT                        0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK                                  0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK                                  0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK                              0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK                              0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK                              0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK                              0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK                          0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK                          0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK                          0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK                          0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK                          0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK                          0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK                          0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK                          0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE19
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT                    0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT                           0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT                           0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT                          0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT                          0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT                          0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK                      0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK                             0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK                             0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK                            0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK                            0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK                            0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE20
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT                                    0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT                                  0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT                             0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT                                  0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT                                    0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT                                    0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT                                    0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT                                    0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT                                    0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT                                    0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK                                      0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK                                    0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK                               0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK                                    0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK                                      0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK                                      0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK                                      0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK                                      0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK                                      0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK                                      0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE21
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT                          0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT                          0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT                          0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT                          0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT                          0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT                          0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT                        0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT                           0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT                           0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT                           0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT                           0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT                            0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT                     0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT                         0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK                            0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK                            0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK                            0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK                            0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK                            0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK                            0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK                          0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK                             0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK                             0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK                             0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK                             0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK                             0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK                              0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK                       0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK                           0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE22
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT__SHIFT                                            0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT__SHIFT                                            0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT__SHIFT                                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT                          0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT                             0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_HG_READY_INT_MASK                                              0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_LS_READY_INT_MASK                                              0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__ABM0_BL_UPDATE_INT_MASK                                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK                            0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK                               0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK                               0x80000000L
+//DC_GPU_TIMER_START_POSITION_VREADY
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT                      0x0
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT                      0x4
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT                      0x8
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT                      0xc
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT                      0x10
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT                      0x14
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK                        0x00000007L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK                        0x00000070L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK                        0x00000700L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK                        0x00007000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK                        0x00070000L
+#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK                        0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT                          0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT                          0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT                          0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT                          0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT                          0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT                          0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT                          0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT                          0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK                            0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK                            0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK                            0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK                            0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK                            0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK                            0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK                            0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK                            0x70000000L
+//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT  0x0
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT  0x4
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT  0x8
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT  0xc
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT  0x10
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT  0x14
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK    0x00000007L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK    0x00000070L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK    0x00000700L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK    0x00007000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK    0x00070000L
+#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK    0x00700000L
+//DC_GPU_TIMER_START_POSITION_FLIP_AWAY
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT                0x0
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT                0x4
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT                0x8
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT                0xc
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT                0x10
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT                0x14
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT                0x18
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT                0x1c
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK                  0x00000007L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK                  0x00000070L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK                  0x00000700L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK                  0x00007000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK                  0x00070000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK                  0x00700000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK                  0x07000000L
+#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK                  0x70000000L
+//DISP_INTERRUPT_STATUS_CONTINUE23
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT                         0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT                         0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT                         0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT                         0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT                         0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT                         0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT                       0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT                       0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT                       0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT                       0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT                       0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT                       0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT__SHIFT                           0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1a
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT                                0x1b
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK                           0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK                           0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK                           0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK                           0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK                           0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK                           0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK                         0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK                         0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK                         0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK                         0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK                         0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK                         0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_MASK                             0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x04000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK                                  0x08000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE24
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT                              0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT                              0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT                          0xc
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT                           0xd
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                    0xe
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                     0xf
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                     0x10
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                      0x11
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT                   0x12
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT                    0x13
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT                    0x14
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT                     0x15
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT                              0x16
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT                              0x17
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT                              0x18
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT                      0x19
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT                               0x1c
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT                               0x1d
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT__SHIFT                                    0x1e
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT                             0x1f
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK                                0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK                                0x00000800L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK                            0x00001000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK                             0x00002000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                      0x00004000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                       0x00008000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                       0x00010000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                        0x00020000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK                     0x00040000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK                      0x00080000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK                      0x00100000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK                       0x00200000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK                                0x00400000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK                                0x00800000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK                                0x01000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK                        0x02000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER0_INTERRUPT_MASK                                 0x10000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__HPO_PERFMON_COUNTER1_INTERRUPT_MASK                                 0x20000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__MMHUBBUB_WARMUP_INTERRUPT_MASK                                      0x40000000L
+#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK                               0x80000000L
+//DISP_INTERRUPT_STATUS_CONTINUE25
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT__SHIFT                                            0x0
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT__SHIFT                                            0x1
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT__SHIFT                                           0x2
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT__SHIFT                                            0x3
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT__SHIFT                                            0x4
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT__SHIFT                                           0x5
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT__SHIFT                                            0x6
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT__SHIFT                                            0x7
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT__SHIFT                                           0x8
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT__SHIFT                                            0x9
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT__SHIFT                                            0xa
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT__SHIFT                                           0xb
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_HG_READY_INT_MASK                                              0x00000001L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_LS_READY_INT_MASK                                              0x00000002L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM2_BL_UPDATE_INT_MASK                                             0x00000004L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_HG_READY_INT_MASK                                              0x00000008L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_LS_READY_INT_MASK                                              0x00000010L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM3_BL_UPDATE_INT_MASK                                             0x00000020L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_HG_READY_INT_MASK                                              0x00000040L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_LS_READY_INT_MASK                                              0x00000080L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM4_BL_UPDATE_INT_MASK                                             0x00000100L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_HG_READY_INT_MASK                                              0x00000200L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_LS_READY_INT_MASK                                              0x00000400L
+#define DISP_INTERRUPT_STATUS_CONTINUE25__ABM5_BL_UPDATE_INT_MASK                                             0x00000800L
+//DCCG_INTERRUPT_DEST
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT                                        0x0
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT                                        0x1
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT                                        0x2
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT                                        0x3
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT                                        0x4
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT                                        0x5
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT                                 0xe
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT                                 0xf
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK                                          0x00000001L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK                                          0x00000002L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK                                          0x00000004L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK                                          0x00000008L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK                                          0x00000010L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK                                          0x00000020L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK                                   0x00004000L
+#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK                                   0x00008000L
+//DMU_INTERRUPT_DEST
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT                                                  0x0
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT                                                  0x1
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT                                                  0x2
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT                                                  0x3
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT                                            0x4
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT                                             0x5
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT                                            0x6
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT                                             0x7
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT                                           0x8
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT                                            0x9
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT                                           0xa
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT                                            0xb
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST__SHIFT                                      0xe
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x10
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST__SHIFT                                      0x11
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST__SHIFT                                      0x12
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST__SHIFT                                     0x13
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT                                                  0x18
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT                                 0x19
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST__SHIFT                                      0x1b
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST__SHIFT                                                0x1c
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK                                                    0x00000001L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK                                                    0x00000002L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK                                                    0x00000004L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK                                                    0x00000008L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK                                              0x00000010L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK                                               0x00000020L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK                                              0x00000040L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK                                               0x00000080L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK                                             0x00000100L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK                                              0x00000200L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK                                             0x00000400L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK                                              0x00000800L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_HG_READY_INTERRUPT_DEST_MASK                                        0x00004000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_LS_READY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM0_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00010000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_HG_READY_INTERRUPT_DEST_MASK                                        0x00020000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_LS_READY_INTERRUPT_DEST_MASK                                        0x00040000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_ABM1_BL_UPDATE_INTERRUPT_DEST_MASK                                       0x00080000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK                                                    0x01000000L
+#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK                                   0x02000000L
+#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_DMCU_INTERNAL_INTERRUPT_DEST_MASK                                        0x08000000L
+#define DMU_INTERRUPT_DEST__DMCU_IHC_SCP_INTERRUPT_DEST_MASK                                                  0x10000000L
+//DMU_INTERRUPT_DEST2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST__SHIFT                                     0x0
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST__SHIFT                                     0x1
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x2
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST__SHIFT                                     0x3
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST__SHIFT                                     0x4
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x5
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST__SHIFT                                     0x6
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST__SHIFT                                     0x7
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0x8
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST__SHIFT                                     0x9
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST__SHIFT                                     0xa
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST__SHIFT                                    0xb
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_HG_READY_INTERRUPT_DEST_MASK                                       0x00000001L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_LS_READY_INTERRUPT_DEST_MASK                                       0x00000002L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM2_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_HG_READY_INTERRUPT_DEST_MASK                                       0x00000008L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_LS_READY_INTERRUPT_DEST_MASK                                       0x00000010L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM3_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_HG_READY_INTERRUPT_DEST_MASK                                       0x00000040L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_LS_READY_INTERRUPT_DEST_MASK                                       0x00000080L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM4_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_HG_READY_INTERRUPT_DEST_MASK                                       0x00000200L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_LS_READY_INTERRUPT_DEST_MASK                                       0x00000400L
+#define DMU_INTERRUPT_DEST2__DMCU_IHC_ABM5_BL_UPDATE_INTERRUPT_DEST_MASK                                      0x00000800L
+//DCPG_INTERRUPT_DEST
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x0
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x1
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x2
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x3
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x4
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x5
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x6
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT                                  0x7
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x10
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x11
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x12
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x13
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x14
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x15
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x16
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT                                0x17
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000001L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000002L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000004L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000008L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000010L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000020L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000040L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK                                    0x00000080L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00010000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00020000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00040000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00080000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00100000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00200000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00400000L
+#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK                                  0x00800000L
+//DCPG_INTERRUPT_DEST2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT                                0x0
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT                                0x1
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT                                0x2
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT                                0x3
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT                                0x4
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT                                0x5
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x6
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x7
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x8
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0x9
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xa
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT                              0xb
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000001L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000002L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000004L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000008L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000010L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK                                  0x00000020L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000040L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000080L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000100L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000200L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000400L
+#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK                                0x00000800L
+//MMHUBBUB_INTERRUPT_DEST
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST__SHIFT                                        0x0
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x1
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x2
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT                                       0x3
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT                                       0x4
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT                                       0x5
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT                                    0x8
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                          0xc
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                          0xd
+#define MMHUBBUB_INTERRUPT_DEST__VGA_IHC_VGA_CRT_INTERRUPT_DEST_MASK                                          0x00000001L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000002L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000004L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK                                         0x00000008L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK                                         0x00000010L
+#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK                                         0x00000020L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK                                      0x00000100L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                            0x00001000L
+#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                            0x00002000L
+//WB_INTERRUPT_DEST
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x1
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0x9
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT                                    0xb
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xc
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xd
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0xe
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0xf
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                     0x10
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                     0x11
+#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000002L
+#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000200L
+#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK                                      0x00000800L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00001000L
+#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00002000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00004000L
+#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00008000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                       0x00010000L
+#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                       0x00020000L
+//DCHUB_INTERRUPT_DEST
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x0
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x2
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x3
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x4
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x5
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x6
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x7
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x8
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x9
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xa
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xb
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0xc
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0xd
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0xe
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0xf
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x10
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x11
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x12
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x13
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x14
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x15
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x16
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x17
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x18
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x19
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1a
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1b
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT                                          0x1c
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT                                           0x1d
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT                                          0x1e
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                         0x1f
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000001L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000002L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000004L
+#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000008L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000010L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000020L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000040L
+#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000080L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00000100L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00000200L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00000400L
+#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00000800L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00001000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00002000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00004000L
+#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00008000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00010000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00020000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00040000L
+#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00080000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x00100000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x00200000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x00400000L
+#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x00800000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x01000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x02000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x04000000L
+#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x08000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK                                            0x10000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK                                             0x20000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK                                            0x40000000L
+#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                           0x80000000L
+//DCHUB_PERFCOUNTER_INTERRUPT_DEST
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                   0xc
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                   0xd
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0xe
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0xf
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x10
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x11
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x12
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x13
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x14
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x15
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x16
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x17
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x18
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x19
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1a
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1b
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                    0x1c
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                    0x1d
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                     0x00001000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                     0x00002000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00004000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00008000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00010000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00020000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00040000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00080000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00100000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00200000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x00400000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x00800000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x01000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x02000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x04000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x08000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                      0x10000000L
+#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                      0x20000000L
+//DCHUB_INTERRUPT_DEST2
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x0
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x1
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x2
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x3
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x4
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x5
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x6
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x7
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0x8
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0x9
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xa
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xb
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xc
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xd
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT                                           0xe
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT                                      0xf
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT                                      0x18
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT                                       0x19
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT                           0x1a
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000001L
+#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000002L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000004L
+#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000008L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000010L
+#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000020L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000040L
+#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000080L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000100L
+#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000200L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00000400L
+#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00000800L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00001000L
+#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00002000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK                                             0x00004000L
+#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK                                        0x00008000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK                                        0x01000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK                                         0x02000000L
+#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK                             0x04000000L
+//DPP_PERFCOUNTER_INTERRUPT_DEST
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xc
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xd
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0xe
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0xf
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x10
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x11
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x12
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x13
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x14
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x15
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x16
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x17
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x18
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x19
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                       0x1a
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                       0x1b
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00001000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00002000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00004000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00008000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00010000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00020000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00040000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00080000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00100000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00200000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x00400000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x00800000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x01000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x02000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                         0x04000000L
+#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                         0x08000000L
+//MPC_INTERRUPT_DEST
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT                                                 0x0
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT                                                 0x1
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT                                                 0x2
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT                                                 0x3
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT                                                 0x4
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT                                                 0x5
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT                                                 0x6
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT                                                 0x7
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK                                                   0x00000001L
+#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK                                                   0x00000002L
+#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK                                                   0x00000004L
+#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK                                                   0x00000008L
+#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK                                                   0x00000010L
+#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK                                                   0x00000020L
+#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK                                                   0x00000040L
+#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK                                                   0x00000080L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPP_INTERRUPT_DEST
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//OPTC_INTERRUPT_DEST
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                  0xc
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                  0xd
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x18
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x19
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1a
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1b
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1c
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT                                   0x1d
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                    0x00001000L
+#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                    0x00002000L
+#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x01000000L
+#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x02000000L
+#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x04000000L
+#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x08000000L
+#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x10000000L
+#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK                                     0x20000000L
+//OTG0_INTERRUPT_DEST
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG1_INTERRUPT_DEST
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG2_INTERRUPT_DEST
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG3_INTERRUPT_DEST
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG4_INTERRUPT_DEST
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//OTG5_INTERRUPT_DEST
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT                                            0x0
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT                                        0x1
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT                                          0x2
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT                                          0x3
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT                               0x4
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT                             0x5
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT                                         0x6
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT                                         0x7
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT                                     0x8
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT                                     0x9
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT                                     0xa
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT                                     0xb
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT                     0xf
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT                                          0x10
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT                                            0x11
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT                                         0x12
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT                                  0x13
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT                                     0x14
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK                                              0x00000001L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK                                          0x00000002L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK                                            0x00000004L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK                                            0x00000008L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK                                 0x00000010L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK                               0x00000020L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK                                           0x00000040L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK                                           0x00000080L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK                                       0x00000100L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK                                       0x00000200L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK                                       0x00000400L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK                                       0x00000800L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK                       0x00008000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK                                            0x00010000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK                                              0x00020000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK                                           0x00040000L
+#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK                                    0x00080000L
+#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK                                       0x00100000L
+//DIG_INTERRUPT_DEST
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x0
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x1
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x2
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x3
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x4
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x5
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x6
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT                            0x7
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x8
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0x9
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xa
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xb
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xc
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xd
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xe
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT                        0xf
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000001L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000002L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000004L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000008L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000010L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000020L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000040L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK                              0x00000080L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000100L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000200L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000400L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00000800L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00001000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00002000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00004000L
+#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK                          0x00008000L
+//I2C_DDC_HPD_INTERRUPT_DEST
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT                                0x0
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT                           0x1
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT                           0x2
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT                           0x3
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT                           0x4
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT                           0x5
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT                           0x6
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT                         0x7
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x10
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x11
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x12
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x13
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x14
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT                            0x15
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT                          0x16
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK                                  0x00000001L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK                             0x00000002L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK                             0x00000004L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK                             0x00000008L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK                             0x00000010L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK                             0x00000020L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK                             0x00000040L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK                           0x00000080L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00010000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00020000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00040000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00080000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00100000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK                              0x00200000L
+#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK                            0x00400000L
+//DIO_INTERRUPT_DEST
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0xc
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0xd
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00002000L
+//DCIO_INTERRUPT_DEST
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x0
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x1
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x2
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x3
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x4
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x5
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x6
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT                                    0x10
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000002L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000004L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000008L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000020L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00000040L
+#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK                                      0x00010000L
+//HPD_INTERRUPT_DEST
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT                                               0x0
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT                                               0x1
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT                                               0x2
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT                                               0x3
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT                                               0x4
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT                                               0x5
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT                                            0x8
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT                                            0x9
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT                                            0xa
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT                                            0xb
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT                                            0xc
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT                                            0xd
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK                                                 0x00000001L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK                                                 0x00000002L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK                                                 0x00000004L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK                                                 0x00000008L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK                                                 0x00000010L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK                                                 0x00000020L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK                                              0x00000100L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK                                              0x00000200L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK                                              0x00000400L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK                                              0x00000800L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK                                              0x00001000L
+#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK                                              0x00002000L
+//AZ_INTERRUPT_DEST
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x0
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x1
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x2
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x3
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x4
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x5
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x6
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT                              0x7
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x8
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT                                     0x9
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xa
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xb
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xc
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xd
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xe
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT                                     0xf
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x10
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x11
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x12
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x13
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x14
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x15
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x16
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT                                    0x17
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                      0x1e
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                      0x1f
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000001L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000002L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000004L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000008L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000010L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000020L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000040L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK                                0x00000080L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000100L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000200L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000400L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK                                       0x00000800L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK                                       0x00001000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK                                       0x00002000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK                                       0x00004000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK                                       0x00008000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK                                      0x00010000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK                                      0x00020000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK                                      0x00040000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK                                      0x00080000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK                                      0x00100000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK                                      0x00200000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK                                      0x00400000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK                                      0x00800000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                        0x40000000L
+#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                        0x80000000L
+//AUX_INTERRUPT_DEST
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x0
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x1
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x2
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x3
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x4
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x5
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x6
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x7
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT                                       0x8
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT                                       0x9
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT                                       0xa
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT                                       0xb
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x10
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x11
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x12
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x13
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x14
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x15
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x16
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x17
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x18
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x19
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST__SHIFT                            0x1a
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST__SHIFT                                0x1b
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000001L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000002L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000004L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000008L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000010L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000020L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000040L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000080L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000100L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000200L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK                                         0x00000400L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK                                         0x00000800L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00010000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00020000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00040000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00080000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00100000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00200000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x00400000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x00800000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x01000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x02000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT_DEST_MASK                              0x04000000L
+#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_GTC_SYNC_ERROR_INTERRUPT_DEST_MASK                                  0x08000000L
+//DSC_INTERRUPT_DEST
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x0
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x1
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x2
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x3
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x4
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x5
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x6
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x7
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x8
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x9
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xa
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xb
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0xc
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0xd
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0xe
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0xf
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x10
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x11
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x12
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x13
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST__SHIFT                                    0x14
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT                                         0x15
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                   0x16
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                   0x17
+#define DSC_INTERRUPT_DEST__DSC0_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000001L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000002L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000004L
+#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000008L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000010L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000020L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000040L
+#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000080L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00000100L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00000200L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00000400L
+#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00000800L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00001000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00002000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00004000L
+#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00008000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00010000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00020000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00040000L
+#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00080000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_INPUT_UNDERFLOW_INTERRUPT_DEST_MASK                                      0x00100000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK                                           0x00200000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                     0x00400000L
+#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                     0x00800000L
+//HPO_INTERRUPT_DEST
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT                                    0x2
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT                                    0x3
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK                                      0x00000004L
+#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK                                      0x00000008L
+
+
+// addressBlock: dce_dc_dmu_dmu_misc_dispdec
+//CC_DC_PIPE_DIS
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT                                                                    0x0
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT                                                                0x10
+#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK                                                                      0x000000FFL
+#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK                                                                  0x00010000L
+//DMU_CLK_CNTL
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT                                                                 0x0
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT                                                           0x4
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT                                                          0x5
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT                                                        0x6
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT                                                               0x8
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON__SHIFT                                                          0x9
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT                                                        0xa
+#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK                                                                   0x0000000FL
+#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK                                                             0x00000010L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK                                                            0x00000020L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK                                                          0x00000040L
+#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK                                                                 0x00000100L
+#define DMU_CLK_CNTL__DISPCLK_G_DMCU_CLOCK_ON_MASK                                                            0x00000200L
+#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK                                                          0x00000400L
+//DMU_MEM_PWR_CNTL
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL__SHIFT                                                   0x0
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE__SHIFT                                                      0x1
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS__SHIFT                                                        0x3
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE__SHIFT                                                      0x4
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE__SHIFT                                                      0x8
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS__SHIFT                                                        0x9
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE__SHIFT                                                      0xa
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_MODE_SEL_MASK                                                     0x00000001L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_FORCE_MASK                                                        0x00000006L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_DIS_MASK                                                          0x00000008L
+#define DMU_MEM_PWR_CNTL__DMCU_ERAM_MEM_PWR_STATE_MASK                                                        0x00000030L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_FORCE_MASK                                                        0x00000100L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_DIS_MASK                                                          0x00000200L
+#define DMU_MEM_PWR_CNTL__DMCU_IRAM_MEM_PWR_STATE_MASK                                                        0x00000400L
+//DMCU_SMU_INTERRUPT_CNTL
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_INT__SHIFT                                                      0x0
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG__SHIFT                                                          0x10
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_INT_MASK                                                        0x00000001L
+#define DMCU_SMU_INTERRUPT_CNTL__DMCU_SMU_MSG_MASK                                                            0xFFFF0000L
+//SMU_INTERRUPT_CONTROL
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT                                                       0x0
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT                                                       0x4
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT                                                        0x10
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK                                                         0x00000001L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK                                                         0x00000010L
+#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK                                                          0xFFFF0000L
+//ZSC_CNTL
+#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT                                                                     0x0
+#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK                                                                       0x00000003L
+//ZSC_CNTL2
+#define ZSC_CNTL2__ALLOW_Z10__SHIFT                                                                           0x0
+#define ZSC_CNTL2__ALLOW_Z10_MASK                                                                             0x00000001L
+//DMU_MISC_ALLOW_DS_FORCE
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT                                            0x0
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT                                         0x4
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK                                              0x00000001L
+#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK                                           0x00000010L
+//ZSC_STATUS
+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT                                                          0x0
+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT                                                   0x4
+#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT                                                                   0x8
+#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT                                                                   0x9
+#define ZSC_STATUS__FENCE_STATUS__SHIFT                                                                       0xa
+#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK                                                            0x00000003L
+#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK                                                     0x00000030L
+#define ZSC_STATUS__FENCE_REQ_STATUS_MASK                                                                     0x00000100L
+#define ZSC_STATUS__FENCE_ACK_STATUS_MASK                                                                     0x00000200L
+#define ZSC_STATUS__FENCE_STATUS_MASK                                                                         0x00000C00L
+
+
+// addressBlock: dce_dc_dmu_dc_pg_dispdec
+//DOMAIN0_PG_CONFIG
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN0_PG_STATUS
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN1_PG_CONFIG
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN1_PG_STATUS
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN2_PG_CONFIG
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN2_PG_STATUS
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN3_PG_CONFIG
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                        0x0
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                           0x8
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                          0x00000001L
+#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                             0x00000100L
+//DOMAIN3_PG_STATUS
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                    0x1c
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                     0x1e
+#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                      0x10000000L
+#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                       0xC0000000L
+//DOMAIN16_PG_CONFIG
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN16_PG_STATUS
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN17_PG_CONFIG
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN17_PG_STATUS
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DOMAIN18_PG_CONFIG
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT                                                       0x0
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT                                                          0x8
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK                                                         0x00000001L
+#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK                                                            0x00000100L
+//DOMAIN18_PG_STATUS
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT                                                   0x1c
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT                                                    0x1e
+#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK                                                     0x10000000L
+#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK                                                      0xC0000000L
+//DCPG_INTERRUPT_STATUS
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT                                           0x0
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x1
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT                                           0x2
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x3
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT                                           0x4
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x5
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT                                           0x6
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT                                         0x7
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000002L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK                                             0x00000004L
+#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000020L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK                                             0x00000040L
+#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK                                           0x00000080L
+//DCPG_INTERRUPT_STATUS_2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT                                        0x0
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x1
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT                                        0x2
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x3
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT                                        0x4
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT                                      0x5
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK                                          0x00000001L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000002L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK                                          0x00000004L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000008L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK                                          0x00000010L
+#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK                                        0x00000020L
+//DCPG_INTERRUPT_CONTROL_1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT                                            0x0
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT                                           0x1
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT                                          0x2
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT                                         0x3
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT                                            0x4
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT                                           0x5
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT                                          0x6
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT                                         0x7
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT                                            0x8
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT                                           0x9
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT                                          0xa
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT                                         0xb
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT                                            0xc
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT                                           0xd
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT                                          0xe
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT                                         0xf
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK                                              0x00000001L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK                                             0x00000002L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK                                            0x00000004L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK                                           0x00000008L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK                                              0x00000010L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK                                             0x00000020L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK                                            0x00000040L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK                                           0x00000080L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK                                              0x00000100L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK                                             0x00000200L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK                                            0x00000400L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK                                           0x00000800L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK                                              0x00001000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK                                             0x00002000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK                                            0x00004000L
+#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK                                           0x00008000L
+//DCPG_INTERRUPT_CONTROL_3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK__SHIFT                                           0x0
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT                                          0x1
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT                                         0x2
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT                                        0x3
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK__SHIFT                                           0x4
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT                                          0x5
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT                                         0x6
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT                                        0x7
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK__SHIFT                                           0x8
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT                                          0x9
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT                                         0xa
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT                                        0xb
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_MASK_MASK                                             0x00000001L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_UP_INT_CLEAR_MASK                                            0x00000002L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_MASK_MASK                                           0x00000004L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK                                          0x00000008L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_MASK_MASK                                             0x00000010L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_UP_INT_CLEAR_MASK                                            0x00000020L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_MASK_MASK                                           0x00000040L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK                                          0x00000080L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_MASK_MASK                                             0x00000100L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_UP_INT_CLEAR_MASK                                            0x00000200L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_MASK_MASK                                           0x00000400L
+#define DCPG_INTERRUPT_CONTROL_3__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK                                          0x00000800L
+//DC_IP_REQUEST_CNTL
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT                                                              0x0
+#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK                                                                0x00000001L
+
+
+// addressBlock: dce_dc_dmu_dmcub_dispdec
+//DMCUB_REGION0_OFFSET
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION0_OFFSET_HIGH
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION1_OFFSET
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION1_OFFSET_HIGH
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION2_OFFSET
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION2_OFFSET_HIGH
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION4_OFFSET
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION4_OFFSET_HIGH
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION5_OFFSET
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION5_OFFSET_HIGH
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION6_OFFSET
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION6_OFFSET_HIGH
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION7_OFFSET
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT                                                     0x8
+#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK                                                       0xFFFFFF00L
+//DMCUB_REGION7_OFFSET_HIGH
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT                                           0x0
+#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK                                             0x0000FFFFL
+//DMCUB_REGION0_TOP_ADDRESS
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION1_TOP_ADDRESS
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION2_TOP_ADDRESS
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION4_TOP_ADDRESS
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION5_TOP_ADDRESS
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION6_TOP_ADDRESS
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION7_TOP_ADDRESS
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT                                           0x0
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT                                                0x1f
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK                                             0x1FFFFFFFL
+#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK                                                  0x80000000L
+//DMCUB_REGION3_CW0_BASE_ADDRESS
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW1_BASE_ADDRESS
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW2_BASE_ADDRESS
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW3_BASE_ADDRESS
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW4_BASE_ADDRESS
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW5_BASE_ADDRESS
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW6_BASE_ADDRESS
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW7_BASE_ADDRESS
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT                                 0x0
+#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK                                   0x1FFFFFFFL
+//DMCUB_REGION3_CW0_TOP_ADDRESS
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW1_TOP_ADDRESS
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW2_TOP_ADDRESS
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW3_TOP_ADDRESS
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW4_TOP_ADDRESS
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW5_TOP_ADDRESS
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW6_TOP_ADDRESS
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW7_TOP_ADDRESS
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT                                        0x1f
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK                                     0x1FFFFFFFL
+#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK                                          0x80000000L
+//DMCUB_REGION3_CW0_OFFSET
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW0_OFFSET_HIGH
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW1_OFFSET
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW1_OFFSET_HIGH
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW2_OFFSET
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW2_OFFSET_HIGH
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW3_OFFSET
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW3_OFFSET_HIGH
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW4_OFFSET
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW4_OFFSET_HIGH
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW5_OFFSET
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW5_OFFSET_HIGH
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW6_OFFSET
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW6_OFFSET_HIGH
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_REGION3_CW7_OFFSET
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT                                             0x8
+#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK                                               0xFFFFFF00L
+//DMCUB_REGION3_CW7_OFFSET_HIGH
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT                                   0x0
+#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK                                     0x0000FFFFL
+//DMCUB_INTERRUPT_ENABLE
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK                                     0x00002000L
+//DMCUB_INTERRUPT_ACK
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT                                                      0x0
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT                                                      0x1
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT                                                0x2
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT                                                 0x3
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT                                                0x4
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT                                                 0x5
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT                                               0x6
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT                                                0x7
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT                                               0x8
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT                                                0x9
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT                                                      0xa
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT                                                      0xb
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT                                                      0xc
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT                                         0xd
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK                                                        0x00000001L
+#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK                                                        0x00000002L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK                                                  0x00000004L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK                                                   0x00000008L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK                                                  0x00000010L
+#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK                                                   0x00000020L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK                                                 0x00000040L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK                                                  0x00000080L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK                                                 0x00000100L
+#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK                                                  0x00000200L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK                                                        0x00000400L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK                                                        0x00000800L
+#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK                                                        0x00001000L
+#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK                                           0x00002000L
+//DMCUB_INTERRUPT_STATUS
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT                                                  0x0
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT                                                  0x1
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT                                            0x2
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT                                             0x3
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT                                            0x4
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT                                             0x5
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT                                           0x6
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT                                            0x7
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT                                           0x8
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT                                            0x9
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT                                                  0xa
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT                                                  0xb
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT                                                  0xc
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT                                          0xd
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT                                                 0xe
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT                                                 0xf
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK                                                    0x00000001L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK                                                    0x00000002L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK                                              0x00000004L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK                                               0x00000008L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK                                              0x00000010L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK                                               0x00000020L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK                                             0x00000040L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK                                              0x00000080L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK                                             0x00000100L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK                                              0x00000200L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK                                                    0x00000400L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK                                                    0x00000800L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK                                                    0x00001000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK                                            0x00002000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK                                                   0x00004000L
+#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK                                                   0x00008000L
+//DMCUB_INTERRUPT_TYPE
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT                                                    0x0
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT                                                    0x1
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT                                              0x2
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT                                               0x3
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT                                              0x4
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT                                               0x5
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT                                             0x6
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT                                              0x7
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT                                             0x8
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT                                              0x9
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT                                                    0xa
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT                                                    0xb
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT                                                    0xc
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT                                   0xd
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK                                                      0x00000001L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK                                                      0x00000002L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK                                                0x00000004L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK                                                 0x00000008L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK                                                0x00000010L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK                                                 0x00000020L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK                                               0x00000040L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK                                                0x00000080L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK                                               0x00000100L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK                                                0x00000200L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK                                                      0x00000400L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK                                                      0x00000800L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK                                                      0x00001000L
+#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK                                     0x00002000L
+//DMCUB_EXT_INTERRUPT_STATUS
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT                                          0x0
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT                                             0x8
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK                                            0x000000FFL
+#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK                                               0x0000FF00L
+//DMCUB_EXT_INTERRUPT_CTXID
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT                                           0x0
+#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK                                             0x0FFFFFFFL
+//DMCUB_EXT_INTERRUPT_ACK
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT                                               0x0
+#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK                                                 0x00000001L
+//DMCUB_INST_FETCH_FAULT_ADDR
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_DATA_WRITE_FAULT_ADDR
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT                                       0x0
+#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK                                         0xFFFFFFFFL
+//DMCUB_SEC_CNTL
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT                                                              0x8
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT                                                                0x10
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT                                                   0x11
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT                                                        0x14
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT                                                         0x15
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT                                                   0x18
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT                                                   0x19
+#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK                                                                0x00003F00L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK                                                                  0x00010000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK                                                     0x00020000L
+#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK                                                          0x00100000L
+#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK                                                           0x00200000L
+#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK                                                     0x01000000L
+#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK                                                     0x02000000L
+//DMCUB_MEM_CNTL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT                                                            0x0
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT                                                             0x4
+#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK                                                              0x0000000FL
+#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK                                                               0x000000F0L
+//DMCUB_INBOX0_BASE_ADDRESS
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX0_SIZE
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_WPTR
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX0_RPTR
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_BASE_ADDRESS
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT                                           0x0
+#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK                                             0xFFFFFFFFL
+//DMCUB_INBOX1_SIZE
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT                                                           0x0
+#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_WPTR
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_INBOX1_RPTR
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT                                                           0x0
+#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK                                                             0xFFFFFFFFL
+//DMCUB_OUTBOX0_BASE_ADDRESS
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_SIZE
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_WPTR
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX0_RPTR
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_BASE_ADDRESS
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT                                         0x0
+#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_SIZE
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_WPTR
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_OUTBOX1_RPTR
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT                                                         0x0
+#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK                                                           0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_TRIGGER1
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT                                                     0x0
+#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK                                                       0xFFFFFFFFL
+//DMCUB_TIMER_WINDOW
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT                                                         0x0
+#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK                                                           0x00000007L
+//DMCUB_SCRATCH0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH1
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH2
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH3
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH4
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH5
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH6
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH7
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH8
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH9
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT                                                                 0x0
+#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK                                                                   0xFFFFFFFFL
+//DMCUB_SCRATCH10
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT                                                               0x0
+#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH11
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT                                                               0x0
+#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH12
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT                                                               0x0
+#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH13
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT                                                               0x0
+#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH14
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT                                                               0x0
+#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK                                                                 0xFFFFFFFFL
+//DMCUB_SCRATCH15
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT                                                               0x0
+#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK                                                                 0xFFFFFFFFL
+//DMCUB_CNTL
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT                                                                0x0
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT                                                          0x8
+#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT                                                                       0x10
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT                                                      0x12
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT                                                                 0x13
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT                                                            0x14
+#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK                                                                  0x000000FFL
+#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK                                                            0x00000100L
+#define DMCUB_CNTL__DMCUB_ENABLE_MASK                                                                         0x00010000L
+#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK                                                        0x00040000L
+#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK                                                                   0x00080000L
+#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK                                                              0x00100000L
+//DMCUB_GPINT_DATAIN0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAIN1
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK                                                         0xFFFFFFFFL
+//DMCUB_GPINT_DATAOUT
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT                                                       0x0
+#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK                                                         0xFFFFFFFFL
+//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT                         0x0
+#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK                           0xFFFFFFFFL
+//DMCUB_LS_WAKE_INT_ENABLE
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT                                             0x0
+#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK                                               0xFFFFFFFFL
+//DMCUB_MEM_PWR_CNTL
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT                                                        0x1
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT                                                          0x3
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT                                                        0x4
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK                                                          0x00000006L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK                                                            0x00000008L
+#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK                                                          0x00000030L
+//DMCUB_TIMER_CURRENT
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT                                                       0x0
+#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK                                                         0xFFFFFFFFL
+//DMCUB_PROC_ID
+#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT                                                                   0x0
+#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK                                                                     0x0000FFFFL
+//DMCUB_CNTL2
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT                                                                  0x0
+#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK                                                                    0x00000001L
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
+//DWB_ENABLE_CLK_CTRL
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT                                                                0x0
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT                                                    0x4
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT                                                    0x8
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT                                                          0xc
+#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK                                                                  0x00000001L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK                                                      0x00000010L
+#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK                                                      0x00000100L
+#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK                                                            0x00003000L
+//DWB_MEM_PWR_CTRL
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT                                                   0xc
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT                                                   0x14
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK                                                     0x00003000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK                                                     0x00300000L
+//FC_MODE_CTRL
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT                                                              0x0
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT                                                            0x4
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT                                                                0x8
+#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT                                                                 0xc
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT                                                           0x10
+#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT                                                                   0x14
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT                                                      0x1f
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK                                                                0x00000001L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK                                                              0x00000030L
+#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK                                                                  0x00000100L
+#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK                                                                   0x00003000L
+#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK                                                             0x00010000L
+#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK                                                                     0x00100000L
+#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK                                                        0x80000000L
+//FC_FLOW_CTRL
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT                                                       0x0
+#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK                                                         0x00000FFFL
+//FC_WINDOW_START
+#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT                                                             0x0
+#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT                                                             0x10
+#define FC_WINDOW_START__FC_WINDOW_START_X_MASK                                                               0x00001FFFL
+#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK                                                               0x1FFF0000L
+//FC_WINDOW_SIZE
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT                                                                0x0
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT                                                               0x10
+#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK                                                                  0x00000FFFL
+#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK                                                                 0x0FFF0000L
+//FC_SOURCE_SIZE
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT                                                                0x0
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT                                                               0x10
+#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK                                                                  0x00007FFFL
+#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK                                                                 0x7FFF0000L
+//DWB_UPDATE_CTRL
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT                                                               0x0
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT                                                            0x4
+#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK                                                                 0x00000001L
+#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK                                                              0x00000010L
+//DWB_CRC_CTRL
+#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT                                                                       0x0
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT                                                                  0x4
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT                                                                  0x8
+#define DWB_CRC_CTRL__DWB_CRC_EN_MASK                                                                         0x00000001L
+#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK                                                                    0x00000300L
+//DWB_CRC_MASK_R_G
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT                                                             0x0
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT                                                           0x10
+#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK                                                               0x0000FFFFL
+#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK                                                             0xFFFF0000L
+//DWB_CRC_MASK_B_A
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT                                                            0x0
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT                                                               0x10
+#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK                                                              0x0000FFFFL
+#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK                                                                 0xFFFF0000L
+//DWB_CRC_VAL_R_G
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT                                                               0x0
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT                                                             0x10
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK                                                                 0x0000FFFFL
+#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK                                                               0xFFFF0000L
+//DWB_CRC_VAL_B_A
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT                                                              0x0
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT                                                                 0x10
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK                                                                0x0000FFFFL
+#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK                                                                   0xFFFF0000L
+//DWB_OUT_CTRL
+#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT                                                                       0x0
+#define DWB_OUT_CTRL__OUT_DENORM__SHIFT                                                                       0x4
+#define DWB_OUT_CTRL__OUT_MAX__SHIFT                                                                          0x8
+#define DWB_OUT_CTRL__OUT_MIN__SHIFT                                                                          0x14
+#define DWB_OUT_CTRL__OUT_FORMAT_MASK                                                                         0x00000003L
+#define DWB_OUT_CTRL__OUT_DENORM_MASK                                                                         0x00000030L
+#define DWB_OUT_CTRL__OUT_MAX_MASK                                                                            0x0003FF00L
+#define DWB_OUT_CTRL__OUT_MIN_MASK                                                                            0x3FF00000L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT                             0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK                               0x00000001L
+//DWB_MMHUBBUB_BACKPRESSURE_CNT
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT                                   0x0
+#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK                                     0x0000FFFFL
+//DWB_HOST_READ_CONTROL
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT                                              0x0
+#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK                                                0x000000FFL
+//DWB_OVERFLOW_STATUS
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT                                                    0x0
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT                                                     0x8
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT                                                    0xc
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT                                              0x10
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT                                                0x14
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK                                                      0x00000001L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK                                                       0x00000100L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK                                                      0x00001000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK                                                0x00010000L
+#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK                                                  0x00100000L
+//DWB_OVERFLOW_COUNTER
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT                                                   0x0
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT                                              0x4
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT                                              0x10
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK                                                     0x00000003L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK                                                0x0000FFF0L
+#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK                                                0x0FFF0000L
+//DWB_SOFT_RESET
+#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT                                                                 0x0
+#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK                                                                   0x00000001L
+//DWB_DEBUG_CTRL
+#define DWB_DEBUG_CTRL__DWB_DEBUG_EN__SHIFT                                                                   0x0
+#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL__SHIFT                                                                  0x6
+#define DWB_DEBUG_CTRL__DWB_DEBUG_EN_MASK                                                                     0x00000001L
+#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL_MASK                                                                    0x000000C0L
+
+
+// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
+//DWB_HDR_MULT_COEF
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT                                                           0x0
+#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK                                                             0x0007FFFFL
+//DWB_GAMUT_REMAP_MODE
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT                                                     0x0
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT                                             0x18
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK                                                       0x00000003L
+#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK                                               0x03000000L
+//DWB_GAMUT_REMAP_COEF_FORMAT
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT                                       0x0
+#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK                                         0x00000001L
+//DWB_GAMUT_REMAPA_C11_C12
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C13_C14
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C21_C22
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C23_C24
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C31_C32
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPA_C33_C34
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C11_C12
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C13_C14
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C21_C22
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C23_C24
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C31_C32
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK                                                   0xFFFF0000L
+//DWB_GAMUT_REMAPB_C33_C34
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT                                                 0x0
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT                                                 0x10
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK                                                   0x0000FFFFL
+#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK                                                   0xFFFF0000L
+//DWB_OGAM_CONTROL
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT                                                                0x0
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT                                                              0x4
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT                                                         0x8
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT                                                        0x18
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT                                                      0x1c
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK                                                                  0x00000003L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK                                                                0x00000010L
+#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK                                                           0x00000100L
+#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK                                                          0x03000000L
+#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK                                                        0x10000000L
+//DWB_OGAM_LUT_INDEX
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT                                                         0x0
+#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK                                                           0x000001FFL
+//DWB_OGAM_LUT_DATA
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT                                                           0x0
+#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK                                                             0x0003FFFFL
+//DWB_OGAM_LUT_CONTROL
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                                            0x0
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT                                              0x4
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT                                                    0x8
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT                                                    0xc
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT                                                 0x10
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK                                              0x00000007L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK                                                0x00000030L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK                                                      0x00000100L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK                                                      0x00001000L
+#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK                                                   0x00010000L
+//DWB_OGAM_RAMA_START_CNTL_B
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_G
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_CNTL_R
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMA_START_BASE_CNTL_B
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_G
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_START_BASE_CNTL_R
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMA_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL1_B
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_B
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_G
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_G
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_END_CNTL1_R
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMA_END_CNTL2_R
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMA_OFFSET_B
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_G
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_OFFSET_R
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMA_REGION_0_1
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_2_3
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_4_5
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_6_7
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_8_9
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMA_REGION_10_11
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_12_13
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_14_15
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_16_17
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_18_19
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_20_21
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_22_23
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_24_25
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_26_27
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_28_29
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_30_31
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMA_REGION_32_33
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_START_CNTL_B
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_G
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_CNTL_R
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT                                   0x0
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                           0x14
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK                                     0x0003FFFFL
+#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                             0x07F00000L
+//DWB_OGAM_RAMB_START_BASE_CNTL_B
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_B
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_G
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_G
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_START_BASE_CNTL_R
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                         0x0
+#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK                           0x0003FFFFL
+//DWB_OGAM_RAMB_START_SLOPE_CNTL_R
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                       0x0
+#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                         0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL1_B
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_B
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_G
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_G
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_END_CNTL1_R
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                                   0x0003FFFFL
+//DWB_OGAM_RAMB_END_CNTL2_R
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT                                      0x0
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                                0x10
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK                                        0x0000FFFFL
+#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                                  0xFFFF0000L
+//DWB_OGAM_RAMB_OFFSET_B
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_G
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_OFFSET_R
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT                                                 0x0
+#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK                                                   0x0007FFFFL
+//DWB_OGAM_RAMB_REGION_0_1
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_2_3
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_4_5
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_6_7
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_8_9
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                                 0x0
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                               0xc
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                                 0x10
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                               0x1c
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                                   0x000001FFL
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                                 0x00007000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                                   0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                                 0x70000000L
+//DWB_OGAM_RAMB_REGION_10_11
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_12_13
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_14_15
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_16_17
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_18_19
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_20_21
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_22_23
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_24_25
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_26_27
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_28_29
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_30_31
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                              0x70000000L
+//DWB_OGAM_RAMB_REGION_32_33
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                              0x0
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                            0xc
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                              0x10
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                            0x1c
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                                0x000001FFL
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                              0x00007000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                                0x01FF0000L
+#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                              0x70000000L
+
+
+// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON3_PERFCOUNTER_CNTL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_CNTL2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON3_PERFCOUNTER_STATE
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON3_PERFMON_CNTL
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON3_PERFMON_CNTL2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON3_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON3_PERFMON_CVALUE_LOW
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON3_PERFMON_HI
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON3_PERFMON_LOW
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_vga_dispdec
+//VGA_RENDER_CONTROL
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT                                                             0x0
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT                                                             0x5
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT                                                    0x7
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT                                                 0x8
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT                                                           0x10
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT                                                              0x18
+#define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK                                                               0x0000001FL
+#define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK                                                               0x00000060L
+#define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK                                                      0x00000080L
+#define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK                                                   0x00000100L
+#define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK                                                             0x00030000L
+#define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK                                                                0x01000000L
+//VGA_SEQUENCER_RESET_CONTROL
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x0
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x1
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x2
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x3
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x4
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT                             0x5
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x8
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0x9
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xa
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xb
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xc
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT                      0xd
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT                                      0x10
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT                             0x11
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT                                0x12
+#define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000001L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000002L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000004L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000008L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000010L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK                               0x00000020L
+#define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000100L
+#define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000200L
+#define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000400L
+#define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00000800L
+#define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00001000L
+#define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK                        0x00002000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK                                        0x00010000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK                               0x00020000L
+#define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK                                  0x00FC0000L
+//VGA_MODE_CONTROL
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT                                                               0x0
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT                                                  0x4
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT                                                     0x8
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT                                                      0x10
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT                                                    0x18
+#define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK                                                                 0x00000001L
+#define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK                                                    0x00000030L
+#define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK                                                       0x00000100L
+#define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK                                                        0x00010000L
+#define VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK                                                      0x01000000L
+//VGA_SURFACE_PITCH_SELECT
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT                                             0x0
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT                                            0x8
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK                                               0x00000003L
+#define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK                                              0x00000300L
+//VGA_MEMORY_BASE_ADDRESS
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT                                               0x0
+#define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK                                                 0xFFFFFFFFL
+//VGA_DISPBUF1_SURFACE_ADDR
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_DISPBUF2_SURFACE_ADDR
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT                                           0x0
+#define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK                                             0x01FFFFFFL
+//VGA_MEMORY_BASE_ADDRESS_HIGH
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT                                     0x0
+#define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK                                       0x0000FFFFL
+//VGA_HDP_CONTROL
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT                                                        0x0
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT                                                            0x4
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT                                                         0x8
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT                                                                0x10
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT                                                        0x18
+#define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK                                                          0x00000001L
+#define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK                                                              0x00000010L
+#define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK                                                           0x00000100L
+#define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK                                                                  0x00010000L
+#define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK                                                          0x01000000L
+//VGA_CACHE_CONTROL
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT                                                 0x0
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT                                                      0x8
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT                                                  0x10
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT                                                          0x14
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT                                                        0x18
+#define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK                                                   0x00000001L
+#define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK                                                        0x00000100L
+#define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK                                                    0x00010000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK                                                            0x00100000L
+#define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK                                                          0x3F000000L
+//D1VGA_CONTROL
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT                                                                    0x18
+#define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D1VGA_CONTROL__D1VGA_ROTATE_MASK                                                                      0x03000000L
+//D2VGA_CONTROL
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT                                                                    0x18
+#define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D2VGA_CONTROL__D2VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_STATUS
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT                                                              0x0
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT                                                              0x1
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT                                                          0x2
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT                                                       0x3
+#define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK                                                                0x00000001L
+#define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK                                                                0x00000002L
+#define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK                                                            0x00000004L
+#define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK                                                         0x00000008L
+//VGA_INTERRUPT_CONTROL
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT                                                 0x0
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT                                                 0x8
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT                                             0x10
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT                                          0x18
+#define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK                                                   0x00000001L
+#define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK                                                   0x00000100L
+#define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK                                               0x00010000L
+#define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK                                            0x01000000L
+//VGA_STATUS_CLEAR
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT                                                     0x0
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT                                                     0x8
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT                                                 0x10
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT                                              0x18
+#define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK                                                       0x00000001L
+#define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK                                                       0x00000100L
+#define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK                                                   0x00010000L
+#define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK                                                0x01000000L
+//VGA_INTERRUPT_STATUS
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT                                                0x0
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT                                                0x1
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT                                            0x2
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT                                         0x3
+#define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK                                                  0x00000001L
+#define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK                                                  0x00000002L
+#define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK                                              0x00000004L
+#define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK                                           0x00000008L
+//VGA_MAIN_CONTROL
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT                                                             0x0
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT                                                     0x3
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT                                        0x5
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT                                       0x8
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT                                                0xc
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT                                        0x10
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT                                          0x18
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT                                             0x1a
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT                                                       0x1d
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT                                0x1f
+#define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK                                                               0x00000003L
+#define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK                                                       0x00000018L
+#define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK                                          0x000000E0L
+#define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK                                         0x00000300L
+#define VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK                                                  0x0000F000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK                                          0x00030000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK                                            0x03000000L
+#define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK                                               0x04000000L
+#define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK                                                         0x20000000L
+#define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK                                  0x80000000L
+//VGA_TEST_CONTROL
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT                                                              0x0
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT                                                        0x8
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT                                                         0x10
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT                                               0x18
+#define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK                                                                0x00000001L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK                                                          0x00000100L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK                                                           0x00010000L
+#define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK                                                 0x01000000L
+//VGA_QOS_CTRL
+#define VGA_QOS_CTRL__VGA_READ_QOS__SHIFT                                                                     0x0
+#define VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT                                                                    0x4
+#define VGA_QOS_CTRL__VGA_READ_QOS_MASK                                                                       0x0000000FL
+#define VGA_QOS_CTRL__VGA_WRITE_QOS_MASK                                                                      0x000000F0L
+//D3VGA_CONTROL
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT                                                                    0x18
+#define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D3VGA_CONTROL__D3VGA_ROTATE_MASK                                                                      0x03000000L
+//D4VGA_CONTROL
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT                                                                    0x18
+#define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D4VGA_CONTROL__D4VGA_ROTATE_MASK                                                                      0x03000000L
+//D5VGA_CONTROL
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT                                                                    0x18
+#define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D5VGA_CONTROL__D5VGA_ROTATE_MASK                                                                      0x03000000L
+//D6VGA_CONTROL
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT                                                               0x0
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT                                                             0x8
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT                                                      0x9
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT                                                         0x10
+#define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT                                                                    0x18
+#define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK                                                                 0x00000001L
+#define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK                                                               0x00000100L
+#define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK                                                        0x00000200L
+#define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK                                                           0x00010000L
+#define D6VGA_CONTROL__D6VGA_ROTATE_MASK                                                                      0x03000000L
+//VGA_SOURCE_SELECT
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT                                                            0x0
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT                                                            0x8
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK                                                              0x00000007L
+#define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK                                                              0x00000700L
+
+
+// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
+//MCIF_CONTROL
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT                                                   0x1e
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT                                              0x1f
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK                                                     0x40000000L
+#define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK                                                0x80000000L
+//MCIF_WRITE_COMBINE_CONTROL
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT                                         0x0
+#define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK                                           0x000003FFL
+//MCIF_PHASE0_OUTSTANDING_COUNTER
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE0_OUTSTANDING_COUNTER__MCIF_PHASE0_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE1_OUTSTANDING_COUNTER
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE1_OUTSTANDING_COUNTER__MCIF_PHASE1_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+//MCIF_PHASE2_OUTSTANDING_COUNTER
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER__SHIFT                               0x0
+#define MCIF_PHASE2_OUTSTANDING_COUNTER__MCIF_PHASE2_OUTSTANDING_COUNTER_MASK                                 0x07FFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
+//MCIF_WB_BUFMGR_SW_CONTROL
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT                                               0x0
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT                                            0x4
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT                                           0x5
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT                                      0x6
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT                                    0x7
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT                                              0x8
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT                                           0x18
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK                                                 0x00000001L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK                                              0x00000010L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK                                             0x00000020L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK                                        0x00000040L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK                                      0x00000080L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK                                                0x00000F00L
+#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK                                             0x01000000L
+//MCIF_WB_BUFMGR_STATUS
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT                                           0x0
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT                                            0x1
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT                                    0x2
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT                                                  0x4
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT                                             0x7
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT                                                   0x8
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT                                               0xc
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT                                                 0x1c
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK                                             0x00000001L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK                                              0x00000002L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK                                      0x00000004L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK                                                    0x00000070L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK                                               0x00000080L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK                                                     0x00000F00L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK                                                 0x01FFF000L
+#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK                                                   0x70000000L
+//MCIF_WB_BUF_PITCH
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT                                                      0x8
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT                                                    0x18
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK                                                        0x0000FF00L
+#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK                                                      0xFF000000L
+//MCIF_WB_BUF_1_STATUS
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_1_STATUS2
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_2_STATUS
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_2_STATUS2
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_3_STATUS
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_3_STATUS2
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_BUF_4_STATUS
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT                                                  0x1
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT                                                 0x2
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT                                                   0x3
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT                                                    0x4
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT                                                       0x5
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT                                                     0x8
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT                                                    0xc
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT                                                 0x10
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK                                                       0x00000001L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK                                                    0x00000002L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK                                                   0x00000004L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK                                                     0x00000008L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK                                                      0x00000010L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK                                                         0x000000E0L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK                                                       0x00000F00L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK                                                      0x00007000L
+#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK                                                   0x1FFF0000L
+//MCIF_WB_BUF_4_STATUS2
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT                                               0xd
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT                                               0xe
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT                                           0xf
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT                                                       0x10
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT                                                 0x11
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT                                                 0x12
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT                                                  0x13
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK                                                 0x00002000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK                                                 0x00004000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK                                             0x00008000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK                                                         0x00010000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK                                                   0x00020000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK                                                   0x00040000L
+#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK                                                    0x00080000L
+//MCIF_WB_ARBITRATION_CONTROL
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT                                  0x0
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT                                            0x14
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK                                    0x00000003L
+#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK                                              0xFFF00000L
+//MCIF_WB_SCLK_CHANGE
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT                                                    0x0
+#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK                                                      0x00000001L
+//MCIF_WB_TEST_DEBUG_INDEX
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT                                             0x0
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT                                          0x8
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK                                               0x000000FFL
+#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK                                            0x00000100L
+//MCIF_WB_TEST_DEBUG_DATA
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT                                               0x0
+#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK                                                 0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_Y
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_1_ADDR_C
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_Y
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_2_ADDR_C
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_Y
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_3_ADDR_C
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_Y
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUF_4_ADDR_C
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT                                                     0x0
+#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK                                                       0xFFFFFFFFL
+//MCIF_WB_BUFMGR_VCE_CONTROL
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT                                     0x0
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT                                          0x4
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT                                         0x5
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT                                    0x6
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT                                            0x8
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT                                          0x10
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK                                       0x00000001L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK                                            0x00000010L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK                                           0x00000020L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK                                      0x00000040L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK                                              0x00000F00L
+#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK                                            0x1FFF0000L
+//MCIF_WB_NB_PSTATE_CONTROL
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT                              0x0
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT                                           0x1
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT                                          0x2
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK                                0x00000001L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK                                             0x00000002L
+#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK                                            0x00000004L
+//MCIF_WB_CLOCK_GATER_CONTROL
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT                                  0x0
+#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK                                    0x00000001L
+//MCIF_WB_SELF_REFRESH_CONTROL
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ__SHIFT                                         0x0
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT                                            0x1
+#define MCIF_WB_SELF_REFRESH_CONTROL__DIS_REFRESH_UNDER_NBPREQ_MASK                                           0x00000001L
+#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK                                              0x00000002L
+//MULTI_LEVEL_QOS_CTRL
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT                                                0x0
+#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK                                                  0x003FFFFFL
+//MCIF_WB_BUF_LUMA_SIZE
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT                                                   0x0
+#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK                                                     0x000FFFFFL
+//MCIF_WB_BUF_CHROMA_SIZE
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT                                               0x0
+#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK                                                 0x000FFFFFL
+//MCIF_WB_BUF_1_ADDR_Y_HIGH
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_ADDR_C_HIGH
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_Y_HIGH
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_2_ADDR_C_HIGH
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_Y_HIGH
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_3_ADDR_C_HIGH
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_Y_HIGH
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_4_ADDR_C_HIGH
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT                                           0x0
+#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK                                             0x000000FFL
+//MCIF_WB_BUF_1_RESOLUTION
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_2_RESOLUTION
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_3_RESOLUTION
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_BUF_4_RESOLUTION
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT                                       0x0
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT                                      0x10
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK                                         0x00001FFFL
+#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK                                        0x1FFF0000L
+//MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__SHIFT                 0x0
+#define MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI__MCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_MASK                   0x0000FFFFL
+//MCIF_WB_VMID_CONTROL
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT                                                           0x0
+#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK                                                             0x0000000FL
+//MCIF_WB_MIN_TTO
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT                                                               0x0
+#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK                                                                 0x0007FFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON4_PERFCOUNTER_CNTL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_CNTL2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON4_PERFCOUNTER_STATE
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON4_PERFMON_CNTL
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON4_PERFMON_CNTL2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON4_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON4_PERFMON_CVALUE_LOW
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON4_PERFMON_HI
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON4_PERFMON_LOW
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
+//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT                        0x0
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT                           0x18
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK                          0x001FFFFFL
+#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK                             0x07000000L
+//MCIF_WB_WATERMARK
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT                                                       0x0
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT                                                  0x18
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK                                                         0x001FFFFFL
+#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK                                                    0x07000000L
+//MMHUBBUB_WARMUP_CONFIG
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT                                                    0x10
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT                                                   0x14
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK                                                      0x000F0000L
+#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK                                                     0x00F00000L
+//MMHUBBUB_WARMUP_CONTROL_STATUS
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT                                             0x0
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT                                      0x4
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT                                  0x5
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT                                     0x6
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT                                       0x8
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK                                               0x00000001L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK                                        0x00000010L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK                                    0x00000020L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK                                       0x00000040L
+#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK                                         0x03FFFF00L
+//MMHUBBUB_WARMUP_BASE_ADDR_LOW
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT                                   0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK                                     0xFFFFFFFFL
+//MMHUBBUB_WARMUP_BASE_ADDR_HIGH
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT                                 0x0
+#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK                                   0x000007FFL
+//MMHUBBUB_WARMUP_ADDR_REGION
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT                                       0x0
+#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK                                         0x07FFFFFFL
+//MMHUBBUB_MIN_TTO
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT                                                             0x0
+#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK                                                               0x0007FFFFL
+//MMHUBBUB_CTRL
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT                                                            0x0
+#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK                                                              0x00000003L
+//WBIF_SMU_WM_CONTROL
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT                                                        0x14
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT                                                        0x16
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK                                                          0x00300000L
+#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK                                                          0x00400000L
+//WBIF0_MISC_CTRL
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT                                             0x0
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT                                                     0x10
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT                                                   0x18
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT                                                0x19
+#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK                                               0x000003FFL
+#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK                                                       0x00010000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK                                                     0x01000000L
+#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK                                                  0x02000000L
+//WBIF0_PHASE0_OUTSTANDING_COUNTER
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//WBIF0_PHASE1_OUTSTANDING_COUNTER
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT                          0x0
+#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK                            0x07FFFFFFL
+//VGA_SRC_SPLIT_CNTL
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT                                                              0x0
+#define VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK                                                                0x00000003L
+//MMHUBBUB_MEM_PWR_STATUS
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT                                         0x0
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT                                         0x2
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT                                       0x4
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT                                       0x6
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE__SHIFT                                                     0x1f
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK                                           0x00000003L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK                                           0x0000000CL
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK                                         0x00000030L
+#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK                                         0x000000C0L
+#define MMHUBBUB_MEM_PWR_STATUS__VGA_MEM_PWR_STATE_MASK                                                       0x80000000L
+//MMHUBBUB_MEM_PWR_CNTL
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE__SHIFT                                                       0x0
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS__SHIFT                                                         0x1
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT                                                 0x2
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT                                                   0x4
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT                                              0x5
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT                                               0x7
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT                                             0x8
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_FORCE_MASK                                                         0x00000001L
+#define MMHUBBUB_MEM_PWR_CNTL__VGA_MEM_PWR_DIS_MASK                                                           0x00000002L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK                                                   0x0000000CL
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK                                                     0x00000010L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK                                                0x00000060L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK                                                 0x00000080L
+#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK                                               0x00000100L
+//MMHUBBUB_CLOCK_CNTL
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS__SHIFT                                                  0x6
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS__SHIFT                                                   0x7
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT                                                    0x8
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT                                                  0x9
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT                                                   0xa
+#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGAIF_GATE_DIS_MASK                                                    0x00000040L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_VGAIF_GATE_DIS_MASK                                                     0x00000080L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK                                                      0x00000100L
+#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK                                                    0x00000200L
+#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK                                                     0x00000400L
+//MMHUBBUB_SOFT_RESET
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET__SHIFT                                                            0x0
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET__SHIFT                                                          0x1
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT                                                          0x2
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT                                                          0x8
+#define MMHUBBUB_SOFT_RESET__VGA_SOFT_RESET_MASK                                                              0x00000001L
+#define MMHUBBUB_SOFT_RESET__VGAIF_SOFT_RESET_MASK                                                            0x00000002L
+#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK                                                            0x00000004L
+#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK                                                            0x00000100L
+//DMU_IF_ERR_STATUS
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT                                                      0x0
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT                                                  0x4
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK                                                        0x00000001L
+#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK                                                    0x00000010L
+//MMHUBBUB_CLIENT_UNIT_ID
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID__SHIFT                                                           0x0
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT                                                         0x8
+#define MMHUBBUB_CLIENT_UNIT_ID__VGA_UNIT_ID_MASK                                                             0x0000003FL
+#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK                                                           0x00003F00L
+//MMHUBBUB_WARMUP_VMID_CONTROL
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT                                           0x0
+#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK                                             0x0000000FL
+
+
+// addressBlock: dce_dc_hda_azf0controller_dispdec
+//AZALIA_CONTROLLER_CLOCK_GATING
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT                                            0x0
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT                                                 0x4
+#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK                                              0x00000001L
+#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK                                                   0x00000010L
+//AZALIA_AUDIO_DTO
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT                                                       0x0
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT                                                      0x10
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK                                                         0x0000FFFFL
+#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK                                                        0xFFFF0000L
+//AZALIA_AUDIO_DTO_CONTROL
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT                                               0x8
+#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK                                                 0x00000300L
+//AZALIA_SOCCLK_CONTROL
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT                                  0x1
+#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK                                    0x00000002L
+//AZALIA_UNDERFLOW_FILLER_SAMPLE
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT                                 0x0
+#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK                                   0xFFFFFFFFL
+//AZALIA_DATA_DMA_CONTROL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT                                              0x2
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT                                            0x6
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT                                          0x10
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT                                              0x11
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK                                                      0x00000003L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK                                                0x0000000CL
+#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK                                                    0x00000030L
+#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK                                              0x000000C0L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK                                            0x00010000L
+#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK                                                0x00020000L
+//AZALIA_BDL_DMA_CONTROL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT                                                      0x0
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT                                                0x2
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT                                                    0x4
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT                                              0x6
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK                                                        0x00000003L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK                                                  0x0000000CL
+#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK                                                      0x00000030L
+#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK                                                0x000000C0L
+//AZALIA_RIRB_AND_DP_CONTROL
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT                                                     0x0
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT                                                   0x4
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT                                             0x5
+#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK                                                       0x00000001L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK                                                     0x00000010L
+#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK                                               0x000001E0L
+//AZALIA_CORB_DMA_CONTROL
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT                                                    0x0
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT                                                  0x4
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK                                                      0x00000001L
+#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK                                                    0x00000010L
+//AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT            0x0
+#define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK              0xFFFFFFFFL
+//AZALIA_CYCLIC_BUFFER_SYNC
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT                                           0x0
+#define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK                                             0x00000001L
+//AZALIA_GLOBAL_CAPABILITIES
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT                               0x1
+#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK                                 0x00000006L
+//AZALIA_OUTPUT_PAYLOAD_CAPABILITY
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT                                    0x0
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT                                                   0x10
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK                                      0x0000FFFFL
+#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK                                                     0xFFFF0000L
+//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT                                     0x0
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT                                    0x8
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT                               0x10
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK                                       0x000000FFL
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK                                      0x00000100L
+#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK                                 0x00FF0000L
+//AZALIA_INPUT_PAYLOAD_CAPABILITY
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT                                      0x0
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT                                                     0x10
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK                                        0x0000FFFFL
+#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK                                                       0xFFFF0000L
+//AZALIA_INPUT_CRC0_CONTROL0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC0_CONTROL1
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CONTROL2
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC0_CONTROL3
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC0_RESULT
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT                                                       0x0
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT                                               0x4
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT                                             0x8
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK                                                         0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK                                                 0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK                                               0x00000700L
+//AZALIA_INPUT_CRC1_CONTROL1
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT                                               0x0
+#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK                                                 0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CONTROL2
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT                                          0x0
+#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK                                            0x0000FFFFL
+//AZALIA_INPUT_CRC1_CONTROL3
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT                                     0x4
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT                                       0x8
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK                                                   0x00000001L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK                                       0x00000010L
+#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK                                         0x00000700L
+//AZALIA_INPUT_CRC1_RESULT
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT                                                     0x0
+#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK                                                       0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL0
+#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC0_CONTROL1
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC0_CONTROL2
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC0_CONTROL3
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC0_RESULT
+#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL0
+#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT                                                                   0x0
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT                                                           0x4
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT                                                         0x8
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT                                                           0xc
+#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK                                                                     0x00000001L
+#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK                                                             0x00000010L
+#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK                                                           0x00000700L
+#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK                                                             0x00001000L
+//AZALIA_CRC1_CONTROL1
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT                                                           0x0
+#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK                                                             0xFFFFFFFFL
+//AZALIA_CRC1_CONTROL2
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT                                                      0x0
+#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK                                                        0x0000FFFFL
+//AZALIA_CRC1_CONTROL3
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT                                                             0x0
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT                                                 0x4
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT                                                   0x8
+#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK                                                               0x00000001L
+#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK                                                   0x00000010L
+#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK                                                     0x00000700L
+//AZALIA_CRC1_RESULT
+#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT                                                                 0x0
+#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK                                                                   0xFFFFFFFFL
+//AZALIA_MEM_PWR_CTRL
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT                                                          0x0
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT                                                            0x2
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT                                            0x3
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT                                              0x5
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT                                            0x6
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT                                              0x8
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT                                            0x9
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT                                              0xb
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT                                            0xc
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT                                              0xe
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT                                            0xf
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT                                              0x11
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT                                            0x12
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT                                              0x14
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT                                                       0x1c
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK                                                            0x00000003L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK                                                              0x00000004L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK                                              0x00000018L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK                                                0x00000020L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK                                              0x000000C0L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK                                                0x00000100L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK                                              0x00000600L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK                                                0x00000800L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK                                              0x00003000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK                                                0x00004000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK                                              0x00018000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK                                                0x00020000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK                                              0x000C0000L
+#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK                                                0x00100000L
+#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK                                                         0x30000000L
+//AZALIA_MEM_PWR_STATUS
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT                                                        0x0
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT                                          0x2
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT                                          0x4
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT                                          0x6
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT                                          0x8
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT                                          0xa
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT                                          0xc
+#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK                                                          0x00000003L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK                                            0x0000000CL
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK                                            0x00000030L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK                                            0x000000C0L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK                                            0x00000300L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK                                            0x00000C00L
+#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK                                            0x00003000L
+
+
+// addressBlock: dce_dc_hda_azf0root_dispdec
+//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT                                       0x0
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT                                0x4
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK                                         0x00000007L
+#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK                                  0x00000070L
+//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT                        0x0
+#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK                          0x0000003FL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT                                           0x0
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                           0x4
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK                                             0x00000007L
+#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                             0x00000010L
+//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT                               0x0
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT               0x4
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK                                 0x00000007L
+#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                 0x00000010L
+//AZALIA_F0_GTC_GROUP_OFFSET0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET0__GTC_GROUP_OFFSET0_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET1
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET1__GTC_GROUP_OFFSET1_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET2
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET2__GTC_GROUP_OFFSET2_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET3
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET3__GTC_GROUP_OFFSET3_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET4
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET4__GTC_GROUP_OFFSET4_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET5
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET5__GTC_GROUP_OFFSET5_MASK                                                   0xFFFFFFFFL
+//AZALIA_F0_GTC_GROUP_OFFSET6
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6__SHIFT                                                 0x0
+#define AZALIA_F0_GTC_GROUP_OFFSET6__GTC_GROUP_OFFSET6_MASK                                                   0xFFFFFFFFL
+//REG_DC_AUDIO_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT                                          0x0
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT                          0x4
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK                                            0x00000007L
+#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                            0x00000010L
+//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT                              0x0
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT              0x4
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK                                0x00000007L
+#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK                0x00000010L
+
+
+// addressBlock: dce_dc_hda_az_misc_dispdec
+//AZ_CLOCK_CNTL
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT                                                       0x0
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT                                                              0x8
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT                                                         0x10
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT                                                              0x18
+#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK                                                         0x00000001L
+#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK                                                                0x00000100L
+#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK                                                           0x00010000L
+#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK                                                                0x1F000000L
+
+
+// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON5_PERFCOUNTER_CNTL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_CNTL2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON5_PERFCOUNTER_STATE
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON5_PERFMON_CNTL
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON5_PERFMON_CNTL2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON5_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON5_PERFMON_CVALUE_LOW
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON5_PERFMON_HI
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON5_PERFMON_LOW
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream0_dispdec
+//AZF0STREAM0_AZALIA_STREAM_INDEX
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM0_AZALIA_STREAM_DATA
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream1_dispdec
+//AZF0STREAM1_AZALIA_STREAM_INDEX
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM1_AZALIA_STREAM_DATA
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream2_dispdec
+//AZF0STREAM2_AZALIA_STREAM_INDEX
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM2_AZALIA_STREAM_DATA
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream3_dispdec
+//AZF0STREAM3_AZALIA_STREAM_INDEX
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM3_AZALIA_STREAM_DATA
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream4_dispdec
+//AZF0STREAM4_AZALIA_STREAM_INDEX
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM4_AZALIA_STREAM_DATA
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream5_dispdec
+//AZF0STREAM5_AZALIA_STREAM_INDEX
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM5_AZALIA_STREAM_DATA
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream6_dispdec
+//AZF0STREAM6_AZALIA_STREAM_INDEX
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM6_AZALIA_STREAM_DATA
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream7_dispdec
+//AZF0STREAM7_AZALIA_STREAM_INDEX
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM7_AZALIA_STREAM_DATA
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream8_dispdec
+//AZF0STREAM8_AZALIA_STREAM_INDEX
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM8_AZALIA_STREAM_DATA
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream9_dispdec
+//AZF0STREAM9_AZALIA_STREAM_INDEX
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                       0x0
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                    0x8
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                         0x000000FFL
+#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                      0x00000100L
+//AZF0STREAM9_AZALIA_STREAM_DATA
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                         0x0
+#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream10_dispdec
+//AZF0STREAM10_AZALIA_STREAM_INDEX
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM10_AZALIA_STREAM_DATA
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream11_dispdec
+//AZF0STREAM11_AZALIA_STREAM_INDEX
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM11_AZALIA_STREAM_DATA
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream12_dispdec
+//AZF0STREAM12_AZALIA_STREAM_INDEX
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM12_AZALIA_STREAM_DATA
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream13_dispdec
+//AZF0STREAM13_AZALIA_STREAM_INDEX
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM13_AZALIA_STREAM_DATA
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream14_dispdec
+//AZF0STREAM14_AZALIA_STREAM_INDEX
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM14_AZALIA_STREAM_DATA
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0stream15_dispdec
+//AZF0STREAM15_AZALIA_STREAM_INDEX
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT                                      0x0
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT                                   0x8
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK                                        0x000000FFL
+#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK                                     0x00000100L
+//AZF0STREAM15_AZALIA_STREAM_DATA
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT                                        0x0
+#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT                        0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK                          0x00003FFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK         0x00003FFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT         0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_dispdec
+//DCHUBBUB_ARB_DF_REQ_OUTSTAND
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT                                    0x0
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT                                    0xc
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT                   0x17
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK                                      0x000001FFL
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK                                      0x001FF000L
+#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK                     0xFF800000L
+//DCHUBBUB_ARB_SAT_LEVEL
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT                                                 0x0
+#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK                                                   0xFFFFFFFFL
+//DCHUBBUB_ARB_QOS_FORCE
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT                                           0x0
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT                                          0x8
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT                                          0xc
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK                                             0x0000000FL
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK                                            0x00000100L
+#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK                                            0x0000F000L
+//DCHUBBUB_ARB_DRAM_STATE_CNTL
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT                      0x0
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT                     0x1
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT                     0x4
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT                    0x5
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST__SHIFT  0x8
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL__SHIFT  0x9
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT                                 0xc
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK                        0x00000001L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK                       0x00000002L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK                       0x00000010L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK                      0x00000020L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_AND_SELF_REFRESH_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_MASK  0x00000100L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_FORCE_URGENCY_DURING_DRAM_CLOCK_NBPSTATE_CHANGE_REQUEST_REGARDLESS_OF_ALLOW_SIGNAL_MASK  0x00000200L
+#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK                                   0x00001000L
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT                   0x0
+#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK                     0x00003FFFL
+//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT             0x0
+#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK               0x00003FFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT               0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK                 0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT         0x0
+#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK           0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT                 0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK                   0x0000FFFFL
+//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT           0x0
+#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK             0x000FFFFFL
+//DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__SHIFT  0x0
+#define DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D__DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_MASK   0x0000FFFFL
+//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT                                 0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK                                   0x000003FFL
+//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT                               0x0
+#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK                                 0x000003FFL
+//DCHUBBUB_ARB_HOSTVM_CNTL
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT                                          0x0
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT                                    0x1
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT                                                       0x2
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT                                                  0x3
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT                                                  0x4
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT                                           0x5
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT                                         0x6
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT                                          0x8
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT                                           0x10
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT                                                           0x18
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT                                0x1c
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK                                            0x00000001L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK                                      0x00000002L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK                                                         0x00000004L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK                                                    0x00000008L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK                                                    0x00000010L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK                                             0x00000020L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK                                           0x00000040L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK                                            0x00003F00L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK                                             0x00FF0000L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK                                                             0x0F000000L
+#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK                                  0xF0000000L
+//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT                       0x0
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT       0x4
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT        0x5
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT                      0x8
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT                    0x10
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK                         0x00000003L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK         0x00000010L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK          0x00000020L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK                        0x00000100L
+#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK                      0x00010000L
+//DCHUBBUB_ARB_TIMEOUT_ENABLE
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT                                       0x0
+#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK                                         0x00000001L
+//DCHUBBUB_GLOBAL_TIMER_CNTL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT                                       0x0
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT                                       0xc
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT                                         0x10
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK                                         0x0000000FL
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK                                         0x00001000L
+#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK                                           0xFFFF0000L
+//SURFACE_CHECK0_ADDRESS_LSB
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK0_ADDRESS_MSB
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK1_ADDRESS_LSB
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK1_ADDRESS_MSB
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK2_ADDRESS_LSB
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK2_ADDRESS_MSB
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK                                               0x80000000L
+//SURFACE_CHECK3_ADDRESS_LSB
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK                                           0xFFFFFFFFL
+//SURFACE_CHECK3_ADDRESS_MSB
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT                                         0x0
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT                                             0x1f
+#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK                                           0x0000FFFFL
+#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK                                               0x80000000L
+//VTG0_CONTROL
+#define VTG0_CONTROL__VTG0_FP2__SHIFT                                                                         0x0
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG0_CONTROL__VTG0_ENABLE__SHIFT                                                                      0x1f
+#define VTG0_CONTROL__VTG0_FP2_MASK                                                                           0x00007FFFL
+#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG0_CONTROL__VTG0_ENABLE_MASK                                                                        0x80000000L
+//VTG1_CONTROL
+#define VTG1_CONTROL__VTG1_FP2__SHIFT                                                                         0x0
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG1_CONTROL__VTG1_ENABLE__SHIFT                                                                      0x1f
+#define VTG1_CONTROL__VTG1_FP2_MASK                                                                           0x00007FFFL
+#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG1_CONTROL__VTG1_ENABLE_MASK                                                                        0x80000000L
+//VTG2_CONTROL
+#define VTG2_CONTROL__VTG2_FP2__SHIFT                                                                         0x0
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG2_CONTROL__VTG2_ENABLE__SHIFT                                                                      0x1f
+#define VTG2_CONTROL__VTG2_FP2_MASK                                                                           0x00007FFFL
+#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG2_CONTROL__VTG2_ENABLE_MASK                                                                        0x80000000L
+//VTG3_CONTROL
+#define VTG3_CONTROL__VTG3_FP2__SHIFT                                                                         0x0
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT                                                                 0x10
+#define VTG3_CONTROL__VTG3_ENABLE__SHIFT                                                                      0x1f
+#define VTG3_CONTROL__VTG3_FP2_MASK                                                                           0x00007FFFL
+#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK                                                                   0x7FFF0000L
+#define VTG3_CONTROL__VTG3_ENABLE_MASK                                                                        0x80000000L
+//DCHUBBUB_SOFT_RESET
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT                                                0x0
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT                                                   0x1
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT                                                        0x4
+#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK                                                  0x00000001L
+#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK                                                     0x00000002L
+#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK                                                          0x00000010L
+//DCHUBBUB_CLOCK_CNTL
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT                                                     0x0
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                               0x5
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT                                                0x6
+#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK                                                       0x0000001FL
+#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK                                                 0x00000020L
+#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK                                                  0x00000040L
+//DCFCLK_CNTL
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT                                                              0x0
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT                                                             0x4
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT                                                                   0x1f
+#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK                                                                0x0000000FL
+#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK                                                               0x00000FF0L
+#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK                                                                     0x80000000L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT                                 0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT            0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT                         0x2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT                                    0x3
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT                                0x7
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT                                  0xa
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT                                          0xb
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK                                   0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK              0x00000002L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK                           0x00000004L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK                                      0x00000078L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK                                  0x00000380L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK                                    0x00000400L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK                                            0x003FF800L
+//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT                          0x0
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT                     0x1
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT                         0x4
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT                                     0xc
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT                                     0x13
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT                               0x1f
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK                            0x00000001L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK                       0x0000000EL
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK                           0x00000FF0L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK                                       0x00007000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK                                       0x3FF80000L
+#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK                                 0x80000000L
+//DCHUBBUB_VLINE_SNAPSHOT
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT                                               0x0
+#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK                                                 0x00000001L
+//DCHUBBUB_CTRL_STATUS
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT                                                  0x0
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT                                                      0x2
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT                                                       0x3
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT                                               0x1f
+#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK                                                    0x00000001L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK                                                        0x00000004L
+#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK                                                         0x00000008L
+#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK                                                 0x80000000L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL1
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT                                0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT                         0x6
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK                                  0x0000003FL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK                           0xFFFFFFC0L
+//DCHUBBUB_TIMEOUT_DETECTION_CTRL2
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT                      0x0
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT                                0x1b
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT                                 0x1c
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK                        0x07FFFFFFL
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK                                  0x08000000L
+#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK                                   0x10000000L
+//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT                                 0x0
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT                                 0x1
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT                                  0x2
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT                                   0x3
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK                                   0x00000001L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK                                   0x00000002L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK                                    0x00000004L
+#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK                                     0x000000F8L
+//FMON_CTRL
+#define FMON_CTRL__FMON_START__SHIFT                                                                          0x0
+#define FMON_CTRL__FMON_MODE__SHIFT                                                                           0x1
+#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT                                                                  0x4
+#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT                                                                  0x5
+#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT                                                               0x6
+#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT                                                                  0x7
+#define FMON_CTRL__FMON_STATE__SHIFT                                                                          0x9
+#define FMON_CTRL__FMON_URG_FILTER__SHIFT                                                                     0xc
+#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT                                                                  0xd
+#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT                                                                   0x11
+#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT                                                                   0x16
+#define FMON_CTRL__FMON_SOF_SEL__SHIFT                                                                        0x1b
+#define FMON_CTRL__FMON_START_MASK                                                                            0x00000001L
+#define FMON_CTRL__FMON_MODE_MASK                                                                             0x00000006L
+#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK                                                                    0x00000010L
+#define FMON_CTRL__FMON_STATUS_IGNORE_MASK                                                                    0x00000020L
+#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK                                                                 0x00000040L
+#define FMON_CTRL__FMON_FILTER_UID_EN_MASK                                                                    0x00000180L
+#define FMON_CTRL__FMON_STATE_MASK                                                                            0x00000600L
+#define FMON_CTRL__FMON_URG_FILTER_MASK                                                                       0x00001000L
+#define FMON_CTRL__FMON_URG_THRESHOLD_MASK                                                                    0x0001E000L
+#define FMON_CTRL__FMON_FILTER_UID_1_MASK                                                                     0x003E0000L
+#define FMON_CTRL__FMON_FILTER_UID_2_MASK                                                                     0x07C00000L
+#define FMON_CTRL__FMON_SOF_SEL_MASK                                                                          0x38000000L
+//DCHUBBUB_TEST_DEBUG_INDEX
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT                                           0x0
+#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK                                             0x000000FFL
+//DCHUBBUB_TEST_DEBUG_DATA
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT                                             0x0
+#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
+//DCHUBBUB_SDPIF_CFG0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT                                                         0x1
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT                                                0x3
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT                                                     0x6
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT                                                    0xa
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT                                               0xb
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT                                              0xc
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT                                                 0xd
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT                                                       0xe
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT                                                        0xf
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT                                             0x19
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK                                                    0x00000001L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK                                                           0x00000006L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK                                                  0x00000038L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK                                                       0x000003C0L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK                                                      0x00000400L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK                                                 0x00000800L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK                                                0x00001000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK                                                   0x00002000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK                                                         0x00004000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK                                                          0x00008000L
+#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK                                               0x7E000000L
+//DCHUBBUB_SDPIF_CFG1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT                                                    0x1
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT                                              0x2
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT                                                         0x8
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK                                                   0x00000001L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK                                                      0x00000002L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK                                                0x00000004L
+#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK                                                           0x00000100L
+//DCHUBBUB_SDPIF_CFG2
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT                                                         0x0
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT                                                     0x10
+#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK                                                           0x00000001L
+#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK                                                       0x01FF0000L
+//VM_REQUEST_PHYSICAL
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT                                                      0x0
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT                                                      0x3
+#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK                                                        0x00000001L
+#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK                                                        0x00000008L
+//DCHUBBUB_FORCE_IO_STATUS_0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT                                              0x0
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT                                       0x1
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT                                        0x2
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT                                      0x3
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT                                 0x7
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT                                      0xa
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK                                                0x00000001L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK                                         0x00000002L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK                                          0x00000004L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK                                        0x00000078L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK                                   0x00000380L
+#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK                                        0xFFFFFC00L
+//DCHUBBUB_FORCE_IO_STATUS_1
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT                                      0x0
+#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK                                        0x001FFFFFL
+//DCN_VM_FB_LOCATION_BASE
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                               0x0
+#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                 0x00FFFFFFL
+//DCN_VM_FB_LOCATION_TOP
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                 0x0
+#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                   0x00FFFFFFL
+//DCN_VM_FB_OFFSET
+#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                    0x0
+#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK                                                                      0x00FFFFFFL
+//DCN_VM_AGP_BOT
+#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT                                                                        0x0
+#define DCN_VM_AGP_BOT__AGP_BOT_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_TOP
+#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT                                                                        0x0
+#define DCN_VM_AGP_TOP__AGP_TOP_MASK                                                                          0x00FFFFFFL
+//DCN_VM_AGP_BASE
+#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT                                                                      0x0
+#define DCN_VM_AGP_BASE__AGP_BASE_MASK                                                                        0x00FFFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_START
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT                                                  0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK                                                    0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_END
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT                                                      0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK                                                        0x000FFFFFL
+//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
+#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
+//DCHUBBUB_SDPIF_MEM_PWR_CTRL
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT                                      0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT                                        0x2
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK                                        0x00000003L
+#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK                                          0x00000004L
+//DCHUBBUB_SDPIF_MEM_PWR_STATUS
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT                                    0x0
+#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK                                      0x00000003L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec
+//DCHUBBUB_RET_PATH_DCC_CFG
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN__SHIFT                                                 0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG__DCC_VIDEO_FORMAT_EN_MASK                                                   0x00000001L
+//DCHUBBUB_RET_PATH_DCC_CFG0_0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_0__DCC_CFG0_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG0_1
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG0_1__DCC_CFG0_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_0__DCC_CFG1_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG1_1
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG1_1__DCC_CFG1_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_0__DCC_CFG2_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG2_1
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG2_1__DCC_CFG2_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_0__DCC_CFG3_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG3_1
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG3_1__DCC_CFG3_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_0__DCC_CFG4_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG4_1
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG4_1__DCC_CFG4_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_0__DCC_CFG5_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG5_1
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG5_1__DCC_CFG5_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_0__DCC_CFG6_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG6_1
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG6_1__DCC_CFG6_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_0__DCC_CFG7_CONSTANT_0_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_DCC_CFG7_1
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1__SHIFT                                              0x0
+#define DCHUBBUB_RET_PATH_DCC_CFG7_1__DCC_CFG7_CONSTANT_1_MASK                                                0xFFFFFFFFL
+//DCHUBBUB_RET_PATH_MEM_PWR_CTRL
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT                                0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT                                  0x2
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK                                  0x00000003L
+#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK                                    0x00000004L
+//DCHUBBUB_RET_PATH_MEM_PWR_STATUS
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT                              0x0
+#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK                                0x00000003L
+//DCHUBBUB_CRC_CTRL
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT                                                             0x0
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT                                                        0x1
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT                                              0x2
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT                                              0x3
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT                                                       0x4
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT                                                       0x6
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT                                                       0x8
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT                                                       0xc
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT                                                   0x14
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK                                                               0x00000001L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK                                                          0x00000002L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK                                                0x00000004L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK                                                0x00000008L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK                                                         0x00000030L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK                                                         0x000000C0L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK                                                         0x00000F00L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK                                                         0x00001000L
+#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK                                                     0x00100000L
+//DCHUBBUB_CRC0_VAL_R_G
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_R_G__DCHUBBUB_CRC0_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC0_VAL_B_A
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC0_VAL_B_A__DCHUBBUB_CRC0_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_R_G
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y__SHIFT                                                       0x10
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_R_CR_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_R_G__DCHUBBUB_CRC1_G_Y_MASK                                                         0xFFFF0000L
+//DCHUBBUB_CRC1_VAL_B_A
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB__SHIFT                                                      0x0
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA__SHIFT                                                     0x10
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_B_CB_MASK                                                        0x0000FFFFL
+#define DCHUBBUB_CRC1_VAL_B_A__DCHUBBUB_CRC1_ALPHA_MASK                                                       0xFFFF0000L
+//DCHUBBUB_DCC_STAT_CNTL
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT                                                 0x0
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT                                                   0x1
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT                                                 0x2
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT                                             0x4
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT                                            0x10
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK                                                   0x00000001L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK                                                     0x00000002L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK                                                   0x00000004L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK                                               0x000000F0L
+#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK                                              0xFFFF0000L
+//DCHUBBUB_DCC_STAT0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT                                                0x0
+#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK                                                  0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT1
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT                                                   0x0
+#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK                                                     0xFFFFFFFFL
+//DCHUBBUB_DCC_STAT2
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT                                                  0x0
+#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK                                                    0xFFFFFFFFL
+//DCHUBBUB_COMPBUF_CTRL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT                                                            0x0
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT                                                    0x8
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT                                     0x10
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT                                     0x12
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT                                      0x13
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT                                                            0x1f
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK                                                              0x0000001FL
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK                                                      0x00001F00L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK                                       0x00010000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK                                       0x00040000L
+#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK                                        0x00080000L
+#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK                                                              0x80000000L
+//DCHUBBUB_DET0_CTRL
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_DET1_CTRL
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_DET2_CTRL
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_DET3_CTRL
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT                                                                  0x0
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT                                                          0x8
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK                                                                    0x00000007L
+#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK                                                            0x00000700L
+//DCHUBBUB_MEM_PWR_MODE_CTRL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT                                        0x0
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT                                        0x2
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT                                          0x4
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT                                             0x6
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT                                             0x8
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT                                           0xa
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT                                                  0x10
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT                                              0x12
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT                                                0x14
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT                                                0x18
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT                                               0x19
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT                                               0x1a
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK                                          0x00000003L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK                                          0x0000000CL
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK                                            0x00000030L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK                                               0x000000C0L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK                                             0x00000C00L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK                                                    0x00030000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK                                                0x000C0000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK                                                  0x00300000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK                                                  0x01000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK                                                 0x02000000L
+#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK                                                 0x04000000L
+//COMPBUF_MEM_PWR_CTRL_1
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT                                            0x0
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT                                           0x8
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT                                              0x10
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT                                             0x18
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK                                              0x000000FFL
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK                                             0x0000FF00L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK                                                0x00FF0000L
+#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK                                               0xFF000000L
+//COMPBUF_MEM_PWR_CTRL_2
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT                                       0x0
+#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK                                         0x000000FFL
+//DCHUBBUB_MEM_PWR_STATUS
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT                                                 0x0
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT                                                0x2
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT                                             0x4
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT                                                0x6
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT                                                    0x8
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT                                                    0xa
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT                                                    0xc
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT                                                    0xe
+#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK                                                   0x00000003L
+#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK                                                  0x0000000CL
+#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK                                               0x00000030L
+#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK                                                  0x000000C0L
+#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK                                                      0x00000300L
+#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK                                                      0x00000C00L
+#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK                                                      0x00003000L
+#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK                                                      0x0000C000L
+//COMPBUF_RESERVED_SPACE
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT                                             0x0
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT                                              0x10
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK                                               0x00000FFFL
+#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK                                                0x0FFF0000L
+
+
+// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec
+//DCN_VM_CONTEXT0_CNTL
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT1_CNTL
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT2_CNTL
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT3_CNTL
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT4_CNTL
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT5_CNTL
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT6_CNTL
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT7_CNTL
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT8_CNTL
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT9_CNTL
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT                                             0x1
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT                                        0x3
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK                                               0x00000006L
+#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK                                          0x00000078L
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT               0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK                 0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT          0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK            0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT         0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK           0xFFFFFFFFL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT              0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK                0x0000000FL
+//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_CNTL
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT11_CNTL
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT12_CNTL
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT13_CNTL
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT14_CNTL
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_CONTEXT15_CNTL
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT                                           0x1
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT                                      0x3
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK                                             0x00000006L
+#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK                                        0x00000078L
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT             0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK               0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT        0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK          0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT       0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK         0xFFFFFFFFL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT            0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK              0x0000000FL
+//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT           0x0
+#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK             0xFFFFFFFFL
+//DCN_VM_DEFAULT_ADDR_MSB
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT                                                    0x1c
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT                                                  0x1d
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK                                                 0x0000000FL
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK                                                      0x10000000L
+#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK                                                    0x20000000L
+//DCN_VM_DEFAULT_ADDR_LSB
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT                                               0x0
+#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK                                                 0xFFFFFFFFL
+//DCN_VM_FAULT_CNTL
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT                                                   0x0
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT                                                    0x1
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT                                               0x2
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT                                                  0x8
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT                                                    0x9
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK                                                     0x00000001L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK                                                      0x00000002L
+#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK                                                 0x00000004L
+#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK                                                    0x00000100L
+#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK                                                      0x00000200L
+//DCN_VM_FAULT_STATUS
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT                                                       0x0
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT                                                         0x10
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT                                                 0x14
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT                                                  0x18
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT                                                         0x1a
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT                                             0x1f
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK                                                         0x0000FFFFL
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK                                                           0x000F0000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK                                                   0x00F00000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK                                                    0x03000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK                                                           0x3C000000L
+#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK                                               0x80000000L
+//DCN_VM_FAULT_ADDR_MSB
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK                                                     0x0000000FL
+//DCN_VM_FAULT_ADDR_LSB
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT                                                   0x0
+#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK                                                     0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON6_PERFCOUNTER_CNTL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_CNTL2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON6_PERFCOUNTER_STATE
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON6_PERFMON_CNTL
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON6_PERFMON_CNTL2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON6_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON6_PERFMON_CVALUE_LOW
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON6_PERFMON_HI
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON6_PERFMON_LOW
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
+//HUBP0_DCSURF_SURFACE_CONFIG
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP0_DCSURF_ADDR_CONFIG
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP0_DCSURF_TILING_CONFIG
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP0_DCSURF_PRI_VIEWPORT_START
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP0_DCHUBP_CNTL
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP0_HUBP_CLK_CNTL
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP0_DCHUBP_VMPG_CONFIG
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP0_HUBPREQ_DEBUG_DB
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP0_HUBPREQ_DEBUG
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
+//HUBPREQ0_DCSURF_SURFACE_PITCH
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ0_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ0_VMID_SETTINGS_0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ0_DCSURF_SURFACE_CONTROL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ0_DCSURF_FLIP_CONTROL2
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ0_DCN_EXPANSION_MODE
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ0_DCN_TTU_QOS_WM
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ0_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ0_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ0_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ0_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ0_DCN_DMDATA_VM_CNTL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT                                              0x0
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT                                            0x10
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT                                      0x14
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT                                        0x18
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT                                             0x19
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT                                  0x1a
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT                                                    0x1f
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK                                                0x0000FFFFL
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK                                              0x000F0000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK                                        0x00100000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK                                          0x01000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK                                               0x02000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK                                    0x04000000L
+#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK                                                      0x80000000L
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ0_BLANK_OFFSET_0
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ0_BLANK_OFFSET_1
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ0_DST_DIMENSIONS
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ0_DST_AFTER_SCALER
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ0_PREFETCH_SETTINGS
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ0_PREFETCH_SETTINGS_C
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ0_VBLANK_PARAMETERS_1
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_2
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_3
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_4
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ0_FLIP_PARAMETERS_1
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_2
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_1
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_2
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_3
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_4
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_5
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ0_NOM_PARAMETERS_6
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ0_NOM_PARAMETERS_7
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ0_PER_LINE_DELIVERY_PRE
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ0_PER_LINE_DELIVERY
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ0_CURSOR_SETTINGS
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ0_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ0_VBLANK_PARAMETERS_5
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ0_VBLANK_PARAMETERS_6
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_3
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_4
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_5
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ0_FLIP_PARAMETERS_6
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
+//HUBPRET0_HUBPRET_CONTROL
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET0_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET0_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET0_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET0_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET0_HUBPRET_READ_LINE0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE1
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET0_HUBPRET_INTERRUPT
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET0_HUBPRET_READ_LINE_VALUE
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET0_HUBPRET_READ_LINE_STATUS
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
+//CURSOR0_0_CURSOR_CONTROL
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_0_CURSOR_SIZE
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_0_CURSOR_POSITION
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_0_CURSOR_HOT_SPOT
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_0_CURSOR_STEREO_CONTROL
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_0_CURSOR_DST_OFFSET
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_0_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_0_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_0_DMDATA_ADDRESS_HIGH
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_0_DMDATA_ADDRESS_LOW
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_0_DMDATA_CNTL
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_0_DMDATA_QOS_CNTL
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_0_DMDATA_STATUS
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_0_DMDATA_SW_CNTL
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_0_DMDATA_SW_DATA
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON7_PERFCOUNTER_CNTL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_CNTL2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON7_PERFCOUNTER_STATE
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON7_PERFMON_CNTL
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON7_PERFMON_CNTL2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON7_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON7_PERFMON_CVALUE_LOW
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON7_PERFMON_HI
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON7_PERFMON_LOW
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
+//HUBP1_DCSURF_SURFACE_CONFIG
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP1_DCSURF_ADDR_CONFIG
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP1_DCSURF_TILING_CONFIG
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP1_DCSURF_PRI_VIEWPORT_START
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP1_DCHUBP_CNTL
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP1_HUBP_CLK_CNTL
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP1_DCHUBP_VMPG_CONFIG
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP1_HUBPREQ_DEBUG_DB
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP1_HUBPREQ_DEBUG
+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
+//HUBPREQ1_DCSURF_SURFACE_PITCH
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ1_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ1_VMID_SETTINGS_0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ1_DCSURF_SURFACE_CONTROL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ1_DCSURF_FLIP_CONTROL2
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ1_DCN_EXPANSION_MODE
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ1_DCN_TTU_QOS_WM
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ1_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ1_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ1_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ1_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ1_BLANK_OFFSET_0
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ1_BLANK_OFFSET_1
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ1_DST_DIMENSIONS
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ1_DST_AFTER_SCALER
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ1_PREFETCH_SETTINGS
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ1_PREFETCH_SETTINGS_C
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ1_VBLANK_PARAMETERS_1
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_2
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_3
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_4
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ1_FLIP_PARAMETERS_1
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_2
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_1
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_2
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_3
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_4
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_5
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ1_NOM_PARAMETERS_6
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ1_NOM_PARAMETERS_7
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ1_PER_LINE_DELIVERY_PRE
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ1_PER_LINE_DELIVERY
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ1_CURSOR_SETTINGS
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ1_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ1_VBLANK_PARAMETERS_5
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ1_VBLANK_PARAMETERS_6
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_3
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_4
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_5
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ1_FLIP_PARAMETERS_6
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
+//HUBPRET1_HUBPRET_CONTROL
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET1_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET1_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET1_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET1_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET1_HUBPRET_READ_LINE0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE1
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET1_HUBPRET_INTERRUPT
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET1_HUBPRET_READ_LINE_VALUE
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET1_HUBPRET_READ_LINE_STATUS
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
+//CURSOR0_1_CURSOR_CONTROL
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_1_CURSOR_SIZE
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_1_CURSOR_POSITION
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_1_CURSOR_HOT_SPOT
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_1_CURSOR_STEREO_CONTROL
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_1_CURSOR_DST_OFFSET
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_1_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_1_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_1_DMDATA_ADDRESS_HIGH
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_1_DMDATA_ADDRESS_LOW
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_1_DMDATA_CNTL
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_1_DMDATA_QOS_CNTL
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_1_DMDATA_STATUS
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_1_DMDATA_SW_CNTL
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_1_DMDATA_SW_DATA
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON8_PERFCOUNTER_CNTL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_CNTL2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON8_PERFCOUNTER_STATE
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON8_PERFMON_CNTL
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON8_PERFMON_CNTL2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON8_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON8_PERFMON_CVALUE_LOW
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON8_PERFMON_HI
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON8_PERFMON_LOW
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
+//HUBP2_DCSURF_SURFACE_CONFIG
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP2_DCSURF_ADDR_CONFIG
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP2_DCSURF_TILING_CONFIG
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP2_DCSURF_PRI_VIEWPORT_START
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP2_DCHUBP_CNTL
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP2_HUBP_CLK_CNTL
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP2_DCHUBP_VMPG_CONFIG
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP2_HUBPREQ_DEBUG_DB
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP2_HUBPREQ_DEBUG
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
+//HUBPREQ2_DCSURF_SURFACE_PITCH
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ2_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ2_VMID_SETTINGS_0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ2_DCSURF_SURFACE_CONTROL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ2_DCSURF_FLIP_CONTROL2
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ2_DCN_EXPANSION_MODE
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ2_DCN_TTU_QOS_WM
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ2_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ2_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ2_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ2_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ2_BLANK_OFFSET_0
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ2_BLANK_OFFSET_1
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ2_DST_DIMENSIONS
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ2_DST_AFTER_SCALER
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ2_PREFETCH_SETTINGS
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ2_PREFETCH_SETTINGS_C
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ2_VBLANK_PARAMETERS_1
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_2
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_3
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_4
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ2_FLIP_PARAMETERS_1
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_2
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_1
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_2
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_3
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_4
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_5
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ2_NOM_PARAMETERS_6
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ2_NOM_PARAMETERS_7
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ2_PER_LINE_DELIVERY_PRE
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ2_PER_LINE_DELIVERY
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ2_CURSOR_SETTINGS
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ2_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ2_VBLANK_PARAMETERS_5
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ2_VBLANK_PARAMETERS_6
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_3
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_4
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_5
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ2_FLIP_PARAMETERS_6
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
+//HUBPRET2_HUBPRET_CONTROL
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET2_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET2_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET2_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET2_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET2_HUBPRET_READ_LINE0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE1
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET2_HUBPRET_INTERRUPT
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET2_HUBPRET_READ_LINE_VALUE
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET2_HUBPRET_READ_LINE_STATUS
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
+//CURSOR0_2_CURSOR_CONTROL
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_2_CURSOR_SIZE
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_2_CURSOR_POSITION
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_2_CURSOR_HOT_SPOT
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_2_CURSOR_STEREO_CONTROL
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_2_CURSOR_DST_OFFSET
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_2_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_2_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_2_DMDATA_ADDRESS_HIGH
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_2_DMDATA_ADDRESS_LOW
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_2_DMDATA_CNTL
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_2_DMDATA_QOS_CNTL
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_2_DMDATA_STATUS
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_2_DMDATA_SW_CNTL
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_2_DMDATA_SW_DATA
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON9_PERFCOUNTER_CNTL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                            0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                           0x9
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                             0xc
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                          0xf
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                           0x10
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                     0x16
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                           0x17
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                               0x18
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                             0x19
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                               0x1a
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                             0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                              0x000001FFL
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                             0x00000E00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                               0x00007000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                            0x00008000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                             0x00010000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                       0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                             0x00800000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                 0x01000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                               0x02000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                 0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                               0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_CNTL2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                  0x0
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                        0x3
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                           0x1d
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                    0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                          0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                          0x00000008L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                            0x00003F00L
+#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                             0xE0000000L
+//DC_PERFMON9_PERFCOUNTER_STATE
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                          0x0
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                          0x2
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                          0x4
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                          0x6
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                          0x8
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                          0xa
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                          0xc
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                          0xe
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                          0x10
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                          0x12
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                          0x14
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                          0x16
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                          0x18
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                          0x1a
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                          0x1c
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                          0x1e
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                            0x00000003L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                            0x00000004L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                            0x00000030L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                            0x00000040L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                            0x00000300L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                            0x00000400L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                            0x00003000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                            0x00004000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                            0x00030000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                            0x00040000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                            0x00300000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                            0x00400000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                            0x03000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                            0x04000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                            0x30000000L
+#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                            0x40000000L
+//DC_PERFMON9_PERFMON_CNTL
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                        0x0
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                    0x8
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                                0x1c
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                                0x1d
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                            0x1e
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                               0x1f
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK                                                          0x00000003L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                      0x0FFFFF00L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                  0x10000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                  0x20000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                              0x40000000L
+#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                 0x80000000L
+//DC_PERFMON9_PERFMON_CNTL2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                  0x1
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                        0x2
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                         0xa
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                               0x00000001L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                    0x00000002L
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                          0x000003FCL
+#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                           0x0003FC00L
+//DC_PERFMON9_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                   0x0
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                   0x1
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                   0x2
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                   0x3
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                   0x4
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                   0x5
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                   0x6
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                   0x7
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                      0x8
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                      0x9
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                      0xa
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                      0xb
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                      0xc
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                      0xd
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                      0xe
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                      0xf
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                         0x10
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                     0x00000001L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                     0x00000002L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                     0x00000004L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                     0x00000008L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                     0x00000010L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                     0x00000020L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                     0x00000040L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                     0x00000080L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                        0x00000100L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                        0x00000200L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                        0x00000400L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                        0x00000800L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                        0x00001000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                        0x00002000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                        0x00004000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                        0x00008000L
+#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                           0xFFFF0000L
+//DC_PERFMON9_PERFMON_CVALUE_LOW
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                             0x0
+#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                               0xFFFFFFFFL
+//DC_PERFMON9_PERFMON_HI
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT                                                             0x0
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                       0x1d
+#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK                                                               0x0000FFFFL
+#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK                                                         0xE0000000L
+//DC_PERFMON9_PERFMON_LOW
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT                                                           0x0
+#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
+//HUBP3_DCSURF_SURFACE_CONFIG
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT                                              0x0
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT                                                    0x8
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT                                                       0xa
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT                                                    0xb
+#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK                                                0x0000007FL
+#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK                                                      0x00000300L
+#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK                                                         0x00000400L
+#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK                                                      0x00000800L
+//HUBP3_DCSURF_ADDR_CONFIG
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT                                                            0x0
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT                                                      0x6
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT                                                 0xc
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT                                                             0x10
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK                                                              0x00000007L
+#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK                                                        0x000000C0L
+#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK                                                   0x00003000L
+#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK                                                               0x00070000L
+//HUBP3_DCSURF_TILING_CONFIG
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT                                                            0x0
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT                                                           0x7
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT                                                        0x9
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT                                                       0xb
+#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK                                                              0x0000001FL
+#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK                                                             0x00000180L
+#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK                                                          0x00000200L
+#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK                                                         0x00000800L
+//HUBP3_DCSURF_PRI_VIEWPORT_START
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_START_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT                                          0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT                                          0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK                                            0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK                                            0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT                                        0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT                                       0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_START_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT                                      0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT                                      0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK                                        0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK                                        0x3FFF0000L
+//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT                                    0x0
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT                                   0x10
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK                                      0x00003FFFL
+#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK                                     0x3FFF0000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT                                                     0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT                                            0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT                                                       0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT                                                  0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT                                              0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT                                                  0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT                                                    0x18
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK                                                       0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK                                              0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK                                                         0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK                                                     0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK                                                    0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK                                                0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK                                                    0x00700000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK                                                      0x07000000L
+//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT                                                 0x0
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT                                        0x4
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT                                                   0x8
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT                                               0xb
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT                                              0x10
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT                                          0x12
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT                                              0x14
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK                                                   0x00000007L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK                                          0x00000070L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK                                                     0x00000700L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK                                                 0x00001800L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK                                                0x00030000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK                                            0x000C0000L
+#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK                                                0x00700000L
+//HUBP3_DCHUBP_CNTL
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT                                                               0x0
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT                                                     0x1
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT                                                             0x2
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT                                                               0x3
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT                                                                0x4
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT                                               0x8
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT                                            0x9
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT                                                     0xa
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT                                                   0xb
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT                                                            0xc
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT                                                               0xd
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT                                                 0x10
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT                                                         0x14
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT                                                      0x18
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT                                                   0x1a
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT                                                   0x1b
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT                                                       0x1c
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT                                                        0x1f
+#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK                                                                 0x00000001L
+#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK                                                       0x00000002L
+#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK                                                               0x00000004L
+#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK                                                                 0x00000008L
+#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK                                                                  0x000000F0L
+#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK                                                 0x00000100L
+#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK                                              0x00000200L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK                                                       0x00000400L
+#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK                                                     0x00000800L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK                                                              0x00001000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK                                                                 0x0000E000L
+#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK                                                   0x000F0000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK                                                           0x00F00000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK                                                        0x03000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK                                                     0x04000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK                                                     0x08000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK                                                         0x70000000L
+#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK                                                          0x80000000L
+//HUBP3_HUBP_CLK_CNTL
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT                                                         0x0
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT                                                    0x8
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT                                                    0xc
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT                                                    0x10
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT                                                   0x14
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT                                                    0x15
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT                                                    0x16
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT                                                    0x17
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK                                                           0x00000001L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK                                                      0x00000100L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK                                                      0x00001000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK                                                      0x00010000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK                                                     0x00100000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK                                                      0x00200000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK                                                      0x00400000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK                                                      0x00800000L
+#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK                                                           0xF0000000L
+//HUBP3_DCHUBP_VMPG_CONFIG
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT                                                            0x0
+#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK                                                              0x00000001L
+//HUBP3_HUBPREQ_DEBUG_DB
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT                                                          0x0
+#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK                                                            0xFFFFFFFFL
+//HUBP3_HUBPREQ_DEBUG
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT                                                             0x0
+#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK                                                               0xFFFFFFFFL
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT                              0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT                               0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT                               0x1c
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK                                0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK                                 0x01F00000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK                                 0x30000000L
+//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT                                 0x0
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT                            0x1
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT                          0x4
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT                              0xc
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT                               0x14
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK                                   0x00000001L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK                              0x00000002L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK                            0x00000FF0L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK                                0x0001F000L
+#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK                                 0x01F00000L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
+//HUBPREQ3_DCSURF_SURFACE_PITCH
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT                                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT                                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK                                                             0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK                                                        0x3FFF0000L
+//HUBPREQ3_DCSURF_SURFACE_PITCH_C
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT                                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT                                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK                                                         0x00003FFFL
+#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK                                                    0x3FFF0000L
+//HUBPREQ3_VMID_SETTINGS_0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT                                                                 0x0
+#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK                                                                   0x0000000FL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT                               0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK                                 0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK                       0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT                           0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK                   0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT                       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK               0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT           0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK             0x0000FFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT       0x0
+#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT                 0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK                   0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT       0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK         0x0000FFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT             0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK               0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT   0x0
+#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK     0x0000FFFFL
+//HUBPREQ3_DCSURF_SURFACE_CONTROL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT                                        0x1
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT                                   0x2
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT                                         0x4
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT                                 0x5
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT                                         0x8
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT                                      0x9
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT                                 0xa
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT                                       0xc
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT                               0xd
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT                                      0x10
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT                                    0x11
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT                                    0x12
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT                                  0x13
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK                                             0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK                                          0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK                                     0x0000000CL
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK                                           0x00000010L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK                                   0x00000060L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK                                           0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK                                        0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK                                   0x00000C00L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK                                         0x00001000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK                                 0x00006000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK                                        0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK                                      0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK                                      0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK                                    0x00080000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT                                              0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT                                                0x1
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT                                    0x4
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT                                             0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT                                 0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT                                       0x10
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT                               0x11
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT                              0x12
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT                                       0x14
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK                                                0x00000001L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK                                                  0x00000002L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK                                      0x000000F0L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK                                               0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK                                   0x00003000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK                                         0x00010000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK                                 0x00020000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK                                0x00040000L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK                                         0x3FF00000L
+//HUBPREQ3_DCSURF_FLIP_CONTROL2
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT                                   0x0
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT                                              0x8
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT                                                0x9
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT                                    0xa
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT                                     0xc
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK                                     0x000000FFL
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK                                                0x00000100L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK                                                  0x00000200L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK                                      0x00000400L
+#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK                                       0x00001000L
+//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT                                  0x0
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT                                  0x1
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT                             0x2
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT                             0x3
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT                                     0x8
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT                                0x9
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT                                  0x10
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT                                0x11
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT                             0x12
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT                           0x13
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK                                    0x00000001L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK                                    0x00000002L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK                               0x00000004L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK                               0x00000008L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK                                       0x00000100L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK                                  0x00000200L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK                                    0x00010000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK                                  0x00020000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK                               0x00040000L
+#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK                             0x00080000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT                                           0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK                                             0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT                                 0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT                                         0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK                                   0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK                                           0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT                                       0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK                                         0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT                             0x0
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT                                     0x1c
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK                               0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK                                       0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT                         0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK                           0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT               0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT                       0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK                 0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK                         0xF0000000L
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT                     0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK                       0xFFFFFFFFL
+//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT           0x0
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT                   0x1c
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK             0x0000FFFFL
+#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK                     0xF0000000L
+//HUBPREQ3_DCN_EXPANSION_MODE
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT                                                0x0
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT                                                0x2
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT                                                0x4
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT                                                0x6
+#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK                                                  0x00000003L
+#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK                                                  0x0000000CL
+#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK                                                  0x00000030L
+#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK                                                  0x000000C0L
+//HUBPREQ3_DCN_TTU_QOS_WM
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT                                                      0x0
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT                                                     0x10
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK                                                        0x00003FFFL
+#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK                                                       0x3FFF0000L
+//HUBPREQ3_DCN_GLOBAL_TTU_CNTL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT                                                   0x0
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT                                             0x18
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT                                             0x19
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT                                                     0x1b
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT                                                   0x1c
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK                                                     0x00FFFFFFL
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK                                               0x01000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK                                               0x02000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK                                                       0x08000000L
+#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK                                                     0xF0000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF0_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_SURF1_TTU_CNTL0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                          0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                  0x18
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                 0x1c
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                            0x007FFFFFL
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                    0x0F000000L
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                   0x10000000L
+//HUBPREQ3_DCN_SURF1_TTU_CNTL1
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                      0x0
+#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                        0x007FFFFFL
+//HUBPREQ3_DCN_CUR0_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR0_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_CUR1_TTU_CNTL0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT                                           0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT                                                   0x18
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT                                                  0x1c
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK                                             0x007FFFFFL
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK                                                     0x0F000000L
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK                                                    0x10000000L
+//HUBPREQ3_DCN_CUR1_TTU_CNTL1
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT                                       0x0
+#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK                                         0x007FFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT                       0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK                         0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT                     0x0
+#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK                       0x3FFFFFFFL
+//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                  0x0
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                             0x3
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                0x5
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                   0x6
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                    0x00000001L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                               0x00000018L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                  0x00000020L
+#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                     0x00000040L
+//HUBPREQ3_BLANK_OFFSET_0
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT                                                    0x0
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT                                                       0x10
+#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK                                                      0x00001FFFL
+#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK                                                         0x7FFF0000L
+//HUBPREQ3_BLANK_OFFSET_1
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT                                                  0x0
+#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK                                                    0x0003FFFFL
+//HUBPREQ3_DST_DIMENSIONS
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT                                                     0x0
+#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK                                                       0x001FFFFFL
+//HUBPREQ3_DST_AFTER_SCALER
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT                                               0x0
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT                                                  0x10
+#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK                                                 0x00001FFFL
+#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK                                                    0x00070000L
+//HUBPREQ3_PREFETCH_SETTINGS
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT                                                    0x0
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT                                                     0x18
+#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK                                                      0x003FFFFFL
+#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK                                                       0xFF000000L
+//HUBPREQ3_PREFETCH_SETTINGS_C
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT                                                0x0
+#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK                                                  0x003FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT                                              0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT                                             0x8
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK                                                0x0000007FL
+#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK                                               0x00003F00L
+//HUBPREQ3_VBLANK_PARAMETERS_1
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_2
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT                                    0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK                                      0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_3
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK                                     0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_4
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT                                   0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK                                     0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT                                                  0x0
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT                                                 0x8
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK                                                    0x0000007FL
+#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK                                                   0x00003F00L
+//HUBPREQ3_FLIP_PARAMETERS_1
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_2
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK                                         0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_1
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_2
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT                                             0x0
+#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK                                               0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_3
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT                                          0x0
+#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK                                            0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_4
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_5
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK                                           0x007FFFFFL
+//HUBPREQ3_NOM_PARAMETERS_6
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT                                            0x0
+#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK                                              0x0001FFFFL
+//HUBPREQ3_NOM_PARAMETERS_7
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT                                         0x0
+#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK                                           0x007FFFFFL
+//HUBPREQ3_PER_LINE_DELIVERY_PRE
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT                                 0x0
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT                                 0x10
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK                                   0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK                                   0x1FFF0000L
+//HUBPREQ3_PER_LINE_DELIVERY
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT                                         0x0
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT                                         0x10
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK                                           0x00001FFFL
+#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK                                           0x1FFF0000L
+//HUBPREQ3_CURSOR_SETTINGS
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT                                                 0x0
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT                                             0x8
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT                                                 0x10
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT                                             0x18
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK                                                   0x000000FFL
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK                                               0x00000300L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK                                                   0x00FF0000L
+#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK                                               0x03000000L
+//HUBPREQ3_REF_FREQ_TO_PIX_FREQ
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT                                            0x0
+#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK                                              0x001FFFFFL
+//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT                                          0x0
+#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK                                            0x00007FFFL
+//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT                                          0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT                                            0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT                                          0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT                                            0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT                                          0x8
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT                                            0xa
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT                                           0xc
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT                                             0xe
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK                                            0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK                                              0x00000004L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK                                            0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK                                              0x00000040L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK                                            0x00000300L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK                                              0x00000400L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK                                             0x00003000L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK                                               0x00004000L
+//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT                                        0x0
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT                                        0x2
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT                                        0x4
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT                                         0x6
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK                                          0x00000003L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK                                          0x0000000CL
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK                                          0x00000030L
+#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK                                           0x000000C0L
+//HUBPREQ3_VBLANK_PARAMETERS_5
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT                                       0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK                                         0x007FFFFFL
+//HUBPREQ3_VBLANK_PARAMETERS_6
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT                                         0x0
+#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK                                           0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_3
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT                                           0x0
+#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK                                             0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_4
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT                                             0x0
+#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK                                               0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_5
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT                                        0x0
+#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK                                          0x007FFFFFL
+//HUBPREQ3_FLIP_PARAMETERS_6
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT                                       0x0
+#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK                                         0x007FFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
+//HUBPRET3_HUBPRET_CONTROL
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT                                            0xf
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT                                                   0x10
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT                                                     0x12
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT                                                    0x14
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT                                                    0x16
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT                                                0x18
+#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK                                            0x00001FF0L
+#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK                                              0x00008000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK                                                     0x00030000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK                                                       0x000C0000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK                                                      0x00300000L
+#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK                                                      0x00C00000L
+#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK                                                  0xFF000000L
+//HUBPRET3_HUBPRET_MEM_PWR_CTRL
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT                                             0x8
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT                                               0xa
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT                                            0x10
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT                                              0x12
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT                                          0x14
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK                                               0x00000300L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK                                                 0x00000400L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK                                              0x00030000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK                                                0x00040000L
+#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK                                            0x00300000L
+//HUBPRET3_HUBPRET_MEM_PWR_STATUS
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT                                          0x4
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK                                             0x0000000CL
+#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK                                            0x00000030L
+//HUBPRET3_HUBPRET_READ_LINE_CTRL0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT                         0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK                           0x0000FFFFL
+//HUBPRET3_HUBPRET_READ_LINE_CTRL1
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT                    0x0
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT                                0x10
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK                      0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK                                  0xFFFF0000L
+//HUBPRET3_HUBPRET_READ_LINE0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE1
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT                                             0x0
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT                                               0x10
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK                                               0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK                                                 0x3FFF0000L
+//HUBPRET3_HUBPRET_INTERRUPT
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT                                           0x1
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT                                           0x2
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT                                               0x4
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT                                           0x5
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT                                           0x6
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT                                              0x8
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT                                          0x9
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT                                          0xa
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT                                                 0xc
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT                                             0xd
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT                                             0xe
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT                                             0x10
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT                                         0x11
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT                                         0x12
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK                                                 0x00000001L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK                                             0x00000002L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK                                             0x00000004L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK                                                 0x00000010L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK                                             0x00000020L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK                                             0x00000040L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK                                                0x00000100L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK                                            0x00000200L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK                                            0x00000400L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK                                                   0x00001000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK                                               0x00002000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK                                               0x00004000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK                                               0x00010000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK                                           0x00020000L
+#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK                                           0x00040000L
+//HUBPRET3_HUBPRET_READ_LINE_VALUE
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT                                               0x0
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT                                      0x10
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK                                                 0x00003FFFL
+#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK                                        0x3FFF0000L
+//HUBPRET3_HUBPRET_READ_LINE_STATUS
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT                                            0x0
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT                                      0x4
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT                                     0x5
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT                                      0x8
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT                                     0xa
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK                                              0x00000001L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK                                        0x00000010L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK                                       0x00000020L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK                                        0x00000100L
+#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK                                       0x00000400L
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
+//CURSOR0_3_CURSOR_CONTROL
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT                                                        0x0
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT                                                      0x2
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT                                                    0x4
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT                                                          0x8
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT                                                           0xc
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT                                                         0x10
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT                     0x14
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT                                               0x18
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT                                    0x1e
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT                                   0x1f
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK                                                          0x00000001L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK                                                        0x00000004L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK                                                      0x00000010L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK                                                            0x00000700L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK                                                             0x00001000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK                                                           0x00030000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK                       0x00100000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK                                                 0x1F000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK                                      0x40000000L
+#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK                                     0x80000000L
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT                                       0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK                                         0xFFFFFFFFL
+//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT                             0x0
+#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK                               0x0000FFFFL
+//CURSOR0_3_CURSOR_SIZE
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT                                                           0x0
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT                                                            0x10
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK                                                             0x000001FFL
+#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK                                                              0x01FF0000L
+//CURSOR0_3_CURSOR_POSITION
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK                                                     0x00003FFFL
+#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK                                                     0x3FFF0000L
+//CURSOR0_3_CURSOR_HOT_SPOT
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT                                                   0x0
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT                                                   0x10
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK                                                     0x000000FFL
+#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK                                                     0x00FF0000L
+//CURSOR0_3_CURSOR_STEREO_CONTROL
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT                                         0x4
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT                                       0x12
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK                                                0x00000001L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK                                           0x0003FFF0L
+#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK                                         0xFFFC0000L
+//CURSOR0_3_CURSOR_DST_OFFSET
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT                                               0x0
+#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK                                                 0x00001FFFL
+//CURSOR0_3_CURSOR_MEM_PWR_CTRL
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT                                              0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT                                                0x2
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT                                            0x4
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK                                                0x00000003L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK                                                  0x00000004L
+#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK                                              0x00000030L
+//CURSOR0_3_CURSOR_MEM_PWR_STATUS
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT                                            0x0
+#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK                                              0x00000003L
+//CURSOR0_3_DMDATA_ADDRESS_HIGH
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT                                             0x0
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT                                                      0x1e
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK                                               0x0000FFFFL
+#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK                                                        0x40000000L
+//CURSOR0_3_DMDATA_ADDRESS_LOW
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT                                               0x0
+#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK                                                 0xFFFFFFFFL
+//CURSOR0_3_DMDATA_CNTL
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT                                                          0x0
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT                                                           0x1
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT                                                             0x2
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT                                                             0x10
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK                                                            0x00000001L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK                                                             0x00000002L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK                                                               0x00000004L
+#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK                                                               0x0FFF0000L
+//CURSOR0_3_DMDATA_QOS_CNTL
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT                                                     0x0
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT                                                    0x4
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT                                                     0x10
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK                                                       0x00000001L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK                                                      0x000000F0L
+#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK                                                       0xFFFF0000L
+//CURSOR0_3_DMDATA_STATUS
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT                                                           0x0
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT                                                      0x2
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT                                                0x4
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK                                                             0x00000001L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK                                                        0x00000004L
+#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK                                                  0x00000010L
+//CURSOR0_3_DMDATA_SW_CNTL
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT                                                    0x0
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT                                                     0x1
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT                                                       0x10
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK                                                      0x00000001L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK                                                       0x00000002L
+#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK                                                         0x0FFF0000L
+//CURSOR0_3_DMDATA_SW_DATA
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT                                                       0x0
+#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK                                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON10_PERFCOUNTER_CNTL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_CNTL2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON10_PERFCOUNTER_STATE
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON10_PERFMON_CNTL
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON10_PERFMON_CNTL2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON10_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON10_PERFMON_CVALUE_LOW
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON10_PERFMON_HI
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON10_PERFMON_LOW
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG0_FORMAT_CONTROL
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG0_FCNV_FP_BIAS_R
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_G
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_BIAS_B
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_R
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_G
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_FCNV_FP_SCALE_B
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG0_COLOR_KEYER_CONTROL
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG0_COLOR_KEYER_ALPHA
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_RED
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_GREEN
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG0_COLOR_KEYER_BLUE
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG0_ALPHA_2BIT_LUT
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG0_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG0_PRE_DEALPHA
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG0_PRE_CSC_MODE
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG0_PRE_CSC_C11_C12
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C13_C14
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C21_C22
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C23_C24
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C31_C32
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_C33_C34
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C11_C12
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C13_C14
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C21_C22
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C23_C24
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C31_C32
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_PRE_CSC_B_C33_C34
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG0_CNVC_COEF_FORMAT
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG0_PRE_DEGAM
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG0_PRE_REALPHA
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
+//CNVC_CUR0_CURSOR0_CONTROL
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR0_CURSOR0_COLOR0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_COLOR1
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR0_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
+//DSCL0_SCL_COEF_RAM_TAP_SELECT
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL0_SCL_COEF_RAM_TAP_DATA
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL0_SCL_MODE
+#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL0_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL0_SCL_TAP_CONTROL
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL0_DSCL_CONTROL
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL0_DSCL_2TAP_CONTROL
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL0_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_HORZ_FILTER_INIT_C
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL0_SCL_VERT_FILTER_INIT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL0_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL0_SCL_BLACK_COLOR
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL0_DSCL_UPDATE
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL0_DSCL_AUTOCAL
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL0_OTG_H_BLANK
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_OTG_V_BLANK
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL0_RECOUT_START
+#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL0_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL0_RECOUT_SIZE
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL0_MPC_SIZE
+#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL0_LB_DATA_FORMAT
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL0_LB_MEMORY_CTRL
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL0_LB_V_COUNTER
+#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL0_DSCL_MEM_PWR_CTRL
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL0_DSCL_MEM_PWR_STATUS
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL0_OBUF_CONTROL
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL0_OBUF_MEM_PWR_CTRL
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
+//CM0_CM_CONTROL
+#define CM0_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM0_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM0_CM_POST_CSC_CONTROL
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM0_CM_POST_CSC_C11_C12
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C13_C14
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C21_C22
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C23_C24
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C31_C32
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_C33_C34
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM0_CM_POST_CSC_B_C11_C12
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C13_C14
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C21_C22
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C23_C24
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C31_C32
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM0_CM_POST_CSC_B_C33_C34
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_CONTROL
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM0_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM0_CM_GAMUT_REMAP_C11_C12
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C13_C14
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C21_C22
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C23_C24
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C31_C32
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_C33_C34
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C11_C12
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C13_C14
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C21_C22
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C23_C24
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C31_C32
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM0_CM_GAMUT_REMAP_B_C33_C34
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM0_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM0_CM_BIAS_CR_R
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM0_CM_BIAS_Y_G_CB_B
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM0_CM_GAMCOR_CONTROL
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM0_CM_GAMCOR_LUT_INDEX
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM0_CM_GAMCOR_LUT_DATA
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM0_CM_GAMCOR_LUT_CONTROL
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT                                              0x5
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK                                                0x00000020L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMA_OFFSET_B
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_G
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_OFFSET_R
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMA_REGION_0_1
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_2_3
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_4_5
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_6_7
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_8_9
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_10_11
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_12_13
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_14_15
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_16_17
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_18_19
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_20_21
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_22_23
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_24_25
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_26_27
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_28_29
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_30_31
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMA_REGION_32_33
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM0_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM0_CM_GAMCOR_RAMB_OFFSET_B
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_G
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_OFFSET_R
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM0_CM_GAMCOR_RAMB_REGION_0_1
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_2_3
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_4_5
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_6_7
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_8_9
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_10_11
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_12_13
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_14_15
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_16_17
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_18_19
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_20_21
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_22_23
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_24_25
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_26_27
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_28_29
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_30_31
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_GAMCOR_RAMB_REGION_32_33
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_BLNDGAM_CONTROL
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM0_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM0_CM_BLNDGAM_LUT_INDEX
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM0_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM0_CM_BLNDGAM_LUT_DATA
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM0_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM0_CM_BLNDGAM_LUT_CONTROL
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM0_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM0_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM0_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM0_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM0_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM0_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM0_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM0_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM0_CM_HDR_MULT_COEF
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM0_CM_MEM_PWR_CTRL
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM0_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM0_CM_MEM_PWR_STATUS
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM0_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM0_CM_DEALPHA
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM0_CM_COEF_FORMAT
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM0_CM_SHAPER_CONTROL
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM0_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM0_CM_SHAPER_OFFSET_R
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_G
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_OFFSET_B
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM0_CM_SHAPER_SCALE_R
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM0_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM0_CM_SHAPER_SCALE_G_B
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM0_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM0_CM_SHAPER_LUT_INDEX
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM0_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM0_CM_SHAPER_LUT_DATA
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM0_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM0_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM0_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM0_CM_SHAPER_RAMA_START_CNTL_B
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_G
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_START_CNTL_R
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_B
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_G
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_END_CNTL_R
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMA_REGION_0_1
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_2_3
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_4_5
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_6_7
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_8_9
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_10_11
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_12_13
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_14_15
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_16_17
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_18_19
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_20_21
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_22_23
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_24_25
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_26_27
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_28_29
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_30_31
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMA_REGION_32_33
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_B
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_G
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_START_CNTL_R
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM0_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_B
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_G
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_END_CNTL_R
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM0_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM0_CM_SHAPER_RAMB_REGION_0_1
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_2_3
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_4_5
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_6_7
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_8_9
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_10_11
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_12_13
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_14_15
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_16_17
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_18_19
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_20_21
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_22_23
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_24_25
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_26_27
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_28_29
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_30_31
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_SHAPER_RAMB_REGION_32_33
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM0_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM0_CM_MEM_PWR_CTRL2
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM0_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM0_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM0_CM_MEM_PWR_STATUS2
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM0_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM0_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM0_CM_3DLUT_MODE
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM0_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM0_CM_3DLUT_INDEX
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM0_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM0_CM_3DLUT_DATA
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM0_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM0_CM_3DLUT_DATA_30BIT
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM0_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM0_CM_3DLUT_READ_WRITE_CONTROL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM0_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM0_CM_3DLUT_OUT_NORM_FACTOR
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM0_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM0_CM_3DLUT_OUT_OFFSET_R
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_G
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM0_CM_3DLUT_OUT_OFFSET_B
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM0_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM0_CM_TEST_DEBUG_INDEX
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM0_CM_TEST_DEBUG_DATA
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
+//DPP_TOP0_DPP_CONTROL
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP0_DPP_SOFT_RESET
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP0_DPP_CRC_VAL_R_G
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP0_DPP_CRC_VAL_B_A
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP0_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP0_DPP_CRC_CTRL
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP0_HOST_READ_CONTROL
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON11_PERFCOUNTER_CNTL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_CNTL2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON11_PERFCOUNTER_STATE
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON11_PERFMON_CNTL
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON11_PERFMON_CNTL2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON11_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON11_PERFMON_CVALUE_LOW
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON11_PERFMON_HI
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON11_PERFMON_LOW
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG1_FORMAT_CONTROL
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG1_FCNV_FP_BIAS_R
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_G
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_BIAS_B
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_R
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_G
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_FCNV_FP_SCALE_B
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG1_COLOR_KEYER_CONTROL
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG1_COLOR_KEYER_ALPHA
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_RED
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_GREEN
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG1_COLOR_KEYER_BLUE
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG1_ALPHA_2BIT_LUT
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG1_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG1_PRE_DEALPHA
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG1_PRE_CSC_MODE
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG1_PRE_CSC_C11_C12
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C13_C14
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C21_C22
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C23_C24
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C31_C32
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_C33_C34
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C11_C12
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C13_C14
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C21_C22
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C23_C24
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C31_C32
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_PRE_CSC_B_C33_C34
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG1_CNVC_COEF_FORMAT
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG1_PRE_DEGAM
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG1_PRE_REALPHA
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
+//CNVC_CUR1_CURSOR0_CONTROL
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR1_CURSOR0_COLOR0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_COLOR1
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR1_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR1_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
+//DSCL1_SCL_COEF_RAM_TAP_SELECT
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL1_SCL_COEF_RAM_TAP_DATA
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL1_SCL_MODE
+#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL1_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL1_SCL_TAP_CONTROL
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL1_DSCL_CONTROL
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL1_DSCL_2TAP_CONTROL
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL1_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_HORZ_FILTER_INIT_C
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL1_SCL_VERT_FILTER_INIT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL1_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL1_SCL_BLACK_COLOR
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL1_DSCL_UPDATE
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL1_DSCL_AUTOCAL
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL1_OTG_H_BLANK
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_OTG_V_BLANK
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL1_RECOUT_START
+#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL1_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL1_RECOUT_SIZE
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL1_MPC_SIZE
+#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL1_LB_DATA_FORMAT
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL1_LB_MEMORY_CTRL
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL1_LB_V_COUNTER
+#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL1_DSCL_MEM_PWR_CTRL
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL1_DSCL_MEM_PWR_STATUS
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL1_OBUF_CONTROL
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL1_OBUF_MEM_PWR_CTRL
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
+//CM1_CM_CONTROL
+#define CM1_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM1_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM1_CM_POST_CSC_CONTROL
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM1_CM_POST_CSC_C11_C12
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C13_C14
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C21_C22
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C23_C24
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C31_C32
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_C33_C34
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM1_CM_POST_CSC_B_C11_C12
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C13_C14
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C21_C22
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C23_C24
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C31_C32
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM1_CM_POST_CSC_B_C33_C34
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_CONTROL
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM1_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM1_CM_GAMUT_REMAP_C11_C12
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C13_C14
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C21_C22
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C23_C24
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C31_C32
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_C33_C34
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C11_C12
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C13_C14
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C21_C22
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C23_C24
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C31_C32
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM1_CM_GAMUT_REMAP_B_C33_C34
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM1_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM1_CM_BIAS_CR_R
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM1_CM_BIAS_Y_G_CB_B
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM1_CM_GAMCOR_CONTROL
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM1_CM_GAMCOR_LUT_INDEX
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM1_CM_GAMCOR_LUT_DATA
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM1_CM_GAMCOR_LUT_CONTROL
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMA_OFFSET_B
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_G
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_OFFSET_R
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMA_REGION_0_1
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_2_3
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_4_5
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_6_7
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_8_9
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_10_11
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_12_13
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_14_15
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_16_17
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_18_19
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_20_21
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_22_23
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_24_25
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_26_27
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_28_29
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_30_31
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMA_REGION_32_33
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM1_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM1_CM_GAMCOR_RAMB_OFFSET_B
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_G
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_OFFSET_R
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM1_CM_GAMCOR_RAMB_REGION_0_1
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_2_3
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_4_5
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_6_7
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_8_9
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_10_11
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_12_13
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_14_15
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_16_17
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_18_19
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_20_21
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_22_23
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_24_25
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_26_27
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_28_29
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_30_31
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_GAMCOR_RAMB_REGION_32_33
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_BLNDGAM_CONTROL
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM1_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM1_CM_BLNDGAM_LUT_INDEX
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM1_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM1_CM_BLNDGAM_LUT_DATA
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM1_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM1_CM_BLNDGAM_LUT_CONTROL
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM1_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM1_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM1_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM1_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM1_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM1_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM1_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM1_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM1_CM_HDR_MULT_COEF
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM1_CM_MEM_PWR_CTRL
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM1_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM1_CM_MEM_PWR_STATUS
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM1_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM1_CM_DEALPHA
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM1_CM_COEF_FORMAT
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM1_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM1_CM_SHAPER_CONTROL
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM1_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM1_CM_SHAPER_OFFSET_R
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_G
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_OFFSET_B
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM1_CM_SHAPER_SCALE_R
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM1_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM1_CM_SHAPER_SCALE_G_B
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM1_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM1_CM_SHAPER_LUT_INDEX
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM1_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM1_CM_SHAPER_LUT_DATA
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM1_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM1_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM1_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM1_CM_SHAPER_RAMA_START_CNTL_B
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_G
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_START_CNTL_R
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_B
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_G
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_END_CNTL_R
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMA_REGION_0_1
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_2_3
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_4_5
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_6_7
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_8_9
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_10_11
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_12_13
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_14_15
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_16_17
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_18_19
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_20_21
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_22_23
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_24_25
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_26_27
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_28_29
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_30_31
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMA_REGION_32_33
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_B
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_G
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_START_CNTL_R
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM1_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_B
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_G
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_END_CNTL_R
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM1_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM1_CM_SHAPER_RAMB_REGION_0_1
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_2_3
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_4_5
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_6_7
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_8_9
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_10_11
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_12_13
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_14_15
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_16_17
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_18_19
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_20_21
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_22_23
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_24_25
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_26_27
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_28_29
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_30_31
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_SHAPER_RAMB_REGION_32_33
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM1_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM1_CM_MEM_PWR_CTRL2
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM1_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM1_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM1_CM_MEM_PWR_STATUS2
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM1_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM1_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM1_CM_3DLUT_MODE
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM1_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM1_CM_3DLUT_INDEX
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM1_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM1_CM_3DLUT_DATA
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM1_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM1_CM_3DLUT_DATA_30BIT
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM1_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM1_CM_3DLUT_READ_WRITE_CONTROL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM1_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM1_CM_3DLUT_OUT_NORM_FACTOR
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM1_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM1_CM_3DLUT_OUT_OFFSET_R
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_G
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM1_CM_3DLUT_OUT_OFFSET_B
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM1_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM1_CM_TEST_DEBUG_INDEX
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM1_CM_TEST_DEBUG_DATA
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
+//DPP_TOP1_DPP_CONTROL
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP1_DPP_SOFT_RESET
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP1_DPP_CRC_VAL_R_G
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP1_DPP_CRC_VAL_B_A
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP1_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP1_DPP_CRC_CTRL
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP1_HOST_READ_CONTROL
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON12_PERFCOUNTER_CNTL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_CNTL2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON12_PERFCOUNTER_STATE
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON12_PERFMON_CNTL
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON12_PERFMON_CNTL2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON12_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON12_PERFMON_CVALUE_LOW
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON12_PERFMON_HI
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON12_PERFMON_LOW
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG2_FORMAT_CONTROL
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG2_FCNV_FP_BIAS_R
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_G
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_BIAS_B
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_R
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_G
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_FCNV_FP_SCALE_B
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG2_COLOR_KEYER_CONTROL
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG2_COLOR_KEYER_ALPHA
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_RED
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_GREEN
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG2_COLOR_KEYER_BLUE
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG2_ALPHA_2BIT_LUT
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG2_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG2_PRE_DEALPHA
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG2_PRE_CSC_MODE
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG2_PRE_CSC_C11_C12
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C13_C14
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C21_C22
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C23_C24
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C31_C32
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_C33_C34
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C11_C12
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C13_C14
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C21_C22
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C23_C24
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C31_C32
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_PRE_CSC_B_C33_C34
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG2_CNVC_COEF_FORMAT
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG2_PRE_DEGAM
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG2_PRE_REALPHA
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
+//CNVC_CUR2_CURSOR0_CONTROL
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR2_CURSOR0_COLOR0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_COLOR1
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR2_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR2_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
+//DSCL2_SCL_COEF_RAM_TAP_SELECT
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL2_SCL_COEF_RAM_TAP_DATA
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL2_SCL_MODE
+#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL2_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL2_SCL_TAP_CONTROL
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL2_DSCL_CONTROL
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL2_DSCL_2TAP_CONTROL
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL2_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_HORZ_FILTER_INIT_C
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL2_SCL_VERT_FILTER_INIT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL2_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL2_SCL_BLACK_COLOR
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL2_DSCL_UPDATE
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL2_DSCL_AUTOCAL
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL2_OTG_H_BLANK
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_OTG_V_BLANK
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL2_RECOUT_START
+#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL2_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL2_RECOUT_SIZE
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL2_MPC_SIZE
+#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL2_LB_DATA_FORMAT
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL2_LB_MEMORY_CTRL
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL2_LB_V_COUNTER
+#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL2_DSCL_MEM_PWR_CTRL
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL2_DSCL_MEM_PWR_STATUS
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL2_OBUF_CONTROL
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL2_OBUF_MEM_PWR_CTRL
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
+//CM2_CM_CONTROL
+#define CM2_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM2_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM2_CM_POST_CSC_CONTROL
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM2_CM_POST_CSC_C11_C12
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C13_C14
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C21_C22
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C23_C24
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C31_C32
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_C33_C34
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM2_CM_POST_CSC_B_C11_C12
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C13_C14
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C21_C22
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C23_C24
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C31_C32
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM2_CM_POST_CSC_B_C33_C34
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_CONTROL
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM2_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM2_CM_GAMUT_REMAP_C11_C12
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C13_C14
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C21_C22
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C23_C24
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C31_C32
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_C33_C34
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C11_C12
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C13_C14
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C21_C22
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C23_C24
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C31_C32
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM2_CM_GAMUT_REMAP_B_C33_C34
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM2_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM2_CM_BIAS_CR_R
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM2_CM_BIAS_Y_G_CB_B
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM2_CM_GAMCOR_CONTROL
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM2_CM_GAMCOR_LUT_INDEX
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM2_CM_GAMCOR_LUT_DATA
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM2_CM_GAMCOR_LUT_CONTROL
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMA_OFFSET_B
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_G
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_OFFSET_R
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMA_REGION_0_1
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_2_3
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_4_5
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_6_7
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_8_9
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_10_11
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_12_13
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_14_15
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_16_17
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_18_19
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_20_21
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_22_23
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_24_25
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_26_27
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_28_29
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_30_31
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMA_REGION_32_33
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM2_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM2_CM_GAMCOR_RAMB_OFFSET_B
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_G
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_OFFSET_R
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM2_CM_GAMCOR_RAMB_REGION_0_1
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_2_3
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_4_5
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_6_7
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_8_9
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_10_11
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_12_13
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_14_15
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_16_17
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_18_19
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_20_21
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_22_23
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_24_25
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_26_27
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_28_29
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_30_31
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_GAMCOR_RAMB_REGION_32_33
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_BLNDGAM_CONTROL
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM2_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM2_CM_BLNDGAM_LUT_INDEX
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM2_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM2_CM_BLNDGAM_LUT_DATA
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM2_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM2_CM_BLNDGAM_LUT_CONTROL
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM2_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM2_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM2_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM2_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM2_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM2_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM2_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM2_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM2_CM_HDR_MULT_COEF
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM2_CM_MEM_PWR_CTRL
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM2_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM2_CM_MEM_PWR_STATUS
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM2_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM2_CM_DEALPHA
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM2_CM_COEF_FORMAT
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM2_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM2_CM_SHAPER_CONTROL
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM2_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM2_CM_SHAPER_OFFSET_R
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_G
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_OFFSET_B
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM2_CM_SHAPER_SCALE_R
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM2_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM2_CM_SHAPER_SCALE_G_B
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM2_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM2_CM_SHAPER_LUT_INDEX
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM2_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM2_CM_SHAPER_LUT_DATA
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM2_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM2_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM2_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM2_CM_SHAPER_RAMA_START_CNTL_B
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_G
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_START_CNTL_R
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_B
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_G
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_END_CNTL_R
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMA_REGION_0_1
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_2_3
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_4_5
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_6_7
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_8_9
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_10_11
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_12_13
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_14_15
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_16_17
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_18_19
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_20_21
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_22_23
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_24_25
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_26_27
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_28_29
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_30_31
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMA_REGION_32_33
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_B
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_G
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_START_CNTL_R
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM2_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_B
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_G
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_END_CNTL_R
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM2_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM2_CM_SHAPER_RAMB_REGION_0_1
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_2_3
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_4_5
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_6_7
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_8_9
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_10_11
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_12_13
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_14_15
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_16_17
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_18_19
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_20_21
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_22_23
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_24_25
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_26_27
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_28_29
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_30_31
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_SHAPER_RAMB_REGION_32_33
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM2_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM2_CM_MEM_PWR_CTRL2
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM2_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM2_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM2_CM_MEM_PWR_STATUS2
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM2_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM2_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM2_CM_3DLUT_MODE
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM2_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM2_CM_3DLUT_INDEX
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM2_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM2_CM_3DLUT_DATA
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM2_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM2_CM_3DLUT_DATA_30BIT
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM2_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM2_CM_3DLUT_READ_WRITE_CONTROL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM2_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM2_CM_3DLUT_OUT_NORM_FACTOR
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM2_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM2_CM_3DLUT_OUT_OFFSET_R
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_G
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM2_CM_3DLUT_OUT_OFFSET_B
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM2_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM2_CM_TEST_DEBUG_INDEX
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM2_CM_TEST_DEBUG_DATA
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
+//DPP_TOP2_DPP_CONTROL
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP2_DPP_SOFT_RESET
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP2_DPP_CRC_VAL_R_G
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP2_DPP_CRC_VAL_B_A
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP2_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP2_DPP_CRC_CTRL
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP2_HOST_READ_CONTROL
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON13_PERFCOUNTER_CNTL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_CNTL2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON13_PERFCOUNTER_STATE
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON13_PERFMON_CNTL
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON13_PERFMON_CNTL2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON13_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON13_PERFMON_CVALUE_LOW
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON13_PERFMON_HI
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON13_PERFMON_LOW
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
+//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT                                 0x0
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT                                   0x8
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK                                   0x0000007FL
+#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK                                     0x00000100L
+//CNVC_CFG3_FORMAT_CONTROL
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT                                                0x0
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT                                                         0x4
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT                                                             0x8
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT                                                          0xc
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT                                                0xd
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT                                                       0x10
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT                                                     0x11
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT                                                  0x14
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT                                                    0x18
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT                                                    0x1a
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT                                                    0x1c
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK                                                  0x00000001L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK                                                           0x00000010L
+#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK                                                               0x00000100L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK                                                            0x00001000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK                                                  0x00002000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK                                                         0x00010000L
+#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK                                                       0x00020000L
+#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK                                                    0x00100000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK                                                      0x03000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK                                                      0x0C000000L
+#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK                                                      0x30000000L
+//CNVC_CFG3_FCNV_FP_BIAS_R
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_G
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_BIAS_B
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT                                                       0x0
+#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK                                                         0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_R
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_G
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_FCNV_FP_SCALE_B
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT                                                     0x0
+#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK                                                       0x0007FFFFL
+//CNVC_CFG3_COLOR_KEYER_CONTROL
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT                                                  0x0
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT                                                0x4
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK                                                    0x00000001L
+#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK                                                  0x00000030L
+//CNVC_CFG3_COLOR_KEYER_ALPHA
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_RED
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT                                                 0x0
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT                                                0x10
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK                                                   0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK                                                  0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_GREEN
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT                                             0x0
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT                                            0x10
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK                                               0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK                                              0xFFFF0000L
+//CNVC_CFG3_COLOR_KEYER_BLUE
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT                                               0x0
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT                                              0x10
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK                                                 0x0000FFFFL
+#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK                                                0xFFFF0000L
+//CNVC_CFG3_ALPHA_2BIT_LUT
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0__SHIFT                                                      0x0
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1__SHIFT                                                      0x8
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2__SHIFT                                                      0x10
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3__SHIFT                                                      0x18
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT0_MASK                                                        0x000000FFL
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT1_MASK                                                        0x0000FF00L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT2_MASK                                                        0x00FF0000L
+#define CNVC_CFG3_ALPHA_2BIT_LUT__ALPHA_2BIT_LUT3_MASK                                                        0xFF000000L
+//CNVC_CFG3_PRE_DEALPHA
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK                                                      0x00000010L
+//CNVC_CFG3_PRE_CSC_MODE
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT                                                           0x0
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT                                                   0x2
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK                                                             0x00000003L
+#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK                                                     0x0000000CL
+//CNVC_CFG3_PRE_CSC_C11_C12
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C13_C14
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C21_C22
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C23_C24
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C31_C32
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_C33_C34
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT                                                         0x0
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT                                                         0x10
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK                                                           0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK                                                           0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C11_C12
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C13_C14
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C21_C22
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C23_C24
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C31_C32
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_PRE_CSC_B_C33_C34
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT                                                     0x0
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT                                                     0x10
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK                                                       0x0000FFFFL
+#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK                                                       0xFFFF0000L
+//CNVC_CFG3_CNVC_COEF_FORMAT
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT                                                0x0
+#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK                                                  0x00000001L
+//CNVC_CFG3_PRE_DEGAM
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT                                                            0x0
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT                                                          0x4
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK                                                              0x00000003L
+#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK                                                            0x00000070L
+//CNVC_CFG3_PRE_REALPHA
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT                                                          0x0
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT                                                    0x4
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK                                                            0x00000001L
+#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK                                                      0x00000010L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
+//CNVC_CUR3_CURSOR0_CONTROL
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT                                                         0x0
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT                                                 0x1
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT                                                   0x2
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT                                                         0x3
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT                                                           0x4
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT                                             0x7
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT                                                 0x10
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK                                                           0x00000001L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK                                                   0x00000002L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK                                                     0x00000004L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK                                                           0x00000008L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK                                                             0x00000070L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK                                               0x00000080L
+#define CNVC_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK                                                   0x00010000L
+//CNVC_CUR3_CURSOR0_COLOR0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_COLOR1
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT                                                          0x0
+#define CNVC_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK                                                            0x00FFFFFFL
+//CNVC_CUR3_CURSOR0_FP_SCALE_BIAS
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE__SHIFT                                                 0x0
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS__SHIFT                                                  0x10
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE_MASK                                                   0x0000FFFFL
+#define CNVC_CUR3_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS_MASK                                                    0xFFFF0000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
+//DSCL3_SCL_COEF_RAM_TAP_SELECT
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT                                       0x0
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT                                              0x8
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT                                        0x10
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK                                         0x00000003L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK                                                0x00003F00L
+#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK                                          0x00070000L
+//DSCL3_SCL_COEF_RAM_TAP_DATA
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT                                        0x0
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT                                     0xf
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT                                         0x10
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT                                      0x1f
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK                                          0x00003FFFL
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK                                       0x00008000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK                                           0x3FFF0000L
+#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK                                        0x80000000L
+//DSCL3_SCL_MODE
+#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT                                                                      0x0
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT                                                            0x8
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT                                                    0xc
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT                                                           0x10
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT                                                            0x14
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT                                                         0x18
+#define DSCL3_SCL_MODE__DSCL_MODE_MASK                                                                        0x00000007L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK                                                              0x00000100L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK                                                      0x00001000L
+#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK                                                             0x00010000L
+#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK                                                              0x00100000L
+#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK                                                           0x01000000L
+//DSCL3_SCL_TAP_CONTROL
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT                                                          0x0
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT                                                          0x4
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT                                                        0x8
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT                                                        0xc
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK                                                            0x00000007L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK                                                            0x00000070L
+#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK                                                          0x00000700L
+#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK                                                          0x00007000L
+//DSCL3_DSCL_CONTROL
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT                                                          0x0
+#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK                                                            0x00000001L
+//DSCL3_DSCL_2TAP_CONTROL
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x0
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT                                                   0x4
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT                                               0x8
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT                                           0x10
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT                                                   0x14
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT                                               0x18
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK                                             0x00000001L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK                                                     0x00000010L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK                                                 0x00000700L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK                                             0x00010000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK                                                     0x00100000L
+#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK                                                 0x07000000L
+//DSCL3_SCL_MANUAL_REPLICATE_CONTROL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT                              0x0
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT                              0x8
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK                                0x0000000FL
+#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK                                0x00000F00L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_HORZ_FILTER_INIT_C
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT                                           0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK                                             0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT                                                    0x0
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT                                                     0x18
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK                                                      0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK                                                       0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT                                            0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT                                             0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK                                              0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK                                               0x0F000000L
+//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT                                       0x0
+#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK                                         0x07FFFFFFL
+//DSCL3_SCL_VERT_FILTER_INIT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT                                                0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT                                                 0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK                                                  0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK                                                   0x0F000000L
+//DSCL3_SCL_VERT_FILTER_INIT_BOT_C
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT                                        0x0
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT                                         0x18
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK                                          0x00FFFFFFL
+#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK                                           0x0F000000L
+//DSCL3_SCL_BLACK_COLOR
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT                                                   0x0
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT                                                    0x10
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK                                                     0x0000FFFFL
+#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK                                                      0xFFFF0000L
+//DSCL3_DSCL_UPDATE
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT                                                          0x0
+#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK                                                            0x00000001L
+//DSCL3_DSCL_AUTOCAL
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT                                                               0x0
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT                                                           0x8
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT                                                            0xc
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK                                                                 0x00000003L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK                                                             0x00000300L
+#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK                                                              0x00003000L
+//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT                                         0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT                                          0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK                                           0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK                                            0x1FFF0000L
+//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT                                        0x0
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT                                           0x10
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK                                          0x00001FFFL
+#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK                                             0x1FFF0000L
+//DSCL3_OTG_H_BLANK
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_OTG_V_BLANK
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT                                                           0x0
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT                                                             0x10
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK                                                             0x00003FFFL
+#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK                                                               0x3FFF0000L
+//DSCL3_RECOUT_START
+#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT                                                             0x0
+#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT                                                             0x10
+#define DSCL3_RECOUT_START__RECOUT_START_X_MASK                                                               0x00001FFFL
+#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK                                                               0x1FFF0000L
+//DSCL3_RECOUT_SIZE
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT                                                                0x0
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT                                                               0x10
+#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK                                                                  0x00003FFFL
+#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK                                                                 0x3FFF0000L
+//DSCL3_MPC_SIZE
+#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT                                                                      0x0
+#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT                                                                     0x10
+#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK                                                                        0x00003FFFL
+#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK                                                                       0x3FFF0000L
+//DSCL3_LB_DATA_FORMAT
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT                                                            0x0
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT                                                                 0x4
+#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK                                                              0x00000001L
+#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK                                                                   0x00000010L
+//DSCL3_LB_MEMORY_CTRL
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT                                                            0x0
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT                                                        0x8
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT                                                        0x10
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT                                                      0x18
+#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK                                                              0x00000003L
+#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK                                                          0x00003F00L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK                                                          0x007F0000L
+#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK                                                        0x7F000000L
+//DSCL3_LB_V_COUNTER
+#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT                                                                  0x0
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT                                                                0x10
+#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK                                                                    0x00001FFFL
+#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK                                                                  0x1FFF0000L
+//DSCL3_DSCL_MEM_PWR_CTRL
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT                                                       0x2
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT                                                   0x4
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT                                                     0x6
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT                                                   0x8
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT                                                     0xa
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT                                                     0xe
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT                                                   0x10
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT                                                     0x12
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT                                                   0x14
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT                                                     0x16
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT                                                   0x18
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT                                                     0x1a
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT                                                       0x1c
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK                                                         0x00000004L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK                                                     0x00000030L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK                                                       0x00000040L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK                                                     0x00000300L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK                                                       0x00000400L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK                                                       0x00004000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK                                                     0x00030000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK                                                       0x00040000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK                                                     0x00300000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK                                                       0x00400000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK                                                     0x03000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK                                                       0x04000000L
+#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK                                                         0x10000000L
+//DSCL3_DSCL_MEM_PWR_STATUS
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT                                                   0x0
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT                                                 0x2
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT                                                 0x4
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT                                                 0x6
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT                                                 0x8
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT                                                 0xa
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT                                                 0xc
+#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK                                                     0x00000003L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK                                                   0x0000000CL
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK                                                   0x00000030L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK                                                   0x000000C0L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK                                                   0x00000300L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK                                                   0x00000C00L
+#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK                                                   0x00003000L
+//DSCL3_OBUF_CONTROL
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT                                                                0x0
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT                                                       0x1
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT                                                  0x2
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT                                                          0x4
+#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK                                                                  0x00000001L
+#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK                                                         0x00000002L
+#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK                                                    0x00000004L
+#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK                                                            0x000000F0L
+//DSCL3_OBUF_MEM_PWR_CTRL
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT                                                    0x0
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT                                                      0x2
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT                                                     0x8
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT                                                    0x10
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK                                                      0x00000003L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK                                                        0x00000004L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK                                                       0x00000100L
+#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK                                                      0x00030000L
+
+
+// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
+//CM3_CM_CONTROL
+#define CM3_CM_CONTROL__CM_BYPASS__SHIFT                                                                      0x0
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT                                                              0x8
+#define CM3_CM_CONTROL__CM_BYPASS_MASK                                                                        0x00000001L
+#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK                                                                0x00000100L
+//CM3_CM_POST_CSC_CONTROL
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT                                                      0x0
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT                                              0x2
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK                                                        0x00000003L
+#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK                                                0x0000000CL
+//CM3_CM_POST_CSC_C11_C12
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C13_C14
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C21_C22
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C23_C24
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C31_C32
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_C33_C34
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT                                                       0x0
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT                                                       0x10
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK                                                         0x0000FFFFL
+#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK                                                         0xFFFF0000L
+//CM3_CM_POST_CSC_B_C11_C12
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C13_C14
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C21_C22
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C23_C24
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C31_C32
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK                                                     0xFFFF0000L
+//CM3_CM_POST_CSC_B_C33_C34
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT                                                   0x0
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT                                                   0x10
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK                                                     0x0000FFFFL
+#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK                                                     0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_CONTROL
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE__SHIFT                                                0x0
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT__SHIFT                                        0x2
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_MASK                                                  0x00000003L
+#define CM3_CM_GAMUT_REMAP_CONTROL__CM_GAMUT_REMAP_MODE_CURRENT_MASK                                          0x0000000CL
+//CM3_CM_GAMUT_REMAP_C11_C12
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C11_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C11_C12__CM_GAMUT_REMAP_C12_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C13_C14
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C13_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C13_C14__CM_GAMUT_REMAP_C14_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C21_C22
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C21_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C21_C22__CM_GAMUT_REMAP_C22_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C23_C24
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C23_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C23_C24__CM_GAMUT_REMAP_C24_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C31_C32
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C31_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C31_C32__CM_GAMUT_REMAP_C32_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_C33_C34
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33__SHIFT                                                 0x0
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34__SHIFT                                                 0x10
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C33_MASK                                                   0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_C33_C34__CM_GAMUT_REMAP_C34_MASK                                                   0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C11_C12
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C11_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C11_C12__CM_GAMUT_REMAP_B_C12_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C13_C14
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C13_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C13_C14__CM_GAMUT_REMAP_B_C14_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C21_C22
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C21_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C21_C22__CM_GAMUT_REMAP_B_C22_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C23_C24
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C23_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C23_C24__CM_GAMUT_REMAP_B_C24_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C31_C32
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C31_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C31_C32__CM_GAMUT_REMAP_B_C32_MASK                                               0xFFFF0000L
+//CM3_CM_GAMUT_REMAP_B_C33_C34
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33__SHIFT                                             0x0
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34__SHIFT                                             0x10
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C33_MASK                                               0x0000FFFFL
+#define CM3_CM_GAMUT_REMAP_B_C33_C34__CM_GAMUT_REMAP_B_C34_MASK                                               0xFFFF0000L
+//CM3_CM_BIAS_CR_R
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT                                                                 0x0
+#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK                                                                   0x0000FFFFL
+//CM3_CM_BIAS_Y_G_CB_B
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT                                                              0x0
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT                                                             0x10
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK                                                                0x0000FFFFL
+#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK                                                               0xFFFF0000L
+//CM3_CM_GAMCOR_CONTROL
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT                                                          0x0
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT                                                        0x2
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT                                                   0x3
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT                                                  0x4
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT                                                0x6
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK                                                            0x00000003L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK                                                          0x00000004L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK                                                     0x00000008L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK                                                    0x00000030L
+#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK                                                  0x00000040L
+//CM3_CM_GAMCOR_LUT_INDEX
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK                                                     0x000001FFL
+//CM3_CM_GAMCOR_LUT_DATA
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK                                                       0x0003FFFFL
+//CM3_CM_GAMCOR_LUT_CONTROL
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT                                      0x0
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT                                        0x3
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT                                              0x6
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT                                           0x7
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK                                        0x00000007L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK                                          0x00000018L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK                                                0x00000040L
+#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK                                             0x00000080L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMA_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMA_OFFSET_B
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_G
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_OFFSET_R
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMA_REGION_0_1
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_2_3
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_4_5
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_6_7
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_8_9
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_10_11
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_12_13
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_14_15
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_16_17
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_18_19
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_20_21
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_22_23
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_24_25
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_26_27
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_28_29
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_30_31
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMA_REGION_32_33
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT                 0x0
+#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK                   0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT                   0x0
+#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK                     0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_B
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_G
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_END_CNTL1_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK                             0x0003FFFFL
+//CM3_CM_GAMCOR_RAMB_END_CNTL2_R
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT                                0x0
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                          0x10
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK                                  0x0000FFFFL
+#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK                            0xFFFF0000L
+//CM3_CM_GAMCOR_RAMB_OFFSET_B
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_G
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_OFFSET_R
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT                                           0x0
+#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK                                             0x0007FFFFL
+//CM3_CM_GAMCOR_RAMB_REGION_0_1
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_2_3
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_4_5
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_6_7
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_8_9
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_10_11
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_12_13
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_14_15
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_16_17
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_18_19
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_20_21
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_22_23
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_24_25
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_26_27
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_28_29
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_30_31
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_GAMCOR_RAMB_REGION_32_33
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_BLNDGAM_CONTROL
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE__SHIFT                                                        0x0
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT__SHIFT                                                      0x2
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE__SHIFT                                                 0x3
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT__SHIFT                                                0x4
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT__SHIFT                                              0x6
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_MASK                                                          0x00000003L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_MASK                                                        0x00000004L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_PWL_DISABLE_MASK                                                   0x00000008L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_MODE_CURRENT_MASK                                                  0x00000030L
+#define CM3_CM_BLNDGAM_CONTROL__CM_BLNDGAM_SELECT_CURRENT_MASK                                                0x00000040L
+//CM3_CM_BLNDGAM_LUT_INDEX
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX__SHIFT                                                 0x0
+#define CM3_CM_BLNDGAM_LUT_INDEX__CM_BLNDGAM_LUT_INDEX_MASK                                                   0x000001FFL
+//CM3_CM_BLNDGAM_LUT_DATA
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA__SHIFT                                                   0x0
+#define CM3_CM_BLNDGAM_LUT_DATA__CM_BLNDGAM_LUT_DATA_MASK                                                     0x0003FFFFL
+//CM3_CM_BLNDGAM_LUT_CONTROL
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK__SHIFT                                    0x0
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL__SHIFT                                      0x3
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL__SHIFT                                            0x6
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE__SHIFT                                         0x7
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_WRITE_COLOR_MASK_MASK                                      0x00000007L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_READ_COLOR_SEL_MASK                                        0x00000018L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_HOST_SEL_MASK                                              0x00000040L
+#define CM3_CM_BLNDGAM_LUT_CONTROL__CM_BLNDGAM_LUT_CONFIG_MODE_MASK                                           0x00000080L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMA_START_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R__CM_BLNDGAM_RAMA_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_B__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_B__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_G__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_G__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL1_R__CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMA_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMA_END_CNTL2_R__CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMA_OFFSET_B
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_B__CM_BLNDGAM_RAMA_OFFSET_B_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_OFFSET_G
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_G__CM_BLNDGAM_RAMA_OFFSET_G_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_OFFSET_R
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMA_OFFSET_R__CM_BLNDGAM_RAMA_OFFSET_R_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMA_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_0_1__CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_2_3__CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_4_5__CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_6_7__CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_8_9__CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_10_11__CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_12_13__CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_14_15__CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_16_17__CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_18_19__CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_20_21__CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_22_23__CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_24_25__CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_26_27__CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_28_29__CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_30_31__CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMA_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMA_REGION_32_33__CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_B_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_G_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R__SHIFT                           0x0
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                   0x14
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_R_MASK                             0x0003FFFFL
+#define CM3_CM_BLNDGAM_RAMB_START_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                     0x07F00000L
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT               0x0
+#define CM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK                 0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_B_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_G_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT                 0x0
+#define CM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R__CM_BLNDGAM_RAMB_EXP_REGION_START_BASE_R_MASK                   0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_B__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_B
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_B_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_B__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_G__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_G
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_G_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_G__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_END_CNTL1_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL1_R__CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R_MASK                           0x0003FFFFL
+//CM3_CM_BLNDGAM_RAMB_END_CNTL2_R
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R__SHIFT                              0x0
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                        0x10
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_R_MASK                                0x0000FFFFL
+#define CM3_CM_BLNDGAM_RAMB_END_CNTL2_R__CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                          0xFFFF0000L
+//CM3_CM_BLNDGAM_RAMB_OFFSET_B
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_B__CM_BLNDGAM_RAMB_OFFSET_B_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_OFFSET_G
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_G__CM_BLNDGAM_RAMB_OFFSET_G_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_OFFSET_R
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R__SHIFT                                         0x0
+#define CM3_CM_BLNDGAM_RAMB_OFFSET_R__CM_BLNDGAM_RAMB_OFFSET_R_MASK                                           0x0007FFFFL
+//CM3_CM_BLNDGAM_RAMB_REGION_0_1
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_0_1__CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_2_3
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_2_3__CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_4_5
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_4_5__CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_6_7
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_6_7__CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_8_9
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                         0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                       0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                         0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                       0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                           0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                         0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                           0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_8_9__CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                         0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_10_11
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_10_11__CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_12_13
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_12_13__CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_14_15
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_14_15__CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_16_17
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_16_17__CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_18_19
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_18_19__CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_20_21
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_20_21__CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_22_23
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_22_23__CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_24_25
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_24_25__CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_26_27
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_26_27__CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_28_29
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_28_29__CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_30_31
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_30_31__CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_BLNDGAM_RAMB_REGION_32_33
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                      0x0
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                    0xc
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                      0x10
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                    0x1c
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                        0x000001FFL
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                      0x00007000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                        0x01FF0000L
+#define CM3_CM_BLNDGAM_RAMB_REGION_32_33__CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                      0x70000000L
+//CM3_CM_HDR_MULT_COEF
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT                                                         0x0
+#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK                                                           0x0007FFFFL
+//CM3_CM_MEM_PWR_CTRL
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT                                                      0x0
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT                                                        0x2
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE__SHIFT                                                     0x4
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS__SHIFT                                                       0x6
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK                                                        0x00000003L
+#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK                                                          0x00000004L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_FORCE_MASK                                                       0x00000030L
+#define CM3_CM_MEM_PWR_CTRL__BLNDGAM_MEM_PWR_DIS_MASK                                                         0x00000040L
+//CM3_CM_MEM_PWR_STATUS
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT                                                    0x0
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE__SHIFT                                                   0x2
+#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK                                                      0x00000003L
+#define CM3_CM_MEM_PWR_STATUS__BLNDGAM_MEM_PWR_STATE_MASK                                                     0x0000000CL
+//CM3_CM_DEALPHA
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT                                                                  0x0
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT                                                               0x1
+#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK                                                                    0x00000001L
+#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK                                                                 0x00000002L
+//CM3_CM_COEF_FORMAT
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT                                                             0x0
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT                                                    0x4
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT__SHIFT                                                 0x8
+#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
+#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
+#define CM3_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM3_CM_SHAPER_CONTROL
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE__SHIFT                                                      0x0
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT__SHIFT                                                  0x2
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_LUT_MODE_MASK                                                        0x00000003L
+#define CM3_CM_SHAPER_CONTROL__CM_SHAPER_MODE_CURRENT_MASK                                                    0x0000000CL
+//CM3_CM_SHAPER_OFFSET_R
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_R__CM_SHAPER_OFFSET_R_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_G
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_G__CM_SHAPER_OFFSET_G_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_OFFSET_B
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_OFFSET_B__CM_SHAPER_OFFSET_B_MASK                                                       0x0007FFFFL
+//CM3_CM_SHAPER_SCALE_R
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R__SHIFT                                                       0x0
+#define CM3_CM_SHAPER_SCALE_R__CM_SHAPER_SCALE_R_MASK                                                         0x0000FFFFL
+//CM3_CM_SHAPER_SCALE_G_B
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B__SHIFT                                                     0x10
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_G_MASK                                                       0x0000FFFFL
+#define CM3_CM_SHAPER_SCALE_G_B__CM_SHAPER_SCALE_B_MASK                                                       0xFFFF0000L
+//CM3_CM_SHAPER_LUT_INDEX
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX__SHIFT                                                   0x0
+#define CM3_CM_SHAPER_LUT_INDEX__CM_SHAPER_LUT_INDEX_MASK                                                     0x000000FFL
+//CM3_CM_SHAPER_LUT_DATA
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA__SHIFT                                                     0x0
+#define CM3_CM_SHAPER_LUT_DATA__CM_SHAPER_LUT_DATA_MASK                                                       0x00FFFFFFL
+//CM3_CM_SHAPER_LUT_WRITE_EN_MASK
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK__SHIFT                                   0x0
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL__SHIFT                                       0x4
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_EN_MASK_MASK                                     0x00000007L
+#define CM3_CM_SHAPER_LUT_WRITE_EN_MASK__CM_SHAPER_LUT_WRITE_SEL_MASK                                         0x00000010L
+//CM3_CM_SHAPER_RAMA_START_CNTL_B
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_G
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_START_CNTL_R
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMA_START_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_B
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_B__CM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_G
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_G__CM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_END_CNTL_R
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMA_END_CNTL_R__CM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMA_REGION_0_1
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_0_1__CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_2_3
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_2_3__CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_4_5
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_4_5__CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_6_7
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_6_7__CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_8_9
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_8_9__CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_10_11
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_10_11__CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_12_13
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_12_13__CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_14_15
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_14_15__CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_16_17
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_16_17__CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_18_19
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_18_19__CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_20_21
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_20_21__CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_22_23
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_22_23__CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_24_25
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_24_25__CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_26_27
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_26_27__CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_28_29
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_28_29__CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_30_31
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_30_31__CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMA_REGION_32_33
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMA_REGION_32_33__CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_B
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_B_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_G
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_G_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_START_CNTL_R
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                             0x0
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT                     0x14
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_R_MASK                               0x0003FFFFL
+#define CM3_CM_SHAPER_RAMB_START_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                       0x07F00000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_B
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_B_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_B__CM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_G
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_G_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_G__CM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_END_CNTL_R
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                                 0x0
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                            0x10
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_R_MASK                                   0x0000FFFFL
+#define CM3_CM_SHAPER_RAMB_END_CNTL_R__CM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                              0x3FFF0000L
+//CM3_CM_SHAPER_RAMB_REGION_0_1
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_0_1__CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_2_3
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_2_3__CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_4_5
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_4_5__CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_6_7
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_6_7__CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_8_9
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                           0x0
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                         0xc
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                           0x10
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                         0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                             0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                           0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                             0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_8_9__CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                           0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_10_11
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_10_11__CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_12_13
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_12_13__CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_14_15
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_14_15__CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_16_17
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_16_17__CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_18_19
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_18_19__CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_20_21
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_20_21__CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_22_23
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_22_23__CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_24_25
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_24_25__CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_26_27
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_26_27__CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_28_29
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_28_29__CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_30_31
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_30_31__CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_SHAPER_RAMB_REGION_32_33
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                        0x0
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT                      0xc
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                        0x10
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT                      0x1c
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                          0x000001FFL
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                        0x00007000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                          0x01FF0000L
+#define CM3_CM_SHAPER_RAMB_REGION_32_33__CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                        0x70000000L
+//CM3_CM_MEM_PWR_CTRL2
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE__SHIFT                                                     0x8
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS__SHIFT                                                       0xa
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE__SHIFT                                                   0xc
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS__SHIFT                                                     0xe
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_FORCE_MASK                                                       0x00000300L
+#define CM3_CM_MEM_PWR_CTRL2__SHAPER_MEM_PWR_DIS_MASK                                                         0x00000400L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_FORCE_MASK                                                     0x00003000L
+#define CM3_CM_MEM_PWR_CTRL2__HDR3DLUT_MEM_PWR_DIS_MASK                                                       0x00004000L
+//CM3_CM_MEM_PWR_STATUS2
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE__SHIFT                                                   0x4
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE__SHIFT                                                 0x6
+#define CM3_CM_MEM_PWR_STATUS2__SHAPER_MEM_PWR_STATE_MASK                                                     0x00000030L
+#define CM3_CM_MEM_PWR_STATUS2__HDR3DLUT_MEM_PWR_STATE_MASK                                                   0x000000C0L
+//CM3_CM_3DLUT_MODE
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE__SHIFT                                                               0x0
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE__SHIFT                                                               0x4
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT__SHIFT                                                       0x8
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_MASK                                                                 0x00000003L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_SIZE_MASK                                                                 0x00000010L
+#define CM3_CM_3DLUT_MODE__CM_3DLUT_MODE_CURRENT_MASK                                                         0x00000300L
+//CM3_CM_3DLUT_INDEX
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX__SHIFT                                                             0x0
+#define CM3_CM_3DLUT_INDEX__CM_3DLUT_INDEX_MASK                                                               0x000007FFL
+//CM3_CM_3DLUT_DATA
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0__SHIFT                                                              0x0
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1__SHIFT                                                              0x10
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA0_MASK                                                                0x0000FFFFL
+#define CM3_CM_3DLUT_DATA__CM_3DLUT_DATA1_MASK                                                                0xFFFF0000L
+//CM3_CM_3DLUT_DATA_30BIT
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT__SHIFT                                                   0x2
+#define CM3_CM_3DLUT_DATA_30BIT__CM_3DLUT_DATA_30BIT_MASK                                                     0xFFFFFFFCL
+//CM3_CM_3DLUT_READ_WRITE_CONTROL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK__SHIFT                                        0x0
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL__SHIFT                                              0x4
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN__SHIFT                                             0x8
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL__SHIFT                                             0x10
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_WRITE_EN_MASK_MASK                                          0x0000000FL
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_RAM_SEL_MASK                                                0x00000010L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_30BIT_EN_MASK                                               0x00000100L
+#define CM3_CM_3DLUT_READ_WRITE_CONTROL__CM_3DLUT_READ_SEL_MASK                                               0x00030000L
+//CM3_CM_3DLUT_OUT_NORM_FACTOR
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR__SHIFT                                         0x0
+#define CM3_CM_3DLUT_OUT_NORM_FACTOR__CM_3DLUT_OUT_NORM_FACTOR_MASK                                           0x0000FFFFL
+//CM3_CM_3DLUT_OUT_OFFSET_R
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_OFFSET_R_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_R__CM_3DLUT_OUT_SCALE_R_MASK                                                  0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_G
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_OFFSET_G_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_G__CM_3DLUT_OUT_SCALE_G_MASK                                                  0xFFFF0000L
+//CM3_CM_3DLUT_OUT_OFFSET_B
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B__SHIFT                                               0x0
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B__SHIFT                                                0x10
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_OFFSET_B_MASK                                                 0x0000FFFFL
+#define CM3_CM_3DLUT_OUT_OFFSET_B__CM_3DLUT_OUT_SCALE_B_MASK                                                  0xFFFF0000L
+//CM3_CM_TEST_DEBUG_INDEX
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
+//CM3_CM_TEST_DEBUG_DATA
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT                                                     0x0
+#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
+//DPP_TOP3_DPP_CONTROL
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT                                                    0x8
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT                                                0xa
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT                                               0xc
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT                                                    0xe
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                   0x10
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT                                                   0x12
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT                                                         0x1c
+#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK                                                           0x00000010L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK                                                      0x00000100L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK                                                  0x00000400L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK                                                 0x00001000L
+#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK                                                      0x00004000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                     0x00010000L
+#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK                                                     0x00040000L
+#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK                                                           0x70000000L
+//DPP_TOP3_DPP_SOFT_RESET
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT                                                       0x0
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT                                                       0x4
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT                                                         0x8
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT                                                       0xc
+#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK                                                         0x00000001L
+#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK                                                         0x00000010L
+#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK                                                           0x00000100L
+#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK                                                         0x00001000L
+//DPP_TOP3_DPP_CRC_VAL_R_G
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y__SHIFT                                                          0x10
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_R_CR_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_R_G__DPP_CRC_G_Y_MASK                                                            0xFFFF0000L
+//DPP_TOP3_DPP_CRC_VAL_B_A
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB__SHIFT                                                         0x0
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA__SHIFT                                                        0x10
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_B_CB_MASK                                                           0x0000FFFFL
+#define DPP_TOP3_DPP_CRC_VAL_B_A__DPP_CRC_ALPHA_MASK                                                          0xFFFF0000L
+//DPP_TOP3_DPP_CRC_CTRL
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT                                                              0x0
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT                                                         0x1
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT                                                0x2
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT                                                    0x3
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT                                                         0x4
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT                                                       0x6
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT                                                     0x7
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT                                                  0x9
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT                                                  0xb
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL__SHIFT                                               0xe
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT                                                            0x10
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK                                                                0x00000001L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK                                                           0x00000002L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK                                                  0x00000004L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK                                                      0x00000008L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK                                                           0x00000030L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK                                                         0x00000040L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK                                                       0x00000180L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK                                                    0x00000600L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK                                                    0x00003800L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CURSOR_FORMAT_SEL_MASK                                                 0x0000C000L
+#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK                                                              0xFFFF0000L
+//DPP_TOP3_HOST_READ_CONTROL
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                             0x0
+#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                               0x000000FFL
+
+
+// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON14_PERFCOUNTER_CNTL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_CNTL2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON14_PERFCOUNTER_STATE
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON14_PERFMON_CNTL
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON14_PERFMON_CNTL2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON14_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON14_PERFMON_CVALUE_LOW
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON14_PERFMON_HI
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON14_PERFMON_LOW
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mpc_mpcc0_dispdec
+//MPCC0_MPCC_TOP_SEL
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_BOT_SEL
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC0_MPCC_OPP_ID
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC0_MPCC_CONTROL
+#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC0_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC0_MPCC_SM_CONTROL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC0_MPCC_UPDATE_LOCK_SEL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC0_MPCC_TOP_GAIN
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_INSIDE
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC0_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC0_MPCC_BG_R_CR
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_BG_G_Y
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC0_MPCC_BG_B_CB
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC0_MPCC_MEM_PWR_CTRL
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC0_MPCC_STATUS
+#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc1_dispdec
+//MPCC1_MPCC_TOP_SEL
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_BOT_SEL
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC1_MPCC_OPP_ID
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC1_MPCC_CONTROL
+#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC1_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC1_MPCC_SM_CONTROL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC1_MPCC_UPDATE_LOCK_SEL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC1_MPCC_TOP_GAIN
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_INSIDE
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC1_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC1_MPCC_BG_R_CR
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_BG_G_Y
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC1_MPCC_BG_B_CB
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC1_MPCC_MEM_PWR_CTRL
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC1_MPCC_STATUS
+#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc2_dispdec
+//MPCC2_MPCC_TOP_SEL
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_BOT_SEL
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC2_MPCC_OPP_ID
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC2_MPCC_CONTROL
+#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC2_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC2_MPCC_SM_CONTROL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC2_MPCC_UPDATE_LOCK_SEL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC2_MPCC_TOP_GAIN
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_INSIDE
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC2_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC2_MPCC_BG_R_CR
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_BG_G_Y
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC2_MPCC_BG_B_CB
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC2_MPCC_MEM_PWR_CTRL
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC2_MPCC_STATUS
+#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpcc3_dispdec
+//MPCC3_MPCC_TOP_SEL
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_BOT_SEL
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT                                                               0x0
+#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK                                                                 0x0000000FL
+//MPCC3_MPCC_OPP_ID
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT                                                                 0x0
+#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK                                                                   0x0000000FL
+//MPCC3_MPCC_CONTROL
+#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT                                                                  0x0
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT                                                       0x4
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT                                                 0x6
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT                                              0x7
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT                                                                0x8
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT                                                         0xb
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA__SHIFT                                                          0x10
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN__SHIFT                                                           0x18
+#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK                                                                    0x00000003L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK                                                         0x00000030L
+#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK                                                   0x00000040L
+#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK                                                0x00000080L
+#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK                                                                  0x00000700L
+#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK                                                           0x00000800L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_ALPHA_MASK                                                            0x00FF0000L
+#define MPCC3_MPCC_CONTROL__MPCC_GLOBAL_GAIN_MASK                                                             0xFF000000L
+//MPCC3_MPCC_SM_CONTROL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT                                                              0x0
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT                                                            0x1
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT                                                       0x4
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT                                                       0x5
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT                                            0x8
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT                                              0x10
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT                                               0x18
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK                                                                0x00000001L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK                                                              0x0000000EL
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK                                                         0x00000010L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK                                                         0x00000020L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK                                              0x00000300L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK                                                0x00030000L
+#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK                                                 0x01000000L
+//MPCC3_MPCC_UPDATE_LOCK_SEL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT                                               0x0
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT                                          0x4
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK                                                 0x0000000FL
+#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK                                            0x00000070L
+//MPCC3_MPCC_TOP_GAIN
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT                                                             0x0
+#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK                                                               0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_INSIDE
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT                                               0x0
+#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK                                                 0x0007FFFFL
+//MPCC3_MPCC_BOT_GAIN_OUTSIDE
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT                                             0x0
+#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK                                               0x0007FFFFL
+//MPCC3_MPCC_BG_R_CR
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_BG_G_Y
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT                                                                 0x0
+#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK                                                                   0x00000FFFL
+//MPCC3_MPCC_BG_B_CB
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT                                                               0x0
+#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK                                                                 0x00000FFFL
+//MPCC3_MPCC_MEM_PWR_CTRL
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT                                               0x0
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT                                                 0x2
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT                                            0x4
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT                                               0x8
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK                                                 0x00000003L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK                                                   0x00000004L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK                                              0x00000030L
+#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK                                                 0x00000300L
+//MPCC3_MPCC_STATUS
+#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT                                                                   0x0
+#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT                                                                   0x1
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT                                                               0x2
+#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK                                                                     0x00000001L
+#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK                                                                     0x00000002L
+#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK                                                                 0x00000004L
+
+
+// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
+//MPC_CLOCK_CONTROL
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT                                                      0x1
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT                                                            0x4
+#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK                                                        0x00000002L
+#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK                                                              0x00000030L
+//MPC_SOFT_RESET
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT                                                               0x0
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT                                                               0x1
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT                                                               0x2
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT                                                               0x3
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT                                                            0xa
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT                                                            0xb
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT                                                            0xc
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT                                                            0xd
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT                                                            0x14
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT                                                            0x15
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT                                                            0x16
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT                                                            0x17
+#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT                                                                 0x1f
+#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK                                                                 0x00000001L
+#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK                                                                 0x00000002L
+#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK                                                                 0x00000004L
+#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK                                                                 0x00000008L
+#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK                                                              0x00000400L
+#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK                                                              0x00000800L
+#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK                                                              0x00001000L
+#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK                                                              0x00002000L
+#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK                                                              0x00100000L
+#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK                                                              0x00200000L
+#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK                                                              0x00400000L
+#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK                                                              0x00800000L
+#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK                                                                   0x80000000L
+//MPC_CRC_CTRL
+#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT                                                                       0x0
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT                                                                  0x4
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT                                                              0x8
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT                                                                0xa
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT                                                           0xc
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT                                                                  0x18
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT                                                         0x1c
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT                                                           0x1e
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT                                                              0x1f
+#define MPC_CRC_CTRL__MPC_CRC_EN_MASK                                                                         0x00000001L
+#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK                                                                    0x00000010L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK                                                                0x00000300L
+#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK                                                                  0x00000400L
+#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK                                                             0x00003000L
+#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK                                                                    0x03000000L
+#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK                                                           0x10000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK                                                             0x40000000L
+#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK                                                                0x80000000L
+//MPC_CRC_SEL_CONTROL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT                                                           0x0
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT                                                           0x4
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT                                                           0x8
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT                                                              0x10
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK                                                             0x0000000FL
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK                                                             0x000000F0L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK                                                             0x00000300L
+#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK                                                                0xFFFF0000L
+//MPC_CRC_RESULT_AR
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_A_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_AR__MPC_CRC_RESULT_R_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_GB
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G__SHIFT                                                            0x0
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B__SHIFT                                                            0x10
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_G_MASK                                                              0x0000FFFFL
+#define MPC_CRC_RESULT_GB__MPC_CRC_RESULT_B_MASK                                                              0xFFFF0000L
+//MPC_CRC_RESULT_C
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C__SHIFT                                                             0x0
+#define MPC_CRC_RESULT_C__MPC_CRC_RESULT_C_MASK                                                               0x0000FFFFL
+//MPC_PERFMON_EVENT_CTRL
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT                                                   0x0
+#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK                                                     0x00000001L
+//MPC_BYPASS_BG_AR
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT                                                          0x0
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK                                                            0x0000FFFFL
+#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK                                                             0xFFFF0000L
+//MPC_BYPASS_BG_GB
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT                                                            0x0
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT                                                           0x10
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK                                                              0x0000FFFFL
+#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK                                                             0xFFFF0000L
+//MPC_HOST_READ_CONTROL
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT                                                  0x0
+#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK                                                    0x000000FFL
+//MPC_DPP_PENDING_STATUS
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT                                         0x0
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT                                          0x1
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT                                          0x2
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT                                         0x4
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT                                          0x5
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT                                          0x6
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT                                         0x8
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT                                          0x9
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT                                          0xa
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT                                         0xc
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT                                          0xd
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT                                          0xe
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK                                           0x00000001L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK                                            0x00000002L
+#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK                                            0x00000004L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK                                           0x00000010L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK                                            0x00000020L
+#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK                                            0x00000040L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK                                           0x00000100L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK                                            0x00000200L
+#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK                                            0x00000400L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK                                           0x00001000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK                                            0x00002000L
+#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK                                            0x00004000L
+//MPC_PENDING_STATUS_MISC
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT                                        0x0
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT                                        0x1
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT                                        0x2
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT                                        0x3
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT                                           0x8
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT                                           0x9
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT                                           0xa
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT                                           0xb
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT                                         0x10
+#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK                                          0x00000001L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK                                          0x00000002L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK                                          0x00000004L
+#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK                                          0x00000008L
+#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK                                             0x00000100L
+#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK                                             0x00000200L
+#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK                                             0x00000400L
+#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK                                             0x00000800L
+#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK                                           0x00010000L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET1
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET1
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET1
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET1
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET1
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET2
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET2
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET2
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET2
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET2
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//ADR_CFG_CUR_VUPDATE_LOCK_SET3
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT                                    0x0
+#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK                                      0x00000001L
+//ADR_CFG_VUPDATE_LOCK_SET3
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT                                            0x0
+#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK                                              0x00000001L
+//ADR_VUPDATE_LOCK_SET3
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CFG_VUPDATE_LOCK_SET3
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//CUR_VUPDATE_LOCK_SET3
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT                                                    0x0
+#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK                                                      0x00000001L
+//MPC_DWB0_MUX
+#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT                                                                     0x0
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT                                                              0x4
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK                                                                       0x0000000FL
+#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK                                                                0x000000F0L
+
+
+// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON15_PERFCOUNTER_CNTL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_CNTL2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON15_PERFCOUNTER_STATE
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON15_PERFMON_CNTL
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON15_PERFMON_CNTL2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON15_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON15_PERFMON_CVALUE_LOW
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON15_PERFMON_HI
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON15_PERFMON_LOW
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
+//MPCC_OGAM0_MPCC_OGAM_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
+//MPCC_OGAM1_MPCC_OGAM_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
+//MPCC_OGAM2_MPCC_OGAM_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
+//MPCC_OGAM3_MPCC_OGAM_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT                                                   0x0
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT                                                 0x2
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT                                            0x3
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT                                           0x7
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT                                         0x9
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK                                                     0x00000003L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK                                                   0x00000004L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK                                              0x00000008L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK                                             0x00000180L
+#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK                                           0x00000200L
+//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT                                            0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK                                              0x000001FFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_DATA
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT                                              0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK                                                0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT                               0x0
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT                                 0x3
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT                                       0x5
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT                                       0x6
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT                                    0x7
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK                                 0x00000007L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK                                   0x00000018L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK                                         0x00000020L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK                                         0x00000040L
+#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK                                      0x00000080L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT          0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK            0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT            0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK              0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK                      0x0003FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT                         0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT                   0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK                           0x0000FFFFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK                     0xFFFF0000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT                                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK                                      0x0007FFFFL
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT                          0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK                            0x00000001L
+//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT                                        0x0
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT                                0x7
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK                                          0x00000003L
+#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK                                  0x00000180L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK                                     0xFFFF0000L
+//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT                                   0x0
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT                                   0x10
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK                                     0x0000FFFFL
+#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK                                     0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
+//MPC_OUT0_MUX
+#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT0_DENORM_CONTROL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT0_DENORM_CLAMP_G_Y
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT0_DENORM_CLAMP_B_CB
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT1_MUX
+#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT1_DENORM_CONTROL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT1_DENORM_CLAMP_G_Y
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT1_DENORM_CLAMP_B_CB
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT2_MUX
+#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT2_DENORM_CONTROL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT2_DENORM_CLAMP_G_Y
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT2_DENORM_CLAMP_B_CB
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT3_MUX
+#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT                                                                      0x0
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT                                                  0x5
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT                                                   0x7
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT                                                     0x8
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT                                                             0x9
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT                                                        0xa
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT                                                       0xb
+#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK                                                                        0x0000000FL
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK                                                    0x00000020L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK                                                     0x00000080L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK                                                       0x00000100L
+#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK                                                               0x00000200L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK                                                          0x00000400L
+#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK                                                         0x007FF800L
+//MPC_OUT3_DENORM_CONTROL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT                                         0x0
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT                                         0xc
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT                                                   0x18
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK                                           0x00000FFFL
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK                                           0x00FFF000L
+#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK                                                     0x07000000L
+//MPC_OUT3_DENORM_CLAMP_G_Y
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT                                        0x0
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT                                        0xc
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK                                          0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK                                          0x00FFF000L
+//MPC_OUT3_DENORM_CLAMP_B_CB
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT                                      0x0
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT                                      0xc
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK                                        0x00000FFFL
+#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK                                        0x00FFF000L
+//MPC_OUT_CSC_COEF_FORMAT
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT                                                 0x0
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT                                                 0x1
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT                                                 0x2
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT                                                 0x3
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK                                                   0x00000001L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK                                                   0x00000002L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK                                                   0x00000004L
+#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK                                                   0x00000008L
+//MPC_OUT0_CSC_MODE
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT0_CSC_C11_C12_A
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_A
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_A
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_A
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_A
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_A
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C11_C12_B
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C13_C14_B
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C21_C22_B
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C23_C24_B
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C31_C32_B
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT0_CSC_C33_C34_B
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_MODE
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT1_CSC_C11_C12_A
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_A
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_A
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_A
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_A
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_A
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C11_C12_B
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C13_C14_B
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C21_C22_B
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C23_C24_B
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C31_C32_B
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT1_CSC_C33_C34_B
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_MODE
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT2_CSC_C11_C12_A
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_A
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_A
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_A
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_A
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_A
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C11_C12_B
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C13_C14_B
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C21_C22_B
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C23_C24_B
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C31_C32_B
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT2_CSC_C33_C34_B
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_MODE
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT                                                               0x0
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT                                                       0x7
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK                                                                 0x00000003L
+#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK                                                         0x00000180L
+//MPC_OUT3_CSC_C11_C12_A
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_A
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_A
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_A
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_A
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_A
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C11_C12_B
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C13_C14_B
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C21_C22_B
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C23_C24_B
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C31_C32_B
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK                                                           0xFFFF0000L
+//MPC_OUT3_CSC_C33_C34_B
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT                                                         0x0
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT                                                         0x10
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK                                                           0x0000FFFFL
+#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK                                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
+//MPC_RMU_CONTROL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX__SHIFT                                                                  0x0
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS__SHIFT                                                           0x4
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX__SHIFT                                                                  0x8
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS__SHIFT                                                           0xc
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_MASK                                                                    0x0000000FL
+#define MPC_RMU_CONTROL__MPC_RMU0_MUX_STATUS_MASK                                                             0x000000F0L
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_MASK                                                                    0x00000F00L
+#define MPC_RMU_CONTROL__MPC_RMU1_MUX_STATUS_MASK                                                             0x0000F000L
+//MPC_RMU_MEM_PWR_CTRL
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE__SHIFT                                                   0x0
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS__SHIFT                                                     0x2
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE__SHIFT                                            0x4
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE__SHIFT                                             0x6
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE__SHIFT                                                0x8
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE__SHIFT                                                   0xa
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS__SHIFT                                                     0xc
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE__SHIFT                                            0xe
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE__SHIFT                                             0x10
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE__SHIFT                                                0x12
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_FORCE_MASK                                                     0x00000003L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_PWR_DIS_MASK                                                       0x00000004L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_SHAPER_MEM_PWR_STATE_MASK                                              0x00000030L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_3DLUT_MEM_PWR_STATE_MASK                                               0x000000C0L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU0_MEM_LOW_PWR_MODE_MASK                                                  0x00000300L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_FORCE_MASK                                                     0x00000C00L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_PWR_DIS_MASK                                                       0x00001000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_SHAPER_MEM_PWR_STATE_MASK                                              0x0000C000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_3DLUT_MEM_PWR_STATE_MASK                                               0x00030000L
+#define MPC_RMU_MEM_PWR_CTRL__MPC_RMU1_MEM_LOW_PWR_MODE_MASK                                                  0x000C0000L
+//MPC_RMU0_SHAPER_CONTROL
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU0_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU0_SHAPER_OFFSET_R
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_G
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_OFFSET_B
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU0_SHAPER_SCALE_R
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU0_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU0_SHAPER_SCALE_G_B
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU0_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU0_SHAPER_LUT_INDEX
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU0_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU0_SHAPER_LUT_DATA
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU0_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU0_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU0_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU0_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU0_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU0_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU0_3DLUT_MODE
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU0_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU0_3DLUT_INDEX
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU0_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU0_3DLUT_DATA
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU0_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU0_3DLUT_DATA_30BIT
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU0_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU0_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU0_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU0_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU0_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU0_3DLUT_OUT_OFFSET_R
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_G
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU0_3DLUT_OUT_OFFSET_B
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU0_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+//MPC_RMU1_SHAPER_CONTROL
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE__SHIFT                                               0x0
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT__SHIFT                                           0x8
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_LUT_MODE_MASK                                                 0x00000003L
+#define MPC_RMU1_SHAPER_CONTROL__MPC_RMU_SHAPER_MODE_CURRENT_MASK                                             0x00000300L
+//MPC_RMU1_SHAPER_OFFSET_R
+#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_R__MPC_RMU_SHAPER_OFFSET_R_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_OFFSET_G
+#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_G__MPC_RMU_SHAPER_OFFSET_G_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_OFFSET_B
+#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_OFFSET_B__MPC_RMU_SHAPER_OFFSET_B_MASK                                                0x0007FFFFL
+//MPC_RMU1_SHAPER_SCALE_R
+#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R__SHIFT                                                0x0
+#define MPC_RMU1_SHAPER_SCALE_R__MPC_RMU_SHAPER_SCALE_R_MASK                                                  0x0000FFFFL
+//MPC_RMU1_SHAPER_SCALE_G_B
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B__SHIFT                                              0x10
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_G_MASK                                                0x0000FFFFL
+#define MPC_RMU1_SHAPER_SCALE_G_B__MPC_RMU_SHAPER_SCALE_B_MASK                                                0xFFFF0000L
+//MPC_RMU1_SHAPER_LUT_INDEX
+#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX__SHIFT                                            0x0
+#define MPC_RMU1_SHAPER_LUT_INDEX__MPC_RMU_SHAPER_LUT_INDEX_MASK                                              0x000000FFL
+//MPC_RMU1_SHAPER_LUT_DATA
+#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA__SHIFT                                              0x0
+#define MPC_RMU1_SHAPER_LUT_DATA__MPC_RMU_SHAPER_LUT_DATA_MASK                                                0x00FFFFFFL
+//MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK__SHIFT                            0x0
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL__SHIFT                                0x4
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_EN_MASK_MASK                              0x00000007L
+#define MPC_RMU1_SHAPER_LUT_WRITE_EN_MASK__MPC_RMU_SHAPER_LUT_WRITE_SEL_MASK                                  0x00000010L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_B
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_G
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_START_CNTL_R
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMA_START_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_B
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_B__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_G
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_G__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_END_CNTL_R
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMA_END_CNTL_R__MPC_RMU_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMA_REGION_0_1
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_0_1__MPC_RMU_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_2_3
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_2_3__MPC_RMU_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_4_5
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_4_5__MPC_RMU_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_6_7
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_6_7__MPC_RMU_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_8_9
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_8_9__MPC_RMU_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_10_11
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_10_11__MPC_RMU_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_12_13
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_12_13__MPC_RMU_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_14_15
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_14_15__MPC_RMU_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_16_17
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_16_17__MPC_RMU_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_18_19
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_18_19__MPC_RMU_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_20_21
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_20_21__MPC_RMU_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_22_23
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_22_23__MPC_RMU_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_24_25
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_24_25__MPC_RMU_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_26_27
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_26_27__MPC_RMU_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_28_29
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_28_29__MPC_RMU_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_30_31
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_30_31__MPC_RMU_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMA_REGION_32_33
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMA_REGION_32_33__MPC_RMU_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_B
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_B_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_G
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_G_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_START_CNTL_R
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R__SHIFT                      0x0
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT              0x14
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_R_MASK                        0x0003FFFFL
+#define MPC_RMU1_SHAPER_RAMB_START_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK                0x07F00000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_B
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_B_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_B__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_G
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_G_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_G__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_END_CNTL_R
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R__SHIFT                          0x0
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT                     0x10
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_R_MASK                            0x0000FFFFL
+#define MPC_RMU1_SHAPER_RAMB_END_CNTL_R__MPC_RMU_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK                       0x3FFF0000L
+//MPC_RMU1_SHAPER_RAMB_REGION_0_1
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_0_1__MPC_RMU_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_2_3
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_2_3__MPC_RMU_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_4_5
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_4_5__MPC_RMU_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_6_7
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_6_7__MPC_RMU_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_8_9
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT                    0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT                  0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT                    0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT                  0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK                      0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK                    0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK                      0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_8_9__MPC_RMU_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK                    0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_10_11
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_10_11__MPC_RMU_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_12_13
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_12_13__MPC_RMU_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_14_15
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_14_15__MPC_RMU_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_16_17
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_16_17__MPC_RMU_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_18_19
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_18_19__MPC_RMU_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_20_21
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_20_21__MPC_RMU_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_22_23
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_22_23__MPC_RMU_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_24_25
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_24_25__MPC_RMU_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_26_27
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_26_27__MPC_RMU_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_28_29
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_28_29__MPC_RMU_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_30_31
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_30_31__MPC_RMU_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_SHAPER_RAMB_REGION_32_33
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT                 0x0
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT               0xc
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT                 0x10
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT               0x1c
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK                   0x000001FFL
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK                 0x00007000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK                   0x01FF0000L
+#define MPC_RMU1_SHAPER_RAMB_REGION_32_33__MPC_RMU_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK                 0x70000000L
+//MPC_RMU1_3DLUT_MODE
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE__SHIFT                                                        0x0
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE__SHIFT                                                        0x4
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT__SHIFT                                                0x8
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_MASK                                                          0x00000003L
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_SIZE_MASK                                                          0x00000010L
+#define MPC_RMU1_3DLUT_MODE__MPC_RMU_3DLUT_MODE_CURRENT_MASK                                                  0x00000300L
+//MPC_RMU1_3DLUT_INDEX
+#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX__SHIFT                                                      0x0
+#define MPC_RMU1_3DLUT_INDEX__MPC_RMU_3DLUT_INDEX_MASK                                                        0x000007FFL
+//MPC_RMU1_3DLUT_DATA
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0__SHIFT                                                       0x0
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1__SHIFT                                                       0x10
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA0_MASK                                                         0x0000FFFFL
+#define MPC_RMU1_3DLUT_DATA__MPC_RMU_3DLUT_DATA1_MASK                                                         0xFFFF0000L
+//MPC_RMU1_3DLUT_DATA_30BIT
+#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT__SHIFT                                            0x2
+#define MPC_RMU1_3DLUT_DATA_30BIT__MPC_RMU_3DLUT_DATA_30BIT_MASK                                              0xFFFFFFFCL
+//MPC_RMU1_3DLUT_READ_WRITE_CONTROL
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK__SHIFT                                 0x0
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL__SHIFT                                       0x4
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN__SHIFT                                      0x8
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL__SHIFT                                      0x10
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_WRITE_EN_MASK_MASK                                   0x0000000FL
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_RAM_SEL_MASK                                         0x00000010L
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_30BIT_EN_MASK                                        0x00000100L
+#define MPC_RMU1_3DLUT_READ_WRITE_CONTROL__MPC_RMU_3DLUT_READ_SEL_MASK                                        0x00030000L
+//MPC_RMU1_3DLUT_OUT_NORM_FACTOR
+#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR__SHIFT                                  0x0
+#define MPC_RMU1_3DLUT_OUT_NORM_FACTOR__MPC_RMU_3DLUT_OUT_NORM_FACTOR_MASK                                    0x0000FFFFL
+//MPC_RMU1_3DLUT_OUT_OFFSET_R
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_OFFSET_R_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_R__MPC_RMU_3DLUT_OUT_SCALE_R_MASK                                           0xFFFF0000L
+//MPC_RMU1_3DLUT_OUT_OFFSET_G
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_OFFSET_G_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_G__MPC_RMU_3DLUT_OUT_SCALE_G_MASK                                           0xFFFF0000L
+//MPC_RMU1_3DLUT_OUT_OFFSET_B
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B__SHIFT                                        0x0
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B__SHIFT                                         0x10
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_OFFSET_B_MASK                                          0x0000FFFFL
+#define MPC_RMU1_3DLUT_OUT_OFFSET_B__MPC_RMU_3DLUT_OUT_SCALE_B_MASK                                           0xFFFF0000L
+
+
+// addressBlock: dce_dc_opp_abm0_dispdec
+//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM0_BL1_PWM_USER_LEVEL
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM0_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM0_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM0_BL1_PWM_ABM_CNTL
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM0_BL1_PWM_GRP2_REG_LOCK
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM0_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM0_DC_ABM1_CNTL
+#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM0_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_12
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_THRES_34
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM0_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM0_DC_ABM1_ACE_CNTL_MISC
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM0_DC_ABM1_HG_MISC_CTRL
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM0_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM0_DC_ABM1_LS_PIXEL_COUNT
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM0_DC_ABM1_HG_SAMPLE_RATE
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_LS_SAMPLE_RATE
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_1
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_2
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_3
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_4
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_5
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_6
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_7
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_8
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_9
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM0_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_10
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_11
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_12
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_13
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_14
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_15
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_16
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_17
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_18
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_19
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_20
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_21
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_22
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_23
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_HG_RESULT_24
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM0_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM0_DC_ABM1_BL_MASTER_LOCK
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm1_dispdec
+//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM1_BL1_PWM_USER_LEVEL
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM1_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM1_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM1_BL1_PWM_ABM_CNTL
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM1_BL1_PWM_GRP2_REG_LOCK
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM1_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM1_DC_ABM1_CNTL
+#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM1_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_12
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_THRES_34
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM1_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM1_DC_ABM1_ACE_CNTL_MISC
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM1_DC_ABM1_HG_MISC_CTRL
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM1_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM1_DC_ABM1_LS_PIXEL_COUNT
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM1_DC_ABM1_HG_SAMPLE_RATE
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_LS_SAMPLE_RATE
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_1
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_2
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_3
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_4
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_5
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_6
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_7
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_8
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_9
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM1_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_10
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_11
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_12
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_13
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_14
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_15
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_16
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_17
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_18
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_19
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_20
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_21
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_22
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_23
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_HG_RESULT_24
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM1_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM1_DC_ABM1_BL_MASTER_LOCK
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm2_dispdec
+//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM2_BL1_PWM_USER_LEVEL
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM2_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM2_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM2_BL1_PWM_ABM_CNTL
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM2_BL1_PWM_GRP2_REG_LOCK
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM2_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM2_DC_ABM1_CNTL
+#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM2_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_12
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_THRES_34
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM2_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM2_DC_ABM1_ACE_CNTL_MISC
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM2_DC_ABM1_HG_MISC_CTRL
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM2_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM2_DC_ABM1_LS_PIXEL_COUNT
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM2_DC_ABM1_HG_SAMPLE_RATE
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_LS_SAMPLE_RATE
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_1
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_2
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_3
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_4
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_5
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_6
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_7
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_8
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_9
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM2_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_10
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_11
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_12
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_13
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_14
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_15
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_16
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_17
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_18
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_19
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_20
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_21
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_22
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_23
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_HG_RESULT_24
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM2_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM2_DC_ABM1_BL_MASTER_LOCK
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_abm3_dispdec
+//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT                                  0x0
+#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK                                    0x0001FFFFL
+//ABM3_BL1_PWM_USER_LEVEL
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT                                                    0x0
+#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK                                                      0x0001FFFFL
+//ABM3_BL1_PWM_TARGET_ABM_LEVEL
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT                                        0x0
+#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_CURRENT_ABM_LEVEL
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT                                      0x0
+#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK                                        0x0001FFFFL
+//ABM3_BL1_PWM_FINAL_DUTY_CYCLE
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT                                        0x0
+#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK                                          0x0001FFFFL
+//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT                                    0x0
+#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK                                      0x0001FFFFL
+//ABM3_BL1_PWM_ABM_CNTL
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT                                                      0x0
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT                                            0x1
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT                                0x2
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT                                   0x3
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT                               0x10
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK                                                        0x00000001L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK                                              0x00000002L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK                                  0x00000004L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK                                     0x00000008L
+#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK                                 0xFFFF0000L
+//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT                     0x0
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT          0x1
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT                  0x8
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT  0x10
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                         0x1f
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK                       0x00000001L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK            0x00000002L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK                    0x0000FF00L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK  0x00FF0000L
+#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                           0x80000000L
+//ABM3_BL1_PWM_GRP2_REG_LOCK
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT                                              0x0
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT                                    0x8
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT                                 0x10
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT                                  0x11
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT                              0x18
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT                                 0x1f
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK                                                0x00000001L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK                                      0x00000100L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK                                   0x00010000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK                                    0x000E0000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK                                0x01000000L
+#define ABM3_BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK                                   0x80000000L
+//ABM3_DC_ABM1_CNTL
+#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT                                                                     0x0
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT                                                      0x4
+#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK                                                                       0x00000001L
+#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK                                                        0x00000010L
+//ABM3_DC_ABM1_IPCSC_COEFF_SEL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT                                           0x0
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT                                           0x8
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT                                           0x10
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK                                             0x0000000FL
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK                                             0x00000F00L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK                                             0x000F0000L
+#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK                                                 0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT                                              0x0
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT                                             0x10
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT                                                 0x1f
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK                                                0x00007FFFL
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK                                               0x07FF0000L
+#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK                                                   0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_12
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_THRES_34
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT                                                    0x0
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT                                                    0x10
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT                                      0x1c
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT                                   0x1d
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT                                    0x1e
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT                                                       0x1f
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK                                                      0x000003FFL
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK                                                      0x03FF0000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK                                        0x10000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK                                     0x20000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK                                      0x40000000L
+#define ABM3_DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK                                                         0x80000000L
+//ABM3_DC_ABM1_ACE_CNTL_MISC
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT                                       0x0
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT                                 0x8
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK                                         0x00000001L
+#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK                                   0x00000100L
+//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT                              0x0
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT                              0x1
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT                              0x2
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT                             0x8
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT                             0x9
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT                             0xa
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x10
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x18
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT                       0x1f
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK                                0x00000001L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK                                0x00000002L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK                                0x00000004L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK                               0x00000100L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK                               0x00000200L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK                               0x00000400L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x00010000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x01000000L
+#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK                         0x80000000L
+//ABM3_DC_ABM1_HG_MISC_CTRL
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT                                             0x0
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT                                                    0x8
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT                                           0xc
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT                                       0x10
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT                                      0x14
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT                             0x17
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT                             0x18
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT                            0x1c
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT                                     0x1d
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT                                   0x1e
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT                                                  0x1f
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK                                               0x00000003L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK                                                      0x00000100L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK                                             0x00001000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK                                         0x00030000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK                                        0x00100000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK                               0x00800000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK                               0x07000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK                              0x10000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK                                       0x20000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK                                     0x40000000L
+#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK                                                    0x80000000L
+//ABM3_DC_ABM1_LS_SUM_OF_LUMA
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK                                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_LS_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT                                                 0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT                                                 0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK                                                   0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK                                                   0x03FF0000L
+//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT                               0x0
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT                               0x10
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK                                 0x000003FFL
+#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK                                 0x03FF0000L
+//ABM3_DC_ABM1_LS_PIXEL_COUNT
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT                                               0x0
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT                                           0x18
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK                                                 0x00FFFFFFL
+#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_SUM_OF_LUMA_MSB_MASK                                             0xFF000000L
+//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT                       0x0
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT                       0x10
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT                                  0x1f
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK                         0x000003FFL
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK                         0x03FF0000L
+#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK                                    0x80000000L
+//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT                           0x0
+#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK                             0x00FFFFFFL
+//ABM3_DC_ABM1_HG_SAMPLE_RATE
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_LS_SAMPLE_RATE
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT                                      0x0
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT                           0x1
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT                                   0x8
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT                0x10
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT                                                0x1f
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK                                        0x00000001L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK                             0x00000002L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK                                     0x0000FF00L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK                  0x00FF0000L
+#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK                                                  0x80000000L
+//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT                               0x0
+#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK                                 0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT                             0x0
+#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK                               0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT                           0x0
+#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK                             0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_1
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_2
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_3
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_4
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_5
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_6
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_7
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_8
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_9
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT                                                     0x0
+#define ABM3_DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK                                                       0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_10
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_11
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_12
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_13
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_14
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_15
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_16
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_17
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_18
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_19
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_20
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_21
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_22
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_23
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_HG_RESULT_24
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT                                                   0x0
+#define ABM3_DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK                                                     0xFFFFFFFFL
+//ABM3_DC_ABM1_BL_MASTER_LOCK
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT                                               0x1f
+#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK                                                 0x80000000L
+
+
+// addressBlock: dce_dc_opp_dpg0_dispdec
+//DPG0_DPG_CONTROL
+#define DPG0_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG0_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG0_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG0_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG0_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG0_DPG_RAMP_CONTROL
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG0_DPG_DIMENSIONS
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG0_DPG_COLOUR_R_CR
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG0_DPG_COLOUR_G_Y
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG0_DPG_COLOUR_B_CB
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG0_DPG_OFFSET_SEGMENT
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG0_DPG_STATUS
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt0_dispdec
+//FMT0_FMT_CLAMP_COMPONENT_R
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_G
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT0_FMT_CLAMP_COMPONENT_B
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT0_FMT_DYNAMIC_EXP_CNTL
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT0_FMT_CONTROL
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT0_FMT_BIT_DEPTH_CONTROL
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT0_FMT_DITHER_RAND_R_SEED
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_G_SEED
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT0_FMT_DITHER_RAND_B_SEED
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT0_FMT_CLAMP_CNTL
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT0_FMT_MAP420_MEMORY_CONTROL
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT0_FMT_422_CONTROL
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf0_dispdec
+//OPPBUF0_OPPBUF_CONTROL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF0_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF0_OPPBUF_CONTROL1
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe0_dispdec
+//OPP_PIPE0_OPP_PIPE_CONTROL
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg1_dispdec
+//DPG1_DPG_CONTROL
+#define DPG1_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG1_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG1_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG1_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG1_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG1_DPG_RAMP_CONTROL
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG1_DPG_DIMENSIONS
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG1_DPG_COLOUR_R_CR
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG1_DPG_COLOUR_G_Y
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG1_DPG_COLOUR_B_CB
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG1_DPG_OFFSET_SEGMENT
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG1_DPG_STATUS
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt1_dispdec
+//FMT1_FMT_CLAMP_COMPONENT_R
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_G
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT1_FMT_CLAMP_COMPONENT_B
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT1_FMT_DYNAMIC_EXP_CNTL
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT1_FMT_CONTROL
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT1_FMT_BIT_DEPTH_CONTROL
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT1_FMT_DITHER_RAND_R_SEED
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_G_SEED
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT1_FMT_DITHER_RAND_B_SEED
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT1_FMT_CLAMP_CNTL
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT1_FMT_MAP420_MEMORY_CONTROL
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT1_FMT_422_CONTROL
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf1_dispdec
+//OPPBUF1_OPPBUF_CONTROL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF1_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF1_OPPBUF_CONTROL1
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe1_dispdec
+//OPP_PIPE1_OPP_PIPE_CONTROL
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg2_dispdec
+//DPG2_DPG_CONTROL
+#define DPG2_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG2_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG2_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG2_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG2_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG2_DPG_RAMP_CONTROL
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG2_DPG_DIMENSIONS
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG2_DPG_COLOUR_R_CR
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG2_DPG_COLOUR_G_Y
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG2_DPG_COLOUR_B_CB
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG2_DPG_OFFSET_SEGMENT
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG2_DPG_STATUS
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt2_dispdec
+//FMT2_FMT_CLAMP_COMPONENT_R
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_G
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT2_FMT_CLAMP_COMPONENT_B
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT2_FMT_DYNAMIC_EXP_CNTL
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT2_FMT_CONTROL
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT2_FMT_BIT_DEPTH_CONTROL
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT2_FMT_DITHER_RAND_R_SEED
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_G_SEED
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT2_FMT_DITHER_RAND_B_SEED
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT2_FMT_CLAMP_CNTL
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT2_FMT_MAP420_MEMORY_CONTROL
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT2_FMT_422_CONTROL
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf2_dispdec
+//OPPBUF2_OPPBUF_CONTROL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF2_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF2_OPPBUF_CONTROL1
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe2_dispdec
+//OPP_PIPE2_OPP_PIPE_CONTROL
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dpg3_dispdec
+//DPG3_DPG_CONTROL
+#define DPG3_DPG_CONTROL__DPG_EN__SHIFT                                                                       0x0
+#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT                                                                     0x4
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT                                                            0x8
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT                                                                0xc
+#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT                                                                     0x10
+#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT                                                                     0x14
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT                                                           0x18
+#define DPG3_DPG_CONTROL__DPG_EN_MASK                                                                         0x00000001L
+#define DPG3_DPG_CONTROL__DPG_MODE_MASK                                                                       0x00000070L
+#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK                                                              0x00000100L
+#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK                                                                  0x00003000L
+#define DPG3_DPG_CONTROL__DPG_VRES_MASK                                                                       0x000F0000L
+#define DPG3_DPG_CONTROL__DPG_HRES_MASK                                                                       0x00F00000L
+#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK                                                             0x01000000L
+//DPG3_DPG_RAMP_CONTROL
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT                                                        0x0
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT                                                                0x18
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT                                                                0x1c
+#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK                                                          0x0000FFFFL
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK                                                                  0x0F000000L
+#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK                                                                  0xF0000000L
+//DPG3_DPG_DIMENSIONS
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT                                                         0x0
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT                                                          0x10
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK                                                           0x00003FFFL
+#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK                                                            0x3FFF0000L
+//DPG3_DPG_COLOUR_R_CR
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK                                                           0xFFFF0000L
+//DPG3_DPG_COLOUR_G_Y
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT                                                           0x0
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT                                                           0x10
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK                                                             0x0000FFFFL
+#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK                                                             0xFFFF0000L
+//DPG3_DPG_COLOUR_B_CB
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT                                                         0x0
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT                                                         0x10
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK                                                           0x0000FFFFL
+#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK                                                           0xFFFF0000L
+//DPG3_DPG_OFFSET_SEGMENT
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT                                                          0x0
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT                                                     0x10
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK                                                            0x00003FFFL
+#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK                                                       0x3FFF0000L
+//DPG3_DPG_STATUS
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT                                                     0x0
+#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK                                                       0x00000001L
+
+
+// addressBlock: dce_dc_opp_fmt3_dispdec
+//FMT3_FMT_CLAMP_COMPONENT_R
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_G
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK                                                    0xFFFF0000L
+//FMT3_FMT_CLAMP_COMPONENT_B
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT                                                  0x0
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT                                                  0x10
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK                                                    0x0000FFFFL
+#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK                                                    0xFFFF0000L
+//FMT3_FMT_DYNAMIC_EXP_CNTL
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT                                                  0x0
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT                                                0x4
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK                                                    0x00000001L
+#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK                                                  0x00000010L
+//FMT3_FMT_CONTROL
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT                                                      0x0
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT                                         0x8
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT                                    0xc
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT                                                           0x10
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT                                                         0x12
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT                                                        0x14
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT                                                0x15
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                         0x18
+#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK                                                        0x00000001L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK                                           0x00000F00L
+#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK                                      0x00003000L
+#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK                                                             0x00030000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK                                                           0x000C0000L
+#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK                                                          0x00100000L
+#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK                                                  0x00200000L
+#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                           0x01000000L
+//FMT3_FMT_BIT_DEPTH_CONTROL
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT                                                    0x0
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT                                                  0x1
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT                                                 0x4
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT                                              0x8
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT                                            0x9
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT                                           0xb
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT                                            0xd
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT                                              0xe
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT                                         0xf
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT                                             0x10
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT                                          0x11
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT                                         0x15
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT                                                 0x18
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT                                          0x19
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT                                                      0x1a
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT                                                      0x1c
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT                                                      0x1e
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK                                                      0x00000001L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK                                                    0x00000002L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK                                                   0x00000030L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK                                                0x00000100L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK                                              0x00000600L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK                                             0x00001800L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK                                              0x00002000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK                                                0x00004000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK                                           0x00008000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK                                               0x00010000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK                                            0x00060000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK                                           0x00600000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK                                                   0x01000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK                                            0x02000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK                                                        0x0C000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK                                                        0x30000000L
+#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK                                                        0xC0000000L
+//FMT3_FMT_DITHER_RAND_R_SEED
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK                                                     0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_G_SEED
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT                                                    0x10
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK                                                      0xFFFF0000L
+//FMT3_FMT_DITHER_RAND_B_SEED
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT                                                   0x0
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT                                                   0x10
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK                                                     0x000000FFL
+#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK                                                     0xFFFF0000L
+//FMT3_FMT_CLAMP_CNTL
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT                                                         0x0
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT                                                    0x10
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK                                                           0x00000001L
+#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK                                                      0x00070000L
+//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT                     0x0
+#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK                       0x00001FFFL
+//FMT3_FMT_MAP420_MEMORY_CONTROL
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT                                        0x0
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT                                          0x4
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT                                        0x8
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                0xc
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK                                          0x00000003L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK                                            0x00000010L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK                                          0x00000300L
+#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK                                  0x00003000L
+//FMT3_FMT_422_CONTROL
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT                                          0x0
+#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK                                            0x00000001L
+
+
+// addressBlock: dce_dc_opp_oppbuf3_dispdec
+//OPPBUF3_OPPBUF_CONTROL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT                                                    0x0
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT                                               0x14
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT                                                0x18
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT                                           0x1c
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK                                                      0x00003FFFL
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK                                              0x00070000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK                                                 0x00F00000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK                                                  0x0F000000L
+#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK                                             0x10000000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT                                     0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT                                     0xa
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT                                            0x14
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK                                       0x000003FFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK                                       0x000FFC00L
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK                                              0xFFF00000L
+//OPPBUF3_OPPBUF_3D_PARAMETERS_1
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT                                            0x0
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT                                            0x10
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK                                              0x00000FFFL
+#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK                                              0x0FFF0000L
+//OPPBUF3_OPPBUF_CONTROL1
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT                                      0x0
+#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK                                        0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_pipe3_dispdec
+//OPP_PIPE3_OPP_PIPE_CONTROL
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT                                                  0x0
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT                                                  0x1
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT                                         0x4
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK                                                    0x00000001L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK                                                    0x00000002L
+#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK                                           0x00000010L
+
+
+// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT                                            0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT                                       0x4
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT                                   0x8
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT                                     0xa
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT                                0xc
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT                                  0xe
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT                                  0x14
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT                                 0x18
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT                              0x1c
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK                                              0x00000001L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK                                         0x00000010L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK                                     0x00000300L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK                                       0x00000400L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK                                  0x00003000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK                                    0x00004000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK                                    0x00300000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK                                   0x01000000L
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK                                0x10000000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT                                             0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK                                               0x0000FFFFL
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_A_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0__OPP_PIPE_CRC_RESULT_R_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B__SHIFT                                      0x10
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_G_MASK                                        0x0000FFFFL
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1__OPP_PIPE_CRC_RESULT_B_MASK                                        0xFFFF0000L
+//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C__SHIFT                                      0x0
+#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2__OPP_PIPE_CRC_RESULT_C_MASK                                        0x0000FFFFL
+
+
+// addressBlock: dce_dc_opp_dscrm0_dispdec
+//DSCRM0_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm1_dispdec
+//DSCRM1_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_dscrm2_dispdec
+//DSCRM2_DSCRM_DSC_FORWARD_CONFIG
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT                                          0x0
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT                                     0x4
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                    0x8
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT                                   0xc
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK                                            0x00000001L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK                                       0x00000070L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                      0x00000100L
+#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK                                     0x00001000L
+
+
+// addressBlock: dce_dc_opp_opp_top_dispdec
+//OPP_TOP_CLK_CONTROL
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT                                                0x4
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT                                                         0xc
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT                                                         0xd
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT                                                         0xe
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT                                                         0xf
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK                                                  0x00000010L
+#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK                                                            0x00000F00L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK                                                           0x00001000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK                                                           0x00002000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK                                                           0x00004000L
+#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK                                                           0x00008000L
+//OPP_ABM_CONTROL
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT                                                             0x0
+#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK                                                               0x00000007L
+
+
+// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON16_PERFCOUNTER_CNTL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_CNTL2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON16_PERFCOUNTER_STATE
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON16_PERFMON_CNTL
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON16_PERFMON_CNTL2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON16_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON16_PERFMON_CVALUE_LOW
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON16_PERFMON_HI
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON16_PERFMON_LOW
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm0_dispdec
+//ODM0_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM0_OPTC_DATA_SOURCE_SELECT
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM0_OPTC_DATA_FORMAT_CONTROL
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM0_OPTC_BYTES_PER_PIXEL
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM0_OPTC_WIDTH_CONTROL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM0_OPTC_INPUT_CLOCK_CONTROL
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM0_OPTC_MEMORY_CONFIG
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM0_OPTC_INPUT_SPARE_REGISTER
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm1_dispdec
+//ODM1_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM1_OPTC_DATA_SOURCE_SELECT
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM1_OPTC_DATA_FORMAT_CONTROL
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM1_OPTC_BYTES_PER_PIXEL
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM1_OPTC_WIDTH_CONTROL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM1_OPTC_INPUT_CLOCK_CONTROL
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM1_OPTC_MEMORY_CONFIG
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM1_OPTC_INPUT_SPARE_REGISTER
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm2_dispdec
+//ODM2_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM2_OPTC_DATA_SOURCE_SELECT
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM2_OPTC_DATA_FORMAT_CONTROL
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM2_OPTC_BYTES_PER_PIXEL
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM2_OPTC_WIDTH_CONTROL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM2_OPTC_INPUT_CLOCK_CONTROL
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM2_OPTC_MEMORY_CONFIG
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM2_OPTC_INPUT_SPARE_REGISTER
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_odm3_dispdec
+//ODM3_OPTC_INPUT_GLOBAL_CONTROL
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT                                          0x0
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT                                          0x8
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE__SHIFT                                        0x9
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT                                 0xa
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT                                      0xb
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT                                           0xc
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT                                0xd
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT                                     0x1f
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK                                            0x00000001L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK                                            0x00000100L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_TYPE_MASK                                          0x00000200L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK                                   0x00000400L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK                                        0x00000800L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK                                             0x00001000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK                                  0x00002000L
+#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK                                       0x80000000L
+//ODM3_OPTC_DATA_SOURCE_SELECT
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT                                        0x0
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT                                       0x8
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT                                                0x10
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT                                                0x14
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT                                                0x18
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT                                                0x1c
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK                                          0x00000003L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK                                         0x00000300L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK                                                  0x000F0000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK                                                  0x00F00000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK                                                  0x0F000000L
+#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK                                                  0xF0000000L
+//ODM3_OPTC_DATA_FORMAT_CONTROL
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT                                                0x0
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT                                                   0x4
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK                                                  0x00000003L
+#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK                                                     0x00000030L
+//ODM3_OPTC_BYTES_PER_PIXEL
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT                                            0x0
+#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK                                              0x7FFFFFFFL
+//ODM3_OPTC_WIDTH_CONTROL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT                                                    0x0
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT                                                  0x10
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK                                                      0x00001FFFL
+#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK                                                    0x1FFF0000L
+//ODM3_OPTC_INPUT_CLOCK_CONTROL
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT                                         0x0
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT                                               0x1
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT                                               0x2
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK                                           0x00000001L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK                                                 0x00000002L
+#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK                                                 0x00000004L
+//ODM3_OPTC_MEMORY_CONFIG
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT                                                          0x0
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT                                                   0x10
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK                                                            0x0000FFFFL
+#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK                                                     0xFFFF0000L
+//ODM3_OPTC_INPUT_SPARE_REGISTER
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT                                           0x0
+#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg0_dispdec
+//OTG0_OTG_H_TOTAL
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_H_BLANK_START_END
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_H_SYNC_A
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_H_SYNC_A_CNTL
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG0_OTG_H_TIMING_CNTL
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG0_OTG_V_TOTAL
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG0_OTG_V_TOTAL_MIN
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MAX
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_MID
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG0_OTG_V_TOTAL_CONTROL
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG0_OTG_V_TOTAL_INT_STATUS
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG0_OTG_VSYNC_NOM_INT_STATUS
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG0_OTG_V_BLANK_START_END
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG0_OTG_V_SYNC_A
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG0_OTG_V_SYNC_A_CNTL
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG0_OTG_TRIGA_CNTL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGA_MANUAL_TRIG
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_TRIGB_CNTL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG0_OTG_TRIGB_MANUAL_TRIG
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG0_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG0_OTG_FLOW_CONTROL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG0_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG0_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG0_OTG_CONTROL
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG0_OTG_INTERLACE_CONTROL
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG0_OTG_INTERLACE_STATUS
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG0_OTG_PIXEL_DATA_READBACK0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG0_OTG_PIXEL_DATA_READBACK1
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG0_OTG_STATUS
+#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG0_OTG_STATUS_POSITION
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG0_OTG_NOM_VERT_POSITION
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG0_OTG_STATUS_FRAME_COUNT
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG0_OTG_STATUS_VF_COUNT
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_STATUS_HV_COUNT
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG0_OTG_COUNT_CONTROL
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG0_OTG_COUNT_RESET
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG0_OTG_VERT_SYNC_CONTROL
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG0_OTG_STEREO_STATUS
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG0_OTG_STEREO_CONTROL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG0_OTG_SNAPSHOT_STATUS
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG0_OTG_SNAPSHOT_CONTROL
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG0_OTG_SNAPSHOT_POSITION
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG0_OTG_SNAPSHOT_FRAME
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG0_OTG_INTERRUPT_CONTROL
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG0_OTG_UPDATE_LOCK
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG0_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG0_OTG_MASTER_EN
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG0_OTG_CRC_CNTL
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG0_OTG_CRC_CNTL2
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG0_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG0_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC0_DATA_RG
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC0_DATA_B
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG0_OTG_CRC1_DATA_RG
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC1_DATA_B
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_RG
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC2_DATA_B
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_RG
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG0_OTG_CRC3_DATA_B
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG0_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG0_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG0_OTG_STATIC_SCREEN_CONTROL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG0_OTG_3D_STRUCTURE_CONTROL
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG0_OTG_GSL_VSYNC_GAP
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG0_OTG_MASTER_UPDATE_MODE
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG0_OTG_CLOCK_CONTROL
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG0_OTG_VSTARTUP_PARAM
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG0_OTG_VUPDATE_PARAM
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG0_OTG_VREADY_PARAM
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG0_OTG_GLOBAL_SYNC_STATUS
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG0_OTG_MASTER_UPDATE_LOCK
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG0_OTG_GSL_CONTROL
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG0_OTG_GSL_WINDOW_X
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG0_OTG_GSL_WINDOW_Y
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG0_OTG_VUPDATE_KEEPOUT
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL1
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL2
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG0_OTG_GLOBAL_CONTROL3
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG0_OTG_GLOBAL_CONTROL4
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG0_OTG_TRIG_MANUAL_CONTROL
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_MANUAL_FLOW_CONTROL
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG0_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG0_OTG_DRR_TIMING_INT_STATUS
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG0_OTG_DRR_V_TOTAL_CHANGE
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG0_OTG_DRR_TRIGGER_WINDOW
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG0_OTG_DRR_CONTROL
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG0_OTG_M_CONST_DTO0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG0_OTG_M_CONST_DTO1
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG0_OTG_REQUEST_CONTROL
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG0_OTG_DSC_START_POSITION
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG0_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG0_OTG_PIPE_UPDATE_STATUS
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG0_OTG_SPARE_REGISTER
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg1_dispdec
+//OTG1_OTG_H_TOTAL
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_H_BLANK_START_END
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_H_SYNC_A
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_H_SYNC_A_CNTL
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG1_OTG_H_TIMING_CNTL
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG1_OTG_V_TOTAL
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG1_OTG_V_TOTAL_MIN
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MAX
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_MID
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG1_OTG_V_TOTAL_CONTROL
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG1_OTG_V_TOTAL_INT_STATUS
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG1_OTG_VSYNC_NOM_INT_STATUS
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG1_OTG_V_BLANK_START_END
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG1_OTG_V_SYNC_A
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG1_OTG_V_SYNC_A_CNTL
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG1_OTG_TRIGA_CNTL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGA_MANUAL_TRIG
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_TRIGB_CNTL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG1_OTG_TRIGB_MANUAL_TRIG
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG1_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG1_OTG_FLOW_CONTROL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG1_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG1_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG1_OTG_CONTROL
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG1_OTG_INTERLACE_CONTROL
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG1_OTG_INTERLACE_STATUS
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG1_OTG_PIXEL_DATA_READBACK0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG1_OTG_PIXEL_DATA_READBACK1
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG1_OTG_STATUS
+#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG1_OTG_STATUS_POSITION
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG1_OTG_NOM_VERT_POSITION
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG1_OTG_STATUS_FRAME_COUNT
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG1_OTG_STATUS_VF_COUNT
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_STATUS_HV_COUNT
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG1_OTG_COUNT_CONTROL
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG1_OTG_COUNT_RESET
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG1_OTG_VERT_SYNC_CONTROL
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG1_OTG_STEREO_STATUS
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG1_OTG_STEREO_CONTROL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG1_OTG_SNAPSHOT_STATUS
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG1_OTG_SNAPSHOT_CONTROL
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG1_OTG_SNAPSHOT_POSITION
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG1_OTG_SNAPSHOT_FRAME
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG1_OTG_INTERRUPT_CONTROL
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG1_OTG_UPDATE_LOCK
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG1_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG1_OTG_MASTER_EN
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG1_OTG_CRC_CNTL
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG1_OTG_CRC_CNTL2
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG1_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG1_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC0_DATA_RG
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC0_DATA_B
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG1_OTG_CRC1_DATA_RG
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC1_DATA_B
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_RG
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC2_DATA_B
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_RG
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG1_OTG_CRC3_DATA_B
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG1_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG1_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG1_OTG_STATIC_SCREEN_CONTROL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG1_OTG_3D_STRUCTURE_CONTROL
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG1_OTG_GSL_VSYNC_GAP
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG1_OTG_MASTER_UPDATE_MODE
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG1_OTG_CLOCK_CONTROL
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG1_OTG_VSTARTUP_PARAM
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG1_OTG_VUPDATE_PARAM
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG1_OTG_VREADY_PARAM
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG1_OTG_GLOBAL_SYNC_STATUS
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG1_OTG_MASTER_UPDATE_LOCK
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG1_OTG_GSL_CONTROL
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG1_OTG_GSL_WINDOW_X
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG1_OTG_GSL_WINDOW_Y
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG1_OTG_VUPDATE_KEEPOUT
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL1
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL2
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG1_OTG_GLOBAL_CONTROL3
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG1_OTG_GLOBAL_CONTROL4
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG1_OTG_TRIG_MANUAL_CONTROL
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_MANUAL_FLOW_CONTROL
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG1_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG1_OTG_DRR_TIMING_INT_STATUS
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG1_OTG_DRR_V_TOTAL_CHANGE
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG1_OTG_DRR_TRIGGER_WINDOW
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG1_OTG_DRR_CONTROL
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG1_OTG_M_CONST_DTO0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG1_OTG_M_CONST_DTO1
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG1_OTG_REQUEST_CONTROL
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG1_OTG_DSC_START_POSITION
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG1_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG1_OTG_PIPE_UPDATE_STATUS
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG1_OTG_SPARE_REGISTER
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg2_dispdec
+//OTG2_OTG_H_TOTAL
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_H_BLANK_START_END
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_H_SYNC_A
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_H_SYNC_A_CNTL
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG2_OTG_H_TIMING_CNTL
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG2_OTG_V_TOTAL
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG2_OTG_V_TOTAL_MIN
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MAX
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_MID
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG2_OTG_V_TOTAL_CONTROL
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG2_OTG_V_TOTAL_INT_STATUS
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG2_OTG_VSYNC_NOM_INT_STATUS
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG2_OTG_V_BLANK_START_END
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG2_OTG_V_SYNC_A
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG2_OTG_V_SYNC_A_CNTL
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG2_OTG_TRIGA_CNTL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGA_MANUAL_TRIG
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_TRIGB_CNTL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG2_OTG_TRIGB_MANUAL_TRIG
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG2_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG2_OTG_FLOW_CONTROL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG2_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG2_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG2_OTG_CONTROL
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG2_OTG_INTERLACE_CONTROL
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG2_OTG_INTERLACE_STATUS
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG2_OTG_PIXEL_DATA_READBACK0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG2_OTG_PIXEL_DATA_READBACK1
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG2_OTG_STATUS
+#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG2_OTG_STATUS_POSITION
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG2_OTG_NOM_VERT_POSITION
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG2_OTG_STATUS_FRAME_COUNT
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG2_OTG_STATUS_VF_COUNT
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_STATUS_HV_COUNT
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG2_OTG_COUNT_CONTROL
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG2_OTG_COUNT_RESET
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG2_OTG_VERT_SYNC_CONTROL
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG2_OTG_STEREO_STATUS
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG2_OTG_STEREO_CONTROL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG2_OTG_SNAPSHOT_STATUS
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG2_OTG_SNAPSHOT_CONTROL
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG2_OTG_SNAPSHOT_POSITION
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG2_OTG_SNAPSHOT_FRAME
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG2_OTG_INTERRUPT_CONTROL
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG2_OTG_UPDATE_LOCK
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG2_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG2_OTG_MASTER_EN
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG2_OTG_CRC_CNTL
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG2_OTG_CRC_CNTL2
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG2_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG2_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC0_DATA_RG
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC0_DATA_B
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG2_OTG_CRC1_DATA_RG
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC1_DATA_B
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_RG
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC2_DATA_B
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_RG
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG2_OTG_CRC3_DATA_B
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG2_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG2_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG2_OTG_STATIC_SCREEN_CONTROL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG2_OTG_3D_STRUCTURE_CONTROL
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG2_OTG_GSL_VSYNC_GAP
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG2_OTG_MASTER_UPDATE_MODE
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG2_OTG_CLOCK_CONTROL
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG2_OTG_VSTARTUP_PARAM
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG2_OTG_VUPDATE_PARAM
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG2_OTG_VREADY_PARAM
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG2_OTG_GLOBAL_SYNC_STATUS
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG2_OTG_MASTER_UPDATE_LOCK
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG2_OTG_GSL_CONTROL
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG2_OTG_GSL_WINDOW_X
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG2_OTG_GSL_WINDOW_Y
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG2_OTG_VUPDATE_KEEPOUT
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL1
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL2
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG2_OTG_GLOBAL_CONTROL3
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG2_OTG_GLOBAL_CONTROL4
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG2_OTG_TRIG_MANUAL_CONTROL
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_MANUAL_FLOW_CONTROL
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG2_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG2_OTG_DRR_TIMING_INT_STATUS
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG2_OTG_DRR_V_TOTAL_CHANGE
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG2_OTG_DRR_TRIGGER_WINDOW
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG2_OTG_DRR_CONTROL
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG2_OTG_M_CONST_DTO0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG2_OTG_M_CONST_DTO1
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG2_OTG_REQUEST_CONTROL
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG2_OTG_DSC_START_POSITION
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG2_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG2_OTG_PIPE_UPDATE_STATUS
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG2_OTG_SPARE_REGISTER
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_otg3_dispdec
+//OTG3_OTG_H_TOTAL
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_H_BLANK_START_END
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_H_SYNC_A
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_H_SYNC_A_CNTL
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT                                                     0x10
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT                                                    0x11
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK                                                       0x00010000L
+#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK                                                      0x00020000L
+//OTG3_OTG_H_TIMING_CNTL
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT                                                  0x0
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE__SHIFT                                           0x8
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK                                                    0x00000003L
+#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_UPDATE_MODE_MASK                                             0x00000100L
+//OTG3_OTG_V_TOTAL
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT                                                                  0x0
+#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK                                                                    0x00007FFFL
+//OTG3_OTG_V_TOTAL_MIN
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MAX
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_MID
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT                                                          0x0
+#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK                                                            0x00007FFFL
+//OTG3_OTG_V_TOTAL_CONTROL
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT                                                  0x0
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT                                                  0x1
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT                                      0x2
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT                                      0x3
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT                                              0x4
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT                                          0x5
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT                                             0x8
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT                                             0x10
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK                                                    0x00000001L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK                                                    0x00000002L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK                                        0x00000004L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK                                        0x00000008L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK                                                0x00000010L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK                                            0x00000020L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK                                               0x0000FF00L
+#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK                                               0xFFFF0000L
+//OTG3_OTG_V_TOTAL_INT_STATUS
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT                                0x0
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT                            0x4
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT                            0x8
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT                            0xc
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK                                  0x00000001L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK                              0x00000010L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK                              0x00000100L
+#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK                              0x00001000L
+//OTG3_OTG_VSYNC_NOM_INT_STATUS
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT                                                   0x0
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT                                         0x4
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK                                                     0x00000001L
+#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK                                           0x00000010L
+//OTG3_OTG_V_BLANK_START_END
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT                                                  0x0
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT                                                    0x10
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK                                                    0x00007FFFL
+#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK                                                      0x7FFF0000L
+//OTG3_OTG_V_SYNC_A
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT                                                          0x0
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT                                                            0x10
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK                                                            0x00007FFFL
+#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK                                                              0x7FFF0000L
+//OTG3_OTG_V_SYNC_A_CNTL
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT                                                       0x0
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT                                                        0x8
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK                                                         0x00000001L
+#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK                                                          0x00000100L
+//OTG3_OTG_TRIGA_CNTL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGA_MANUAL_TRIG
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_TRIGB_CNTL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT                                                   0x0
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT                                              0x5
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT                                                 0x8
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT                                                0xb
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT                                                    0xc
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT                                                 0xd
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT                                                        0xe
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT                                         0x10
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT                                        0x12
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT                                                0x14
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT                                                           0x18
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT                                                           0x1f
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK                                                     0x0000001FL
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK                                                0x000000E0L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK                                                   0x00000700L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK                                                  0x00000800L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK                                                      0x00001000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK                                                   0x00002000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK                                                          0x00004000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK                                           0x00030000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK                                          0x000C0000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK                                                  0x00300000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK                                                             0x1F000000L
+#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK                                                             0x80000000L
+//OTG3_OTG_TRIGB_MANUAL_TRIG
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT                                              0x0
+#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK                                                0x00000001L
+//OTG3_OTG_FORCE_COUNT_NOW_CNTL
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT                                        0x0
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT                                       0x4
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT                                    0x8
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT                                    0x10
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT                                       0x18
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK                                          0x00000003L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK                                         0x00000010L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK                                      0x00000100L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK                                      0x00010000L
+#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK                                         0x01000000L
+//OTG3_OTG_FLOW_CONTROL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT__SHIFT                                          0x0
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY__SHIFT                                               0x8
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY__SHIFT                                            0x10
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS__SHIFT                                           0x18
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_SOURCE_SELECT_MASK                                            0x0000001FL
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_POLARITY_MASK                                                 0x00000100L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_GRANULARITY_MASK                                              0x00010000L
+#define OTG3_OTG_FLOW_CONTROL__OTG_FLOW_CONTROL_INPUT_STATUS_MASK                                             0x01000000L
+//OTG3_OTG_STEREO_FORCE_NEXT_EYE
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT                                      0x0
+#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK                                        0x00000003L
+//OTG3_OTG_CONTROL
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT                                                                0x0
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT                                                       0x8
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT                                                         0xc
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT                                                        0xd
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT                                                    0xe
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT                                                  0x10
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT                                                                  0x14
+#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK                                                                  0x00000001L
+#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK                                                         0x00000300L
+#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK                                                           0x00001000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK                                                          0x00002000L
+#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK                                                      0x00004000L
+#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK                                                    0x00010000L
+#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK                                                                    0x00300000L
+//OTG3_OTG_INTERLACE_CONTROL
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT                                               0x0
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT                                     0x10
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK                                       0x00030000L
+//OTG3_OTG_INTERLACE_STATUS
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT                                         0x0
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT                                            0x1
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK                                           0x00000001L
+#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK                                              0x00000002L
+//OTG3_OTG_PIXEL_DATA_READBACK0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT                                          0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT                                          0x10
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK                                            0x0000FFFFL
+#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK                                            0xFFFF0000L
+//OTG3_OTG_PIXEL_DATA_READBACK1
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT                                           0x0
+#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK                                             0x0000FFFFL
+//OTG3_OTG_STATUS
+#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT                                                                   0x0
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT                                                             0x1
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT                                                                  0x2
+#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT                                                                  0x3
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT                                                      0x5
+#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT                                                                   0x10
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT                                                             0x11
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT                                                                  0x12
+#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK                                                                     0x00000001L
+#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK                                                               0x00000002L
+#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK                                                                    0x00000004L
+#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK                                                                    0x00000008L
+#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK                                                        0x00000020L
+#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK                                                                     0x00010000L
+#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK                                                               0x00020000L
+#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK                                                                    0x00040000L
+//OTG3_OTG_STATUS_POSITION
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT                                                       0x0
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT                                                       0x10
+#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK                                                         0x00007FFFL
+#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK                                                         0x7FFF0000L
+//OTG3_OTG_NOM_VERT_POSITION
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT                                                 0x0
+#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK                                                   0x00007FFFL
+//OTG3_OTG_STATUS_FRAME_COUNT
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT                                                   0x0
+#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK                                                     0x00FFFFFFL
+//OTG3_OTG_STATUS_VF_COUNT
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_STATUS_HV_COUNT
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT                                                         0x0
+#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK                                                           0x7FFFFFFFL
+//OTG3_OTG_COUNT_CONTROL
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT                                                  0x0
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT                                              0x1
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK                                                    0x00000001L
+#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK                                                0x0000001EL
+//OTG3_OTG_COUNT_RESET
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT                                                    0x0
+#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK                                                      0x00000001L
+//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT                        0x0
+#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK                          0x00000001L
+//OTG3_OTG_VERT_SYNC_CONTROL
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT                                    0x8
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT                                          0x10
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK                                      0x00000100L
+#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK                                            0x00030000L
+//OTG3_OTG_STEREO_STATUS
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT                                                 0x0
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT                                                 0x8
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT                                                 0x10
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT                                                    0x14
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT                                      0x18
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT                                         0x1e
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT                                        0x1f
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK                                                   0x00000001L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK                                                   0x00000100L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK                                                   0x00010000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK                                                      0x00100000L
+#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK                                        0x03000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK                                           0x40000000L
+#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK                                          0x80000000L
+//OTG3_OTG_STEREO_CONTROL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT                                       0x0
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT                                       0xf
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT                                          0x11
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT                                  0x12
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT                                                 0x13
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT                                        0x14
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT                                                     0x15
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT                                                         0x18
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK                                         0x00007FFFL
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK                                         0x00008000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK                                            0x00020000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK                                    0x00040000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK                                                   0x00080000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK                                          0x00100000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK                                                       0x00200000L
+#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK                                                           0x01000000L
+//OTG3_OTG_SNAPSHOT_STATUS
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT                                                0x0
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT                                                   0x1
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT                                          0x2
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK                                                  0x00000001L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK                                                     0x00000002L
+#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK                                            0x00000004L
+//OTG3_OTG_SNAPSHOT_CONTROL
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT                                          0x0
+#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK                                            0x00000003L
+//OTG3_OTG_SNAPSHOT_POSITION
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT                                            0x0
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT                                            0x10
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK                                              0x00007FFFL
+#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK                                              0x7FFF0000L
+//OTG3_OTG_SNAPSHOT_FRAME
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT                                              0x0
+#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK                                                0x00FFFFFFL
+//OTG3_OTG_INTERRUPT_CONTROL
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT                                               0x0
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT                                              0x1
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT                                        0x8
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT                                       0x9
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT                                  0x10
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT                                 0x11
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT                                                  0x18
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT                                                  0x19
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT                                                 0x1a
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT                                                 0x1b
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT                                              0x1c
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT                                             0x1d
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT                                          0x1e
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT                                         0x1f
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK                                                 0x00000001L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK                                                0x00000002L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK                                          0x00000100L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK                                         0x00000200L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK                                    0x00010000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK                                   0x00020000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK                                                    0x01000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK                                                    0x02000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK                                                   0x04000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK                                                   0x08000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK                                                0x10000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK                                               0x20000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK                                            0x40000000L
+#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK                                           0x80000000L
+//OTG3_OTG_UPDATE_LOCK
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT                                                          0x0
+#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK                                                            0x00000001L
+//OTG3_OTG_DOUBLE_BUFFER_CONTROL
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT                                             0x0
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING__SHIFT                        0x2
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT                             0x4
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT                                   0x5
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT                                  0x6
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT                          0x7
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT                                           0x8
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT                                 0x9
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING__SHIFT                             0xa
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT                                0x18
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK                                               0x00000001L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING_MASK                          0x00000004L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK                               0x00000010L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK                                     0x00000020L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK                                    0x00000040L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK                            0x00000080L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK                                             0x00000100L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK                                   0x00000200L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DSC_POSITION_DB_UPDATE_PENDING_MASK                               0x00000400L
+#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK                                  0x03000000L
+//OTG3_OTG_MASTER_EN
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT                                                              0x0
+#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK                                                                0x00000001L
+//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT                        0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK                        0x00007FFFL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK                          0x7FFF0000L
+//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT                  0x4
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT                                         0x1c
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK                    0x00000010L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK                           0x01000000L
+#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK                                           0x10000000L
+//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT                      0x0
+#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK                        0x00007FFFL
+//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT                       0x8
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT                           0xc
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT                       0x10
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT                            0x14
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT                         0x18
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK                         0x00000100L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK                             0x00001000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK                         0x00010000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK                              0x00100000L
+#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK                           0x01000000L
+//OTG3_OTG_CRC_CNTL
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT                                                                  0x0
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN__SHIFT                                                        0x1
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE__SHIFT                                                      0x2
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT                                                          0x3
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT                                                             0x4
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT                                                   0x5
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT                                                                 0x7
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT                                                         0x8
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT                                                      0xc
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT                                         0x13
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT                                                             0x14
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT                                                             0x18
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT                                                   0x1c
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT                                                   0x1d
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT                                                   0x1e
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT                                                   0x1f
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK                                                                    0x00000001L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_EN_MASK                                                          0x00000002L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_DUAL_LINK_MODE_MASK                                                        0x00000004L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK                                                            0x00000008L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK                                                               0x00000010L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK                                                     0x00000060L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK                                                                   0x00000080L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK                                                           0x00000300L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK                                                        0x00003000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK                                           0x00080000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK                                                               0x00700000L
+#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK                                                               0x07000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK                                                     0x10000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK                                                     0x20000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK                                                     0x40000000L
+#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK                                                     0x80000000L
+//OTG3_OTG_CRC_CNTL2
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE__SHIFT                                                           0x0
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE__SHIFT                                           0x1
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE__SHIFT                                             0x4
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT__SHIFT                                                        0x8
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DSC_MODE_MASK                                                             0x00000001L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_COMBINE_MODE_MASK                                             0x00000002L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_STREAM_SPLIT_MODE_MASK                                               0x00000030L
+#define OTG3_OTG_CRC_CNTL2__OTG_CRC_DATA_FORMAT_MASK                                                          0x00000300L
+//OTG3_OTG_CRC0_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC0_DATA_RG
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_RG__CRC0_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC0_DATA_B
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC0_DATA_B__CRC0_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC1_WINDOWA_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_X_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT                                      0x0
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT                                        0x10
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK                                        0x00007FFFL
+#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK                                          0x7FFF0000L
+//OTG3_OTG_CRC1_DATA_RG
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_RG__CRC1_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC1_DATA_B
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC1_DATA_B__CRC1_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_RG
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_RG__CRC2_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC2_DATA_B
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC2_DATA_B__CRC2_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_RG
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR__SHIFT                                                               0x0
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y__SHIFT                                                                0x10
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_R_CR_MASK                                                                 0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_RG__CRC3_G_Y_MASK                                                                  0xFFFF0000L
+//OTG3_OTG_CRC3_DATA_B
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT                                                                0x0
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C__SHIFT                                                                   0x10
+#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK                                                                  0x0000FFFFL
+#define OTG3_OTG_CRC3_DATA_B__CRC3_C_MASK                                                                     0xFFFF0000L
+//OTG3_OTG_CRC_SIG_RED_GREEN_MASK
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT                                          0x0
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT                                        0x10
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK                                            0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK                                          0xFFFF0000L
+//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT                                      0x0
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT                                   0x10
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK                                        0x0000FFFFL
+#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK                                     0xFFFF0000L
+//OTG3_OTG_STATIC_SCREEN_CONTROL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT                                   0x0
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT                                  0x10
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT                                          0x18
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT                                                  0x19
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT                                          0x1a
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT                                           0x1b
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT                                            0x1c
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT                                     0x1e
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT                               0x1f
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK                                     0x0000FFFFL
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK                                    0x00FF0000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK                                            0x01000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK                                                    0x02000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK                                            0x04000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK                                             0x08000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK                                              0x10000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK                                       0x40000000L
+#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK                                 0x80000000L
+//OTG3_OTG_3D_STRUCTURE_CONTROL
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT                                             0x0
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT                                  0x8
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT                                 0xc
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT                                  0x10
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT                          0x11
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT                                        0x12
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK                                               0x00000001L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK                                    0x00000300L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK                                   0x00001000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK                                    0x00010000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK                            0x00020000L
+#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK                                          0x000C0000L
+//OTG3_OTG_GSL_VSYNC_GAP
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT                                                0x0
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT                                                0x8
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT                                           0x10
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT                                                 0x11
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT                                                0x13
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT                                        0x17
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT                                                      0x18
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK                                                  0x000000FFL
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK                                                  0x0000FF00L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK                                             0x00010000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK                                                   0x00060000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK                                                  0x00080000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK                                          0x00800000L
+#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK                                                        0xFF000000L
+//OTG3_OTG_MASTER_UPDATE_MODE
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT                                     0x0
+#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK                                       0x00000003L
+//OTG3_OTG_CLOCK_CONTROL
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT                                                           0x0
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT                                                     0x1
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT                                                         0x4
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT                                                           0x8
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT                                                               0x10
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK                                                             0x00000001L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK                                                       0x00000002L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK                                                           0x00000010L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK                                                             0x00000100L
+#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK                                                                 0x00010000L
+//OTG3_OTG_VSTARTUP_PARAM
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT                                                        0x0
+#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK                                                          0x000003FFL
+//OTG3_OTG_VUPDATE_PARAM
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT                                                         0x0
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT                                                          0x10
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK                                                           0x0000FFFFL
+#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK                                                            0x03FF0000L
+//OTG3_OTG_VREADY_PARAM
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT                                                           0x0
+#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK                                                             0x0000FFFFL
+//OTG3_OTG_GLOBAL_SYNC_STATUS
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT                                                   0x0
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT                                                 0x1
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT                                           0x2
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT                                               0x3
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT                                              0x4
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT                                                    0x5
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT                                                  0x6
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT                                          0x7
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT                                            0x8
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT                                                0x9
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT                                               0xa
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT                                                    0xb
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT                                            0xc
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT                                          0xd
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT                                    0xe
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT                                        0xf
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT                                       0x10
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT                                            0x11
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT                                                     0x12
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT                                                   0x13
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT                                             0x14
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT                                                 0x15
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT                                                0x16
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT                                              0x18
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT                                               0x19
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK                                                     0x00000001L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK                                                   0x00000002L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK                                             0x00000004L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK                                                 0x00000008L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK                                                0x00000010L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK                                                      0x00000020L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK                                                    0x00000040L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK                                            0x00000080L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK                                              0x00000100L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK                                                  0x00000200L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK                                                 0x00000400L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK                                                      0x00000800L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK                                              0x00001000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK                                            0x00002000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK                                      0x00004000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK                                          0x00008000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK                                         0x00010000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK                                              0x00020000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK                                                       0x00040000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK                                                     0x00080000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK                                               0x00100000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK                                                   0x00200000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK                                                  0x00400000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK                                                0x01000000L
+#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK                                                 0x02000000L
+//OTG3_OTG_MASTER_UPDATE_LOCK
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT                                            0x0
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT                                                0x8
+#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK                                              0x00000001L
+#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK                                                  0x00000100L
+//OTG3_OTG_GSL_CONTROL
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT                                                              0x0
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT                                                              0x1
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT                                                              0x2
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT                                                        0x3
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT                                                      0x4
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT                                                      0x8
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT                                                      0x10
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT                                                 0x1c
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT                                            0x1f
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK                                                                0x00000001L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK                                                                0x00000002L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK                                                                0x00000004L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK                                                          0x00000008L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK                                                        0x00000030L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK                                                        0x00000F00L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK                                                        0x001F0000L
+#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK                                                   0x10000000L
+#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK                                              0x80000000L
+//OTG3_OTG_GSL_WINDOW_X
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK                                                      0x7FFF0000L
+//OTG3_OTG_GSL_WINDOW_Y
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT                                                  0x0
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT                                                    0x10
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK                                                    0x00007FFFL
+#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK                                                      0x7FFF0000L
+//OTG3_OTG_VUPDATE_KEEPOUT
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT                      0x0
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT                        0x10
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT                            0x1f
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK                        0x0000FFFFL
+#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK                          0x03FF0000L
+#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK                              0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT                                             0x1f
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK                                               0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL1
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT                                        0x0
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT                                          0x10
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT                                       0x1f
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK                                          0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK                                            0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK                                         0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL2
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT                                                0xa
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT                                              0x10
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT                                           0x19
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT                                            0x1e
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT                                                    0x1f
+#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK                                                  0x00000400L
+#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK                                                0x00070000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK                                             0x0E000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK                                              0x40000000L
+#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK                                                      0x80000000L
+//OTG3_OTG_GLOBAL_CONTROL3
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT                                          0x0
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT                                     0x4
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT                                                 0x10
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT                                                   0x14
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK                                            0x00000003L
+#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK                                       0x00000030L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK                                                   0x00030000L
+#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK                                                     0x00300000L
+//OTG3_OTG_GLOBAL_CONTROL4
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT                                                0x0
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT                                                0x10
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT                                               0x1f
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK                                                  0x00007FFFL
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK                                                  0x7FFF0000L
+#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK                                                 0x80000000L
+//OTG3_OTG_TRIG_MANUAL_CONTROL
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_MANUAL_FLOW_CONTROL
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL__SHIFT                                              0x0
+#define OTG3_OTG_MANUAL_FLOW_CONTROL__MANUAL_FLOW_CONTROL_MASK                                                0x00000001L
+//OTG3_OTG_DRR_TIMING_INT_STATUS
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT                                 0x0
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT                             0x4
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT                           0x8
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT                         0xc
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT                        0xd
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT                                 0x10
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT                             0x14
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT                           0x18
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT                         0x1c
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT                        0x1d
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK                                   0x00000001L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK                               0x00000010L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK                             0x00000100L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK                           0x00001000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK                          0x00002000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK                                   0x00010000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK                               0x00100000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK                             0x01000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK                           0x10000000L
+#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK                          0x20000000L
+//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT                            0x0
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT                            0x10
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK                              0x00007FFFL
+#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK                              0x7FFF0000L
+//OTG3_OTG_DRR_V_TOTAL_CHANGE
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT                                      0x0
+#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK                                        0x00007FFFL
+//OTG3_OTG_DRR_TRIGGER_WINDOW
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT                                    0x0
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT                                      0x10
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK                                      0x00007FFFL
+#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK                                        0x7FFF0000L
+//OTG3_OTG_DRR_CONTROL
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT                                                    0x0
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT                                             0x10
+#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK                                                      0x00000003L
+#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK                                               0x7FFF0000L
+//OTG3_OTG_M_CONST_DTO0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT                                                   0x0
+#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK                                                     0xFFFFFFFFL
+//OTG3_OTG_M_CONST_DTO1
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT                                                  0x0
+#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK                                                    0xFFFFFFFFL
+//OTG3_OTG_REQUEST_CONTROL
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT                                     0x0
+#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK                                       0x00000001L
+//OTG3_OTG_DSC_START_POSITION
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X__SHIFT                                          0x0
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM__SHIFT                                   0x10
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_X_MASK                                            0x00007FFFL
+#define OTG3_OTG_DSC_START_POSITION__OTG_DSC_START_POSITION_LINE_NUM_MASK                                     0x03FF0000L
+//OTG3_OTG_PIPE_UPDATE_STATUS
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT                                                  0x0
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT                                         0x4
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT                                         0x8
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT                                        0x10
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK                                                    0x00000001L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK                                           0x00000010L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK                                           0x00000100L
+#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK                                          0x00010000L
+//OTG3_OTG_SPARE_REGISTER
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT                                                         0x0
+#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK                                                           0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_optc_optc_misc_dispdec
+//DWB_SOURCE_SELECT
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT__SHIFT                                                     0x0
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT__SHIFT                                                     0x3
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT__SHIFT                                                     0x6
+#define DWB_SOURCE_SELECT__OPTC_DWB0_SOURCE_SELECT_MASK                                                       0x00000007L
+#define DWB_SOURCE_SELECT__OPTC_DWB1_SOURCE_SELECT_MASK                                                       0x00000038L
+#define DWB_SOURCE_SELECT__OPTC_DWB2_SOURCE_SELECT_MASK                                                       0x000001C0L
+//GSL_SOURCE_SELECT
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT                                                       0x0
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT                                                       0x4
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT                                                       0x8
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT                                                         0x10
+#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK                                                         0x00000007L
+#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK                                                         0x00000070L
+#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK                                                         0x00000700L
+#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK                                                           0x00070000L
+//OPTC_CLOCK_CONTROL
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT                                                    0x0
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT                                                    0x1
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT                                                          0x8
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK                                                      0x00000001L
+#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK                                                      0x00000002L
+#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK                                                            0x00000F00L
+//ODM_MEM_PWR_CTRL
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT                                                           0x0
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT                                                             0x2
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT                                                           0x4
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT                                                             0x6
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT                                                           0x8
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT                                                             0xa
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT                                                           0xc
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT                                                             0xe
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT                                                           0x10
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT                                                             0x12
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT                                                           0x14
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT                                                             0x16
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT                                                           0x18
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT                                                             0x1a
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT                                                           0x1c
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT                                                             0x1e
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK                                                             0x00000003L
+#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK                                                               0x00000004L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK                                                             0x00000030L
+#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK                                                               0x00000040L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK                                                             0x00000300L
+#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK                                                               0x00000400L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK                                                             0x00003000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK                                                               0x00004000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK                                                             0x00030000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK                                                               0x00040000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK                                                             0x00300000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK                                                               0x00400000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK                                                             0x03000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK                                                               0x04000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK                                                             0x30000000L
+#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK                                                               0x40000000L
+//ODM_MEM_PWR_CTRL3
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT                                                 0x0
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT                                                     0x2
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK                                                   0x00000003L
+#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK                                                       0x0000000CL
+//ODM_MEM_PWR_STATUS
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT                                                         0x0
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT                                                         0x2
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT                                                         0x4
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT                                                         0x6
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT                                                         0x8
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT                                                         0xa
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT                                                         0xc
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT                                                         0xe
+#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK                                                           0x00000003L
+#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK                                                           0x0000000CL
+#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK                                                           0x00000030L
+#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK                                                           0x000000C0L
+#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK                                                           0x00000300L
+#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK                                                           0x00000C00L
+#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK                                                           0x00003000L
+#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK                                                           0x0000C000L
+//OPTC_MISC_SPARE_REGISTER
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT                                                  0x0
+#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK                                                    0x000000FFL
+
+
+// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON17_PERFCOUNTER_CNTL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_CNTL2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON17_PERFCOUNTER_STATE
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON17_PERFMON_CNTL
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON17_PERFMON_CNTL2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON17_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON17_PERFMON_CVALUE_LOW
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON17_PERFMON_HI
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON17_PERFMON_LOW
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dio_hpd0_dispdec
+//HPD0_DC_HPD_INT_STATUS
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD0_DC_HPD_INT_CONTROL
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD0_DC_HPD_CONTROL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD0_DC_HPD_FAST_TRAIN_CNTL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD0_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd1_dispdec
+//HPD1_DC_HPD_INT_STATUS
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD1_DC_HPD_INT_CONTROL
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD1_DC_HPD_CONTROL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD1_DC_HPD_FAST_TRAIN_CNTL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD1_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd2_dispdec
+//HPD2_DC_HPD_INT_STATUS
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD2_DC_HPD_INT_CONTROL
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD2_DC_HPD_CONTROL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD2_DC_HPD_FAST_TRAIN_CNTL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD2_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd3_dispdec
+//HPD3_DC_HPD_INT_STATUS
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD3_DC_HPD_INT_CONTROL
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD3_DC_HPD_CONTROL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD3_DC_HPD_FAST_TRAIN_CNTL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD3_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_hpd4_dispdec
+//HPD4_DC_HPD_INT_STATUS
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT                                                      0x0
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT                                                           0x1
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT                                                   0x4
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT                                       0xc
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT                                    0x18
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK                                                        0x00000001L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK                                                             0x00000002L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK                                                     0x00000010L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK                                         0x000FF000L
+#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK                                      0xFF000000L
+//HPD4_DC_HPD_INT_CONTROL
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT                                                        0x0
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT                                                   0x8
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT                                                         0x10
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT                                                     0x14
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT                                                      0x18
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK                                                          0x00000001L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK                                                     0x00000100L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK                                                           0x00010000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK                                                       0x00100000L
+#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK                                                        0x01000000L
+//HPD4_DC_HPD_CONTROL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT                                                   0x0
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT                                                       0x10
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT                                                                 0x1c
+#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK                                                     0x00001FFFL
+#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK                                                         0x03FF0000L
+#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK                                                                   0x10000000L
+//HPD4_DC_HPD_FAST_TRAIN_CNTL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT                                       0x0
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT                                   0xc
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT                                          0x18
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT                                      0x1c
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK                                         0x000000FFL
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK                                     0x000FF000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK                                            0x01000000L
+#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK                                        0x10000000L
+//HPD4_DC_HPD_TOGGLE_FILT_CNTL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT                                         0x0
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT                                      0x14
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK                                           0x000000FFL
+#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK                                        0x0FF00000L
+
+
+// addressBlock: dce_dc_dio_dp0_dispdec
+//DP0_DP_LINK_CNTL
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP0_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP0_DP_PIXEL_FORMAT
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP0_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP0_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP0_DP_MSA_COLORIMETRY
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP0_DP_CONFIG
+#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP0_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP0_DP_VID_STREAM_CNTL
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP0_DP_STEER_FIFO
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP0_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP0_DP_MSA_MISC
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP0_DP_DPHY_INTERNAL_CTRL
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP0_DP_VID_TIMING
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP0_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP0_DP_VID_N
+#define DP0_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP0_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP0_DP_VID_M
+#define DP0_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP0_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP0_DP_LINK_FRAMING_CNTL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP0_DP_HBR2_EYE_PATTERN
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP0_DP_VID_MSA_VBID
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP0_DP_VID_INTERRUPT_CNTL
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP0_DP_DPHY_CNTL
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP0_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP0_DP_DPHY_SYM0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM1
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP0_DP_DPHY_SYM2
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP0_DP_DPHY_8B10B_CNTL
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP0_DP_DPHY_PRBS_CNTL
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP0_DP_DPHY_SCRAM_CNTL
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP0_DP_DPHY_CRC_EN
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP0_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP0_DP_DPHY_CRC_CNTL
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP0_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP0_DP_DPHY_CRC_RESULT
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP0_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP0_DP_DPHY_CRC_MST_CNTL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP0_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP0_DP_DPHY_CRC_MST_STATUS
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP0_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP0_DP_DPHY_FAST_TRAINING
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP0_DP_DPHY_FAST_TRAINING_STATUS
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP0_DP_SEC_CNTL
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP0_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL1
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_FRAMING1
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING2
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP0_DP_SEC_FRAMING3
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP0_DP_SEC_FRAMING4
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP0_DP_SEC_AUD_N
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_N_READBACK
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_AUD_M
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP0_DP_SEC_AUD_M_READBACK
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP0_DP_SEC_TIMESTAMP
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP0_DP_SEC_PACKET_CNTL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP0_DP_MSE_RATE_CNTL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP0_DP_MSE_RATE_UPDATE
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP0_DP_MSE_SAT0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT1
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT2
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP0_DP_MSE_SAT_UPDATE
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP0_DP_MSE_LINK_TIMING
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP0_DP_MSE_MISC_CNTL
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP0_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP0_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP0_DP_MSE_SAT0_STATUS
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT1_STATUS
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSE_SAT2_STATUS
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP0_DP_MSA_TIMING_PARAM1
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM2
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP0_DP_MSA_TIMING_PARAM3
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP0_DP_MSA_TIMING_PARAM4
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP0_DP_MSO_CNTL
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP0_DP_MSO_CNTL1
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP0_DP_DSC_CNTL
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP0_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP0_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP0_DP_SEC_CNTL2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP0_DP_SEC_CNTL3
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL4
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL5
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_SEC_CNTL6
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP0_DP_SEC_CNTL7
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP0_DP_DB_CNTL
+#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP0_DP_MSA_VBID_MISC
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP0_DP_SEC_METADATA_TRANSMISSION
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP0_DP_DSC_BYTES_PER_PIXEL
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP0_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP0_DP_ALPM_CNTL
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP0_DP_GSP8_CNTL
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP9_CNTL
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP0_DP_GSP10_CNTL
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP11_CNTL
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP0_DP_GSP_EN_DB_STATUS
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig0_dispdec
+//DIG0_DIG_FE_CNTL
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG0_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG0_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG0_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG0_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG0_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG0_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG0_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG0_DIG_OUTPUT_CRC_CNTL
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG0_DIG_OUTPUT_CRC_RESULT
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG0_DIG_CLOCK_PATTERN
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG0_DIG_TEST_PATTERN
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG0_DIG_RANDOM_PATTERN_SEED
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG0_DIG_FIFO_STATUS
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG0_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG0_HDMI_METADATA_PACKET_CONTROL
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG0_HDMI_CONTROL
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG0_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG0_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG0_HDMI_STATUS
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG0_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG0_HDMI_AUDIO_PACKET_CONTROL
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG0_HDMI_ACR_PACKET_CONTROL
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG0_HDMI_VBI_PACKET_CONTROL
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG0_HDMI_INFOFRAME_CONTROL0
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG0_HDMI_INFOFRAME_CONTROL1
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG0_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG0_HDMI_GC
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG0_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG0_HDMI_DB_CONTROL
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG0_HDMI_ACR_32_0
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_32_1
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_44_0
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_44_1
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_48_0
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG0_HDMI_ACR_48_1
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG0_HDMI_ACR_STATUS_0
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG0_HDMI_ACR_STATUS_1
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG0_AFMT_CNTL
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG0_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG0_DIG_BE_CNTL
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG0_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG0_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG0_DIG_BE_EN_CNTL
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG0_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG0_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG0_TMDS_CNTL
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG0_TMDS_CONTROL_CHAR
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG0_TMDS_CONTROL0_FEEDBACK
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG0_TMDS_STEREOSYNC_CTL_SEL
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG0_TMDS_CTL_BITS
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG0_TMDS_DCBALANCER_CONTROL
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG0_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG0_TMDS_CTL0_1_GEN_CNTL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG0_TMDS_CTL2_3_GEN_CNTL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG0_DIG_VERSION
+#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG0_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG0_FORCE_DIG_DISABLE
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG0_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp1_dispdec
+//DP1_DP_LINK_CNTL
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP1_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP1_DP_PIXEL_FORMAT
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP1_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP1_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP1_DP_MSA_COLORIMETRY
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP1_DP_CONFIG
+#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP1_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP1_DP_VID_STREAM_CNTL
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP1_DP_STEER_FIFO
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP1_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP1_DP_MSA_MISC
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP1_DP_DPHY_INTERNAL_CTRL
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP1_DP_VID_TIMING
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP1_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP1_DP_VID_N
+#define DP1_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP1_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP1_DP_VID_M
+#define DP1_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP1_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP1_DP_LINK_FRAMING_CNTL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP1_DP_HBR2_EYE_PATTERN
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP1_DP_VID_MSA_VBID
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP1_DP_VID_INTERRUPT_CNTL
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP1_DP_DPHY_CNTL
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP1_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP1_DP_DPHY_SYM0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM1
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP1_DP_DPHY_SYM2
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP1_DP_DPHY_8B10B_CNTL
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP1_DP_DPHY_PRBS_CNTL
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP1_DP_DPHY_SCRAM_CNTL
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP1_DP_DPHY_CRC_EN
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP1_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP1_DP_DPHY_CRC_CNTL
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP1_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP1_DP_DPHY_CRC_RESULT
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP1_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP1_DP_DPHY_CRC_MST_CNTL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP1_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP1_DP_DPHY_CRC_MST_STATUS
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP1_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP1_DP_DPHY_FAST_TRAINING
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP1_DP_DPHY_FAST_TRAINING_STATUS
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP1_DP_SEC_CNTL
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP1_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL1
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_FRAMING1
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING2
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP1_DP_SEC_FRAMING3
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP1_DP_SEC_FRAMING4
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP1_DP_SEC_AUD_N
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_N_READBACK
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_AUD_M
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP1_DP_SEC_AUD_M_READBACK
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP1_DP_SEC_TIMESTAMP
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP1_DP_SEC_PACKET_CNTL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP1_DP_MSE_RATE_CNTL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP1_DP_MSE_RATE_UPDATE
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP1_DP_MSE_SAT0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT1
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT2
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP1_DP_MSE_SAT_UPDATE
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP1_DP_MSE_LINK_TIMING
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP1_DP_MSE_MISC_CNTL
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP1_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP1_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP1_DP_MSE_SAT0_STATUS
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT1_STATUS
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSE_SAT2_STATUS
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP1_DP_MSA_TIMING_PARAM1
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM2
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP1_DP_MSA_TIMING_PARAM3
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP1_DP_MSA_TIMING_PARAM4
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP1_DP_MSO_CNTL
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP1_DP_MSO_CNTL1
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP1_DP_DSC_CNTL
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP1_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP1_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP1_DP_SEC_CNTL2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP1_DP_SEC_CNTL3
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL4
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL5
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_SEC_CNTL6
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP1_DP_SEC_CNTL7
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP1_DP_DB_CNTL
+#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP1_DP_MSA_VBID_MISC
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP1_DP_SEC_METADATA_TRANSMISSION
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP1_DP_DSC_BYTES_PER_PIXEL
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP1_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP1_DP_ALPM_CNTL
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP1_DP_GSP8_CNTL
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP9_CNTL
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP1_DP_GSP10_CNTL
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP11_CNTL
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP1_DP_GSP_EN_DB_STATUS
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig1_dispdec
+//DIG1_DIG_FE_CNTL
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG1_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG1_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG1_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG1_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG1_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG1_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG1_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG1_DIG_OUTPUT_CRC_CNTL
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG1_DIG_OUTPUT_CRC_RESULT
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG1_DIG_CLOCK_PATTERN
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG1_DIG_TEST_PATTERN
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG1_DIG_RANDOM_PATTERN_SEED
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG1_DIG_FIFO_STATUS
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG1_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG1_HDMI_METADATA_PACKET_CONTROL
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG1_HDMI_CONTROL
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG1_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG1_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG1_HDMI_STATUS
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG1_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG1_HDMI_AUDIO_PACKET_CONTROL
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG1_HDMI_ACR_PACKET_CONTROL
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG1_HDMI_VBI_PACKET_CONTROL
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG1_HDMI_INFOFRAME_CONTROL0
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG1_HDMI_INFOFRAME_CONTROL1
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG1_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG1_HDMI_GC
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG1_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG1_HDMI_DB_CONTROL
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG1_HDMI_ACR_32_0
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_32_1
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_44_0
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_44_1
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_48_0
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG1_HDMI_ACR_48_1
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG1_HDMI_ACR_STATUS_0
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG1_HDMI_ACR_STATUS_1
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG1_AFMT_CNTL
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG1_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG1_DIG_BE_CNTL
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG1_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG1_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG1_DIG_BE_EN_CNTL
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG1_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG1_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG1_TMDS_CNTL
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG1_TMDS_CONTROL_CHAR
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG1_TMDS_CONTROL0_FEEDBACK
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG1_TMDS_STEREOSYNC_CTL_SEL
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG1_TMDS_CTL_BITS
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG1_TMDS_DCBALANCER_CONTROL
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG1_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG1_TMDS_CTL0_1_GEN_CNTL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG1_TMDS_CTL2_3_GEN_CNTL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG1_DIG_VERSION
+#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG1_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG1_FORCE_DIG_DISABLE
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG1_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp2_dispdec
+//DP2_DP_LINK_CNTL
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP2_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP2_DP_PIXEL_FORMAT
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP2_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP2_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP2_DP_MSA_COLORIMETRY
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP2_DP_CONFIG
+#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP2_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP2_DP_VID_STREAM_CNTL
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP2_DP_STEER_FIFO
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP2_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP2_DP_MSA_MISC
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP2_DP_DPHY_INTERNAL_CTRL
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP2_DP_VID_TIMING
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP2_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP2_DP_VID_N
+#define DP2_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP2_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP2_DP_VID_M
+#define DP2_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP2_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP2_DP_LINK_FRAMING_CNTL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP2_DP_HBR2_EYE_PATTERN
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP2_DP_VID_MSA_VBID
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP2_DP_VID_INTERRUPT_CNTL
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP2_DP_DPHY_CNTL
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP2_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP2_DP_DPHY_SYM0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM1
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP2_DP_DPHY_SYM2
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP2_DP_DPHY_8B10B_CNTL
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP2_DP_DPHY_PRBS_CNTL
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP2_DP_DPHY_SCRAM_CNTL
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP2_DP_DPHY_CRC_EN
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP2_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP2_DP_DPHY_CRC_CNTL
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP2_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP2_DP_DPHY_CRC_RESULT
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP2_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP2_DP_DPHY_CRC_MST_CNTL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP2_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP2_DP_DPHY_CRC_MST_STATUS
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP2_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP2_DP_DPHY_FAST_TRAINING
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP2_DP_DPHY_FAST_TRAINING_STATUS
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP2_DP_SEC_CNTL
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP2_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL1
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_FRAMING1
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING2
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP2_DP_SEC_FRAMING3
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP2_DP_SEC_FRAMING4
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP2_DP_SEC_AUD_N
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_N_READBACK
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_AUD_M
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP2_DP_SEC_AUD_M_READBACK
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP2_DP_SEC_TIMESTAMP
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP2_DP_SEC_PACKET_CNTL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP2_DP_MSE_RATE_CNTL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP2_DP_MSE_RATE_UPDATE
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP2_DP_MSE_SAT0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT1
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT2
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP2_DP_MSE_SAT_UPDATE
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP2_DP_MSE_LINK_TIMING
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP2_DP_MSE_MISC_CNTL
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP2_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP2_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP2_DP_MSE_SAT0_STATUS
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT1_STATUS
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSE_SAT2_STATUS
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP2_DP_MSA_TIMING_PARAM1
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM2
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP2_DP_MSA_TIMING_PARAM3
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP2_DP_MSA_TIMING_PARAM4
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP2_DP_MSO_CNTL
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP2_DP_MSO_CNTL1
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP2_DP_DSC_CNTL
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP2_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP2_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP2_DP_SEC_CNTL2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP2_DP_SEC_CNTL3
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL4
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL5
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_SEC_CNTL6
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP2_DP_SEC_CNTL7
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP2_DP_DB_CNTL
+#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP2_DP_MSA_VBID_MISC
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP2_DP_SEC_METADATA_TRANSMISSION
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP2_DP_DSC_BYTES_PER_PIXEL
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP2_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP2_DP_ALPM_CNTL
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP2_DP_GSP8_CNTL
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP9_CNTL
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP2_DP_GSP10_CNTL
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP11_CNTL
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP2_DP_GSP_EN_DB_STATUS
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig2_dispdec
+//DIG2_DIG_FE_CNTL
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG2_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG2_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG2_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG2_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG2_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG2_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG2_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG2_DIG_OUTPUT_CRC_CNTL
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG2_DIG_OUTPUT_CRC_RESULT
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG2_DIG_CLOCK_PATTERN
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG2_DIG_TEST_PATTERN
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG2_DIG_RANDOM_PATTERN_SEED
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG2_DIG_FIFO_STATUS
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG2_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG2_HDMI_METADATA_PACKET_CONTROL
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG2_HDMI_CONTROL
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG2_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG2_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG2_HDMI_STATUS
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG2_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG2_HDMI_AUDIO_PACKET_CONTROL
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG2_HDMI_ACR_PACKET_CONTROL
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG2_HDMI_VBI_PACKET_CONTROL
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG2_HDMI_INFOFRAME_CONTROL0
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG2_HDMI_INFOFRAME_CONTROL1
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG2_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG2_HDMI_GC
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG2_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG2_HDMI_DB_CONTROL
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG2_HDMI_ACR_32_0
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_32_1
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_44_0
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_44_1
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_48_0
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG2_HDMI_ACR_48_1
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG2_HDMI_ACR_STATUS_0
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG2_HDMI_ACR_STATUS_1
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG2_AFMT_CNTL
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG2_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG2_DIG_BE_CNTL
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG2_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG2_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG2_DIG_BE_EN_CNTL
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG2_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG2_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG2_TMDS_CNTL
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG2_TMDS_CONTROL_CHAR
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG2_TMDS_CONTROL0_FEEDBACK
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG2_TMDS_STEREOSYNC_CTL_SEL
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG2_TMDS_CTL_BITS
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG2_TMDS_DCBALANCER_CONTROL
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG2_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG2_TMDS_CTL0_1_GEN_CNTL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG2_TMDS_CTL2_3_GEN_CNTL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG2_DIG_VERSION
+#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG2_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG2_FORCE_DIG_DISABLE
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG2_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp3_dispdec
+//DP3_DP_LINK_CNTL
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP3_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP3_DP_PIXEL_FORMAT
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP3_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP3_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP3_DP_MSA_COLORIMETRY
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP3_DP_CONFIG
+#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP3_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP3_DP_VID_STREAM_CNTL
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP3_DP_STEER_FIFO
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP3_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP3_DP_MSA_MISC
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP3_DP_DPHY_INTERNAL_CTRL
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP3_DP_VID_TIMING
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP3_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP3_DP_VID_N
+#define DP3_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP3_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP3_DP_VID_M
+#define DP3_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP3_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP3_DP_LINK_FRAMING_CNTL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP3_DP_HBR2_EYE_PATTERN
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP3_DP_VID_MSA_VBID
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP3_DP_VID_INTERRUPT_CNTL
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP3_DP_DPHY_CNTL
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP3_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP3_DP_DPHY_SYM0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM1
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP3_DP_DPHY_SYM2
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP3_DP_DPHY_8B10B_CNTL
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP3_DP_DPHY_PRBS_CNTL
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP3_DP_DPHY_SCRAM_CNTL
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP3_DP_DPHY_CRC_EN
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP3_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP3_DP_DPHY_CRC_CNTL
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP3_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP3_DP_DPHY_CRC_RESULT
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP3_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP3_DP_DPHY_CRC_MST_CNTL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP3_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP3_DP_DPHY_CRC_MST_STATUS
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP3_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP3_DP_DPHY_FAST_TRAINING
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP3_DP_DPHY_FAST_TRAINING_STATUS
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP3_DP_SEC_CNTL
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP3_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL1
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_FRAMING1
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING2
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP3_DP_SEC_FRAMING3
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP3_DP_SEC_FRAMING4
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP3_DP_SEC_AUD_N
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_N_READBACK
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_AUD_M
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP3_DP_SEC_AUD_M_READBACK
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP3_DP_SEC_TIMESTAMP
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP3_DP_SEC_PACKET_CNTL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP3_DP_MSE_RATE_CNTL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP3_DP_MSE_RATE_UPDATE
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP3_DP_MSE_SAT0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT1
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT2
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP3_DP_MSE_SAT_UPDATE
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP3_DP_MSE_LINK_TIMING
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP3_DP_MSE_MISC_CNTL
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP3_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP3_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP3_DP_MSE_SAT0_STATUS
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT1_STATUS
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSE_SAT2_STATUS
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP3_DP_MSA_TIMING_PARAM1
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM2
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP3_DP_MSA_TIMING_PARAM3
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP3_DP_MSA_TIMING_PARAM4
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP3_DP_MSO_CNTL
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP3_DP_MSO_CNTL1
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP3_DP_DSC_CNTL
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP3_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP3_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP3_DP_SEC_CNTL2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP3_DP_SEC_CNTL3
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL4
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL5
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_SEC_CNTL6
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP3_DP_SEC_CNTL7
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP3_DP_DB_CNTL
+#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP3_DP_MSA_VBID_MISC
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP3_DP_SEC_METADATA_TRANSMISSION
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP3_DP_DSC_BYTES_PER_PIXEL
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP3_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP3_DP_ALPM_CNTL
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP3_DP_GSP8_CNTL
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP9_CNTL
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP3_DP_GSP10_CNTL
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP11_CNTL
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP3_DP_GSP_EN_DB_STATUS
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig3_dispdec
+//DIG3_DIG_FE_CNTL
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG3_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG3_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG3_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG3_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG3_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG3_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG3_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG3_DIG_OUTPUT_CRC_CNTL
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG3_DIG_OUTPUT_CRC_RESULT
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG3_DIG_CLOCK_PATTERN
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG3_DIG_TEST_PATTERN
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG3_DIG_RANDOM_PATTERN_SEED
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG3_DIG_FIFO_STATUS
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG3_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG3_HDMI_METADATA_PACKET_CONTROL
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG3_HDMI_CONTROL
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG3_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG3_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG3_HDMI_STATUS
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG3_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG3_HDMI_AUDIO_PACKET_CONTROL
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG3_HDMI_ACR_PACKET_CONTROL
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG3_HDMI_VBI_PACKET_CONTROL
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG3_HDMI_INFOFRAME_CONTROL0
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG3_HDMI_INFOFRAME_CONTROL1
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG3_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG3_HDMI_GC
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG3_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG3_HDMI_DB_CONTROL
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG3_HDMI_ACR_32_0
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_32_1
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_44_0
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_44_1
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_48_0
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG3_HDMI_ACR_48_1
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG3_HDMI_ACR_STATUS_0
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG3_HDMI_ACR_STATUS_1
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG3_AFMT_CNTL
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG3_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG3_DIG_BE_CNTL
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG3_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG3_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG3_DIG_BE_EN_CNTL
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG3_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG3_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG3_TMDS_CNTL
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG3_TMDS_CONTROL_CHAR
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG3_TMDS_CONTROL0_FEEDBACK
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG3_TMDS_STEREOSYNC_CTL_SEL
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG3_TMDS_CTL_BITS
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG3_TMDS_DCBALANCER_CONTROL
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG3_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG3_TMDS_CTL0_1_GEN_CNTL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG3_TMDS_CTL2_3_GEN_CNTL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG3_DIG_VERSION
+#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG3_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG3_FORCE_DIG_DISABLE
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG3_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dp4_dispdec
+//DP4_DP_LINK_CNTL
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT                                                    0x4
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT                                                               0x8
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT                                                       0x11
+#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK                                                      0x00000010L
+#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK                                                                 0x00000100L
+#define DP4_DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK                                                         0x00020000L
+//DP4_DP_PIXEL_FORMAT
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT                                                         0x0
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT                                                        0x18
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE__SHIFT                                                          0x1c
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK                                                           0x00000007L
+#define DP4_DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK                                                          0x07000000L
+#define DP4_DP_PIXEL_FORMAT__DP_PIXEL_COMBINE_MASK                                                            0x30000000L
+//DP4_DP_MSA_COLORIMETRY
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT                                                           0x18
+#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK                                                             0xFF000000L
+//DP4_DP_CONFIG
+#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT                                                                    0x0
+#define DP4_DP_CONFIG__DP_UDI_LANES_MASK                                                                      0x00000003L
+//DP4_DP_VID_STREAM_CNTL
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT                                                   0x0
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT                                                0x8
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT                                                   0x10
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT                                           0x14
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK                                                     0x00000001L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK                                                  0x00000300L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK                                                     0x00010000L
+#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK                                             0x00100000L
+//DP4_DP_STEER_FIFO
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT                                                         0x0
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT                                                      0x4
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT                                                       0x5
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT                                                       0x6
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT                                                      0x7
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT                                                         0x8
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT                                                          0xc
+#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK                                                           0x00000001L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK                                                        0x00000010L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK                                                         0x00000020L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK                                                         0x00000040L
+#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK                                                        0x00000080L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK                                                           0x00000100L
+#define DP4_DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK                                                            0x00001000L
+//DP4_DP_MSA_MISC
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT                                                                  0x0
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT                                                                  0x8
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT                                                                  0x10
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT                                                                  0x18
+#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK                                                                    0x000000FFL
+#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK                                                                    0x0000FF00L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK                                                                    0x00FF0000L
+#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK                                                                    0xFF000000L
+//DP4_DP_DPHY_INTERNAL_CTRL
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT                                         0x0
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT                                        0x4
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK                                           0x00000001L
+#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK                                          0x00000010L
+//DP4_DP_VID_TIMING
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT                                               0x4
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT                                                           0x8
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL__SHIFT                                                                0xa
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT                                                                0xc
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT                                                                0x18
+#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK                                                 0x00000010L
+#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK                                                             0x00000100L
+#define DP4_DP_VID_TIMING__DP_VID_N_MUL_MASK                                                                  0x00000C00L
+#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK                                                                  0x00003000L
+#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK                                                                  0xFF000000L
+//DP4_DP_VID_N
+#define DP4_DP_VID_N__DP_VID_N__SHIFT                                                                         0x0
+#define DP4_DP_VID_N__DP_VID_N_MASK                                                                           0x00FFFFFFL
+//DP4_DP_VID_M
+#define DP4_DP_VID_M__DP_VID_M__SHIFT                                                                         0x0
+#define DP4_DP_VID_M__DP_VID_M_MASK                                                                           0x00FFFFFFL
+//DP4_DP_LINK_FRAMING_CNTL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT                                                  0x0
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT                                                      0x18
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT                                           0x1c
+#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK                                                    0x0003FFFFL
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK                                                        0x01000000L
+#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK                                             0x10000000L
+//DP4_DP_HBR2_EYE_PATTERN
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT                                            0x0
+#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK                                              0x00000001L
+//DP4_DP_VID_MSA_VBID
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT                                                       0x0
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT                                                     0x18
+#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK                                                         0x00000FFFL
+#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK                                                       0x01000000L
+//DP4_DP_VID_INTERRUPT_CNTL
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT                                           0x0
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT                                           0x1
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT                                          0x2
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK                                             0x00000001L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK                                             0x00000002L
+#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK                                            0x00000004L
+//DP4_DP_DPHY_CNTL
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT                                                         0x0
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT                                                         0x1
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT                                                         0x2
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT                                                         0x3
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT                                                                  0x4
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT                                                        0x5
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT                                                       0x6
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT                                                           0x8
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT                                                                  0x10
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT                                                             0x18
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK                                                           0x00000001L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK                                                           0x00000002L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK                                                           0x00000004L
+#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK                                                           0x00000008L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK                                                                    0x00000010L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK                                                          0x00000020L
+#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK                                                         0x00000040L
+#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK                                                             0x00000100L
+#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK                                                                    0x00010000L
+#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK                                                               0x01000000L
+//DP4_DP_DPHY_TRAINING_PATTERN_SEL
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT                                    0x0
+#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK                                      0x00000003L
+//DP4_DP_DPHY_SYM0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM1
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT                                                                    0x14
+#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK                                                                      0x000FFC00L
+#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK                                                                      0x3FF00000L
+//DP4_DP_DPHY_SYM2
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT                                                                    0x0
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT                                                                    0xa
+#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK                                                                      0x000003FFL
+#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK                                                                      0x000FFC00L
+//DP4_DP_DPHY_8B10B_CNTL
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT                                                       0x8
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT                                                    0x10
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT                                                    0x18
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK                                                         0x00000100L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK                                                      0x00010000L
+#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK                                                      0x01000000L
+//DP4_DP_DPHY_PRBS_CNTL
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT                                                            0x0
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT                                                           0x4
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT                                                          0x8
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK                                                              0x00000001L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK                                                             0x00000030L
+#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK                                                            0x7FFFFF00L
+//DP4_DP_DPHY_SCRAM_CNTL
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT                                                     0x0
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT                                                 0x4
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT                                                0x8
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT                                                   0x18
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK                                                       0x00000001L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK                                                   0x00000010L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK                                                  0x0003FF00L
+#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK                                                     0x01000000L
+//DP4_DP_DPHY_CRC_EN
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT                                                                0x0
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT                                                           0x4
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT                                                      0x8
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK                                                                  0x00000001L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK                                                             0x00000010L
+#define DP4_DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK                                                        0x00000100L
+//DP4_DP_DPHY_CRC_CNTL
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT                                                           0x0
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT                                                             0x4
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT                                                            0x10
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK                                                             0x00000001L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK                                                               0x00000030L
+#define DP4_DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK                                                              0x00FF0000L
+//DP4_DP_DPHY_CRC_RESULT
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT                                                        0x0
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT                                                       0x8
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT                                                       0x10
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT                                                       0x18
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK                                                          0x000000FFL
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK                                                         0x0000FF00L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK                                                         0x00FF0000L
+#define DP4_DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK                                                         0xFF000000L
+//DP4_DP_DPHY_CRC_MST_CNTL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT                                              0x0
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT                                               0x8
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK                                                0x0000003FL
+#define DP4_DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK                                                 0x00003F00L
+//DP4_DP_DPHY_CRC_MST_STATUS
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT                                            0x0
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT                                           0x8
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT                                       0x10
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK                                              0x00000001L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK                                             0x00000100L
+#define DP4_DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK                                         0x00010000L
+//DP4_DP_DPHY_FAST_TRAINING
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT                                       0x0
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT                                         0x1
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT                            0x2
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT                              0x4
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT                                         0x8
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT                                         0x14
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK                                         0x00000001L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK                                           0x00000002L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK                              0x00000004L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK                                0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK                                           0x000FFF00L
+#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK                                           0xFFF00000L
+//DP4_DP_DPHY_FAST_TRAINING_STATUS
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT                                     0x0
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT                         0x4
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT                             0x8
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT                              0xc
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK                                       0x00000007L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK                           0x00000010L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK                               0x00000100L
+#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK                                0x00001000L
+//DP4_DP_SEC_CNTL
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT                                                          0x0
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT                                                            0x14
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT                                                            0x15
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT                                                            0x16
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT                                                            0x17
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT                                                            0x18
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT                                                            0x19
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT                                                            0x1a
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT                                                            0x1b
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK                                                            0x00000001L
+#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK                                                              0x00100000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK                                                              0x00200000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK                                                              0x00400000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK                                                              0x00800000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK                                                              0x01000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK                                                              0x02000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK                                                              0x04000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK                                                              0x08000000L
+#define DP4_DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL1
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT                                                           0x0
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT                                                   0x1
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT                                                         0x4
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT                                                             0x5
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT                                                     0x6
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT                                             0x7
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT                                                   0x9
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT                                                   0xa
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT                                                   0xb
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT                                                   0xc
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT                                                   0xd
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT                                                   0xe
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT                                                   0xf
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK                                                             0x00000001L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK                                                     0x00000002L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK                                                           0x00000010L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK                                                               0x00000020L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK                                                       0x00000040L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK                                               0x00000080L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK                                                     0x00000200L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK                                                     0x00000400L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK                                                     0x00000800L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK                                                     0x00001000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK                                                     0x00002000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK                                                     0x00004000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK                                                     0x00008000L
+#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_FRAMING1
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT                                               0x0
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK                                                 0x00000FFFL
+#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING2
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT                                                     0x0
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT                                              0x10
+#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK                                                       0x0000FFFFL
+#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK                                                0xFFFF0000L
+//DP4_DP_SEC_FRAMING3
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT                                                    0x0
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT                                                0x10
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK                                                      0x00003FFFL
+#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK                                                  0xFFFF0000L
+//DP4_DP_SEC_FRAMING4
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT                                                      0x0
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT                                                   0x14
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT                                                      0x18
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT                                                         0x1c
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT                                                  0x1d
+#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK                                                        0x00000001L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK                                                     0x00100000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK                                                        0x01000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK                                                           0x10000000L
+#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK                                                    0x20000000L
+//DP4_DP_SEC_AUD_N
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_N_READBACK
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_AUD_M
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT                                                                 0x0
+#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK                                                                   0x00FFFFFFL
+//DP4_DP_SEC_AUD_M_READBACK
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT                                               0x0
+#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK                                                 0x00FFFFFFL
+//DP4_DP_SEC_TIMESTAMP
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT                                                    0x0
+#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK                                                      0x00000001L
+//DP4_DP_SEC_PACKET_CNTL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT                                                 0x1
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT                                                    0x4
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT                                                         0x8
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                      0x10
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK                                                   0x0000000EL
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK                                                      0x00000010L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK                                                           0x00003F00L
+#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                        0x00010000L
+//DP4_DP_MSE_RATE_CNTL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT                                                            0x0
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT                                                            0x1a
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK                                                              0x03FFFFFFL
+#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK                                                              0xFC000000L
+//DP4_DP_MSE_RATE_UPDATE
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT                                             0x0
+#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK                                               0x00000001L
+//DP4_DP_MSE_SAT0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT1
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT2
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT                                                               0x0
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT                                                        0x8
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT                                                               0x10
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT                                                        0x18
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK                                                                 0x00000007L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK                                                          0x00003F00L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK                                                                 0x00070000L
+#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK                                                          0x3F000000L
+//DP4_DP_MSE_SAT_UPDATE
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT                                                       0x0
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT                                                   0x8
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK                                                         0x00000003L
+#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK                                                     0x00000100L
+//DP4_DP_MSE_LINK_TIMING
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT                                                      0x0
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT                                                       0x10
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK                                                        0x000003FFL
+#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK                                                         0x00030000L
+//DP4_DP_MSE_MISC_CNTL
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT                                                        0x0
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT                                                    0x4
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT                                                      0x8
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK                                                          0x00000001L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK                                                      0x00000010L
+#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK                                                        0x00000100L
+//DP4_DP_DPHY_BS_SR_SWAP_CNTL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT                                                0x0
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT                                              0xf
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT                                          0x10
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK                                                  0x000003FFL
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK                                                0x00008000L
+#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK                                            0x00010000L
+//DP4_DP_DPHY_HBR2_PATTERN_CONTROL
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT                                 0x0
+#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK                                   0x00000007L
+//DP4_DP_MSE_SAT0_STATUS
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT1_STATUS
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSE_SAT2_STATUS
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT                                                 0x0
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT                                          0x8
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT                                                 0x10
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT                                          0x18
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK                                                   0x00000007L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK                                            0x00003F00L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK                                                   0x00070000L
+#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK                                            0x3F000000L
+//DP4_DP_MSA_TIMING_PARAM1
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM2
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT                                                        0x0
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK                                                          0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK                                                          0xFFFF0000L
+//DP4_DP_MSA_TIMING_PARAM3
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT                                                    0x0
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT                                                 0xf
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT                                                    0x10
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT                                                 0x1f
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK                                                      0x00007FFFL
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK                                                   0x00008000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK                                                      0x7FFF0000L
+#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK                                                   0x80000000L
+//DP4_DP_MSA_TIMING_PARAM4
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT                                                       0x0
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT                                                        0x10
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK                                                         0x0000FFFFL
+#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK                                                          0xFFFF0000L
+//DP4_DP_MSO_CNTL
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT                                                         0x0
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT                                                      0x4
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT                                                         0x8
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT                                                         0xc
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT                                                         0x10
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT                                                         0x14
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT                                                        0x1c
+#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK                                                           0x00000003L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK                                                        0x000000F0L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK                                                           0x00000F00L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK                                                           0x0000F000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK                                                           0x000F0000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK                                                           0x00F00000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK                                                          0xF0000000L
+//DP4_DP_MSO_CNTL1
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT                                                       0x4
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT                                                       0x8
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT                                                       0xc
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT                                                       0x10
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT                                                       0x14
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE__SHIFT                                                        0x18
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT                                                       0x1c
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK                                                         0x000000F0L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK                                                         0x00000F00L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK                                                         0x0000F000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK                                                         0x000F0000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK                                                         0x00F00000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_MPG_ENABLE_MASK                                                          0x0F000000L
+#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK                                                         0xF0000000L
+//DP4_DP_DSC_CNTL
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE__SHIFT                                                                   0x0
+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH__SHIFT                                                            0x10
+#define DP4_DP_DSC_CNTL__DP_DSC_MODE_MASK                                                                     0x00000003L
+#define DP4_DP_DSC_CNTL__DP_DSC_SLICE_WIDTH_MASK                                                              0x1FFF0000L
+//DP4_DP_SEC_CNTL2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT                                                             0x0
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT                                             0x2
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT                                                    0x3
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT                                                             0x4
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT                                             0x6
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT                                                    0x7
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT                                                             0x8
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT                                             0xa
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT                                                    0xb
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT                                                             0xc
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT                                                    0xf
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT                                                             0x10
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT                                             0x12
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT                                                             0x14
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT                                             0x16
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT                                                             0x18
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT                                             0x1a
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT                                                    0x1b
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT                                                             0x1c
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK                                                               0x00000001L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK                                               0x00000004L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK                                                      0x00000008L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK                                                               0x00000010L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK                                               0x00000040L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK                                                      0x00000080L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK                                                               0x00000100L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK                                               0x00000400L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK                                                      0x00000800L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK                                                               0x00001000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK                                                      0x00008000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK                                                               0x00010000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK                                               0x00040000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK                                                               0x00100000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK                                               0x00400000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK                                                               0x01000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK                                               0x04000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK                                                      0x08000000L
+#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK                                                               0x10000000L
+//DP4_DP_SEC_CNTL3
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL4
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL5
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_SEC_CNTL6
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT                                                         0x0
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT                                                    0x10
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT                                                    0x11
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT                                                    0x12
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT                                                    0x13
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT                                                    0x14
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT                                                    0x15
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT                                                    0x16
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT                                                    0x17
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT                                                    0x18
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT                                                    0x19
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT                                                   0x1a
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT                                                   0x1b
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK                                                           0x0000FFFFL
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK                                                      0x00010000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK                                                      0x00020000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK                                                      0x00040000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK                                                      0x00080000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK                                                      0x00100000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK                                                      0x00200000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK                                                      0x00400000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK                                                      0x00800000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK                                                      0x01000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK                                                      0x02000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK                                                     0x04000000L
+#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK                                                     0x08000000L
+//DP4_DP_SEC_CNTL7
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT                                                      0x0
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT                                                     0x1
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT                                                      0x4
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT                                                     0x5
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT                                                      0x8
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT                                                     0x9
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT                                                      0xc
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT                                                     0xd
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT                                                      0x10
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT                                                     0x11
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT                                                      0x14
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT                                                     0x15
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT                                                      0x18
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT                                                     0x19
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT                                                      0x1c
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT                                                     0x1d
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK                                                        0x00000001L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK                                                       0x00000002L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK                                                        0x00000010L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK                                                       0x00000020L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK                                                        0x00000100L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK                                                       0x00000200L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK                                                        0x00001000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK                                                       0x00002000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK                                                        0x00010000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK                                                       0x00020000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK                                                        0x00100000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK                                                       0x00200000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK                                                        0x01000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK                                                       0x02000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK                                                        0x10000000L
+#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK                                                       0x20000000L
+//DP4_DP_DB_CNTL
+#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT                                                                  0x0
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT                                                                    0x4
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT                                                                0x5
+#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT                                                                     0x8
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT                                                                  0xc
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT                                                          0xf
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT                                                            0x10
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT                                                        0x11
+#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK                                                                    0x00000001L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK                                                                      0x00000010L
+#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK                                                                  0x00000020L
+#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK                                                                       0x00000100L
+#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK                                                                    0x00001000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK                                                            0x00008000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK                                                              0x00010000L
+#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK                                                          0x00020000L
+//DP4_DP_MSA_VBID_MISC
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT                                         0x0
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                                      0x4
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT                                                        0x8
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT                                                        0x9
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT                                                     0xc
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT                                                     0xd
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT                                                  0xf
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT                                                        0x10
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK                                           0x00000003L
+#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                                        0x00000010L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK                                                          0x00000100L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK                                                          0x00000200L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK                                                       0x00001000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK                                                       0x00002000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK                                                    0x00008000L
+#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK                                                          0xFFFF0000L
+//DP4_DP_SEC_METADATA_TRANSMISSION
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT                                0x0
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT                        0x1
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT                            0x4
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT                                  0x10
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK                                  0x00000001L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK                          0x00000002L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK                              0x000000F0L
+#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK                                    0xFFFF0000L
+//DP4_DP_DSC_BYTES_PER_PIXEL
+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL__SHIFT                                             0x0
+#define DP4_DP_DSC_BYTES_PER_PIXEL__DP_DSC_BYTES_PER_PIXEL_MASK                                               0x7FFFFFFFL
+//DP4_DP_ALPM_CNTL
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT                                                         0x0
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT                                                      0x1
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT                                                       0x2
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT                                                    0x3
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT                                            0x4
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT                                        0x5
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT                                             0x10
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK                                                           0x00000001L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK                                                        0x00000002L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK                                                         0x00000004L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK                                                      0x00000008L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK                                              0x00000010L
+#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK                                          0x00000020L
+#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK                                               0xFFFF0000L
+//DP4_DP_GSP8_CNTL
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP9_CNTL
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT                                                       0x0
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT                                                           0x4
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT                                                   0x5
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT                                                     0x6
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT                                                             0x7
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT                                                    0x8
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT                                                     0xc
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT                                                      0xd
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT                                             0xe
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT                                                         0x10
+#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK                                                         0x0000000FL
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK                                                             0x00000010L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK                                                     0x00000020L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK                                                       0x00000040L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK                                                               0x00000080L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK                                                      0x00000100L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK                                                       0x00001000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK                                                        0x00002000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK                                               0x00004000L
+#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK                                                           0xFFFF0000L
+//DP4_DP_GSP10_CNTL
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP11_CNTL
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT                                                     0x0
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT                                                         0x4
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT                                                 0x5
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT                                                   0x6
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT                                                           0x7
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT                                                  0x8
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT                                                   0xc
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT                                                    0xd
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT                                           0xe
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT                                                       0x10
+#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK                                                       0x0000000FL
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK                                                           0x00000010L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK                                                   0x00000020L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK                                                     0x00000040L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK                                                             0x00000080L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK                                                    0x00000100L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK                                                     0x00001000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK                                                      0x00002000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK                                             0x00004000L
+#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK                                                         0xFFFF0000L
+//DP4_DP_GSP_EN_DB_STATUS
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT                                             0x0
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT                                             0x1
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT                                             0x2
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT                                             0x3
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT                                             0x4
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT                                             0x5
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT                                             0x6
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT                                             0x7
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT                                             0x8
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT                                             0x9
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT                                            0xa
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT                                            0xb
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK                                               0x00000001L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK                                               0x00000002L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK                                               0x00000004L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK                                               0x00000008L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK                                               0x00000010L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK                                               0x00000020L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK                                               0x00000040L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK                                               0x00000080L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK                                               0x00000100L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK                                               0x00000200L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK                                              0x00000400L
+#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK                                              0x00000800L
+
+
+// addressBlock: dce_dc_dio_dig4_dispdec
+//DIG4_DIG_FE_CNTL
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT                                                            0x0
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT                                                        0x4
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT                                                       0x8
+#define DIG4_DIG_FE_CNTL__DIG_START__SHIFT                                                                    0xa
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT                                                    0xc
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT__SHIFT                                                       0x10
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN__SHIFT                                                              0x12
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT                                          0x13
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT                                                             0x18
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING__SHIFT                                                          0x1c
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT__SHIFT                                                            0x1e
+#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK                                                              0x00000007L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK                                                          0x00000070L
+#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK                                                         0x00000100L
+#define DIG4_DIG_FE_CNTL__DIG_START_MASK                                                                      0x00000400L
+#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK                                                      0x00007000L
+#define DIG4_DIG_FE_CNTL__DIG_INPUT_PIXEL_SELECT_MASK                                                         0x00030000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_EN_MASK                                                                0x00040000L
+#define DIG4_DIG_FE_CNTL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK                                            0x00080000L
+#define DIG4_DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK                                                               0x01000000L
+#define DIG4_DIG_FE_CNTL__TMDS_PIXEL_ENCODING_MASK                                                            0x10000000L
+#define DIG4_DIG_FE_CNTL__TMDS_COLOR_FORMAT_MASK                                                              0xC0000000L
+//DIG4_DIG_OUTPUT_CRC_CNTL
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT                                                    0x0
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT                                              0x4
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT                                              0x8
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK                                                      0x00000001L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK                                                0x00000010L
+#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK                                                0x00000300L
+//DIG4_DIG_OUTPUT_CRC_RESULT
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT                                              0x0
+#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK                                                0x3FFFFFFFL
+//DIG4_DIG_CLOCK_PATTERN
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT                                                      0x0
+#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK                                                        0x000003FFL
+//DIG4_DIG_TEST_PATTERN
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT                                                 0x0
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT                                              0x1
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT                                               0x4
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT                                                0x5
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT                                      0x6
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT                                                 0x10
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK                                                   0x00000001L
+#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK                                                0x00000002L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK                                                 0x00000010L
+#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK                                                  0x00000020L
+#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK                                        0x00000040L
+#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK                                                   0x03FF0000L
+//DIG4_DIG_RANDOM_PATTERN_SEED
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT                                          0x0
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT                                       0x18
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK                                            0x00FFFFFFL
+#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK                                         0x01000000L
+//DIG4_DIG_FIFO_STATUS
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT                                                     0x0
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT                                             0x1
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT                                                 0x2
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT                                                       0x8
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT                                               0xa
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT                                                   0x16
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC__SHIFT                                                  0x1a
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT                                                      0x1d
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT                                             0x1e
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT                                             0x1f
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK                                                       0x00000001L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK                                               0x00000002L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK                                                   0x000000FCL
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK                                                         0x00000100L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK                                                 0x0000FC00L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK                                                     0x03C00000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_READ_CLOCK_SRC_MASK                                                    0x04000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK                                                        0x20000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK                                               0x40000000L
+#define DIG4_DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK                                               0x80000000L
+//DIG4_HDMI_METADATA_PACKET_CONTROL
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT                                 0x0
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT                         0x4
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT                                 0x8
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT                                   0x10
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK                                   0x00000001L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK                           0x00000010L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK                                   0x00000100L
+#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK                                     0xFFFF0000L
+//DIG4_HDMI_CONTROL
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT                                                           0x0
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT                                                       0x1
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT                                                     0x2
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT                                            0x3
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT                                                     0x4
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT                                                              0x8
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT                                                             0x9
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT                                           0x10
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT                                                      0x18
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT                                                       0x1c
+#define DIG4_HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK                                                             0x00000001L
+#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK                                                         0x00000002L
+#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK                                                       0x00000004L
+#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK                                              0x00000008L
+#define DIG4_HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK                                                       0x00000010L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK                                                                0x00000100L
+#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK                                                               0x00000200L
+#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK                                             0x003F0000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK                                                        0x01000000L
+#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK                                                         0x30000000L
+//DIG4_HDMI_STATUS
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT                                                           0x0
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT                                                      0x10
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT                                                        0x14
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT                                                               0x1b
+#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK                                                             0x00000001L
+#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK                                                        0x00010000L
+#define DIG4_HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK                                                          0x00100000L
+#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK                                                                 0x08000000L
+//DIG4_HDMI_AUDIO_PACKET_CONTROL
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT                                            0x4
+#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK                                              0x00000030L
+//DIG4_HDMI_ACR_PACKET_CONTROL
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT                                                    0x0
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT                                                    0x1
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT                                                  0x4
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT                                                  0x8
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT                                               0xc
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT                                              0x10
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT                                          0x1f
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK                                                      0x00000001L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK                                                      0x00000002L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK                                                    0x00000030L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK                                                    0x00000100L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK                                                 0x00001000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK                                                0x00070000L
+#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK                                            0x80000000L
+//DIG4_HDMI_VBI_PACKET_CONTROL
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT                                                   0x0
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT                                                     0x4
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT                                                     0x5
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT                                                   0x8
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT                                                   0x9
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT                                                   0x10
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK                                                     0x00000001L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK                                                       0x00000010L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK                                                       0x00000020L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK                                                     0x00000100L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK                                                     0x00000200L
+#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK                                                     0x003F0000L
+//DIG4_HDMI_INFOFRAME_CONTROL0
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT                                             0x4
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT                                             0x5
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT                                              0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT                                              0x9
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK                                               0x00000010L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK                                               0x00000020L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK                                                0x00000100L
+#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK                                                0x00000200L
+//DIG4_HDMI_INFOFRAME_CONTROL1
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT                                             0x8
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT                                              0x10
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK                                               0x00003F00L
+#define DIG4_HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK                                                0x003F0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT                                          0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT                                          0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT                           0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT                                          0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT                                          0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT                           0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT                                          0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT                           0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT                                          0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT                                          0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT                           0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT                                          0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT                                          0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT                                0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT                           0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT                                          0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT                                          0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT                                0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT                           0x1f
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK                                            0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK                                            0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK                             0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK                                            0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK                                            0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK                             0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK                                            0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK                                            0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK                             0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK                                            0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK                                            0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK                             0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK                                            0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK                                            0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK                                  0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK                             0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK                                            0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK                                            0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK                                  0x40000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK                             0x80000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT                                          0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT                           0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT                                          0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT                                          0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT                           0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT                                         0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT                                         0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT                               0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT                          0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT                                         0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT                                         0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT                               0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT                          0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT                                         0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT                               0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT                          0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT                                         0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT                                         0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT                          0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT                                         0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT                                         0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT                          0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK                                            0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK                                            0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK                             0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK                                            0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK                                            0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK                             0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK                                           0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK                                           0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK                                 0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK                            0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK                                           0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK                                           0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK                                 0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK                            0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK                                           0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK                                           0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK                                 0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK                            0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK                                           0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK                                           0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK                            0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK                                           0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK                                           0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK                            0x08000000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT                                0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT                        0x1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT                                0x2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT                        0x3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT                                0x4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT                        0x5
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT                                0x6
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT                        0x7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT                                0x8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT                        0x9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT                                0xa
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT                        0xb
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT                                0xc
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT                        0xd
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT                                0xe
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT                        0xf
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT                        0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT                        0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT                               0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT                       0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT                               0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT                       0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT                               0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT                       0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT                       0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT                       0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK                                  0x00000001L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK                          0x00000002L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK                                  0x00000004L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK                          0x00000008L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK                                  0x00000010L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK                          0x00000020L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK                                  0x00000040L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK                          0x00000080L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK                                  0x00000100L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK                          0x00000200L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK                                  0x00000400L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK                          0x00000800L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK                                  0x00001000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK                          0x00002000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK                                  0x00004000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK                          0x00008000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK                          0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK                          0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK                                 0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK                         0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK                                 0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK                         0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK                                 0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK                         0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK                         0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK                         0x20000000L
+//DIG4_HDMI_GC
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT                                                                   0x0
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT                                                              0x2
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT                                                               0x4
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT                                                               0x8
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT                                                      0xc
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK                                                                     0x00000001L
+#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK                                                                0x00000004L
+#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK                                                                 0x00000010L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK                                                                 0x00000F00L
+#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK                                                        0x00001000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL1
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL2
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL3
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL4
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL7
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT                                          0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT                                          0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK                                            0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK                                            0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL8
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL9
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT                                         0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT                                         0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK                                           0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK                                           0xFFFF0000L
+//DIG4_HDMI_GENERIC_PACKET_CONTROL10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT                                        0x0
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT                                0x10
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT                                0x11
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT                                0x12
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT                                0x13
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT                                0x14
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT                                0x15
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT                                0x16
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT                                0x17
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT                                0x18
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT                                0x19
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT                               0x1a
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT                               0x1b
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT                               0x1c
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT                               0x1d
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT                               0x1e
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK                                          0x0000FFFFL
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK                                  0x00010000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK                                  0x00020000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK                                  0x00040000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK                                  0x00080000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK                                  0x00100000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK                                  0x00200000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK                                  0x00400000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK                                  0x00800000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK                                  0x01000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK                                  0x02000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK                                 0x04000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK                                 0x08000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK                                 0x10000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK                                 0x20000000L
+#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK                                 0x40000000L
+//DIG4_HDMI_DB_CONTROL
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT                                                          0x0
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT                                                            0x4
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT                                                        0x5
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT                                                             0x8
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT                                                          0xc
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT                                                       0xf
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT                                                         0x10
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT                                                     0x11
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK                                                            0x00000001L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK                                                              0x00000010L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK                                                          0x00000020L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK                                                               0x00000100L
+#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK                                                            0x00001000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK                                                         0x00008000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK                                                           0x00010000L
+#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK                                                       0x00020000L
+//DIG4_HDMI_ACR_32_0
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_32_1
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_44_0
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_44_1
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_48_0
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT                                                            0xc
+#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK                                                              0xFFFFF000L
+//DIG4_HDMI_ACR_48_1
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT                                                              0x0
+#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK                                                                0x000FFFFFL
+//DIG4_HDMI_ACR_STATUS_0
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT                                                           0xc
+#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK                                                             0xFFFFF000L
+//DIG4_HDMI_ACR_STATUS_1
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT                                                             0x0
+#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK                                                               0x000FFFFFL
+//DIG4_AFMT_CNTL
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN__SHIFT                                                            0x0
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON__SHIFT                                                            0x8
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_EN_MASK                                                              0x00000001L
+#define DIG4_AFMT_CNTL__AFMT_AUDIO_CLOCK_ON_MASK                                                              0x00000100L
+//DIG4_DIG_BE_CNTL
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT                                                         0x0
+#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT                                                                     0x1
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT                                                             0x2
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT                                                         0x8
+#define DIG4_DIG_BE_CNTL__DIG_MODE__SHIFT                                                                     0x10
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT                                                               0x1c
+#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK                                                           0x00000001L
+#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK                                                                       0x00000002L
+#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK                                                               0x00000004L
+#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK                                                           0x00007F00L
+#define DIG4_DIG_BE_CNTL__DIG_MODE_MASK                                                                       0x00070000L
+#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK                                                                 0x70000000L
+//DIG4_DIG_BE_EN_CNTL
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT                                                                0x0
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT                                                          0x8
+#define DIG4_DIG_BE_EN_CNTL__DIG_ENABLE_MASK                                                                  0x00000001L
+#define DIG4_DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK                                                            0x00000100L
+//DIG4_TMDS_CNTL
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT                                                                0x0
+#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK                                                                  0x00000001L
+//DIG4_TMDS_CONTROL_CHAR
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT                                              0x0
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT                                              0x1
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT                                              0x2
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT                                              0x3
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK                                                0x00000001L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK                                                0x00000002L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK                                                0x00000004L
+#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK                                                0x00000008L
+//DIG4_TMDS_CONTROL0_FEEDBACK
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT                                     0x0
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT                                      0x8
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK                                       0x00000003L
+#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK                                        0x00000300L
+//DIG4_TMDS_STEREOSYNC_CTL_SEL
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT                                          0x0
+#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK                                            0x00000003L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK                                         0x03FF0000L
+//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT                                       0x0
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT                                       0x10
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK                                         0x000003FFL
+#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK                                         0x03FF0000L
+//DIG4_TMDS_CTL_BITS
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT                                                                  0x0
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT                                                                  0x8
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT                                                                  0x10
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT                                                                  0x18
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK                                                                    0x00000001L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK                                                                    0x00000100L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK                                                                    0x00010000L
+#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK                                                                    0x01000000L
+//DIG4_TMDS_DCBALANCER_CONTROL
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT                                               0x0
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT                                               0x4
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT                                          0x8
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT                                          0x10
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT                                            0x18
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK                                                 0x00000001L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK                                                 0x00000070L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK                                            0x00000100L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK                                            0x000F0000L
+#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK                                              0x01000000L
+//DIG4_TMDS_SYNC_DCBALANCE_CHAR
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT                                          0x0
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT                                          0x10
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK                                            0x000003FFL
+#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK                                            0x03FF0000L
+//DIG4_TMDS_CTL0_1_GEN_CNTL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT                                                0x1f
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK                                              0x10000000L
+#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK                                                  0x80000000L
+//DIG4_TMDS_CTL2_3_GEN_CNTL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT                                                  0x0
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT                                                0x4
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT                                               0x7
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT                                           0x8
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT                                         0xa
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT                                              0xb
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT                                            0xc
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT                                                  0x10
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT                                                0x14
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT                                               0x17
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT                                           0x18
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT                                         0x1a
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT                                              0x1b
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT                                            0x1c
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK                                                    0x0000000FL
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK                                                  0x00000070L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK                                                 0x00000080L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK                                             0x00000300L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK                                           0x00000400L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK                                                0x00000800L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK                                              0x00001000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK                                                    0x000F0000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK                                                  0x00700000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK                                                 0x00800000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK                                             0x03000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK                                           0x04000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK                                                0x08000000L
+#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK                                              0x10000000L
+//DIG4_DIG_VERSION
+#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT                                                                     0x0
+#define DIG4_DIG_VERSION__DIG_TYPE_MASK                                                                       0x00000001L
+//DIG4_FORCE_DIG_DISABLE
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE__SHIFT                                                      0x0
+#define DIG4_FORCE_DIG_DISABLE__FORCE_DIG_DISABLE_MASK                                                        0x00000001L
+
+
+// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
+//AFMT0_AFMT_VBI_PACKET_CONTROL
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT0_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT0_AFMT_AUDIO_INFO0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT0_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT0_AFMT_AUDIO_INFO1
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT0_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT0_AFMT_60958_0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT0_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT0_AFMT_60958_1
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT0_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_CONTROL
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT0_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT0_AFMT_RAMP_CONTROL0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT0_AFMT_RAMP_CONTROL1
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT0_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT0_AFMT_RAMP_CONTROL2
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_RAMP_CONTROL3
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT0_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT0_AFMT_60958_2
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT0_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT0_AFMT_AUDIO_CRC_RESULT
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT0_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT0_AFMT_STATUS
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT0_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT0_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT0_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT0_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT0_AFMT_INFOFRAME_CONTROL0
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT0_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT0_AFMT_INTERRUPT_STATUS
+//AFMT0_AFMT_AUDIO_SRC_CONTROL
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT0_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT0_AFMT_MEM_PWR
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT0_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
+//AFMT1_AFMT_VBI_PACKET_CONTROL
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT1_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT1_AFMT_AUDIO_INFO0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT1_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT1_AFMT_AUDIO_INFO1
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT1_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT1_AFMT_60958_0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT1_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT1_AFMT_60958_1
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT1_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_CONTROL
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT1_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT1_AFMT_RAMP_CONTROL0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT1_AFMT_RAMP_CONTROL1
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT1_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT1_AFMT_RAMP_CONTROL2
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_RAMP_CONTROL3
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT1_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT1_AFMT_60958_2
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT1_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT1_AFMT_AUDIO_CRC_RESULT
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT1_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT1_AFMT_STATUS
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT1_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT1_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT1_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT1_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT1_AFMT_INFOFRAME_CONTROL0
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT1_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT1_AFMT_INTERRUPT_STATUS
+//AFMT1_AFMT_AUDIO_SRC_CONTROL
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT1_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT1_AFMT_MEM_PWR
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT1_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
+//AFMT2_AFMT_VBI_PACKET_CONTROL
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT2_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT2_AFMT_AUDIO_INFO0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT2_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT2_AFMT_AUDIO_INFO1
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT2_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT2_AFMT_60958_0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT2_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT2_AFMT_60958_1
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT2_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_CONTROL
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT2_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT2_AFMT_RAMP_CONTROL0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT2_AFMT_RAMP_CONTROL1
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT2_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT2_AFMT_RAMP_CONTROL2
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_RAMP_CONTROL3
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT2_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT2_AFMT_60958_2
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT2_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT2_AFMT_AUDIO_CRC_RESULT
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT2_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT2_AFMT_STATUS
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT2_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT2_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT2_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT2_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT2_AFMT_INFOFRAME_CONTROL0
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT2_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT2_AFMT_INTERRUPT_STATUS
+//AFMT2_AFMT_AUDIO_SRC_CONTROL
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT2_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT2_AFMT_MEM_PWR
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT2_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
+//AFMT3_AFMT_VBI_PACKET_CONTROL
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT3_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT3_AFMT_AUDIO_INFO0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT3_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT3_AFMT_AUDIO_INFO1
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT3_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT3_AFMT_60958_0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT3_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT3_AFMT_60958_1
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT3_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_CONTROL
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT3_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT3_AFMT_RAMP_CONTROL0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT3_AFMT_RAMP_CONTROL1
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT3_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT3_AFMT_RAMP_CONTROL2
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_RAMP_CONTROL3
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT3_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT3_AFMT_60958_2
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT3_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT3_AFMT_AUDIO_CRC_RESULT
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT3_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT3_AFMT_STATUS
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT3_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT3_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT3_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT3_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT3_AFMT_INFOFRAME_CONTROL0
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT3_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT3_AFMT_INTERRUPT_STATUS
+//AFMT3_AFMT_AUDIO_SRC_CONTROL
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT3_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT3_AFMT_MEM_PWR
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT3_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
+//AFMT4_AFMT_VBI_PACKET_CONTROL
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT4_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT4_AFMT_AUDIO_INFO0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT4_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT4_AFMT_AUDIO_INFO1
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT4_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT4_AFMT_60958_0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT4_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT4_AFMT_60958_1
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT4_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_CONTROL
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT4_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT4_AFMT_RAMP_CONTROL0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT4_AFMT_RAMP_CONTROL1
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT4_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT4_AFMT_RAMP_CONTROL2
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_RAMP_CONTROL3
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT4_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT4_AFMT_60958_2
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT4_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT4_AFMT_AUDIO_CRC_RESULT
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT4_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT4_AFMT_STATUS
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT4_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT4_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT4_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT4_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT4_AFMT_INFOFRAME_CONTROL0
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT4_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT4_AFMT_INTERRUPT_STATUS
+//AFMT4_AFMT_AUDIO_SRC_CONTROL
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT4_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT4_AFMT_MEM_PWR
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT4_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
+//DME0_DME_CONTROL
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME0_DME_MEMORY_CONTROL
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
+//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG0_VPG_GENERIC_PACKET_DATA
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG0_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG0_VPG_GENERIC_STATUS
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG0_VPG_MEM_PWR
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG0_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG0_VPG_ISRC1_2_DATA
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG0_VPG_MPEG_INFO0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG0_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG0_VPG_MPEG_INFO1
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG0_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
+//DME1_DME_CONTROL
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME1_DME_MEMORY_CONTROL
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
+//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG1_VPG_GENERIC_PACKET_DATA
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG1_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG1_VPG_GENERIC_STATUS
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG1_VPG_MEM_PWR
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG1_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG1_VPG_ISRC1_2_DATA
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG1_VPG_MPEG_INFO0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG1_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG1_VPG_MPEG_INFO1
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG1_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
+//DME2_DME_CONTROL
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME2_DME_MEMORY_CONTROL
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
+//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG2_VPG_GENERIC_PACKET_DATA
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG2_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG2_VPG_GENERIC_STATUS
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG2_VPG_MEM_PWR
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG2_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG2_VPG_ISRC1_2_DATA
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG2_VPG_MPEG_INFO0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG2_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG2_VPG_MPEG_INFO1
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG2_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
+//DME3_DME_CONTROL
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME3_DME_MEMORY_CONTROL
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
+//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG3_VPG_GENERIC_PACKET_DATA
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG3_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG3_VPG_GENERIC_STATUS
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG3_VPG_MEM_PWR
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG3_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG3_VPG_ISRC1_2_DATA
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG3_VPG_MPEG_INFO0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG3_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG3_VPG_MPEG_INFO1
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG3_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
+//DME4_DME_CONTROL
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME4_DME_MEMORY_CONTROL
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
+//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG4_VPG_GENERIC_PACKET_DATA
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG4_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG4_VPG_GENERIC_STATUS
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG4_VPG_MEM_PWR
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG4_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG4_VPG_ISRC1_2_DATA
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG4_VPG_MPEG_INFO0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG4_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG4_VPG_MPEG_INFO1
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG4_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_dio_dp_aux0_dispdec
+//DP_AUX0_AUX_CONTROL
+#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX0_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX0_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX0_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX0_AUX_SW_CONTROL
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX0_AUX_ARB_CONTROL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX0_AUX_INTERRUPT_CONTROL
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX0_AUX_SW_STATUS
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX0_AUX_LS_STATUS
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX0_AUX_SW_DATA
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX0_AUX_LS_DATA
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX0_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX0_AUX_DPHY_TX_CONTROL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX0_AUX_DPHY_RX_CONTROL1
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX0_AUX_DPHY_TX_STATUS
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX0_AUX_DPHY_RX_STATUS
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX0_AUX_GTC_SYNC_STATUS
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX0_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX0_AUX_PHY_WAKE_CNTL
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux1_dispdec
+//DP_AUX1_AUX_CONTROL
+#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX1_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX1_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX1_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX1_AUX_SW_CONTROL
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX1_AUX_ARB_CONTROL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX1_AUX_INTERRUPT_CONTROL
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX1_AUX_SW_STATUS
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX1_AUX_LS_STATUS
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX1_AUX_SW_DATA
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX1_AUX_LS_DATA
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX1_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX1_AUX_DPHY_TX_CONTROL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX1_AUX_DPHY_RX_CONTROL1
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX1_AUX_DPHY_TX_STATUS
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX1_AUX_DPHY_RX_STATUS
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX1_AUX_GTC_SYNC_STATUS
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX1_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX1_AUX_PHY_WAKE_CNTL
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux2_dispdec
+//DP_AUX2_AUX_CONTROL
+#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX2_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX2_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX2_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX2_AUX_SW_CONTROL
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX2_AUX_ARB_CONTROL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX2_AUX_INTERRUPT_CONTROL
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX2_AUX_SW_STATUS
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX2_AUX_LS_STATUS
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX2_AUX_SW_DATA
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX2_AUX_LS_DATA
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX2_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX2_AUX_DPHY_TX_CONTROL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX2_AUX_DPHY_RX_CONTROL1
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX2_AUX_DPHY_TX_STATUS
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX2_AUX_DPHY_RX_STATUS
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX2_AUX_GTC_SYNC_STATUS
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX2_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX2_AUX_PHY_WAKE_CNTL
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux3_dispdec
+//DP_AUX3_AUX_CONTROL
+#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX3_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX3_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX3_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX3_AUX_SW_CONTROL
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX3_AUX_ARB_CONTROL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX3_AUX_INTERRUPT_CONTROL
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX3_AUX_SW_STATUS
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX3_AUX_LS_STATUS
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX3_AUX_SW_DATA
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX3_AUX_LS_DATA
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX3_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX3_AUX_DPHY_TX_CONTROL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX3_AUX_DPHY_RX_CONTROL1
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX3_AUX_DPHY_TX_STATUS
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX3_AUX_DPHY_RX_STATUS
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX3_AUX_GTC_SYNC_STATUS
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX3_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX3_AUX_PHY_WAKE_CNTL
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dp_aux4_dispdec
+//DP_AUX4_AUX_CONTROL
+#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT                                                                    0x0
+#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT                                                                 0x4
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT                                                            0x5
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT                                                            0x8
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT                                                     0xc
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT                                                     0x10
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT                                                           0x12
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT                                                               0x14
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT                                                         0x18
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT                                                             0x1c
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_CONTROL__SPARE_0__SHIFT                                                                   0x1e
+#define DP_AUX4_AUX_CONTROL__SPARE_1__SHIFT                                                                   0x1f
+#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK                                                                      0x00000001L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK                                                                   0x00000010L
+#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK                                                              0x00000020L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK                                                              0x00000100L
+#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK                                                       0x00001000L
+#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK                                                       0x00010000L
+#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK                                                             0x00040000L
+#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK                                                                 0x00700000L
+#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK                                                           0x01000000L
+#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK                                                               0x10000000L
+#define DP_AUX4_AUX_CONTROL__AUX_DEGLITCH_EN_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_0_MASK                                                                     0x40000000L
+#define DP_AUX4_AUX_CONTROL__SPARE_1_MASK                                                                     0x80000000L
+//DP_AUX4_AUX_SW_CONTROL
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT                                                              0x0
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT                                                       0x2
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT                                                     0x4
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT                                                        0x10
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK                                                                0x00000001L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK                                                         0x00000004L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK                                                       0x000000F0L
+#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK                                                          0x001F0000L
+//DP_AUX4_AUX_ARB_CONTROL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT                                                      0x0
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT                                                0x2
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT                                                   0x8
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT                                                   0xa
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT                                                0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT                                        0x10
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT                                             0x11
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT                                              0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT                                      0x18
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT                                           0x19
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK                                                        0x00000003L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK                                                  0x0000000CL
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK                                                     0x00000100L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK                                                     0x00000400L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK                                                  0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK                                          0x00010000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK                                               0x00020000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK                                                0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK                                        0x01000000L
+#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK                                             0x02000000L
+//DP_AUX4_AUX_INTERRUPT_CONTROL
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT                                                 0x0
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT                                                 0x1
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT                                                0x2
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT                                                 0x4
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT                                                 0x5
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT                                                0x6
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT__SHIFT                                      0x8
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK__SHIFT                                      0x9
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK__SHIFT                                 0xa
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT__SHIFT                                          0xc
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK__SHIFT                                          0xd
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK__SHIFT                                     0xe
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK                                                   0x00000002L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK                                                  0x00000004L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK                                                   0x00000010L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK                                                   0x00000020L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK                                                  0x00000040L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK                                        0x00000100L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_ACK_MASK                                        0x00000200L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_LOCK_DONE_INT_MASK_MASK                                   0x00000400L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK                                            0x00001000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_ACK_MASK                                            0x00002000L
+#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_GTC_SYNC_ERROR_INT_MASK_MASK                                       0x00004000L
+//DP_AUX4_AUX_SW_STATUS
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT                                                          0x1d
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK                                                            0xE0000000L
+//DP_AUX4_AUX_LS_STATUS
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT                                                             0x0
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT                                                              0x1
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT                                                 0x4
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT                                                       0x7
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT                                                      0x8
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT                                                       0x9
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT                                                  0xa
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT                                                     0xb
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT                                                0xc
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT                                                  0xe
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT                                                0x11
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT                                                0x12
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT                                                 0x13
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT                                                   0x14
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT                                                0x16
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT                                                0x17
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT                                                 0x18
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT                                                           0x1d
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT                                                          0x1e
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT                                                      0x1f
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK                                                               0x00000001L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK                                                                0x00000002L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK                                                   0x00000070L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK                                                         0x00000080L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK                                                        0x00000100L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK                                                         0x00000200L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK                                                    0x00000400L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK                                                       0x00000800L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK                                                  0x00001000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK                                                    0x00004000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK                                                  0x00020000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK                                                  0x00040000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK                                                   0x00080000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK                                                     0x00100000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK                                                  0x00400000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK                                                  0x00800000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK                                                   0x1F000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK                                                             0x20000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK                                                            0x40000000L
+#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK                                                        0x80000000L
+//DP_AUX4_AUX_SW_DATA
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT                                                            0x0
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT                                              0x1f
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK                                                              0x00000001L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK                                                                0x001F0000L
+#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK                                                0x80000000L
+//DP_AUX4_AUX_LS_DATA
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT                                                               0x8
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT                                                              0x10
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK                                                                 0x0000FF00L
+#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK                                                                0x001F0000L
+//DP_AUX4_AUX_DPHY_TX_REF_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT                                                0x0
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT                                                   0x4
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT                                                0x10
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK                                                  0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK                                                     0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK                                                  0x01FF0000L
+//DP_AUX4_AUX_DPHY_TX_CONTROL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT                                              0x0
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT                                          0x4
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT                                             0x6
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT                                          0x8
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT                                          0x10
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK                                                0x0000000FL
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK                                            0x00000030L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK                                               0x00000040L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK                                            0x00003F00L
+#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK                                            0x00070000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT                                              0x4
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT                                       0xc
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT                                      0x10
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT                        0x11
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT                               0x12
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT                                0x13
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT                                          0x14
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT                                       0x1c
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK                                                0x00000070L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK                                              0x00000700L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK                                         0x00003000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK                                        0x00010000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK                          0x00020000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK                                 0x00040000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK                                  0x00080000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK                                            0x00300000L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK                                         0x70000000L
+//DP_AUX4_AUX_DPHY_RX_CONTROL1
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT                                            0x0
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT                                               0x8
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT                                           0xf
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK                                              0x000000FFL
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK                                                 0x00007F00L
+#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK                                             0x00018000L
+//DP_AUX4_AUX_DPHY_TX_STATUS
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT                                                      0x0
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT                                                       0x4
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT                                             0x10
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK                                                        0x00000001L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK                                                         0x00000070L
+#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK                                               0x01FF0000L
+//DP_AUX4_AUX_DPHY_RX_STATUS
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT                                                       0x0
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT                                            0x8
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT                                       0x10
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT                                             0x15
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK                                                         0x00000007L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK                                              0x00001F00L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK                                         0x001F0000L
+#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK                                               0x3FE00000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT                                                  0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN__SHIFT                                           0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL__SHIFT                                     0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD__SHIFT                                     0xc
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD__SHIFT                                   0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ__SHIFT                                           0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW__SHIFT                               0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT__SHIFT                             0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_EN_MASK                                             0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_IMPCAL_INTERVAL_MASK                                       0x00000F00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_PERIOD_MASK                                       0x0000F000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_MAINT_PERIOD_MASK                                     0x00070000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_BLOCK_REQ_MASK                                             0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_INTERVAL_RESET_WINDOW_MASK                                 0x00C00000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT_MASK                               0x03000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD__SHIFT                          0x0
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD__SHIFT                           0x8
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN__SHIFT                          0x10
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT__SHIFT                      0x14
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_POTENTIAL_ERROR_THRESHOLD_MASK                            0x0000001FL
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_DEFINITE_ERROR_THRESHOLD_MASK                             0x00001F00L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN_MASK                            0x00030000L
+#define DP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL__AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT_MASK                        0x00300000L
+//DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE__SHIFT                         0x0
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST__SHIFT                                 0x4
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED__SHIFT                 0x8
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE__SHIFT                    0x9
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL__SHIFT                    0x10
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED__SHIFT                     0x14
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK__SHIFT                 0x15
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED__SHIFT                 0x16
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK__SHIFT             0x17
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED__SHIFT                  0x18
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK__SHIFT              0x19
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE__SHIFT                                0x1c
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_COMPLETE_MASK                           0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_LOST_MASK                                   0x00000010L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED_MASK                   0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE_MASK                      0x00001E00L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL_MASK                      0x00010000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_MASK                       0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK_MASK                   0x00200000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_MASK                   0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK_MASK               0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_MASK                    0x01000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK_MASK                0x02000000L
+#define DP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS__AUX_GTC_SYNC_CTRL_STATE_MASK                                  0xF0000000L
+//DP_AUX4_AUX_GTC_SYNC_STATUS
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE__SHIFT                                                 0x0
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ__SHIFT                                                  0x1
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE__SHIFT                                     0x4
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT__SHIFT                                              0x7
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW__SHIFT                                          0x8
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON__SHIFT                                           0x9
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE__SHIFT                                      0xa
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE__SHIFT                                         0xb
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL__SHIFT                                    0xc
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP__SHIFT                                      0xe
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L__SHIFT                                    0x11
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H__SHIFT                                    0x12
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START__SHIFT                                     0x13
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET__SHIFT                                       0x14
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H__SHIFT                                    0x16
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L__SHIFT                                    0x17
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT__SHIFT                                     0x18
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED__SHIFT                                               0x1d
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX__SHIFT                                          0x1e
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_DONE_MASK                                                   0x00000001L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REQ_MASK                                                    0x00000002L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_TIMEOUT_STATE_MASK                                       0x00000070L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_TIMEOUT_MASK                                                0x00000080L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_OVERFLOW_MASK                                            0x00000100L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_HPD_DISCON_MASK                                             0x00000200L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_PARTIAL_BYTE_MASK                                        0x00000400L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NON_AUX_MODE_MASK                                           0x00000800L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_MIN_COUNT_VIOL_MASK                                      0x00001000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_STOP_MASK                                        0x00004000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_L_MASK                                      0x00020000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_SYNC_INVALID_H_MASK                                      0x00040000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_INVALID_START_MASK                                       0x00080000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_NO_DET_MASK                                         0x00100000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_H_MASK                                      0x00400000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_RX_RECV_INVALID_L_MASK                                      0x00800000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_REPLY_BYTE_COUNT_MASK                                       0x1F000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_SYNC_NACKED_MASK                                                 0x20000000L
+#define DP_AUX4_AUX_GTC_SYNC_STATUS__AUX_GTC_MASTER_REQ_BY_RX_MASK                                            0x40000000L
+//DP_AUX4_AUX_PHY_WAKE_CNTL
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT                                                  0x0
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT                                             0x1
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT                                            0x2
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT                                                 0x3
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK                                                    0x00000001L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK                                               0x00000002L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK                                              0x00000004L
+#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK                                                   0x00000008L
+
+
+// addressBlock: dce_dc_dio_dout_i2c_dispdec
+//DC_I2C_CONTROL
+#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT                                                                      0x0
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT                                                              0x1
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT                                                              0x2
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT                                                         0x3
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT                                                              0x8
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT                                                       0x14
+#define DC_I2C_CONTROL__DC_I2C_GO_MASK                                                                        0x00000001L
+#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK                                                                0x00000002L
+#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK                                                                0x00000004L
+#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK                                                           0x00000008L
+#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK                                                                0x00000700L
+#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK                                                         0x00300000L
+//DC_I2C_ARBITRATION
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT                                                         0x0
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT                                                  0x2
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT                                                     0x4
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT                                                       0x8
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT                                                       0xc
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT                                                  0x14
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT                                               0x15
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT                                                0x18
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT                                             0x19
+#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK                                                           0x00000003L
+#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK                                                    0x0000000CL
+#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK                                                       0x00000010L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK                                                         0x00000100L
+#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK                                                         0x00001000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK                                                    0x00100000L
+#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK                                                 0x00200000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK                                                  0x01000000L
+#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK                                               0x02000000L
+//DC_I2C_INTERRUPT_CONTROL
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT                                                   0x0
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT                                                   0x1
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT                                                  0x2
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT                                              0x4
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT                                              0x5
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT                                             0x6
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT                                              0x8
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT                                              0x9
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT                                             0xa
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT                                              0xc
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT                                              0xd
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT                                             0xe
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT                                              0x10
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT                                              0x11
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT                                             0x12
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT                                              0x14
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT                                              0x15
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT                                             0x16
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT                                              0x18
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT                                              0x19
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT                                             0x1a
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT                                            0x1b
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT                                            0x1c
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT                                           0x1d
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK                                                     0x00000001L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK                                                     0x00000002L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK                                                    0x00000004L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK                                                0x00000010L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK                                                0x00000020L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK                                               0x00000040L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK                                                0x00000100L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK                                                0x00000200L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK                                               0x00000400L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK                                                0x00001000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK                                                0x00002000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK                                               0x00004000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK                                                0x00010000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK                                                0x00020000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK                                               0x00040000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK                                                0x00100000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK                                                0x00200000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK                                               0x00400000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK                                                0x01000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK                                                0x02000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK                                               0x04000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK                                              0x08000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK                                              0x10000000L
+#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK                                             0x20000000L
+//DC_I2C_SW_STATUS
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT                                                             0x0
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT                                                               0x2
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT                                                            0x4
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT                                                            0x5
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT                                                        0x6
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT                                                    0x7
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT                                                    0x8
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT                                                              0xc
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT                                                              0xd
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT                                                              0xe
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT                                                              0xf
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT                                                                0x12
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK                                                               0x00000003L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK                                                                 0x00000004L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK                                                              0x00000010L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK                                                              0x00000020L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK                                                          0x00000040L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK                                                      0x00000080L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK                                                      0x00000100L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK                                                                0x00001000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK                                                                0x00002000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK                                                                0x00004000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK                                                                0x00008000L
+#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK                                                                  0x00040000L
+//DC_I2C_DDC1_HW_STATUS
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC2_HW_STATUS
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC3_HW_STATUS
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC4_HW_STATUS
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC5_HW_STATUS
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT                                                   0x0
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT                                                     0x3
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT                                                      0x10
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT                                                      0x11
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT                                          0x14
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT                                 0x18
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT                                           0x1c
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK                                                     0x00000003L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK                                                       0x00000008L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK                                                        0x00010000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK                                                        0x00020000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK                                            0x00100000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK                                   0x0F000000L
+#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK                                             0x70000000L
+//DC_I2C_DDC1_SPEED
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC1_SETUP
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC2_SPEED
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC2_SETUP
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC3_SPEED
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC3_SETUP
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC4_SPEED
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC4_SETUP
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_DDC5_SPEED
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT                                                       0x0
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT                                     0x4
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT                                          0x8
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT                                                        0x10
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK                                                         0x00000003L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK                                       0x00000010L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK                                            0x00000300L
+#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK                                                          0xFFFF0000L
+//DC_I2C_DDC5_SETUP
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT                                                   0x0
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT                                                  0x1
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT                                               0x2
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT                                              0x4
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT                                                0x5
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT                                                          0x6
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT                                                    0x7
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT                                                0x8
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT                                         0x10
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT                                                      0x18
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK                                                     0x00000001L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK                                                    0x00000002L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK                                                 0x00000004L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK                                                0x00000010L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK                                                  0x00000020L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK                                                            0x00000040L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK                                                      0x00000080L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK                                                  0x0000FF00L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK                                           0x00FF0000L
+#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK                                                        0xFF000000L
+//DC_I2C_TRANSACTION0
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION1
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION2
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK                                                               0x03FF0000L
+//DC_I2C_TRANSACTION3
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT                                                                0x0
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT                                                      0x8
+#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT                                                             0xc
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT                                                              0xd
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT                                                             0x10
+#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK                                                                  0x00000001L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK                                                        0x00000100L
+#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK                                                               0x00001000L
+#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK                                                                0x00002000L
+#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK                                                               0x03FF0000L
+//DC_I2C_DATA
+#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT                                                                    0x0
+#define DC_I2C_DATA__DC_I2C_DATA__SHIFT                                                                       0x8
+#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT                                                                      0x10
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT                                                                0x1f
+#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK                                                                      0x00000001L
+#define DC_I2C_DATA__DC_I2C_DATA_MASK                                                                         0x0000FF00L
+#define DC_I2C_DATA__DC_I2C_INDEX_MASK                                                                        0x03FF0000L
+#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK                                                                  0x80000000L
+//DC_I2C_EDID_DETECT_CTRL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT                                          0x0
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT                              0x14
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT                                         0x1c
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK                                            0x0000FFFFL
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK                                0x00F00000L
+#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK                                           0x10000000L
+//DC_I2C_READ_REQUEST_INTERRUPT
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT                               0x0
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT                                    0x1
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT                                    0x2
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT                                   0x3
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT                               0x4
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT                                    0x5
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT                                    0x6
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT                                   0x7
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT                               0x8
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT                                    0x9
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT                                    0xa
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT                                   0xb
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT                               0xc
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT                                    0xd
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT                                    0xe
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT                                   0xf
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT                               0x10
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT                                    0x11
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT                                    0x12
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT                                   0x13
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT                               0x14
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT                                    0x15
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT                                    0x16
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT                                   0x17
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT                             0x18
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT                                  0x19
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT                                  0x1a
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT                                 0x1b
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT                              0x1e
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT                                0x1f
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK                                 0x00000001L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK                                      0x00000002L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK                                      0x00000004L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK                                     0x00000008L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK                                 0x00000010L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK                                      0x00000020L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK                                      0x00000040L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK                                     0x00000080L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK                                 0x00000100L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK                                      0x00000200L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK                                      0x00000400L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK                                     0x00000800L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK                                 0x00001000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK                                      0x00002000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK                                      0x00004000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK                                     0x00008000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK                                 0x00010000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK                                      0x00020000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK                                      0x00040000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK                                     0x00080000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK                                 0x00100000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK                                      0x00200000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK                                      0x00400000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK                                     0x00800000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK                               0x01000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK                                    0x02000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK                                    0x04000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK                                   0x08000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK                                0x40000000L
+#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK                                  0x80000000L
+
+
+// addressBlock: dce_dc_dio_dio_misc_dispdec
+//DIO_SCRATCH0
+#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT                                                                     0x0
+#define DIO_SCRATCH0__DIO_SCRATCH0_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH1
+#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT                                                                     0x0
+#define DIO_SCRATCH1__DIO_SCRATCH1_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH2
+#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT                                                                     0x0
+#define DIO_SCRATCH2__DIO_SCRATCH2_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH3
+#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT                                                                     0x0
+#define DIO_SCRATCH3__DIO_SCRATCH3_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH4
+#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT                                                                     0x0
+#define DIO_SCRATCH4__DIO_SCRATCH4_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH5
+#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT                                                                     0x0
+#define DIO_SCRATCH5__DIO_SCRATCH5_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH6
+#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT                                                                     0x0
+#define DIO_SCRATCH6__DIO_SCRATCH6_MASK                                                                       0xFFFFFFFFL
+//DIO_SCRATCH7
+#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT                                                                     0x0
+#define DIO_SCRATCH7__DIO_SCRATCH7_MASK                                                                       0xFFFFFFFFL
+//DIO_MEM_PWR_STATUS
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT                                                          0x0
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT                                                          0x3
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT                                                          0x4
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT                                                          0x5
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT                                                          0x6
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT                                                          0x7
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT                                                          0x8
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT                                                          0x9
+#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK                                                            0x00000001L
+#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK                                                            0x00000008L
+#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK                                                            0x00000200L
+//DIO_MEM_PWR_CTRL
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT                                                        0x0
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT                                                          0x1
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT                                                          0x4
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT                                                          0x5
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT                                                          0x6
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT                                                          0x7
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT                                                          0x8
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT                                                          0x9
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT                                                          0xa
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK                                                          0x00000001L
+#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK                                                            0x00000002L
+#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK                                                            0x00000010L
+#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK                                                            0x00000020L
+#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK                                                            0x00000040L
+#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK                                                            0x00000080L
+#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK                                                            0x00000100L
+#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK                                                            0x00000200L
+#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK                                                            0x00000400L
+//DIO_MEM_PWR_CTRL2
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT                                                       0x18
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT                                                       0x19
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1a
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1b
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1c
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1d
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT                                                       0x1e
+#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK                                                         0x01000000L
+#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK                                                         0x02000000L
+#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK                                                         0x04000000L
+#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK                                                         0x08000000L
+#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK                                                         0x10000000L
+#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK                                                         0x20000000L
+#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK                                                         0x40000000L
+//DIO_CLK_CNTL
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS__SHIFT                                                           0x5
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS__SHIFT                                                            0xa
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT                                                          0x18
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT                                                          0x19
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT                                                          0x1a
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT                                                          0x1b
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT                                                          0x1c
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT                                                          0x1d
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS__SHIFT                                                          0x1e
+#define DIO_CLK_CNTL__DISPCLK_R_DIO_GATE_DIS_MASK                                                             0x00000020L
+#define DIO_CLK_CNTL__REFCLK_R_DIO_GATE_DIS_MASK                                                              0x00000400L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK                                                            0x01000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK                                                            0x02000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK                                                            0x04000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK                                                            0x08000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK                                                            0x10000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK                                                            0x20000000L
+#define DIO_CLK_CNTL__DISPCLK_G_DIGG_GATE_DIS_MASK                                                            0x40000000L
+//DIO_POWER_MANAGEMENT_CNTL
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT                                                     0x0
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT                                                     0x8
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK                                                       0x00000001L
+#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK                                                       0x00000100L
+//DIG_SOFT_RESET
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT                                                             0x0
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT                                                             0x1
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT                                                             0x4
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT                                                             0x5
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT                                                             0x8
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT                                                             0x9
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT                                                             0xc
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT                                                             0xd
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT                                                             0x10
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT                                                             0x11
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT                                                             0x14
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT                                                             0x15
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET__SHIFT                                                             0x18
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET__SHIFT                                                             0x19
+#define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK                                                               0x00000001L
+#define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK                                                               0x00000002L
+#define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK                                                               0x00000010L
+#define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK                                                               0x00000020L
+#define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK                                                               0x00000100L
+#define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK                                                               0x00000200L
+#define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK                                                               0x00001000L
+#define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK                                                               0x00002000L
+#define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK                                                               0x00010000L
+#define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK                                                               0x00020000L
+#define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK                                                               0x00100000L
+#define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK                                                               0x00200000L
+#define DIG_SOFT_RESET__DIGG_FE_SOFT_RESET_MASK                                                               0x01000000L
+#define DIG_SOFT_RESET__DIGG_BE_SOFT_RESET_MASK                                                               0x02000000L
+//DIO_CLK_CNTL2
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL__SHIFT                                                                0x0
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS__SHIFT                                                         0x7
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS__SHIFT                                                         0x8
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS__SHIFT                                                         0x9
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x11
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x12
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x13
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x14
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x15
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x16
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS__SHIFT                                                      0x17
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS__SHIFT                                                           0x18
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS__SHIFT                                                           0x19
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS__SHIFT                                                           0x1a
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS__SHIFT                                                           0x1b
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS__SHIFT                                                           0x1c
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS__SHIFT                                                           0x1d
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS__SHIFT                                                           0x1e
+#define DIO_CLK_CNTL2__DIO_TEST_CLK_SEL_MASK                                                                  0x0000007FL
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTA_GATE_DIS_MASK                                                           0x00000080L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTB_GATE_DIS_MASK                                                           0x00000100L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTC_GATE_DIS_MASK                                                           0x00000200L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTD_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTE_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTF_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL2__SOCCLK_G_AFMTG_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_G_AFMT_GATE_DIS_MASK                                                        0x00020000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_G_AFMT_GATE_DIS_MASK                                                        0x00040000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_G_AFMT_GATE_DIS_MASK                                                        0x00080000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_G_AFMT_GATE_DIS_MASK                                                        0x00100000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_G_AFMT_GATE_DIS_MASK                                                        0x00200000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_G_AFMT_GATE_DIS_MASK                                                        0x00400000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_G_AFMT_GATE_DIS_MASK                                                        0x00800000L
+#define DIO_CLK_CNTL2__SYMCLKA_FE_R_GATE_DIS_MASK                                                             0x01000000L
+#define DIO_CLK_CNTL2__SYMCLKB_FE_R_GATE_DIS_MASK                                                             0x02000000L
+#define DIO_CLK_CNTL2__SYMCLKC_FE_R_GATE_DIS_MASK                                                             0x04000000L
+#define DIO_CLK_CNTL2__SYMCLKD_FE_R_GATE_DIS_MASK                                                             0x08000000L
+#define DIO_CLK_CNTL2__SYMCLKE_FE_R_GATE_DIS_MASK                                                             0x10000000L
+#define DIO_CLK_CNTL2__SYMCLKF_FE_R_GATE_DIS_MASK                                                             0x20000000L
+#define DIO_CLK_CNTL2__SYMCLKG_FE_R_GATE_DIS_MASK                                                             0x40000000L
+//DIO_CLK_CNTL3
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x0
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x1
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x2
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x3
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x4
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x5
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS__SHIFT                                                      0x6
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS__SHIFT                                                         0xa
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS__SHIFT                                                         0xb
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS__SHIFT                                                         0xc
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS__SHIFT                                                         0xd
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS__SHIFT                                                         0xe
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS__SHIFT                                                         0xf
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS__SHIFT                                                         0x10
+#define DIO_CLK_CNTL3__SYMCLKA_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000001L
+#define DIO_CLK_CNTL3__SYMCLKB_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000002L
+#define DIO_CLK_CNTL3__SYMCLKC_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000004L
+#define DIO_CLK_CNTL3__SYMCLKD_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000008L
+#define DIO_CLK_CNTL3__SYMCLKE_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000010L
+#define DIO_CLK_CNTL3__SYMCLKF_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000020L
+#define DIO_CLK_CNTL3__SYMCLKG_FE_G_TMDS_GATE_DIS_MASK                                                        0x00000040L
+#define DIO_CLK_CNTL3__SYMCLKA_G_TMDS_GATE_DIS_MASK                                                           0x00000400L
+#define DIO_CLK_CNTL3__SYMCLKB_G_TMDS_GATE_DIS_MASK                                                           0x00000800L
+#define DIO_CLK_CNTL3__SYMCLKC_G_TMDS_GATE_DIS_MASK                                                           0x00001000L
+#define DIO_CLK_CNTL3__SYMCLKD_G_TMDS_GATE_DIS_MASK                                                           0x00002000L
+#define DIO_CLK_CNTL3__SYMCLKE_G_TMDS_GATE_DIS_MASK                                                           0x00004000L
+#define DIO_CLK_CNTL3__SYMCLKF_G_TMDS_GATE_DIS_MASK                                                           0x00008000L
+#define DIO_CLK_CNTL3__SYMCLKG_G_TMDS_GATE_DIS_MASK                                                           0x00010000L
+//DIO_HDMI_RXSTATUS_TIMER_CONTROL
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT                                0x0
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT                                  0x4
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT                                0x8
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT                                  0xc
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT                              0x10
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK                                  0x00000001L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK                                    0x00000010L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK                                  0x00000100L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK                                    0x00001000L
+#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK                                0x0FFF0000L
+//DIO_GENERIC_INTERRUPT_MESSAGE
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS__SHIFT                                    0x0
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE__SHIFT                                   0x1
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_STATUS_MASK                                      0x00000001L
+#define DIO_GENERIC_INTERRUPT_MESSAGE__DIO_GENERIC_INTERRUPT_MESSAGE_MASK                                     0xFFFFFFFEL
+//DIO_GENERIC_INTERRUPT_CLEAR
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR__SHIFT                                       0x0
+#define DIO_GENERIC_INTERRUPT_CLEAR__DIO_GENERIC_INTERRUPT_CLEAR_MASK                                         0x00000001L
+//DIO_LINKA_CNTL
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKA_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKA_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKA_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKB_CNTL
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKB_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKB_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKB_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKC_CNTL
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKC_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKC_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKC_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKD_CNTL
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKD_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKD_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKD_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKE_CNTL
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKE_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKE_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKE_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+//DIO_LINKF_CNTL
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL__SHIFT                                                                   0x0
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL__SHIFT                                                               0x4
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL__SHIFT                                                                 0x8
+#define DIO_LINKF_CNTL__ENC_TYPE_SEL_MASK                                                                     0x00000003L
+#define DIO_LINKF_CNTL__HPO_HDMI_ENC_SEL_MASK                                                                 0x00000070L
+#define DIO_LINKF_CNTL__HPO_DP_ENC_SEL_MASK                                                                   0x00000700L
+
+
+// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON18_PERFCOUNTER_CNTL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_CNTL2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON18_PERFCOUNTER_STATE
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON18_PERFMON_CNTL
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON18_PERFMON_CNTL2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON18_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON18_PERFMON_CVALUE_LOW
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON18_PERFMON_HI
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON18_PERFMON_LOW
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE__SHIFT                                                 0x4
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE__SHIFT                                                 0x5
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE__SHIFT                                                 0x6
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE__SHIFT                                                 0x7
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE__SHIFT                                                 0x8
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE__SHIFT                                                 0x9
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE_MASK                                                   0x00000010L
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE_MASK                                                   0x00000020L
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE_MASK                                                   0x00000040L
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE_MASK                                                   0x00000080L
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE_MASK                                                   0x00000100L
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE_MASK                                                   0x00000200L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dce_dc_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_PWRSEQ1_EN
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_pwrseq0_dispdec_pwrseq_dispdec
+//PWRSEQ0_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ0_PANEL_PWRSEQ_CNTL
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ0_PANEL_PWRSEQ_STATE
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ0_BL_PWM_CNTL
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ0_BL_PWM_CNTL2
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ0_BL_PWM_PERIOD_CNTL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ0_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ0_PWRSEQ_SPARE
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_pwrseq1_dispdec_pwrseq_dispdec
+//PWRSEQ1_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ1_PANEL_PWRSEQ_CNTL
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ1_PANEL_PWRSEQ_STATE
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ1_BL_PWM_CNTL
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ1_BL_PWM_CNTL2
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ1_BL_PWM_PERIOD_CNTL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ1_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ1_PWRSEQ_SPARE
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
+//DSCC0_DSCC_CONFIG0
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT                                                   0x0
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK                                                     0x0000000FL
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC0_DSCC_CONFIG1
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC0_DSCC_STATUS
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC0_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC0_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC0_DSCC_PPS_CONFIG0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG1
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG2
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG3
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG4
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG5
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG6
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC0_DSCC_PPS_CONFIG7
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG8
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG9
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC0_DSCC_PPS_CONFIG11
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC0_DSCC_PPS_CONFIG12
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG13
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG14
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC0_DSCC_PPS_CONFIG15
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG16
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG17
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG18
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG19
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG20
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG21
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC0_DSCC_PPS_CONFIG22
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC0_DSCC_MEM_POWER_CONTROL
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC0_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC0_DSCC_MAX_ABS_ERROR0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC0_DSCC_MAX_ABS_ERROR1
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
+//DSCCIF0_DSCCIF_CONFIG0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF0_DSCCIF_CONFIG1
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF0_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
+//DSC_TOP0_DSC_TOP_CONTROL
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP0_DSC_DEBUG_CONTROL
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON19_PERFCOUNTER_CNTL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_CNTL2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON19_PERFCOUNTER_STATE
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON19_PERFMON_CNTL
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON19_PERFMON_CNTL2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON19_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON19_PERFMON_CVALUE_LOW
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON19_PERFMON_HI
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON19_PERFMON_LOW
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
+//DSCC1_DSCC_CONFIG0
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC1_DSCC_CONFIG1
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC1_DSCC_STATUS
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC1_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC1_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC1_DSCC_PPS_CONFIG0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG1
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG2
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG3
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG4
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG5
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG6
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC1_DSCC_PPS_CONFIG7
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG8
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG9
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC1_DSCC_PPS_CONFIG11
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC1_DSCC_PPS_CONFIG12
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG13
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG14
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC1_DSCC_PPS_CONFIG15
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG16
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG17
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG18
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG19
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG20
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG21
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC1_DSCC_PPS_CONFIG22
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC1_DSCC_MEM_POWER_CONTROL
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC1_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC1_DSCC_MAX_ABS_ERROR0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC1_DSCC_MAX_ABS_ERROR1
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
+//DSCCIF1_DSCCIF_CONFIG0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF1_DSCCIF_CONFIG1
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF1_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
+//DSC_TOP1_DSC_TOP_CONTROL
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP1_DSC_DEBUG_CONTROL
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON20_PERFCOUNTER_CNTL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_CNTL2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON20_PERFCOUNTER_STATE
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON20_PERFMON_CNTL
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON20_PERFMON_CNTL2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON20_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON20_PERFMON_CVALUE_LOW
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON20_PERFMON_HI
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON20_PERFMON_LOW
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
+//DSCC2_DSCC_CONFIG0
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT                                                  0x4
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT                                                  0x8
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT                                     0x10
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK                                                    0x00000030L
+#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK                                                    0x00000100L
+#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK                                       0xFFFF0000L
+//DSCC2_DSCC_CONFIG1
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT                                        0x0
+#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK                                          0x0003FFFFL
+//DSCC2_DSCC_STATUS
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x0
+#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x00000001L
+//DSCC2_DSCC_INTERRUPT_CONTROL_STATUS
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED__SHIFT                       0x0
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED__SHIFT                       0x1
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED__SHIFT                       0x2
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED__SHIFT                       0x3
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED__SHIFT                      0x4
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED__SHIFT                      0x5
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED__SHIFT                      0x6
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED__SHIFT                      0x7
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED__SHIFT         0x8
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED__SHIFT         0x9
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED__SHIFT         0xa
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED__SHIFT         0xb
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x10
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x11
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x12
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN__SHIFT                0x13
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x14
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x15
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x16
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN__SHIFT               0x17
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x18
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x19
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1a
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN__SHIFT  0x1b
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_MASK                         0x00000001L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_MASK                         0x00000002L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_MASK                         0x00000004L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_MASK                         0x00000008L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_MASK                        0x00000010L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_MASK                        0x00000020L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_MASK                        0x00000040L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_MASK                        0x00000080L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_MASK           0x00000100L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_MASK           0x00000200L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_MASK           0x00000400L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_MASK           0x00000800L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00010000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00020000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00040000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN_MASK                  0x00080000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00100000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00200000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00400000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN_MASK                 0x00800000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN_MASK    0x01000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN_MASK    0x02000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN_MASK    0x04000000L
+#define DSCC2_DSCC_INTERRUPT_CONTROL_STATUS__DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN_MASK    0x08000000L
+//DSCC2_DSCC_PPS_CONFIG0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT                                                      0x0
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT                                                      0x4
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT                                                         0x8
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT                                                          0x18
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x1c
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK                                                        0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK                                                        0x000000F0L
+#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK                                                           0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK                                                            0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG1
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT                                                             0xa
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT                                                             0xb
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT                                                            0xc
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT                                                      0xd
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT                                                             0xe
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT                                                             0xf
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK                                                           0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK                                                               0x00000400L
+#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK                                                               0x00000800L
+#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK                                                              0x00001000L
+#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK                                                        0x00002000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK                                                               0x00004000L
+#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK                                                               0x00008000L
+#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG2
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG3
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT                                                            0x0
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK                                                              0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG4
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT                                                     0x0
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT                                                      0x10
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK                                                       0x000003FFL
+#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK                                                        0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG5
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT                                                    0x0
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT                                               0x10
+#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK                                                      0x0000003FL
+#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK                                                 0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG6
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT                                               0x0
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT                                                 0x18
+#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK                                                 0x00000FFFL
+#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK                                                   0x1F000000L
+//DSCC2_DSCC_PPS_CONFIG7
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK                                                         0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG8
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT                                                 0x10
+#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK                                                   0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG9
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT                                                           0x10
+#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK                                                           0x0000FFFFL
+#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK                                                             0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK                                                         0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK                                                         0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK                                                           0xFFFF0000L
+//DSCC2_DSCC_PPS_CONFIG11
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT                                                  0x8
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT                                                  0x10
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT                                                      0x18
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT                                                      0x1c
+#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK                                                          0x0000000FL
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK                                                    0x00001F00L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK                                                    0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK                                                        0x0F000000L
+#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK                                                        0xF0000000L
+//DSCC2_DSCC_PPS_CONFIG12
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG13
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT                                                        0x18
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK                                                          0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK                                                          0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG14
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT                                                        0x8
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT                                                       0x10
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT                                                       0x18
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK                                                          0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK                                                          0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK                                                         0x00FF0000L
+#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK                                                         0xFF000000L
+//DSCC2_DSCC_PPS_CONFIG15
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT                                                       0x0
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT                                                       0x8
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK                                                         0x000000FFL
+#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK                                                         0x0000FF00L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG16
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG17
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG18
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG19
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT                                                         0x10
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT                                                         0x15
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT                                                     0x1a
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK                                                           0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK                                                           0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK                                                       0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG20
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT                                                         0x0
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT                                                         0x5
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT                                                     0xa
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK                                                           0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK                                                           0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK                                                       0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG21
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK                                                      0xFC000000L
+//DSCC2_DSCC_PPS_CONFIG22
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT                                                        0x0
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT                                                        0x5
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT                                                    0xa
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT                                                        0x10
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT                                                        0x15
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT                                                    0x1a
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK                                                          0x0000001FL
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK                                                          0x000003E0L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK                                                      0x0000FC00L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK                                                          0x001F0000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK                                                          0x03E00000L
+#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK                                                      0xFC000000L
+//DSCC2_DSCC_MEM_POWER_CONTROL
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                 0x0
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE__SHIFT                                               0x4
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS__SHIFT                                                 0x8
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE__SHIFT                                               0x10
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE__SHIFT                                    0x14
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS__SHIFT                                      0x18
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE__SHIFT                                    0x1c
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK                                   0x00000003L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_FORCE_MASK                                                 0x00000030L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_DIS_MASK                                                   0x00000100L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_MEM_PWR_STATE_MASK                                                 0x00030000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_FORCE_MASK                                      0x00300000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_DIS_MASK                                        0x01000000L
+#define DSCC2_DSCC_MEM_POWER_CONTROL__DSCC_NATIVE_422_MEM_PWR_STATE_MASK                                      0x30000000L
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT                               0x0
+#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK                                 0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT                             0x0
+#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK                               0xFFFFFFFFL
+//DSCC2_DSCC_MAX_ABS_ERROR0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT                                              0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT                                             0x10
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK                                                0x0000FFFFL
+#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK                                               0xFFFF0000L
+//DSCC2_DSCC_MAX_ABS_ERROR1
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT                                             0x0
+#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK                                               0x0000FFFFL
+//DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT               0x0
+#define DSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_MASK                 0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
+#define DSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
+//DSCCIF2_DSCCIF_CONFIG0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN__SHIFT                                  0x0
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN__SHIFT                              0x4
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS__SHIFT                              0x8
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT                                                     0xc
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT                                                     0x10
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT                                       0x18
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN_MASK                                    0x00000001L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN_MASK                                0x00000010L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS_MASK                                0x00000100L
+#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK                                                       0x00007000L
+#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK                                                       0x000F0000L
+#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK                                         0x01000000L
+//DSCCIF2_DSCCIF_CONFIG1
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH__SHIFT                                                              0x0
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT__SHIFT                                                             0x10
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_WIDTH_MASK                                                                0x0000FFFFL
+#define DSCCIF2_DSCCIF_CONFIG1__PIC_HEIGHT_MASK                                                               0xFFFF0000L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
+//DSC_TOP2_DSC_TOP_CONTROL
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT                                               0x4
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT                                                0x8
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK                                                 0x00000010L
+#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
+//DSC_TOP2_DSC_DEBUG_CONTROL
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
+
+
+// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON21_PERFCOUNTER_CNTL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_CNTL2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON21_PERFCOUNTER_STATE
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON21_PERFMON_CNTL
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON21_PERFMON_CNTL2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON21_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON21_PERFMON_CVALUE_LOW
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON21_PERFMON_HI
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON21_PERFMON_LOW
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_hpo_top_dispdec
+//HPO_TOP_CLOCK_CONTROL
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT                                                  0x0
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT                                                    0x1
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT                                                   0x4
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT                                                     0x5
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT                                            0x8
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT                                            0x9
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT                                              0xc
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT                                              0xd
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT                                              0x10
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT                                              0x11
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT                                              0x12
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT                                              0x13
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT                                              0x14
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT                                              0x15
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT                                                        0x18
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK                                                    0x00000001L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK                                                      0x00000002L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK                                                     0x00000010L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK                                                       0x00000020L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK                                              0x00000100L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK                                              0x00000200L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK                                                0x00001000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK                                                0x00002000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK                                                0x00010000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK                                                0x00020000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK                                                0x00040000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK                                                0x00080000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK                                                0x00100000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK                                                0x00200000L
+#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK                                                          0x7F000000L
+//HPO_TOP_HW_CONTROL
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT                                                                  0x0
+#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK                                                                    0x00000001L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec
+//DP_STREAM_MAPPER_CONTROL0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL1
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL2
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+//DP_STREAM_MAPPER_CONTROL3
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT                                               0x0
+#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK                                                 0x00000007L
+
+
+// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec
+//DC_PERFMON22_PERFCOUNTER_CNTL
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT                                           0x0
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT                                          0x9
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT                                            0xc
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT                                         0xf
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT                                          0x10
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT                                    0x16
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT                                          0x17
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT                                              0x18
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT                                            0x19
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT                                              0x1a
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT                                            0x1d
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK                                             0x000001FFL
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK                                            0x00000E00L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK                                              0x00007000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK                                           0x00008000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK                                            0x00010000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK                                      0x00400000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK                                            0x00800000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK                                                0x01000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK                                              0x02000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK                                                0x04000000L
+#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK                                              0xE0000000L
+//DC_PERFMON22_PERFCOUNTER_CNTL2
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT                                 0x0
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT                                       0x2
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT                                       0x3
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT                                         0x8
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT                                          0x1d
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK                                   0x00000003L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK                                         0x00000004L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK                                         0x00000008L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK                                           0x00003F00L
+#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK                                            0xE0000000L
+//DC_PERFMON22_PERFCOUNTER_STATE
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT                                         0x0
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT                                         0x2
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT                                         0x4
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT                                         0x6
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT                                         0x8
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT                                         0xa
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT                                         0xc
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT                                         0xe
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT                                         0x10
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT                                         0x12
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT                                         0x14
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT                                         0x16
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT                                         0x18
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT                                         0x1a
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT                                         0x1c
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT                                         0x1e
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK                                           0x00000003L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK                                           0x00000004L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK                                           0x00000030L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK                                           0x00000040L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK                                           0x00000300L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK                                           0x00000400L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK                                           0x00003000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK                                           0x00004000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK                                           0x00030000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK                                           0x00040000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK                                           0x00300000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK                                           0x00400000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK                                           0x03000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK                                           0x04000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK                                           0x30000000L
+#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK                                           0x40000000L
+//DC_PERFMON22_PERFMON_CNTL
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                       0x0
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT                                                   0x8
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT                                               0x1c
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT                                               0x1d
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT                                           0x1e
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT                                              0x1f
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK                                                         0x00000003L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK                                                     0x0FFFFF00L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK                                                 0x10000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK                                                 0x20000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK                                             0x40000000L
+#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK                                                0x80000000L
+//DC_PERFMON22_PERFMON_CNTL2
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT                                            0x0
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT                                                 0x1
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT                                       0x2
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT                                        0xa
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK                                              0x00000001L
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK                                                   0x00000002L
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK                                         0x000003FCL
+#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK                                          0x0003FC00L
+//DC_PERFMON22_PERFMON_CVALUE_INT_MISC
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT                                  0x0
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT                                  0x1
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT                                  0x2
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT                                  0x3
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT                                  0x4
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT                                  0x5
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT                                  0x6
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT                                  0x7
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT                                     0x8
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT                                     0x9
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT                                     0xa
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT                                     0xb
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT                                     0xc
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT                                     0xd
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT                                     0xe
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT                                     0xf
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT                                        0x10
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK                                    0x00000001L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK                                    0x00000002L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK                                    0x00000004L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK                                    0x00000008L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK                                    0x00000010L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK                                    0x00000020L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK                                    0x00000040L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK                                    0x00000080L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK                                       0x00000100L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK                                       0x00000200L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK                                       0x00000400L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK                                       0x00000800L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK                                       0x00001000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK                                       0x00002000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK                                       0x00004000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK                                       0x00008000L
+#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK                                          0xFFFF0000L
+//DC_PERFMON22_PERFMON_CVALUE_LOW
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT                                            0x0
+#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK                                              0xFFFFFFFFL
+//DC_PERFMON22_PERFMON_HI
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT                                                            0x0
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT                                                      0x1d
+#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK                                                              0x0000FFFFL
+#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK                                                        0xE0000000L
+//DC_PERFMON22_PERFMON_LOW
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT                                                          0x0
+#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_afmt_afmt_dispdec
+//AFMT5_AFMT_VBI_PACKET_CONTROL
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE__SHIFT                                0x10
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT                                0x18
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_PACKETS_PER_LINE_MASK                                  0x001F0000L
+#define AFMT5_AFMT_VBI_PACKET_CONTROL__AFMT_HDMI_AUDIO_SEND_MAX_PACKETS_MASK                                  0x01000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL2
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT                                       0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT                                     0x1
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT                                    0x8
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT                                      0x10
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT                                         0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT                                          0x1c
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK                                         0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK                                       0x00000002L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK                                      0x0000FF00L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK                                        0x00FF0000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK                                           0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK                                            0x10000000L
+//AFMT5_AFMT_AUDIO_INFO0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT                                                     0x8
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT                                                     0xb
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT                                        0x10
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT                                                    0x18
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK                                                 0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK                                                       0x00000700L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK                                                       0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK                                          0x00FF0000L
+#define AFMT5_AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK                                                      0x1F000000L
+//AFMT5_AFMT_AUDIO_INFO1
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT                                                     0x0
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT                                                    0xb
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT                                                 0xf
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT                                                 0x10
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK                                                       0x000000FFL
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK                                                      0x00007800L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK                                                   0x00008000L
+#define AFMT5_AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK                                                   0x00030000L
+//AFMT5_AFMT_60958_0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A__SHIFT                                                            0x0
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B__SHIFT                                                            0x1
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C__SHIFT                                                            0x2
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D__SHIFT                                                            0x3
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT                                                         0x6
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT                                                0x8
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT                                                0x10
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT                                           0x18
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT                                               0x1c
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_A_MASK                                                              0x00000001L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_B_MASK                                                              0x00000002L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_C_MASK                                                              0x00000004L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_D_MASK                                                              0x00000038L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_MODE_MASK                                                           0x000000C0L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK                                                  0x0000FF00L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK                                                  0x000F0000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK                                               0x00F00000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK                                             0x0F000000L
+#define AFMT5_AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK                                                 0x30000000L
+//AFMT5_AFMT_60958_1
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT                                                  0x0
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT                                  0x4
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L__SHIFT                                                         0x10
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R__SHIFT                                                         0x12
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK                                                    0x0000000FL
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK                                    0x000000F0L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_L_MASK                                                           0x00010000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_VALID_R_MASK                                                           0x00040000L
+#define AFMT5_AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_CONTROL
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT                                                0x0
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT                                              0x4
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT                                            0x8
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT                                             0x10
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK                                                  0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK                                                0x00000010L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK                                              0x00000100L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK                                              0x0000F000L
+#define AFMT5_AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK                                               0xFFFF0000L
+//AFMT5_AFMT_RAMP_CONTROL0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT                                                  0x1f
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK                                                    0x80000000L
+//AFMT5_AFMT_RAMP_CONTROL1
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT                                           0x18
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK                                                    0x00FFFFFFL
+#define AFMT5_AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK                                             0xFF000000L
+//AFMT5_AFMT_RAMP_CONTROL2
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_RAMP_CONTROL3
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT                                                  0x0
+#define AFMT5_AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK                                                    0x00FFFFFFL
+//AFMT5_AFMT_60958_2
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT                                             0x0
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT                                             0x4
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT                                             0x8
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT                                             0xc
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT                                             0x10
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT                                             0x14
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK                                               0x0000000FL
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK                                               0x000000F0L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK                                               0x00000F00L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK                                               0x0000F000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK                                               0x000F0000L
+#define AFMT5_AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK                                               0x00F00000L
+//AFMT5_AFMT_AUDIO_CRC_RESULT
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT                                               0x0
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT                                                    0x8
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK                                                 0x00000001L
+#define AFMT5_AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK                                                      0xFFFFFF00L
+//AFMT5_AFMT_STATUS
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT                                                           0x4
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT                                                          0x8
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT                                                    0x18
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT                                                    0x1e
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK                                                             0x00000010L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK                                                            0x00000100L
+#define AFMT5_AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK                                                      0x01000000L
+#define AFMT5_AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK                                                      0x40000000L
+//AFMT5_AFMT_AUDIO_PACKET_CONTROL
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT                                        0x0
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE__SHIFT                   0x4
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT                                0xb
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT                                            0xc
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT                                          0xe
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT                                  0x17
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT                                       0x18
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT                                          0x1a
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT                                  0x1e
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK                                          0x00000001L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_DOUBLE_BUFFER_ENABLE_MASK                     0x00000010L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK                                  0x00000800L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK                                              0x00001000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK                                            0x00004000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK                                    0x00800000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK                                         0x01000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK                                            0x04000000L
+#define AFMT5_AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK                                    0x40000000L
+//AFMT5_AFMT_INFOFRAME_CONTROL0
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT                                          0x6
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT                                          0x7
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK                                            0x00000040L
+#define AFMT5_AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK                                            0x00000080L
+//AFMT5_AFMT_INTERRUPT_STATUS
+//AFMT5_AFMT_AUDIO_SRC_CONTROL
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT                                            0x0
+#define AFMT5_AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK                                              0x00000007L
+//AFMT5_AFMT_MEM_PWR
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS__SHIFT                                                           0x0
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE__SHIFT                                                         0x4
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE__SHIFT                                                         0x8
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_DIS_MASK                                                             0x00000001L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_FORCE_MASK                                                           0x00000030L
+#define AFMT5_AFMT_MEM_PWR__AFMT_MEM_PWR_STATE_MASK                                                           0x00000300L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec
+//DME5_DME_CONTROL
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME5_DME_MEMORY_CONTROL
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec
+//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG5_VPG_GENERIC_PACKET_DATA
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG5_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG5_VPG_GENERIC_STATUS
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG5_VPG_MEM_PWR
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG5_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG5_VPG_ISRC1_2_DATA
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG5_VPG_MPEG_INFO0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG5_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG5_VPG_MPEG_INFO1
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG5_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec
+//APG0_APG_CONTROL
+#define APG0_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG0_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG0_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG0_APG_CONTROL2
+#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG0_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG0_APG_DBG_GEN_CONTROL
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT                                                   0x0
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT                                                    0x1
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT                                         0x8
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT                                        0x18
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK                                                     0x00000001L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK                                                      0x00000002L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK                                           0x0000FF00L
+#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK                                          0xFF000000L
+//APG0_APG_PACKET_CONTROL
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG0_APG_AUDIO_CRC_CONTROL
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG0_APG_AUDIO_CRC_CONTROL2
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG0_APG_AUDIO_CRC_RESULT
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG0_APG_STATUS
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG0_APG_STATUS2
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG0_APG_MEM_PWR
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG0_APG_SPARE
+#define APG0_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG0_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec
+//DME6_DME_CONTROL
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME6_DME_MEMORY_CONTROL
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec
+//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG6_VPG_GENERIC_PACKET_DATA
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG6_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG6_VPG_GENERIC_STATUS
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG6_VPG_MEM_PWR
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG6_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG6_VPG_ISRC1_2_DATA
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG6_VPG_MPEG_INFO0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG6_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG6_VPG_MPEG_INFO1
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG6_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec
+//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec
+//APG1_APG_CONTROL
+#define APG1_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG1_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG1_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG1_APG_CONTROL2
+#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG1_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG1_APG_PACKET_CONTROL
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG1_APG_AUDIO_CRC_CONTROL
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG1_APG_AUDIO_CRC_CONTROL2
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG1_APG_AUDIO_CRC_RESULT
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG1_APG_STATUS
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG1_APG_STATUS2
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG1_APG_MEM_PWR
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG1_APG_SPARE
+#define APG1_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG1_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec
+//DME7_DME_CONTROL
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME7_DME_MEMORY_CONTROL
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec
+//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG7_VPG_GENERIC_PACKET_DATA
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG7_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG7_VPG_GENERIC_STATUS
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG7_VPG_MEM_PWR
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG7_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG7_VPG_ISRC1_2_DATA
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG7_VPG_MPEG_INFO0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG7_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG7_VPG_MPEG_INFO1
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG7_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec
+//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec
+//APG2_APG_CONTROL
+#define APG2_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG2_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG2_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG2_APG_CONTROL2
+#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG2_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG2_APG_PACKET_CONTROL
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG2_APG_AUDIO_CRC_CONTROL
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG2_APG_AUDIO_CRC_CONTROL2
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG2_APG_AUDIO_CRC_RESULT
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG2_APG_STATUS
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG2_APG_STATUS2
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG2_APG_MEM_PWR
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG2_APG_SPARE
+#define APG2_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG2_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec
+//DME8_DME_CONTROL
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME8_DME_MEMORY_CONTROL
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec
+//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG8_VPG_GENERIC_PACKET_DATA
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG8_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG8_VPG_GENERIC_STATUS
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG8_VPG_MEM_PWR
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG8_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG8_VPG_ISRC1_2_DATA
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG8_VPG_MPEG_INFO0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG8_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG8_VPG_MPEG_INFO1
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG8_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec
+//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT                             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT                     0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK__SHIFT                      0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT                 0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT                    0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK                               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK                       0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SOCCLK_MASK                        0x00000100L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK                   0x00001000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK                      0x00010000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK  0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT    0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK      0x00000007L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT             0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT              0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT   0x8
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT     0x10
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT         0x14
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT              0x1c
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK               0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK                0x00000010L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK     0x00001F00L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK       0x00010000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK           0x00100000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK  0x01000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK                0x30000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT  0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT  0x1
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT  0x2
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT    0x4
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT      0xc
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT  0x18
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT         0x1f
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK  0x00000001L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK  0x00000002L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK  0x00000004L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK      0x000003F0L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK        0x0000F000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK    0x3F000000L
+#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK           0x80000000L
+//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT                                        0x0
+#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK                                          0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec
+//APG3_APG_CONTROL
+#define APG3_APG_CONTROL__APG_RESET__SHIFT                                                                    0x1
+#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT                                                               0x2
+#define APG3_APG_CONTROL__APG_RESET_MASK                                                                      0x00000002L
+#define APG3_APG_CONTROL__APG_RESET_DONE_MASK                                                                 0x00000004L
+//APG3_APG_CONTROL2
+#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT                                                                  0x0
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT                                                      0x8
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT                                           0x18
+#define APG3_APG_CONTROL2__APG_ENABLE_MASK                                                                    0x00000001L
+#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK                                                        0x0000FF00L
+#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK                                             0x01000000L
+//APG3_APG_PACKET_CONTROL
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT                                                 0x2
+#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK                                                   0x00000004L
+//APG3_APG_AUDIO_CRC_CONTROL
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT                                                   0x0
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT                                                 0x4
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT                                               0xd
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT                                                0x10
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK                                                     0x00000001L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK                                                   0x00000010L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK                                                 0x0000E000L
+#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK                                                  0xFFFF0000L
+//APG3_APG_AUDIO_CRC_CONTROL2
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT                                 0x0
+#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK                                   0x0000FFFFL
+//APG3_APG_AUDIO_CRC_RESULT
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT                                                  0x0
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT                                            0x8
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT                                                       0x10
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK                                                    0x00000001L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK                                              0x00000100L
+#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK                                                         0xFFFF0000L
+//APG3_APG_STATUS
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT                                                              0x4
+#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT                                                                0x8
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT                                                0x18
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT                                          0x19
+#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK                                                                0x00000010L
+#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK                                                                  0x00000100L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK                                                  0x01000000L
+#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK                                            0x02000000L
+//APG3_APG_STATUS2
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT                                                            0x0
+#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK                                                              0x00000001L
+//APG3_APG_MEM_PWR
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT                                                              0x0
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT                                                            0x4
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT                                                            0x8
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT                                              0xc
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK                                                                0x00000001L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK                                                              0x00000030L
+#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK                                                              0x00000300L
+#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK                                                0x00003000L
+//APG3_APG_SPARE
+#define APG3_APG_SPARE__APG_SPARE__SHIFT                                                                      0x0
+#define APG3_APG_SPARE__APG_SPARE_MASK                                                                        0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec
+//DME9_DME_CONTROL
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT                                                   0x0
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT                                                           0x4
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT                                                         0x8
+#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT                                                          0xc
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT                                                            0xd
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT                                                        0x10
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT                                                          0x14
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT                                                 0x18
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT                                             0x19
+#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK                                                     0x00000007L
+#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK                                                             0x00000010L
+#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK                                                           0x00000100L
+#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK                                                            0x00001000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK                                                              0x00002000L
+#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK                                                          0x00010000L
+#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK                                                            0x00100000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK                                                   0x01000000L
+#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK                                               0x02000000L
+//DME9_DME_MEMORY_CONTROL
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT                                                     0x0
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT                                                       0x4
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT                                                     0x8
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT                                   0xc
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK                                                       0x00000003L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK                                                         0x00000010L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK                                                       0x00000300L
+#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK                                     0x00003000L
+
+
+// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec
+//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT                                    0x0
+#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK                                      0x000000FFL
+//VPG9_VPG_GENERIC_PACKET_DATA
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT                                           0x0
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT                                           0x8
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT                                           0x10
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT                                           0x18
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK                                             0x000000FFL
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK                                             0x0000FF00L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK                                             0x00FF0000L
+#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK                                             0xFF000000L
+//VPG9_VPG_GSP_FRAME_UPDATE_CTRL
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT                                      0x0
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT                                      0x1
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT                                      0x2
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT                                      0x3
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT                                      0x4
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT                                      0x5
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT                                      0x6
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT                                      0x7
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT                                      0x8
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT                                      0x9
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT                                     0xa
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT                                     0xb
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT                                     0xc
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT                                     0xd
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT                                     0xe
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT                              0x10
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT                              0x11
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT                              0x12
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT                              0x13
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT                              0x14
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT                              0x15
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT                              0x16
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT                              0x17
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT                              0x18
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT                              0x19
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT                             0x1a
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT                             0x1b
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT                             0x1c
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT                             0x1d
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT                             0x1e
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK                                        0x00000001L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK                                        0x00000002L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK                                        0x00000004L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK                                        0x00000008L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK                                        0x00000010L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK                                        0x00000020L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK                                        0x00000040L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK                                        0x00000080L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK                                        0x00000100L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK                                        0x00000200L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK                                       0x00000400L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK                                       0x00000800L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK                                       0x00001000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK                                       0x00002000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK                                       0x00004000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK                                0x00010000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK                                0x00020000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK                                0x00040000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK                                0x00080000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK                                0x00100000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK                                0x00200000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK                                0x00400000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK                                0x00800000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK                                0x01000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK                                0x02000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK                               0x04000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK                               0x08000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK                               0x10000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK                               0x20000000L
+#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK                               0x40000000L
+//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT                              0x0
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT                              0x1
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT                              0x2
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT                              0x3
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT                              0x4
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT                              0x5
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT                              0x6
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT                              0x7
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT                              0x8
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT                              0x9
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT                             0xa
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT                             0xb
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT                             0xc
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT                             0xd
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT                             0xe
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x10
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x11
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x12
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x13
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x14
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x15
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x16
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x17
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x18
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT                      0x19
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1a
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1b
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1c
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1d
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT                     0x1e
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK                                0x00000001L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK                                0x00000002L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK                                0x00000004L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK                                0x00000008L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK                                0x00000010L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK                                0x00000020L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK                                0x00000040L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK                                0x00000080L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK                                0x00000100L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK                                0x00000200L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK                               0x00000400L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK                               0x00000800L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK                               0x00001000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK                               0x00002000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK                               0x00004000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK                        0x00010000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK                        0x00020000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK                        0x00040000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK                        0x00080000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK                        0x00100000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK                        0x00200000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK                        0x00400000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK                        0x00800000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK                        0x01000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK                        0x02000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK                       0x04000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK                       0x08000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK                       0x10000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK                       0x20000000L
+#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK                       0x40000000L
+//VPG9_VPG_GENERIC_STATUS
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT                                               0x0
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT                                          0x1
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT                                              0x4
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK                                                 0x00000001L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK                                            0x00000002L
+#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK                                                0x00000010L
+//VPG9_VPG_MEM_PWR
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT                                                  0x0
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT                                                    0x4
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT                                                        0x8
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK                                                    0x00000001L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK                                                      0x00000010L
+#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK                                                          0x00000100L
+//VPG9_VPG_ISRC1_2_ACCESS_CTRL
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT                                           0x0
+#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK                                             0x0000000FL
+//VPG9_VPG_ISRC1_2_DATA
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT                                                     0x0
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT                                                     0x8
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT                                                     0x10
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT                                                     0x18
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK                                                       0x000000FFL
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK                                                       0x0000FF00L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK                                                       0x00FF0000L
+#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK                                                       0xFF000000L
+//VPG9_VPG_MPEG_INFO0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM__SHIFT                                                    0x0
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0__SHIFT                                                         0x8
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1__SHIFT                                                         0x10
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2__SHIFT                                                         0x18
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_CHECKSUM_MASK                                                      0x000000FFL
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB0_MASK                                                           0x0000FF00L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB1_MASK                                                           0x00FF0000L
+#define VPG9_VPG_MPEG_INFO0__VPG_MPEG_INFO_MB2_MASK                                                           0xFF000000L
+//VPG9_VPG_MPEG_INFO1
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3__SHIFT                                                         0x0
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF__SHIFT                                                          0x8
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR__SHIFT                                                          0xc
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE__SHIFT                                                      0x10
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MB3_MASK                                                           0x000000FFL
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_MF_MASK                                                            0x00000300L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_FR_MASK                                                            0x00001000L
+#define VPG9_VPG_MPEG_INFO1__VPG_MPEG_INFO_UPDATE_MASK                                                        0x00010000L
+
+
+// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec
+//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT                                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT                                    0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK                                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK                                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK                                      0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT                       0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT                   0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT              0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK                         0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK                          0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK                     0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK                0x00001000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT             0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT            0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK               0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK              0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT                       0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK                         0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK                        0x00000300L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT                                                  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK                                                    0xFFFFFFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK                           0x0000FFFFL
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT           0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                         0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                     0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT                                  0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT                                 0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                  0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT                         0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                      0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK             0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK                           0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                       0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK                                    0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK                                   0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                    0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK                           0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK                        0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT          0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT                        0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT                    0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT                         0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT                                 0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT                                0x7
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT         0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT                 0x9
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT                        0xa
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT                     0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK            0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK                          0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK                      0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK                           0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK                                   0x00000060L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK                                  0x00000080L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK           0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK                   0x00000200L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK                          0x00000400L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK                       0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT                                          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT                                       0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK                                            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK                                         0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT                                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT                                      0x1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT                                      0x2
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT                                      0x3
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT                                     0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT                                    0x5
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT                              0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT                                      0x1c
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT                               0x1d
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK                                        0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK                                        0x00000002L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK                                        0x00000004L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK                                        0x00000008L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK                                       0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK                                      0x00000020L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK                                0x00003F00L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK                                        0x10000000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK                                 0x20000000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT   0x14
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK                          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x000003F0L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK  0x0003F000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK     0x03F00000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT                 0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT          0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT          0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT  0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT  0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK                   0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK            0x00000010L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK            0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK    0x00001000L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK  0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT                   0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT                       0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK                     0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK                         0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT          0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK          0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK            0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT                               0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT                        0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT                               0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK                                 0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK                          0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK                                 0x00000100L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT  0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT  0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK  0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK  0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT                                         0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT                               0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK                                           0x00000001L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK                                 0x00000010L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT0_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT1_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2__SHIFT                                        0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3__SHIFT                                        0x10
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT2_MASK                                          0x0000FFFFL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT3_MASK                                          0xFFFF0000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK                                             0x00000001L
+//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT                      0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT                                    0x4
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT                                      0x8
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT                                    0xc
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK                        0x00000003L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK                                      0x00000030L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK                                        0x00000100L
+#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK                                      0x00003000L
+//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT                                           0x0
+#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK                                             0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec
+//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC0_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM320_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec
+//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT                                   0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT                          0x4
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK                                     0x00000001L
+#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK                            0x00000010L
+//DP_LINK_ENC1_DP_LINK_ENC_SPARE
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT                                              0x0
+#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK                                                0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT                                               0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT                                          0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT                                                     0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT                                                0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK                                                 0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK                                            0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK                                                       0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK                                                  0x00000300L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT                                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT                                              0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT                                              0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT                                       0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT                                        0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK                                                      0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK                                                0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK                                                0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK                                         0x00001000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK                                          0x00030000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK                                              0x00000003L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT                                   0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT                                   0x19
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK                                     0x01FFFFFFL
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK                                     0xFE000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT                                        0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT                                           0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK                                          0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK                                             0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT                                 0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT                                    0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK                                   0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK                                      0x00007F00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT                                           0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT                                           0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT                                             0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT                                           0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT                                             0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT                                           0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK                                               0x00000007L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK                                             0x00000070L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK                                               0x00000700L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK                                             0x00007000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK                                               0x00070000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK                                             0x00700000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK                                               0x07000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK                                             0x70000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK                                         0x7FFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT                                    0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK                                      0x000000FFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT                                             0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK                                               0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT                                            0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK                                              0x00FFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT                                          0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT                               0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT                                        0x3
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT                            0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT                               0x5
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT                             0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT                                    0x7
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK                                            0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK                                 0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK                                          0x00000008L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK                              0x00000010L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK                                 0x00000020L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK                               0x00000040L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK                                      0x00000080L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE__SHIFT                               0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE__SHIFT                                 0x2
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL__SHIFT                               0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE__SHIFT                               0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE__SHIFT                                 0xa
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL__SHIFT                               0xc
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE__SHIFT                               0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE__SHIFT                                 0x12
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL__SHIFT                               0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE__SHIFT                               0x18
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE__SHIFT                                 0x1a
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL__SHIFT                               0x1c
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_ENABLE_MASK                                 0x00000003L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_TYPE_MASK                                   0x00000004L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM0_OVR_SYMBOL_MASK                                 0x000000F0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_ENABLE_MASK                                 0x00000300L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_TYPE_MASK                                   0x00000400L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM1_OVR_SYMBOL_MASK                                 0x0000F000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_ENABLE_MASK                                 0x00030000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_TYPE_MASK                                   0x00040000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM2_OVR_SYMBOL_MASK                                 0x00F00000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_ENABLE_MASK                                 0x03000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_TYPE_MASK                                   0x04000000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_OVERRIDE__STREAM3_OVR_SYMBOL_MASK                                 0xF0000000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE__SHIFT                                           0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET__SHIFT                                            0x1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE__SHIFT                                      0x4
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE__SHIFT                                       0x6
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE__SHIFT                                 0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF__SHIFT                                      0x10
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT__SHIFT                                      0x11
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS__SHIFT                                  0x14
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT__SHIFT                                        0x15
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_ENABLE_MASK                                             0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_RESET_MASK                                              0x00000002L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_LANE_SOURCE_MASK                                        0x00000030L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_TAP_SOURCE_MASK                                         0x000000C0L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_SCHEDULER_SOURCE_MASK                                   0x00003F00L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_IGNORE_VCPF_MASK                                        0x00010000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_START_EVENT_MASK                                        0x000E0000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_USE_NUM_SYMBOLS_MASK                                    0x00100000L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG0__CRC_END_EVENT_MASK                                          0x00600000L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS__SHIFT                                      0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_CONFIG1__CRC_NUM_SYMBOLS_MASK                                        0xFFFFFFFFL
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE__SHIFT                                              0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE__SHIFT                                             0x8
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_DONE_MASK                                                0x00000001L
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_STATUS__CRC_VALUE_MASK                                               0x00FFFF00L
+//DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT__SHIFT                                       0x0
+#define DP_DPHY_SYM321_DP_DPHY_SYM32_CRC_COUNT__CRC_SYMBOL_COUNT_MASK                                         0xFFFFFFFFL
+
+
+// addressBlock: dce_dc_dchvm_hvm_dispdec
+//DCHVM_CTRL0
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT                                                                   0x0
+#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK                                                                     0x00000001L
+//DCHVM_CTRL1
+#define DCHVM_CTRL1__DUMMY1__SHIFT                                                                            0x0
+#define DCHVM_CTRL1__DUMMY1_MASK                                                                              0xFFFFFFFFL
+//DCHVM_CLK_CTRL
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT                                                         0x0
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT                                                         0x1
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT                                                          0x4
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT                                                          0x5
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT                                                          0x8
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT                                                         0xa
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK                                                           0x00000001L
+#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK                                                           0x00000002L
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK                                                            0x00000010L
+#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK                                                            0x00000020L
+#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK                                                            0x00000300L
+#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK                                                           0x00000C00L
+//DCHVM_MEM_CTRL
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT                                                       0x0
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT                                                         0x2
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT                                                      0x4
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK                                                         0x00000001L
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK                                                           0x0000000CL
+#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK                                                        0x00000030L
+//DCHVM_RIOMMU_CTRL0
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT                                                        0x0
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT                                                         0x1
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK                                                          0x00000001L
+#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK                                                           0x00000002L
+//DCHVM_RIOMMU_STAT0
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT                                                              0x0
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT                                                       0x1
+#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK                                                                0x00000001L
+#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK                                                         0x00000002L
+
+// addressBlock: vga_vgaseqind
+//SEQ00
+#define SEQ00__SEQ_RST0B__SHIFT                                                                               0x0
+#define SEQ00__SEQ_RST1B__SHIFT                                                                               0x1
+#define SEQ00__SEQ_RST0B_MASK                                                                                 0x01L
+#define SEQ00__SEQ_RST1B_MASK                                                                                 0x02L
+//SEQ01
+#define SEQ01__SEQ_DOT8__SHIFT                                                                                0x0
+#define SEQ01__SEQ_SHIFT2__SHIFT                                                                              0x2
+#define SEQ01__SEQ_PCLKBY2__SHIFT                                                                             0x3
+#define SEQ01__SEQ_SHIFT4__SHIFT                                                                              0x4
+#define SEQ01__SEQ_MAXBW__SHIFT                                                                               0x5
+#define SEQ01__SEQ_DOT8_MASK                                                                                  0x01L
+#define SEQ01__SEQ_SHIFT2_MASK                                                                                0x04L
+#define SEQ01__SEQ_PCLKBY2_MASK                                                                               0x08L
+#define SEQ01__SEQ_SHIFT4_MASK                                                                                0x10L
+#define SEQ01__SEQ_MAXBW_MASK                                                                                 0x20L
+//SEQ02
+#define SEQ02__SEQ_MAP0_EN__SHIFT                                                                             0x0
+#define SEQ02__SEQ_MAP1_EN__SHIFT                                                                             0x1
+#define SEQ02__SEQ_MAP2_EN__SHIFT                                                                             0x2
+#define SEQ02__SEQ_MAP3_EN__SHIFT                                                                             0x3
+#define SEQ02__SEQ_MAP0_EN_MASK                                                                               0x01L
+#define SEQ02__SEQ_MAP1_EN_MASK                                                                               0x02L
+#define SEQ02__SEQ_MAP2_EN_MASK                                                                               0x04L
+#define SEQ02__SEQ_MAP3_EN_MASK                                                                               0x08L
+//SEQ03
+#define SEQ03__SEQ_FONT_B1__SHIFT                                                                             0x0
+#define SEQ03__SEQ_FONT_B2__SHIFT                                                                             0x1
+#define SEQ03__SEQ_FONT_A1__SHIFT                                                                             0x2
+#define SEQ03__SEQ_FONT_A2__SHIFT                                                                             0x3
+#define SEQ03__SEQ_FONT_B0__SHIFT                                                                             0x4
+#define SEQ03__SEQ_FONT_A0__SHIFT                                                                             0x5
+#define SEQ03__SEQ_FONT_B1_MASK                                                                               0x01L
+#define SEQ03__SEQ_FONT_B2_MASK                                                                               0x02L
+#define SEQ03__SEQ_FONT_A1_MASK                                                                               0x04L
+#define SEQ03__SEQ_FONT_A2_MASK                                                                               0x08L
+#define SEQ03__SEQ_FONT_B0_MASK                                                                               0x10L
+#define SEQ03__SEQ_FONT_A0_MASK                                                                               0x20L
+//SEQ04
+#define SEQ04__SEQ_256K__SHIFT                                                                                0x1
+#define SEQ04__SEQ_ODDEVEN__SHIFT                                                                             0x2
+#define SEQ04__SEQ_CHAIN__SHIFT                                                                               0x3
+#define SEQ04__SEQ_256K_MASK                                                                                  0x02L
+#define SEQ04__SEQ_ODDEVEN_MASK                                                                               0x04L
+#define SEQ04__SEQ_CHAIN_MASK                                                                                 0x08L
+
+
+// addressBlock: vga_vgacrtind
+//CRT00
+#define CRT00__H_TOTAL__SHIFT                                                                                 0x0
+#define CRT00__H_TOTAL_MASK                                                                                   0xFFL
+//CRT01
+#define CRT01__H_DISP_END__SHIFT                                                                              0x0
+#define CRT01__H_DISP_END_MASK                                                                                0xFFL
+//CRT02
+#define CRT02__H_BLANK_START__SHIFT                                                                           0x0
+#define CRT02__H_BLANK_START_MASK                                                                             0xFFL
+//CRT03
+#define CRT03__H_BLANK_END__SHIFT                                                                             0x0
+#define CRT03__H_DE_SKEW__SHIFT                                                                               0x5
+#define CRT03__CR10CR11_R_DIS_B__SHIFT                                                                        0x7
+#define CRT03__H_BLANK_END_MASK                                                                               0x1FL
+#define CRT03__H_DE_SKEW_MASK                                                                                 0x60L
+#define CRT03__CR10CR11_R_DIS_B_MASK                                                                          0x80L
+//CRT04
+#define CRT04__H_SYNC_START__SHIFT                                                                            0x0
+#define CRT04__H_SYNC_START_MASK                                                                              0xFFL
+//CRT05
+#define CRT05__H_SYNC_END__SHIFT                                                                              0x0
+#define CRT05__H_SYNC_SKEW__SHIFT                                                                             0x5
+#define CRT05__H_BLANK_END_B5__SHIFT                                                                          0x7
+#define CRT05__H_SYNC_END_MASK                                                                                0x1FL
+#define CRT05__H_SYNC_SKEW_MASK                                                                               0x60L
+#define CRT05__H_BLANK_END_B5_MASK                                                                            0x80L
+//CRT06
+#define CRT06__V_TOTAL__SHIFT                                                                                 0x0
+#define CRT06__V_TOTAL_MASK                                                                                   0xFFL
+//CRT07
+#define CRT07__V_TOTAL_B8__SHIFT                                                                              0x0
+#define CRT07__V_DISP_END_B8__SHIFT                                                                           0x1
+#define CRT07__V_SYNC_START_B8__SHIFT                                                                         0x2
+#define CRT07__V_BLANK_START_B8__SHIFT                                                                        0x3
+#define CRT07__LINE_CMP_B8__SHIFT                                                                             0x4
+#define CRT07__V_TOTAL_B9__SHIFT                                                                              0x5
+#define CRT07__V_DISP_END_B9__SHIFT                                                                           0x6
+#define CRT07__V_SYNC_START_B9__SHIFT                                                                         0x7
+#define CRT07__V_TOTAL_B8_MASK                                                                                0x01L
+#define CRT07__V_DISP_END_B8_MASK                                                                             0x02L
+#define CRT07__V_SYNC_START_B8_MASK                                                                           0x04L
+#define CRT07__V_BLANK_START_B8_MASK                                                                          0x08L
+#define CRT07__LINE_CMP_B8_MASK                                                                               0x10L
+#define CRT07__V_TOTAL_B9_MASK                                                                                0x20L
+#define CRT07__V_DISP_END_B9_MASK                                                                             0x40L
+#define CRT07__V_SYNC_START_B9_MASK                                                                           0x80L
+//CRT08
+#define CRT08__ROW_SCAN_START__SHIFT                                                                          0x0
+#define CRT08__BYTE_PAN__SHIFT                                                                                0x5
+#define CRT08__ROW_SCAN_START_MASK                                                                            0x1FL
+#define CRT08__BYTE_PAN_MASK                                                                                  0x60L
+//CRT09
+#define CRT09__MAX_ROW_SCAN__SHIFT                                                                            0x0
+#define CRT09__V_BLANK_START_B9__SHIFT                                                                        0x5
+#define CRT09__LINE_CMP_B9__SHIFT                                                                             0x6
+#define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT                                                                      0x7
+#define CRT09__MAX_ROW_SCAN_MASK                                                                              0x1FL
+#define CRT09__V_BLANK_START_B9_MASK                                                                          0x20L
+#define CRT09__LINE_CMP_B9_MASK                                                                               0x40L
+#define CRT09__DOUBLE_CHAR_HEIGHT_MASK                                                                        0x80L
+//CRT0A
+#define CRT0A__CURSOR_START__SHIFT                                                                            0x0
+#define CRT0A__CURSOR_DISABLE__SHIFT                                                                          0x5
+#define CRT0A__CURSOR_START_MASK                                                                              0x1FL
+#define CRT0A__CURSOR_DISABLE_MASK                                                                            0x20L
+//CRT0B
+#define CRT0B__CURSOR_END__SHIFT                                                                              0x0
+#define CRT0B__CURSOR_SKEW__SHIFT                                                                             0x5
+#define CRT0B__CURSOR_END_MASK                                                                                0x1FL
+#define CRT0B__CURSOR_SKEW_MASK                                                                               0x60L
+//CRT0C
+#define CRT0C__DISP_START__SHIFT                                                                              0x0
+#define CRT0C__DISP_START_MASK                                                                                0xFFL
+//CRT0D
+#define CRT0D__DISP_START__SHIFT                                                                              0x0
+#define CRT0D__DISP_START_MASK                                                                                0xFFL
+//CRT0E
+#define CRT0E__CURSOR_LOC_HI__SHIFT                                                                           0x0
+#define CRT0E__CURSOR_LOC_HI_MASK                                                                             0xFFL
+//CRT0F
+#define CRT0F__CURSOR_LOC_LO__SHIFT                                                                           0x0
+#define CRT0F__CURSOR_LOC_LO_MASK                                                                             0xFFL
+//CRT10
+#define CRT10__V_SYNC_START__SHIFT                                                                            0x0
+#define CRT10__V_SYNC_START_MASK                                                                              0xFFL
+//CRT11
+#define CRT11__V_SYNC_END__SHIFT                                                                              0x0
+#define CRT11__V_INTR_CLR__SHIFT                                                                              0x4
+#define CRT11__V_INTR_EN__SHIFT                                                                               0x5
+#define CRT11__SEL5_REFRESH_CYC__SHIFT                                                                        0x6
+#define CRT11__C0T7_WR_ONLY__SHIFT                                                                            0x7
+#define CRT11__V_SYNC_END_MASK                                                                                0x0FL
+#define CRT11__V_INTR_CLR_MASK                                                                                0x10L
+#define CRT11__V_INTR_EN_MASK                                                                                 0x20L
+#define CRT11__SEL5_REFRESH_CYC_MASK                                                                          0x40L
+#define CRT11__C0T7_WR_ONLY_MASK                                                                              0x80L
+//CRT12
+#define CRT12__V_DISP_END__SHIFT                                                                              0x0
+#define CRT12__V_DISP_END_MASK                                                                                0xFFL
+//CRT13
+#define CRT13__DISP_PITCH__SHIFT                                                                              0x0
+#define CRT13__DISP_PITCH_MASK                                                                                0xFFL
+//CRT14
+#define CRT14__UNDRLN_LOC__SHIFT                                                                              0x0
+#define CRT14__ADDR_CNT_BY4__SHIFT                                                                            0x5
+#define CRT14__DOUBLE_WORD__SHIFT                                                                             0x6
+#define CRT14__UNDRLN_LOC_MASK                                                                                0x1FL
+#define CRT14__ADDR_CNT_BY4_MASK                                                                              0x20L
+#define CRT14__DOUBLE_WORD_MASK                                                                               0x40L
+//CRT15
+#define CRT15__V_BLANK_START__SHIFT                                                                           0x0
+#define CRT15__V_BLANK_START_MASK                                                                             0xFFL
+//CRT16
+#define CRT16__V_BLANK_END__SHIFT                                                                             0x0
+#define CRT16__V_BLANK_END_MASK                                                                               0xFFL
+//CRT17
+#define CRT17__RA0_AS_A13B__SHIFT                                                                             0x0
+#define CRT17__RA1_AS_A14B__SHIFT                                                                             0x1
+#define CRT17__VCOUNT_BY2__SHIFT                                                                              0x2
+#define CRT17__ADDR_CNT_BY2__SHIFT                                                                            0x3
+#define CRT17__WRAP_A15TOA0__SHIFT                                                                            0x5
+#define CRT17__BYTE_MODE__SHIFT                                                                               0x6
+#define CRT17__CRTC_SYNC_EN__SHIFT                                                                            0x7
+#define CRT17__RA0_AS_A13B_MASK                                                                               0x01L
+#define CRT17__RA1_AS_A14B_MASK                                                                               0x02L
+#define CRT17__VCOUNT_BY2_MASK                                                                                0x04L
+#define CRT17__ADDR_CNT_BY2_MASK                                                                              0x08L
+#define CRT17__WRAP_A15TOA0_MASK                                                                              0x20L
+#define CRT17__BYTE_MODE_MASK                                                                                 0x40L
+#define CRT17__CRTC_SYNC_EN_MASK                                                                              0x80L
+//CRT18
+#define CRT18__LINE_CMP__SHIFT                                                                                0x0
+#define CRT18__LINE_CMP_MASK                                                                                  0xFFL
+//CRT1E
+#define CRT1E__GRPH_DEC_RD1__SHIFT                                                                            0x1
+#define CRT1E__GRPH_DEC_RD1_MASK                                                                              0x02L
+//CRT1F
+#define CRT1F__GRPH_DEC_RD0__SHIFT                                                                            0x0
+#define CRT1F__GRPH_DEC_RD0_MASK                                                                              0xFFL
+//CRT22
+#define CRT22__GRPH_LATCH_DATA__SHIFT                                                                         0x0
+#define CRT22__GRPH_LATCH_DATA_MASK                                                                           0xFFL
+
+
+// addressBlock: vga_vgagrphind
+//GRA00
+#define GRA00__GRPH_SET_RESET0__SHIFT                                                                         0x0
+#define GRA00__GRPH_SET_RESET1__SHIFT                                                                         0x1
+#define GRA00__GRPH_SET_RESET2__SHIFT                                                                         0x2
+#define GRA00__GRPH_SET_RESET3__SHIFT                                                                         0x3
+#define GRA00__GRPH_SET_RESET0_MASK                                                                           0x01L
+#define GRA00__GRPH_SET_RESET1_MASK                                                                           0x02L
+#define GRA00__GRPH_SET_RESET2_MASK                                                                           0x04L
+#define GRA00__GRPH_SET_RESET3_MASK                                                                           0x08L
+//GRA01
+#define GRA01__GRPH_SET_RESET_ENA0__SHIFT                                                                     0x0
+#define GRA01__GRPH_SET_RESET_ENA1__SHIFT                                                                     0x1
+#define GRA01__GRPH_SET_RESET_ENA2__SHIFT                                                                     0x2
+#define GRA01__GRPH_SET_RESET_ENA3__SHIFT                                                                     0x3
+#define GRA01__GRPH_SET_RESET_ENA0_MASK                                                                       0x01L
+#define GRA01__GRPH_SET_RESET_ENA1_MASK                                                                       0x02L
+#define GRA01__GRPH_SET_RESET_ENA2_MASK                                                                       0x04L
+#define GRA01__GRPH_SET_RESET_ENA3_MASK                                                                       0x08L
+//GRA02
+#define GRA02__GRPH_CCOMP__SHIFT                                                                              0x0
+#define GRA02__GRPH_CCOMP_MASK                                                                                0x0FL
+//GRA03
+#define GRA03__GRPH_ROTATE__SHIFT                                                                             0x0
+#define GRA03__GRPH_FN_SEL__SHIFT                                                                             0x3
+#define GRA03__GRPH_ROTATE_MASK                                                                               0x07L
+#define GRA03__GRPH_FN_SEL_MASK                                                                               0x18L
+//GRA04
+#define GRA04__GRPH_RMAP__SHIFT                                                                               0x0
+#define GRA04__GRPH_RMAP_MASK                                                                                 0x03L
+//GRA05
+#define GRA05__GRPH_WRITE_MODE__SHIFT                                                                         0x0
+#define GRA05__GRPH_READ1__SHIFT                                                                              0x3
+#define GRA05__CGA_ODDEVEN__SHIFT                                                                             0x4
+#define GRA05__GRPH_OES__SHIFT                                                                                0x5
+#define GRA05__GRPH_PACK__SHIFT                                                                               0x6
+#define GRA05__GRPH_WRITE_MODE_MASK                                                                           0x03L
+#define GRA05__GRPH_READ1_MASK                                                                                0x08L
+#define GRA05__CGA_ODDEVEN_MASK                                                                               0x10L
+#define GRA05__GRPH_OES_MASK                                                                                  0x20L
+#define GRA05__GRPH_PACK_MASK                                                                                 0x40L
+//GRA06
+#define GRA06__GRPH_GRAPHICS__SHIFT                                                                           0x0
+#define GRA06__GRPH_ODDEVEN__SHIFT                                                                            0x1
+#define GRA06__GRPH_ADRSEL__SHIFT                                                                             0x2
+#define GRA06__GRPH_GRAPHICS_MASK                                                                             0x01L
+#define GRA06__GRPH_ODDEVEN_MASK                                                                              0x02L
+#define GRA06__GRPH_ADRSEL_MASK                                                                               0x0CL
+//GRA07
+#define GRA07__GRPH_XCARE0__SHIFT                                                                             0x0
+#define GRA07__GRPH_XCARE1__SHIFT                                                                             0x1
+#define GRA07__GRPH_XCARE2__SHIFT                                                                             0x2
+#define GRA07__GRPH_XCARE3__SHIFT                                                                             0x3
+#define GRA07__GRPH_XCARE0_MASK                                                                               0x01L
+#define GRA07__GRPH_XCARE1_MASK                                                                               0x02L
+#define GRA07__GRPH_XCARE2_MASK                                                                               0x04L
+#define GRA07__GRPH_XCARE3_MASK                                                                               0x08L
+//GRA08
+#define GRA08__GRPH_BMSK__SHIFT                                                                               0x0
+#define GRA08__GRPH_BMSK_MASK                                                                                 0xFFL
+
+
+// addressBlock: vga_vgaattrind
+//ATTR00
+#define ATTR00__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR00__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR01
+#define ATTR01__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR01__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR02
+#define ATTR02__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR02__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR03
+#define ATTR03__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR03__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR04
+#define ATTR04__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR04__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR05
+#define ATTR05__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR05__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR06
+#define ATTR06__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR06__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR07
+#define ATTR07__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR07__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR08
+#define ATTR08__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR08__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR09
+#define ATTR09__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR09__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0A
+#define ATTR0A__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0A__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0B
+#define ATTR0B__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0B__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0C
+#define ATTR0C__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0C__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0D
+#define ATTR0D__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0D__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0E
+#define ATTR0E__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0E__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR0F
+#define ATTR0F__ATTR_PAL__SHIFT                                                                               0x0
+#define ATTR0F__ATTR_PAL_MASK                                                                                 0x3FL
+//ATTR10
+#define ATTR10__ATTR_GRPH_MODE__SHIFT                                                                         0x0
+#define ATTR10__ATTR_MONO_EN__SHIFT                                                                           0x1
+#define ATTR10__ATTR_LGRPH_EN__SHIFT                                                                          0x2
+#define ATTR10__ATTR_BLINK_EN__SHIFT                                                                          0x3
+#define ATTR10__ATTR_PANTOPONLY__SHIFT                                                                        0x5
+#define ATTR10__ATTR_PCLKBY2__SHIFT                                                                           0x6
+#define ATTR10__ATTR_CSEL_EN__SHIFT                                                                           0x7
+#define ATTR10__ATTR_GRPH_MODE_MASK                                                                           0x01L
+#define ATTR10__ATTR_MONO_EN_MASK                                                                             0x02L
+#define ATTR10__ATTR_LGRPH_EN_MASK                                                                            0x04L
+#define ATTR10__ATTR_BLINK_EN_MASK                                                                            0x08L
+#define ATTR10__ATTR_PANTOPONLY_MASK                                                                          0x20L
+#define ATTR10__ATTR_PCLKBY2_MASK                                                                             0x40L
+#define ATTR10__ATTR_CSEL_EN_MASK                                                                             0x80L
+//ATTR11
+#define ATTR11__ATTR_OVSC__SHIFT                                                                              0x0
+#define ATTR11__ATTR_OVSC_MASK                                                                                0xFFL
+//ATTR12
+#define ATTR12__ATTR_MAP_EN__SHIFT                                                                            0x0
+#define ATTR12__ATTR_VSMUX__SHIFT                                                                             0x4
+#define ATTR12__ATTR_MAP_EN_MASK                                                                              0x0FL
+#define ATTR12__ATTR_VSMUX_MASK                                                                               0x30L
+//ATTR13
+#define ATTR13__ATTR_PPAN__SHIFT                                                                              0x0
+#define ATTR13__ATTR_PPAN_MASK                                                                                0x0FL
+//ATTR14
+#define ATTR14__ATTR_CSEL1__SHIFT                                                                             0x0
+#define ATTR14__ATTR_CSEL2__SHIFT                                                                             0x2
+#define ATTR14__ATTR_CSEL1_MASK                                                                               0x03L
+#define ATTR14__ATTR_CSEL2_MASK                                                                               0x0CL
+
+
+// addressBlock: azendpoint_f2codecind
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                            0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                       0xb
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                           0xe
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                                0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT                              0xf
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                           0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                              0x00000070L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                          0x00000700L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                         0x00003800L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                             0x00004000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                                  0x00008000L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK                                0x00008000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                                0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                                  0x0000000FL
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                                   0x000000F0L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                         0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                      0x2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                       0x3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                      0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                                 0x5
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                       0x6
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                        0x8
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                                 0x17
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                        0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                         0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                        0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                                   0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                         0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                          0x00007F00L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                                   0x00800000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT                                      0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK                                        0x0000007FL
+//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                                       0x0
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                                    0x14
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                                         0x00000003L
+#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                                      0x00700000L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT                               0x7
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK                                 0x00000080L
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                                           0x000000FFL
+//AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT            0x0
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT              0x1
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT             0x4
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK              0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK                0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK               0x00000070L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT                 0x4
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK                   0x00000010L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT              0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT               0x10
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                0x00000FFFL
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                 0x001F0000L
+//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                             0x0
+#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                               0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT              0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK                0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                                         0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                                           0x00000040L
+//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                       0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                            0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                         0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                                0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                                0x1f
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                                  0x7FFFFFFFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                                  0x80000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT                0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                              0xc
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT                    0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT                     0x14
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                           0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT                  0x1e
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                             0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK                  0x000000F0L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                                 0x00000F00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                                0x0000F000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                      0x000F0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                       0x00F00000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                             0x3F000000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK                    0xC0000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                            0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                               0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                              0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK                    0x0000000FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT                0x6
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                           0x0000003FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK                  0x000000C0L
+//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT                         0x9
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT                 0xa
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK                      0x0000007FL
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK                   0x0000FC00L
+//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT                                         0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT                                    0x7
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK                                    0x00000003L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK                                           0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK                                      0x00000080L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT                                      0x3
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT                            0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT                                0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT                     0x18
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK                                        0x00000078L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK                              0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK                                  0x00FF0000L
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK                                    0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT                       0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT                         0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT                   0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK                         0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK                           0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK                     0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT                                             0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK                                               0x000000FFL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK                                               0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                                    0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                                     0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                      0x00000010L
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK                               0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                           0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                             0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                       0x000000F0L
+//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                                 0x00000001L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                                   0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT                          0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                                     0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK                            0x0000003CL
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT                         0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT                0x2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT                            0x3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT                   0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK                           0x00000003L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK                  0x00000004L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                              0x00000078L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK                     0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT                     0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT            0x6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK                       0x0000003FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK              0x00000040L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT            0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT   0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK              0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK     0x00000010L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT               0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT                     0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                                 0x5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT                           0x7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK                 0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK                       0x00000010L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                                   0x00000060L
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK                             0x00000080L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK                         0x000000F0L
+//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT                       0x0
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT                       0x4
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK                         0x0000000FL
+#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK                         0x000000F0L
+//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                                         0x0
+#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                               0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                                 0x00000001L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                          0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT                    0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                            0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                      0x0000FF00L
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                                           0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                                           0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                                             0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT                       0x1
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                               0x8
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT                             0x10
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                                       0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK                         0x00000002L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                                 0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                               0x00FF0000L
+//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK     0x00000003L
+//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT                     0x4
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK                       0x00000010L
+//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT               0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT              0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT          0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT                     0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT       0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                               0x9
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                         0xa
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                               0xb
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                                  0x14
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK                 0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK                0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK            0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                       0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK         0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                         0x00000100L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                                 0x00000200L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                           0x00000400L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                                 0x00000800L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK         0x000F0000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                                    0x00F00000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                            0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                          0x2
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                            0x3
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                                     0x4
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                      0x5
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                                  0x6
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                               0x7
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                       0x8
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                       0x10
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                                 0x18
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                              0x00000001L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                            0x00000004L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                              0x00000008L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                       0x00000010L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                        0x00000020L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                                    0x00000040L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                                 0x00000080L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                         0x0000FF00L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                         0x00010000L
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                                   0x01000000L
+//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT                   0x0
+#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azendpoint_descriptorind
+//AUDIO_DESCRIPTOR0
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR1
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR2
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR3
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR4
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR5
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR6
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR7
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR8
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR9
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                                                                0x0
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT                                                       0x8
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                                                           0x10
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                                0x18
+#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                                                                  0x00000007L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK                                                         0x0000FF00L
+#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                                                             0x00FF0000L
+#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK                                                  0xFF000000L
+//AUDIO_DESCRIPTOR10
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR11
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR12
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+//AUDIO_DESCRIPTOR13
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                                                               0x0
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT                                                      0x8
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                                                          0x10
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT                                               0x18
+#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                                                                 0x00000007L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK                                                        0x0000FF00L
+#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                                                            0x00FF0000L
+#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK                                                 0xFF000000L
+
+
+// addressBlock: azendpoint_sinkinfoind
+//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT                                   0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK                                     0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK                                               0x0000FFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT                         0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK                           0x000000FFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK                                                      0xFFFFFFFFL
+//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT                                                    0x0
+#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK                                                      0xFFFFFFFFL
+//SINK_DESCRIPTION0
+#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION0__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION1
+#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION1__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION2
+#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION2__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION3
+#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION3__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION4
+#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION4__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION5
+#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION5__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION6
+#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION6__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION7
+#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION7__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION8
+#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION8__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION9
+#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT                                                                 0x0
+#define SINK_DESCRIPTION9__DESCRIPTION_MASK                                                                   0x000000FFL
+//SINK_DESCRIPTION10
+#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION10__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION11
+#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION11__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION12
+#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION12__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION13
+#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION13__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION14
+#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION14__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION15
+#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION15__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION16
+#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION16__DESCRIPTION_MASK                                                                  0x000000FFL
+//SINK_DESCRIPTION17
+#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT                                                                0x0
+#define SINK_DESCRIPTION17__DESCRIPTION_MASK                                                                  0x000000FFL
+
+
+// addressBlock: azf0controller_azinputcrc0resultind
+//AZALIA_INPUT_CRC0_CHANNEL0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL1
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL2
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL3
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL4
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL5
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL6
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC0_CHANNEL7
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azinputcrc1resultind
+//AZALIA_INPUT_CRC1_CHANNEL0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL1
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL2
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL3
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL4
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL5
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL6
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK                                                   0xFFFFFFFFL
+//AZALIA_INPUT_CRC1_CHANNEL7
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT                                                 0x0
+#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK                                                   0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc0resultind
+//AZALIA_CRC0_CHANNEL0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL1
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL2
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL3
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL4
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL5
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL6
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC0_CHANNEL7
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azf0controller_azcrc1resultind
+//AZALIA_CRC1_CHANNEL0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL1
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL2
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL3
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL4
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL5
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL6
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK                                                               0xFFFFFFFFL
+//AZALIA_CRC1_CHANNEL7
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT                                                             0x0
+#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: azinputendpoint_f2codecind
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT                 0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT                     0xe
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                          0xf
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK                     0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                        0x00000070L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK                    0x00000700L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK                   0x00003800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK                       0x00004000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                            0x00008000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                            0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                             0x000000F0L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                               0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                                   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                                0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                                 0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                                0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                           0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                                 0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                                   0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                                  0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                           0x17
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                                 0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                                     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                                  0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                                   0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                                  0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                             0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                                   0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                                     0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                                    0x00007F00L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                             0x00800000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT   0x1
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT           0x4
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                    0x5
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT         0x6
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT           0x8
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                   0x9
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT             0xa
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                   0xb
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                      0x14
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK     0x00000002L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK    0x00000004L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK             0x00000010L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                      0x00000020L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK           0x00000040L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK             0x00000100L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                     0x00000200L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK               0x00000400L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                     0x00000800L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                        0x00F00000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT        0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT         0x10
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK          0x00000FFFL
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK           0x001F0000L
+//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                         0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                                    0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                                      0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                                 0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                                      0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                                   0x00000080L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                          0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT                          0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                            0x7FFFFFFFL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK                            0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT          0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                         0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                        0xc
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT              0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT               0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT                     0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT            0x1e
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK                       0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK            0x000000F0L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                           0x00000F00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                          0x0000F000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK                0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK                 0x00F00000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK                       0x3F000000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK              0xC0000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT                      0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK                         0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK                        0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT            0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT             0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK              0x0000000FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK               0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT          0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK                     0x0000003FL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK            0x000000C0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT                       0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK                         0x000000FFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT                                             0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT                                              0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK                                               0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK                                                0x00000010L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT                     0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK                     0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK                       0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK                 0x000000F0L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT                    0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT              0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK                      0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK                0x0000FF00L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                                   0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                                     0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK                       0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT                         0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT                         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK                           0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK                           0x00000006L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK   0x00000020L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                                     0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT                                0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT                                  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                                   0x1f
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                                       0x00000007L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK                                  0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                                    0x00FF0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                                     0x80000000L
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT                           0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK                             0xFFFFFFFFL
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT         0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT        0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT    0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                          0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT               0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                         0x9
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT                   0xa
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                         0xb
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                            0x14
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK           0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK          0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK      0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                            0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK                 0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK   0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK                   0x00000100L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                           0x00000200L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK                     0x00000400L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                           0x00000800L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK   0x000F0000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                              0x00F00000L
+//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT                      0x0
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                             0x1
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT                    0x2
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT                      0x3
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                               0x4
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                                0x5
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                            0x6
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                         0x7
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                                 0x8
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                                 0x10
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                           0x18
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                        0x00000001L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                               0x00000002L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK                      0x00000004L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                        0x00000008L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                                 0x00000010L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                                  0x00000020L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                              0x00000040L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                           0x00000080L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                                   0x0000FF00L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                                   0x00010000L
+#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                                             0x01000000L
+
+
+// addressBlock: azroot_f2codecind
+//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT            0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK              0xFFFFFFFFL
+//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT                                  0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT                                  0x4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT                                        0x9
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT                       0xa
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK                                    0x0000000FL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK                                    0x000000F0L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK                                          0x00000200L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK                         0x00000400L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT                     0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT                     0x8
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT                     0x10
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT                     0x18
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK                       0x000000FFL
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK                       0x0000FF00L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK                       0x00FF0000L
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK                       0xFF000000L
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT                   0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK                     0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT          0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK            0x000000FFL
+//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT                                            0x0
+#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK                                              0x00000001L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT      0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK        0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT               0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT                0x10
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK                 0x00000FFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK                  0x001F0000L
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK  0xFFFFFFFFL
+//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT  0x0
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT                                       0x1e
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT                                          0x1f
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK    0x3FFFFFFFL
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK                                         0x40000000L
+#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK                                            0x80000000L
+
+
+// addressBlock: azf0stream0_streamind
+//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream1_streamind
+//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream2_streamind
+//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream3_streamind
+//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream4_streamind
+//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream5_streamind
+//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream6_streamind
+//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream7_streamind
+//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream8_streamind
+//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream9_streamind
+//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                            0x0
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                            0x8
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                      0x10
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                              0x0000007FL
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                              0x00007F00L
+#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                        0x00FF0000L
+//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                       0x0
+#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                         0x00000001L
+//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                     0x0
+#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                       0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                     0xFFFFFFFFL
+//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                   0x0
+#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                     0xFFFFFFFFL
+
+
+// addressBlock: azf0stream10_streamind
+//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream11_streamind
+//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream12_streamind
+//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream13_streamind
+//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream14_streamind
+//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0stream15_streamind
+//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT                                           0x0
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT                                           0x8
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT                                     0x10
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK                                             0x0000007FL
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK                                             0x00007F00L
+#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK                                       0x00FF0000L
+//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT                      0x0
+#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK                        0x00000001L
+//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT                    0x0
+#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK                      0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK                    0xFFFFFFFFL
+//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT                  0x0
+#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK                    0xFFFFFFFFL
+
+
+// addressBlock: azf0endpoint0_endpointind
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint1_endpointind
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint2_endpointind
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint3_endpointind
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint4_endpointind
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint5_endpointind
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint6_endpointind
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0endpoint7_endpointind
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT            0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT   0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT           0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT     0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT           0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT              0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK     0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK              0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK   0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK     0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK             0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK       0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK             0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT              0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT         0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT             0xe
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT                  0xf
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK             0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK                0x00000070L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK            0x00000700L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK           0x00003800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK               0x00004000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK                    0x00008000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT                   0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK                    0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK                     0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                           0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT                        0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT                         0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT                        0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT                         0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                           0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT                          0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT                   0x17
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                             0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK                          0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                           0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK                          0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK                     0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                           0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                             0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                            0x00007F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK                     0x00800000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK                 0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK   0x001F0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT                      0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK                           0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK                        0x00700000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK                             0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_OFFSET_CHANGED_MASK  0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__CLEAR_GTC_COUNTER_MIN_MAX_DELTA_MASK   0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_GROUP_MASK  0x00000070L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA__SHIFT                   0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA__GTC_COUNTER_DELTA_MASK                     0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN__GTC_COUNTER_DELTA_MIN_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX__GTC_COUNTER_DELTA_MAX_MASK             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT                  0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT       0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT                 0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT           0xa
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT                 0xb
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT                    0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK   0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK                    0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK         0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK           0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK                   0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK             0x00000400L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK                   0x00000800L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK                      0x00F00000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT              0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT                     0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT                       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT                        0x5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT                    0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                                 0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT                         0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                                   0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK                0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK                       0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK              0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK                0x00000008L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK                         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK                          0x00000020L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK                      0x00000040L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                                   0x00000080L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                           0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                           0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK                                     0x01000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT                         0x7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                              0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                           0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK                    0x7FFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT                           0x6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK                             0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT                  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT                  0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT                     0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT                       0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT               0x12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT                  0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT                         0x1b
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT                    0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK                    0x0000007FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK                    0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK                       0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK                         0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK                 0x00FC0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK                    0x03000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK                           0x78000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK                      0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT      0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK        0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT                 0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK                        0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK                   0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT                0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK                       0x00000007L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK                  0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT                      0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT                      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK                        0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK                        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                               0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT                          0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT                               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK                            0x0000FFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK                                 0xFFFF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK                       0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT                                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK                                   0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT                             0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT                             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK                               0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK                               0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT                             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK                               0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK                               0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT                            0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT                            0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK                              0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK                              0x00FF0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK                              0xFF000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT                            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT                            0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK                              0x000000FFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK                              0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT                     0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT                      0x1f
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK                 0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK                       0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK                        0x80000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT                0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT      0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT             0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT    0x1e
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK               0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK    0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK                   0x00000F00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK                  0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK        0x000F0000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK               0x3F000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK      0xC0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT             0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT             0x9
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT       0xc
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT           0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT             0x11
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT       0x14
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT           0x18
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT             0x19
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT       0x1c
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK               0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK         0x000000F0L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK             0x00000100L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK               0x00000200L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK         0x0000F000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK             0x00010000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK               0x00020000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK         0x00F00000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK             0x01000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK               0x02000000L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK         0xF0000000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT                     0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT            0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK                       0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK              0x0000003CL
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT  0x2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT              0x3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT     0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK             0x00000003L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK    0x00000004L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK                0x00000078L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK       0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK         0x0000003FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000040L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT  0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK  0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK  0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT                   0x5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT             0x7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK   0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK         0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK                     0x00000060L
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK               0x00000080L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK           0x0000000FL
+#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK           0x000000F0L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT                 0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK                   0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT            0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT      0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK              0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK        0x0000FF00L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT                                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK                                             0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK               0xFFFFFFFFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT                             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK                               0x000000FFL
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT                       0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT         0x1
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT                 0x8
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT               0x10
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK                         0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK           0x00000002L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK                   0x0000FF00L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK                 0x00FF0000L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT  0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK  0x00000003L
+//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT       0x4
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK         0x00000010L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT                               0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK                                 0x00000001L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT                           0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT                           0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT                           0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK                             0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK                             0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK                             0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT                         0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT                         0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT                         0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK                           0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK                           0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK                           0x00000100L
+//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT             0x0
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT             0x4
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT             0x8
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK               0x00000001L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK               0x00000010L
+#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK               0x00000100L
+
+
+// addressBlock: azf0inputendpoint0_inputendpointind
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint1_inputendpointind
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint2_inputendpointind
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint3_inputendpointind
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint4_inputendpointind
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint5_inputendpointind
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint6_inputendpointind
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+// addressBlock: azf0inputendpoint7_inputendpointind
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT   0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK   0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK  0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK  0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK     0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT   0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT  0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT  0xe
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT       0xf
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK  0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK     0x00000070L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK  0x00000700L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK  0x00003800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK    0x00004000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK         0x00008000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT       0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT        0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK         0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK          0x000000F0L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT            0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT                0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT             0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT              0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT             0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT        0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT              0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT                0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT               0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT        0x17
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK              0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK                  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK               0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK                0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK               0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK          0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK                0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK                  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK                 0x00007F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK          0x00800000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK      0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK  0x00000FFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK  0x001F0000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT  0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT       0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT  0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT  0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT      0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT  0xa
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT      0xb
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT         0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK  0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK  0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK  0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK         0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK  0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK  0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK        0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK  0x00000400L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK        0x00000800L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK           0x00F00000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT   0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT          0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT  0x2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT   0x3
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT            0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT             0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT         0x6
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT                      0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT              0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT              0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT                        0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK     0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK            0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK   0x00000004L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK     0x00000008L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK              0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK               0x00000020L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK           0x00000040L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK                        0x00000080L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK                0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK                0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK                          0x01000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT              0x7
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK                   0x0000003FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK                0x00000080L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT  0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK   0x7FFFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK   0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT                 0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK                   0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT   0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT   0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT   0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT   0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK     0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK   0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK     0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK   0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK     0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK   0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK     0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT  0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT  0x9
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT  0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT  0x11
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT  0x19
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK  0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK    0x00000002L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK  0x00000100L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK    0x00000200L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK  0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK  0x00010000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK    0x00020000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK  0x01000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK    0x02000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK  0xF0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT                 0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT                  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK                   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK                    0x00000010L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK      0x000000FFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT    0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT          0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT           0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK      0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK            0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK             0x80000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT  0x1c
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK  0x03FFFFFFL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK  0x10000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT      0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT     0xc
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT  0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT  0x14
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT  0x18
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT  0x1e
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK    0x0000000FL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK  0x000000F0L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK        0x00000F00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK       0x0000F000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK  0x000F0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK  0x00F00000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK    0x3F000000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK  0xC0000000L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT  0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK   0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK  0x0000FF00L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT                                0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK                                  0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK    0xFFFFFFFFL
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT      0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT      0x1
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT  0x4
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT  0x5
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK        0x00000001L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK        0x00000006L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK  0x00000010L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK  0x00000020L
+//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT                  0x0
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT             0x8
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT               0x10
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT                0x1f
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK                    0x00000007L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK               0x0000FF00L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK                 0x00FF0000L
+#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK                  0x80000000L
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
new file mode 100644
index 000000000000..92caf8441d1e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_offset.h
@@ -0,0 +1,11936 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dpcs_4_2_0_OFFSET_HEADER
+#define _dpcs_4_2_0_OFFSET_HEADER
+
+
+
+// addressBlock: dpcssys_dpcssys_cr0_dispdec
+// base address: 0x0
+#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR                                                                  0x2934
+#define regDPCSSYS_CR0_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR0_DPCSSYS_CR_DATA                                                                  0x2935
+#define regDPCSSYS_CR0_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr1_dispdec
+// base address: 0x360
+#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR                                                                  0x2a0c
+#define regDPCSSYS_CR1_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR1_DPCSSYS_CR_DATA                                                                  0x2a0d
+#define regDPCSSYS_CR1_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr2_dispdec
+// base address: 0x6c0
+#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR                                                                  0x2ae4
+#define regDPCSSYS_CR2_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR2_DPCSSYS_CR_DATA                                                                  0x2ae5
+#define regDPCSSYS_CR2_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr3_dispdec
+// base address: 0xa20
+#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR                                                                  0x2bbc
+#define regDPCSSYS_CR3_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR3_DPCSSYS_CR_DATA                                                                  0x2bbd
+#define regDPCSSYS_CR3_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_dpcssys_cr4_dispdec
+// base address: 0xd80
+#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR                                                                  0x2c94
+#define regDPCSSYS_CR4_DPCSSYS_CR_ADDR_BASE_IDX                                                         2
+#define regDPCSSYS_CR4_DPCSSYS_CR_DATA                                                                  0x2c95
+#define regDPCSSYS_CR4_DPCSSYS_CR_DATA_BASE_IDX                                                         2
+
+
+// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
+// base address: 0x0
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN                                                                    0x2f10
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f11
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK                                                                  0x2f12
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f13
+#define regPWRSEQ0_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL                                                                    0x2f14
+#define regPWRSEQ0_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE                                                                   0x2f15
+#define regPWRSEQ0_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1                                                                  0x2f16
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2                                                                  0x2f17
+#define regPWRSEQ0_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1                                                                0x2f18
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ0_BL_PWM_CNTL                                                                          0x2f19
+#define regPWRSEQ0_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ0_BL_PWM_CNTL2                                                                         0x2f1a
+#define regPWRSEQ0_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL                                                                   0x2f1b
+#define regPWRSEQ0_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK                                                                 0x2f1c
+#define regPWRSEQ0_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2                                                                0x2f1d
+#define regPWRSEQ0_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ0_PWRSEQ_SPARE                                                                         0x2f21
+#define regPWRSEQ0_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
+// base address: 0x1b0
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN                                                                    0x2f7c
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_EN_BASE_IDX                                                           2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL                                                                  0x2f7d
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_CTRL_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK                                                                  0x2f7e
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_MASK_BASE_IDX                                                         2
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y                                                                   0x2f7f
+#define regPWRSEQ1_DC_GPIO_PWRSEQ_A_Y_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL                                                                    0x2f80
+#define regPWRSEQ1_PANEL_PWRSEQ_CNTL_BASE_IDX                                                           2
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE                                                                   0x2f81
+#define regPWRSEQ1_PANEL_PWRSEQ_STATE_BASE_IDX                                                          2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1                                                                  0x2f82
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY1_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2                                                                  0x2f83
+#define regPWRSEQ1_PANEL_PWRSEQ_DELAY2_BASE_IDX                                                         2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1                                                                0x2f84
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV1_BASE_IDX                                                       2
+#define regPWRSEQ1_BL_PWM_CNTL                                                                          0x2f85
+#define regPWRSEQ1_BL_PWM_CNTL_BASE_IDX                                                                 2
+#define regPWRSEQ1_BL_PWM_CNTL2                                                                         0x2f86
+#define regPWRSEQ1_BL_PWM_CNTL2_BASE_IDX                                                                2
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL                                                                   0x2f87
+#define regPWRSEQ1_BL_PWM_PERIOD_CNTL_BASE_IDX                                                          2
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK                                                                 0x2f88
+#define regPWRSEQ1_BL_PWM_GRP1_REG_LOCK_BASE_IDX                                                        2
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2                                                                0x2f89
+#define regPWRSEQ1_PANEL_PWRSEQ_REF_DIV2_BASE_IDX                                                       2
+#define regPWRSEQ1_PWRSEQ_SPARE                                                                         0x2f8d
+#define regPWRSEQ1_PWRSEQ_SPARE_BASE_IDX                                                                2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
+// base address: 0x0
+#define regRDPCSTX0_RDPCSTX_CNTL                                                                        0x2930
+#define regRDPCSTX0_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL                                                                  0x2931
+#define regRDPCSTX0_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL                                                           0x2932
+#define regRDPCSTX0_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2933
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX0_RDPCS_TX_CR_ADDR                                                                    0x2934
+#define regRDPCSTX0_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX0_RDPCS_TX_CR_DATA                                                                    0x2935
+#define regRDPCSTX0_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL                                                                  0x2936
+#define regRDPCSTX0_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_SCRATCH                                                                     0x2937
+#define regRDPCSTX0_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX0_RDPCSTX_SPARE                                                                       0x2938
+#define regRDPCSTX0_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX0_RDPCSTX_CNTL2                                                                       0x2939
+#define regRDPCSTX0_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x293c
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL0                                                                   0x2940
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL1                                                                   0x2941
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL2                                                                   0x2942
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL3                                                                   0x2943
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL4                                                                   0x2944
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL5                                                                   0x2945
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL6                                                                   0x2946
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL7                                                                   0x2947
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL8                                                                   0x2948
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL9                                                                   0x2949
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL10                                                                  0x294a
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL11                                                                  0x294b
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL12                                                                  0x294c
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL13                                                                  0x294d
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL14                                                                  0x294e
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE0                                                                   0x294f
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE1                                                                   0x2950
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE2                                                                   0x2951
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE3                                                                   0x2952
+#define regRDPCSTX0_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL                                                               0x2953
+#define regRDPCSTX0_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2954
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2955
+#define regRDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG                                                           0x2956
+#define regRDPCSTX0_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL15                                                                  0x2958
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL16                                                                  0x2959
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL17                                                                  0x295a
+#define regRDPCSTX0_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX0_RDPCS_CNTL3                                                                         0x295c
+#define regRDPCSTX0_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x295d
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x295e
+#define regRDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
+// base address: 0x360
+#define regRDPCSTX1_RDPCSTX_CNTL                                                                        0x2a08
+#define regRDPCSTX1_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL                                                                  0x2a09
+#define regRDPCSTX1_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL                                                           0x2a0a
+#define regRDPCSTX1_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2a0b
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX1_RDPCS_TX_CR_ADDR                                                                    0x2a0c
+#define regRDPCSTX1_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX1_RDPCS_TX_CR_DATA                                                                    0x2a0d
+#define regRDPCSTX1_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL                                                                  0x2a0e
+#define regRDPCSTX1_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_SCRATCH                                                                     0x2a0f
+#define regRDPCSTX1_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX1_RDPCSTX_SPARE                                                                       0x2a10
+#define regRDPCSTX1_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX1_RDPCSTX_CNTL2                                                                       0x2a11
+#define regRDPCSTX1_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2a14
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL0                                                                   0x2a18
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL1                                                                   0x2a19
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL2                                                                   0x2a1a
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL3                                                                   0x2a1b
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL4                                                                   0x2a1c
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL5                                                                   0x2a1d
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL6                                                                   0x2a1e
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL7                                                                   0x2a1f
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL8                                                                   0x2a20
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL9                                                                   0x2a21
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL10                                                                  0x2a22
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL11                                                                  0x2a23
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL12                                                                  0x2a24
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL13                                                                  0x2a25
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL14                                                                  0x2a26
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE0                                                                   0x2a27
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE1                                                                   0x2a28
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE2                                                                   0x2a29
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE3                                                                   0x2a2a
+#define regRDPCSTX1_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL                                                               0x2a2b
+#define regRDPCSTX1_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2a2c
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2a2d
+#define regRDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG                                                           0x2a2e
+#define regRDPCSTX1_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL15                                                                  0x2a30
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL16                                                                  0x2a31
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL17                                                                  0x2a32
+#define regRDPCSTX1_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX1_RDPCS_CNTL3                                                                         0x2a34
+#define regRDPCSTX1_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2a35
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2a36
+#define regRDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
+// base address: 0x6c0
+#define regRDPCSTX2_RDPCSTX_CNTL                                                                        0x2ae0
+#define regRDPCSTX2_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL                                                                  0x2ae1
+#define regRDPCSTX2_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL                                                           0x2ae2
+#define regRDPCSTX2_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2ae3
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX2_RDPCS_TX_CR_ADDR                                                                    0x2ae4
+#define regRDPCSTX2_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX2_RDPCS_TX_CR_DATA                                                                    0x2ae5
+#define regRDPCSTX2_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL                                                                  0x2ae6
+#define regRDPCSTX2_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_SCRATCH                                                                     0x2ae7
+#define regRDPCSTX2_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX2_RDPCSTX_SPARE                                                                       0x2ae8
+#define regRDPCSTX2_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX2_RDPCSTX_CNTL2                                                                       0x2ae9
+#define regRDPCSTX2_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2aec
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL0                                                                   0x2af0
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL1                                                                   0x2af1
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL2                                                                   0x2af2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL3                                                                   0x2af3
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL4                                                                   0x2af4
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL5                                                                   0x2af5
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL6                                                                   0x2af6
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL7                                                                   0x2af7
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL8                                                                   0x2af8
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL9                                                                   0x2af9
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL10                                                                  0x2afa
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL11                                                                  0x2afb
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL12                                                                  0x2afc
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL13                                                                  0x2afd
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL14                                                                  0x2afe
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE0                                                                   0x2aff
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE1                                                                   0x2b00
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE2                                                                   0x2b01
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE3                                                                   0x2b02
+#define regRDPCSTX2_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL                                                               0x2b03
+#define regRDPCSTX2_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2b04
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2b05
+#define regRDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG                                                           0x2b06
+#define regRDPCSTX2_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL15                                                                  0x2b08
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL16                                                                  0x2b09
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL17                                                                  0x2b0a
+#define regRDPCSTX2_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX2_RDPCS_CNTL3                                                                         0x2b0c
+#define regRDPCSTX2_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2b0d
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2b0e
+#define regRDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
+// base address: 0xa20
+#define regRDPCSTX3_RDPCSTX_CNTL                                                                        0x2bb8
+#define regRDPCSTX3_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL                                                                  0x2bb9
+#define regRDPCSTX3_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL                                                           0x2bba
+#define regRDPCSTX3_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2bbb
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX3_RDPCS_TX_CR_ADDR                                                                    0x2bbc
+#define regRDPCSTX3_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX3_RDPCS_TX_CR_DATA                                                                    0x2bbd
+#define regRDPCSTX3_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL                                                                  0x2bbe
+#define regRDPCSTX3_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_SCRATCH                                                                     0x2bbf
+#define regRDPCSTX3_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX3_RDPCSTX_SPARE                                                                       0x2bc0
+#define regRDPCSTX3_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX3_RDPCSTX_CNTL2                                                                       0x2bc1
+#define regRDPCSTX3_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2bc4
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL0                                                                   0x2bc8
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL1                                                                   0x2bc9
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL2                                                                   0x2bca
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL3                                                                   0x2bcb
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL4                                                                   0x2bcc
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL5                                                                   0x2bcd
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL6                                                                   0x2bce
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL7                                                                   0x2bcf
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL8                                                                   0x2bd0
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL9                                                                   0x2bd1
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL10                                                                  0x2bd2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL11                                                                  0x2bd3
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL12                                                                  0x2bd4
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL13                                                                  0x2bd5
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL14                                                                  0x2bd6
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE0                                                                   0x2bd7
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE1                                                                   0x2bd8
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE2                                                                   0x2bd9
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE3                                                                   0x2bda
+#define regRDPCSTX3_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL                                                               0x2bdb
+#define regRDPCSTX3_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2bdc
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2bdd
+#define regRDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG                                                           0x2bde
+#define regRDPCSTX3_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL15                                                                  0x2be0
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL16                                                                  0x2be1
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL17                                                                  0x2be2
+#define regRDPCSTX3_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX3_RDPCS_CNTL3                                                                         0x2be4
+#define regRDPCSTX3_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2be5
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2be6
+#define regRDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
+// base address: 0xd80
+#define regRDPCSTX4_RDPCSTX_CNTL                                                                        0x2c90
+#define regRDPCSTX4_RDPCSTX_CNTL_BASE_IDX                                                               2
+#define regRDPCSTX4_RDPCSTX_CLOCK_CNTL                                                                  0x2c91
+#define regRDPCSTX4_RDPCSTX_CLOCK_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL                                                           0x2c92
+#define regRDPCSTX4_RDPCSTX_INTERRUPT_CONTROL_BASE_IDX                                                  2
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA                                                            0x2c93
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_BASE_IDX                                                   2
+#define regRDPCSTX4_RDPCS_TX_CR_ADDR                                                                    0x2c94
+#define regRDPCSTX4_RDPCS_TX_CR_ADDR_BASE_IDX                                                           2
+#define regRDPCSTX4_RDPCS_TX_CR_DATA                                                                    0x2c95
+#define regRDPCSTX4_RDPCS_TX_CR_DATA_BASE_IDX                                                           2
+#define regRDPCSTX4_RDPCS_TX_SRAM_CNTL                                                                  0x2c96
+#define regRDPCSTX4_RDPCS_TX_SRAM_CNTL_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_SCRATCH                                                                     0x2c97
+#define regRDPCSTX4_RDPCSTX_SCRATCH_BASE_IDX                                                            2
+#define regRDPCSTX4_RDPCSTX_SPARE                                                                       0x2c98
+#define regRDPCSTX4_RDPCSTX_SPARE_BASE_IDX                                                              2
+#define regRDPCSTX4_RDPCSTX_CNTL2                                                                       0x2c99
+#define regRDPCSTX4_RDPCSTX_CNTL2_BASE_IDX                                                              2
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG                                                    0x2c9c
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG_BASE_IDX                                           2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL0                                                                   0x2ca0
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL0_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL1                                                                   0x2ca1
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL1_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL2                                                                   0x2ca2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL2_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL3                                                                   0x2ca3
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL3_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL4                                                                   0x2ca4
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL4_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL5                                                                   0x2ca5
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL5_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL6                                                                   0x2ca6
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL6_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL7                                                                   0x2ca7
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL7_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL8                                                                   0x2ca8
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL8_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL9                                                                   0x2ca9
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL9_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL10                                                                  0x2caa
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL10_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL11                                                                  0x2cab
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL11_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL12                                                                  0x2cac
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL12_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL13                                                                  0x2cad
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL13_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL14                                                                  0x2cae
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL14_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE0                                                                   0x2caf
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE0_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE1                                                                   0x2cb0
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE1_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE2                                                                   0x2cb1
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE2_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE3                                                                   0x2cb2
+#define regRDPCSTX4_RDPCSTX_PHY_FUSE3_BASE_IDX                                                          2
+#define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL                                                               0x2cb3
+#define regRDPCSTX4_RDPCSTX_PHY_RX_LD_VAL_BASE_IDX                                                      2
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3                                                        0x2cb4
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3_BASE_IDX                                               2
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6                                                        0x2cb5
+#define regRDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6_BASE_IDX                                               2
+#define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG                                                           0x2cb6
+#define regRDPCSTX4_RDPCSTX_DPALT_CONTROL_REG_BASE_IDX                                                  2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL15                                                                  0x2cb8
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL15_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL16                                                                  0x2cb9
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL16_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL17                                                                  0x2cba
+#define regRDPCSTX4_RDPCSTX_PHY_CNTL17_BASE_IDX                                                         2
+#define regRDPCSTX4_RDPCS_CNTL3                                                                         0x2cbc
+#define regRDPCSTX4_RDPCS_CNTL3_BASE_IDX                                                                2
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD                                                      0x2cbd
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD_BASE_IDX                                             2
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD                                                      0x2cbe
+#define regRDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD_BASE_IDX                                             2
+
+
+// addressBlock: dpcssys_dcio_dcio_dispdec
+// base address: 0x0
+#define regDC_GENERICA                                                                                  0x2868
+#define regDC_GENERICA_BASE_IDX                                                                         2
+#define regDC_GENERICB                                                                                  0x2869
+#define regDC_GENERICB_BASE_IDX                                                                         2
+#define regDCIO_CLOCK_CNTL                                                                              0x286a
+#define regDCIO_CLOCK_CNTL_BASE_IDX                                                                     2
+#define regDC_REF_CLK_CNTL                                                                              0x286b
+#define regDC_REF_CLK_CNTL_BASE_IDX                                                                     2
+#define regUNIPHYA_LINK_CNTL                                                                            0x286d
+#define regUNIPHYA_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYA_CHANNEL_XBAR_CNTL                                                                    0x286e
+#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYB_LINK_CNTL                                                                            0x286f
+#define regUNIPHYB_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYB_CHANNEL_XBAR_CNTL                                                                    0x2870
+#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYC_LINK_CNTL                                                                            0x2871
+#define regUNIPHYC_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYC_CHANNEL_XBAR_CNTL                                                                    0x2872
+#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYD_LINK_CNTL                                                                            0x2873
+#define regUNIPHYD_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYD_CHANNEL_XBAR_CNTL                                                                    0x2874
+#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regUNIPHYE_LINK_CNTL                                                                            0x2875
+#define regUNIPHYE_LINK_CNTL_BASE_IDX                                                                   2
+#define regUNIPHYE_CHANNEL_XBAR_CNTL                                                                    0x2876
+#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX                                                           2
+#define regDCIO_WRCMD_DELAY                                                                             0x287e
+#define regDCIO_WRCMD_DELAY_BASE_IDX                                                                    2
+#define regDC_PINSTRAPS                                                                                 0x2880
+#define regDC_PINSTRAPS_BASE_IDX                                                                        2
+#define regINTERCEPT_STATE                                                                              0x2884
+#define regINTERCEPT_STATE_BASE_IDX                                                                     2
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL                                                             0x288b
+#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX                                                    2
+#define regDCIO_GSL_GENLK_PAD_CNTL                                                                      0x288c
+#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX                                                             2
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL                                                                   0x288d
+#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX                                                          2
+#define regDCIO_SOFT_RESET                                                                              0x289e
+#define regDCIO_SOFT_RESET_BASE_IDX                                                                     2
+
+
+// addressBlock: dpcssys_dcio_dcio_chip_dispdec
+// base address: 0x0
+#define regDC_GPIO_GENERIC_MASK                                                                         0x28c8
+#define regDC_GPIO_GENERIC_MASK_BASE_IDX                                                                2
+#define regDC_GPIO_GENERIC_A                                                                            0x28c9
+#define regDC_GPIO_GENERIC_A_BASE_IDX                                                                   2
+#define regDC_GPIO_GENERIC_EN                                                                           0x28ca
+#define regDC_GPIO_GENERIC_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_GENERIC_Y                                                                            0x28cb
+#define regDC_GPIO_GENERIC_Y_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_MASK                                                                            0x28d0
+#define regDC_GPIO_DDC1_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC1_A                                                                               0x28d1
+#define regDC_GPIO_DDC1_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC1_EN                                                                              0x28d2
+#define regDC_GPIO_DDC1_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC1_Y                                                                               0x28d3
+#define regDC_GPIO_DDC1_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_MASK                                                                            0x28d4
+#define regDC_GPIO_DDC2_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC2_A                                                                               0x28d5
+#define regDC_GPIO_DDC2_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC2_EN                                                                              0x28d6
+#define regDC_GPIO_DDC2_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC2_Y                                                                               0x28d7
+#define regDC_GPIO_DDC2_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_MASK                                                                            0x28d8
+#define regDC_GPIO_DDC3_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC3_A                                                                               0x28d9
+#define regDC_GPIO_DDC3_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC3_EN                                                                              0x28da
+#define regDC_GPIO_DDC3_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC3_Y                                                                               0x28db
+#define regDC_GPIO_DDC3_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_MASK                                                                            0x28dc
+#define regDC_GPIO_DDC4_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC4_A                                                                               0x28dd
+#define regDC_GPIO_DDC4_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC4_EN                                                                              0x28de
+#define regDC_GPIO_DDC4_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC4_Y                                                                               0x28df
+#define regDC_GPIO_DDC4_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_MASK                                                                            0x28e0
+#define regDC_GPIO_DDC5_MASK_BASE_IDX                                                                   2
+#define regDC_GPIO_DDC5_A                                                                               0x28e1
+#define regDC_GPIO_DDC5_A_BASE_IDX                                                                      2
+#define regDC_GPIO_DDC5_EN                                                                              0x28e2
+#define regDC_GPIO_DDC5_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_DDC5_Y                                                                               0x28e3
+#define regDC_GPIO_DDC5_Y_BASE_IDX                                                                      2
+#define regDC_GPIO_DDCVGA_MASK                                                                          0x28e8
+#define regDC_GPIO_DDCVGA_MASK_BASE_IDX                                                                 2
+#define regDC_GPIO_DDCVGA_A                                                                             0x28e9
+#define regDC_GPIO_DDCVGA_A_BASE_IDX                                                                    2
+#define regDC_GPIO_DDCVGA_EN                                                                            0x28ea
+#define regDC_GPIO_DDCVGA_EN_BASE_IDX                                                                   2
+#define regDC_GPIO_DDCVGA_Y                                                                             0x28eb
+#define regDC_GPIO_DDCVGA_Y_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_MASK                                                                           0x28f0
+#define regDC_GPIO_GENLK_MASK_BASE_IDX                                                                  2
+#define regDC_GPIO_GENLK_A                                                                              0x28f1
+#define regDC_GPIO_GENLK_A_BASE_IDX                                                                     2
+#define regDC_GPIO_GENLK_EN                                                                             0x28f2
+#define regDC_GPIO_GENLK_EN_BASE_IDX                                                                    2
+#define regDC_GPIO_GENLK_Y                                                                              0x28f3
+#define regDC_GPIO_GENLK_Y_BASE_IDX                                                                     2
+#define regDC_GPIO_HPD_MASK                                                                             0x28f4
+#define regDC_GPIO_HPD_MASK_BASE_IDX                                                                    2
+#define regDC_GPIO_HPD_A                                                                                0x28f5
+#define regDC_GPIO_HPD_A_BASE_IDX                                                                       2
+#define regDC_GPIO_HPD_EN                                                                               0x28f6
+#define regDC_GPIO_HPD_EN_BASE_IDX                                                                      2
+#define regDC_GPIO_HPD_Y                                                                                0x28f7
+#define regDC_GPIO_HPD_Y_BASE_IDX                                                                       2
+#define regDC_GPIO_PWRSEQ0_EN                                                                           0x28fa
+#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_PAD_STRENGTH_1                                                                       0x28fc
+#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX                                                              2
+#define regDC_GPIO_PAD_STRENGTH_2                                                                       0x28fd
+#define regDC_GPIO_PAD_STRENGTH_2_BASE_IDX                                                              2
+#define regPHY_AUX_CNTL                                                                                 0x28ff
+#define regPHY_AUX_CNTL_BASE_IDX                                                                        2
+#define regDC_GPIO_PWRSEQ1_EN                                                                           0x2902
+#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX                                                                  2
+#define regDC_GPIO_TX12_EN                                                                              0x2915
+#define regDC_GPIO_TX12_EN_BASE_IDX                                                                     2
+#define regDC_GPIO_AUX_CTRL_0                                                                           0x2916
+#define regDC_GPIO_AUX_CTRL_0_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_1                                                                           0x2917
+#define regDC_GPIO_AUX_CTRL_1_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_2                                                                           0x2918
+#define regDC_GPIO_AUX_CTRL_2_BASE_IDX                                                                  2
+#define regDC_GPIO_RXEN                                                                                 0x2919
+#define regDC_GPIO_RXEN_BASE_IDX                                                                        2
+#define regDC_GPIO_PULLUPEN                                                                             0x291a
+#define regDC_GPIO_PULLUPEN_BASE_IDX                                                                    2
+#define regDC_GPIO_AUX_CTRL_3                                                                           0x291b
+#define regDC_GPIO_AUX_CTRL_3_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_4                                                                           0x291c
+#define regDC_GPIO_AUX_CTRL_4_BASE_IDX                                                                  2
+#define regDC_GPIO_AUX_CTRL_5                                                                           0x291d
+#define regDC_GPIO_AUX_CTRL_5_BASE_IDX                                                                  2
+#define regAUXI2C_PAD_ALL_PWR_OK                                                                        0x291e
+#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX                                                               2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec
+// base address: 0x360
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2a00
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2a01
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2a02
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2a03
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2a04
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2a05
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2a06
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2a07
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2a08
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2a09
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2a0a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2a0b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2a0c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2a0d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2a0e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2a0f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2a10
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2a11
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2a12
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2a13
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2a14
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2a15
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2a16
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2a17
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2a18
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2a19
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2a1a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2a1b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2a1c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2a1d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2a1e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2a1f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2a20
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2a21
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2a22
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2a23
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2a24
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2a25
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2a26
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2a27
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2a28
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2a29
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2a2a
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2a2b
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2a2c
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2a2d
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2a2e
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2a2f
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2a30
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2a31
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2a32
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2a33
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2a34
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2a35
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2a36
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2a37
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2a38
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2a39
+#define regDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec
+// base address: 0x6c0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2ad8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2ad9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2ada
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2adb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2adc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2add
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2ade
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2adf
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2ae0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2ae1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2ae2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2ae3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2ae4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2ae5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2ae6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2ae7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2ae8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2ae9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2aea
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2aeb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2aec
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2aed
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2aee
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2aef
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2af0
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2af1
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2af2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2af3
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2af4
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2af5
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2af6
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2af7
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2af8
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2af9
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2afa
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2afb
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2afc
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2afd
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2afe
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2aff
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2b00
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2b01
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2b02
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2b03
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2b04
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2b05
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2b06
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2b07
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2b08
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2b09
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2b0a
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2b0b
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2b0c
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2b0d
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2b0e
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2b0f
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2b10
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2b11
+#define regDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec
+// base address: 0xa20
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2bb0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2bb1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2bb2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2bb3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2bb4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2bb5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2bb6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2bb7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2bb8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2bb9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2bba
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2bbb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2bbc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2bbd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2bbe
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2bbf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2bc0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2bc1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2bc2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2bc3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2bc4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2bc5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2bc6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2bc7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2bc8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2bc9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2bca
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2bcb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2bcc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2bcd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2bce
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2bcf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2bd0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2bd1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2bd2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2bd3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2bd4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2bd5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2bd6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2bd7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2bd8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2bd9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2bda
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2bdb
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2bdc
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2bdd
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2bde
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2bdf
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2be0
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2be1
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2be2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2be3
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2be4
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2be5
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2be6
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2be7
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2be8
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2be9
+#define regDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec
+// base address: 0xd80
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0                                                     0x2c88
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1                                                     0x2c89
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2                                                     0x2c8a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3                                                     0x2c8b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4                                                     0x2c8c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5                                                     0x2c8d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6                                                     0x2c8e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7                                                     0x2c8f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8                                                     0x2c90
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9                                                     0x2c91
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX                                            2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10                                                    0x2c92
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11                                                    0x2c93
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12                                                    0x2c94
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13                                                    0x2c95
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14                                                    0x2c96
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15                                                    0x2c97
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16                                                    0x2c98
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17                                                    0x2c99
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18                                                    0x2c9a
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19                                                    0x2c9b
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20                                                    0x2c9c
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21                                                    0x2c9d
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22                                                    0x2c9e
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23                                                    0x2c9f
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24                                                    0x2ca0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25                                                    0x2ca1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26                                                    0x2ca2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27                                                    0x2ca3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28                                                    0x2ca4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29                                                    0x2ca5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30                                                    0x2ca6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31                                                    0x2ca7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32                                                    0x2ca8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33                                                    0x2ca9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34                                                    0x2caa
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35                                                    0x2cab
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36                                                    0x2cac
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37                                                    0x2cad
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38                                                    0x2cae
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39                                                    0x2caf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40                                                    0x2cb0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41                                                    0x2cb1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42                                                    0x2cb2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43                                                    0x2cb3
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44                                                    0x2cb4
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45                                                    0x2cb5
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46                                                    0x2cb6
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47                                                    0x2cb7
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48                                                    0x2cb8
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49                                                    0x2cb9
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50                                                    0x2cba
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51                                                    0x2cbb
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52                                                    0x2cbc
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53                                                    0x2cbd
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54                                                    0x2cbe
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55                                                    0x2cbf
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56                                                    0x2cc0
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX                                           2
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57                                                    0x2cc1
+#define regDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX                                           2
+
+
+// addressBlock: dpcssys_cr0_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR0_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR0_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR0_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR0_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR0_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR0_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR0_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR0_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR0_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR0_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR0_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR0_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR0_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR0_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR0_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR0_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR0_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR0_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR0_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR0_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR0_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR0_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR0_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr1_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR1_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR1_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR1_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR1_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR1_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR1_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR1_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR1_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR1_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR1_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR1_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR1_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR1_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR1_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR1_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR1_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR1_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR1_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR1_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR1_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR1_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR1_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR1_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR1_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr2_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR2_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR2_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR2_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR2_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR2_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR2_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR2_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR2_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR2_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR2_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR2_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR2_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR2_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR2_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR2_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR2_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR2_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR2_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR2_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR2_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR2_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR2_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR2_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR2_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr3_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR3_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR3_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR3_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR3_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR3_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR3_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR3_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR3_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR3_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR3_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR3_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR3_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR3_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR3_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR3_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR3_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR3_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR3_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR3_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR3_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR3_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR3_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR3_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR3_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+// addressBlock: dpcssys_cr4_rdpcstxcrind
+// base address: 0x0
+#define ixDPCSSYS_CR4_SUP_DIG_IDCODE_LO                                                                0x0000
+#define ixDPCSSYS_CR4_SUP_DIG_IDCODE_HI                                                                0x0001
+#define ixDPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN                                                           0x0002
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN                                                    0x0003
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                   0x0004
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN                                                    0x0005
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                   0x0006
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0                                                          0x0007
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1                                                          0x0008
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2                                                          0x0009
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1                                                         0x000a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2                                                         0x000b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1                                                     0x000c
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2                                                     0x000d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3                                                          0x000e
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4                                                          0x000f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5                                                          0x0010
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN                                                         0x0011
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN                                                      0x0012
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0                                                          0x0013
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1                                                          0x0014
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2                                                          0x0015
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1                                                         0x0016
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2                                                         0x0017
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1                                                     0x0018
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2                                                     0x0019
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3                                                          0x001a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4                                                          0x001b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5                                                          0x001c
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN                                                         0x001d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN                                                      0x001e
+#define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN                                                              0x001f
+#define ixDPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN                                                        0x0020
+#define ixDPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT                                                             0x0021
+#define ixDPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN                                                              0x0022
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0                                                          0x0024
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1                                                          0x0025
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2                                                          0x0026
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3                                                          0x0027
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4                                                          0x0028
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5                                                          0x0029
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6                                                          0x002a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0                                                          0x002b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1                                                          0x002c
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2                                                          0x002d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3                                                          0x002e
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4                                                          0x002f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5                                                          0x0030
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6                                                          0x0031
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN                                                    0x0032
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                   0x0033
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN                                                    0x0034
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                   0x0035
+#define ixDPCSSYS_CR4_SUP_DIG_ASIC_IN                                                                  0x0036
+#define ixDPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN                                                              0x0037
+#define ixDPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN                                                          0x0038
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN                                                         0x0039
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN                                                      0x003a
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN                                                         0x003b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN                                                      0x003c
+#define ixDPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL                                                           0x0040
+#define ixDPCSSYS_CR4_SUP_ANA_RTUNE_CTRL                                                               0x0041
+#define ixDPCSSYS_CR4_SUP_ANA_BG1                                                                      0x0042
+#define ixDPCSSYS_CR4_SUP_ANA_BG2                                                                      0x0043
+#define ixDPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS                                                          0x0044
+#define ixDPCSSYS_CR4_SUP_ANA_BG3                                                                      0x0045
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC1                                                              0x0046
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_MISC2                                                              0x0047
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_OVRD                                                               0x0048
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB1                                                               0x0049
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB2                                                               0x004a
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_ATB3                                                               0x004b
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR1                                                               0x004c
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR2                                                               0x004d
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR3                                                               0x004e
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR4                                                               0x004f
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_CTR5                                                               0x0050
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1                                                          0x0051
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2                                                          0x0052
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC1                                                              0x0053
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_MISC2                                                              0x0054
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_OVRD                                                               0x0055
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB1                                                               0x0056
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB2                                                               0x0057
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_ATB3                                                               0x0058
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR1                                                               0x0059
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR2                                                               0x005a
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR3                                                               0x005b
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR4                                                               0x005c
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_CTR5                                                               0x005d
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1                                                          0x005e
+#define ixDPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2                                                          0x005f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                             0x0061
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                  0x0062
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x0063
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0064
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0065
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0066
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0067
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                              0x0068
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0069
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                                0x006b
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                             0x006d
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                  0x006e
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                     0x006f
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                      0x0070
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                           0x0071
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                               0x0072
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                             0x0073
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                              0x0074
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                      0x0075
+#define ixDPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                                0x0077
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0                                                  0x0078
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1                                                  0x0079
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2                                                  0x007a
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0                                                 0x007b
+#define ixDPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD                                                        0x007c
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG                                                             0x0081
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_STAT                                                               0x0082
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL                                                         0x0083
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL                                                       0x0084
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL                                                       0x0085
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT                                                            0x0086
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT                                                          0x0087
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT                                                          0x0088
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0                                                        0x0089
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1                                                        0x008a
+#define ixDPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE                                                        0x008b
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0                                                     0x008c
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1                                                     0x008d
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2                                                     0x008e
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0                                                     0x008f
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1                                                     0x0090
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2                                                     0x0091
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT                                                       0x0092
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_STAT                                                                 0x0093
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT                                                          0x0094
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                  0x0095
+#define ixDPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                  0x0096
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN                                                      0x1000
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0                                                      0x1001
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1                                                      0x1002
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2                                                      0x1003
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3                                                      0x1004
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4                                                      0x1005
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT                                                       0x1006
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0                                                     0x100f
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN                                                      0x1010
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0                                                      0x1011
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1                                                      0x1012
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2                                                      0x1013
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT                                                       0x1014
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0                                                     0x101b
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5                                                      0x101d
+#define ixDPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1                                                     0x101e
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1020
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1021
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1022
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1023
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1024
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1025
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1026
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1027
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1028
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1029
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x102a
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x102b
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x102c
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x102d
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x102e
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x102f
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1030
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1031
+#define ixDPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL                                                           0x1032
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1                                                       0x1080
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK                                                       0x1081
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0                                                     0x1082
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1                                                     0x1083
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0                                                      0x1084
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1                                                      0x1085
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1                                                      0x1086
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0                                                     0x1087
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1                                                     0x1088
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2                                                     0x1089
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3                                                     0x108a
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4                                                     0x108b
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5                                                     0x108c
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6                                                     0x108d
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x108e
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2                                                     0x108f
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3                                                     0x1090
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4                                                     0x1091
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5                                                     0x1092
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2                                                      0x1093
+#define ixDPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP                                                      0x1094
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT                                                        0x10a0
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x10a1
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x10a2
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x10a3
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x10a4
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x10a5
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x10a6
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x10a7
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x10a8
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0                                                           0x10bb
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x10c2
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x10c3
+#define ixDPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2                                                      0x10c4
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS                                                           0x10e0
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD                                                            0x10e1
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS                                                             0x10e2
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB1                                                                0x10e3
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_ATB2                                                                0x10e4
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC                                                             0x10e5
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1                                                           0x10e6
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE                                                           0x10e7
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL                                                      0x10e8
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK                                                            0x10e9
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC1                                                               0x10ea
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC2                                                               0x10eb
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_MISC3                                                               0x10ec
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED2                                                           0x10ed
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED3                                                           0x10ee
+#define ixDPCSSYS_CR4_LANE0_ANA_TX_RESERVED4                                                           0x10ef
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN                                                      0x1100
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0                                                      0x1101
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1                                                      0x1102
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2                                                      0x1103
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3                                                      0x1104
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4                                                      0x1105
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT                                                       0x1106
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0                                                      0x1107
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1                                                      0x1108
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2                                                      0x1109
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3                                                      0x110a
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4                                                      0x110b
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5                                                      0x110c
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x110d
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x110e
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0                                                     0x110f
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN                                                      0x1110
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0                                                      0x1111
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1                                                      0x1112
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2                                                      0x1113
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT                                                       0x1114
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0                                                      0x1115
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1                                                      0x1116
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1117
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1118
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1119
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x111a
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0                                                     0x111b
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6                                                      0x111c
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5                                                      0x111d
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1                                                     0x111e
+#define ixDPCSSYS_CR4_LANE1_DIG_ASIC_OCLA                                                              0x111f
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1120
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1121
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1122
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1123
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1124
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1125
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1126
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1127
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1128
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1129
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x112a
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x112b
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x112c
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x112d
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x112e
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x112f
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1130
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1131
+#define ixDPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL                                                           0x1132
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1140
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1141
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1142
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1143
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1145
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1146
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1147
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1148
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1149
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x114a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x114b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x114c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x114d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x114e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x114f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1150
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL                                                           0x1151
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR                                                           0x1152
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0                                                       0x1153
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1                                                       0x1154
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2                                                       0x1155
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3                                                       0x1156
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4                                                       0x1157
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT                                                            0x1158
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ                                                           0x1159
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x115a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x115b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1160
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1161
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1162
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1163
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1164
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1165
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1166
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1167
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1168
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1169
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x116a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x116b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x116c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x116d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x116e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x116f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1170
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1171
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1172
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1173
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1174
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1175
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1176
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1177
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1178
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1179
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x117a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x117b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x117c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x117d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x117e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x117f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1                                                       0x1180
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK                                                       0x1181
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0                                                     0x1182
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1                                                     0x1183
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0                                                      0x1184
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1                                                      0x1185
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1                                                      0x1186
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0                                                     0x1187
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1                                                     0x1188
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2                                                     0x1189
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3                                                     0x118a
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4                                                     0x118b
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5                                                     0x118c
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6                                                     0x118d
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x118e
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2                                                     0x118f
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3                                                     0x1190
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4                                                     0x1191
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5                                                     0x1192
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2                                                      0x1193
+#define ixDPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP                                                      0x1194
+#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL                                                        0x1195
+#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1196
+#define ixDPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1197
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT                                                        0x11a0
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x11a1
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x11a2
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x11a3
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x11a4
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x11a5
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x11a6
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x11a7
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x11a8
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x11a9
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x11aa
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x11ab
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x11ac
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x11ad
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL                                                             0x11ae
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL                                                        0x11af
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x11b0
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x11b1
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA                                                     0x11b2
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE                                                        0x11b3
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE                                                           0x11b4
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL                                                     0x11b5
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x11b6
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x11b7
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x11b8
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x11b9
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x11ba
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0                                                           0x11bb
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1                                                           0x11bc
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x11bd
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x11be
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT                                                      0x11bf
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x11c0
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x11c1
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x11c2
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x11c3
+#define ixDPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2                                                      0x11c4
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS                                                           0x11e0
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD                                                            0x11e1
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS                                                             0x11e2
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB1                                                                0x11e3
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_ATB2                                                                0x11e4
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC                                                             0x11e5
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1                                                           0x11e6
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE                                                           0x11e7
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL                                                      0x11e8
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK                                                            0x11e9
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC1                                                               0x11ea
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC2                                                               0x11eb
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_MISC3                                                               0x11ec
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED2                                                           0x11ed
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED3                                                           0x11ee
+#define ixDPCSSYS_CR4_LANE1_ANA_TX_RESERVED4                                                           0x11ef
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_1                                                               0x11f0
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CLK_2                                                               0x11f1
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CDR_DES                                                             0x11f2
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL                                                            0x11f3
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1                                                           0x11f4
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2                                                           0x11f5
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_SQ                                                                  0x11f6
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL1                                                                0x11f7
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_CAL2                                                                0x11f8
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF                                                          0x11f9
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1                                                           0x11fa
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2                                                           0x11fb
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3                                                           0x11fc
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4                                                           0x11fd
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC                                                             0x11fe
+#define ixDPCSSYS_CR4_LANE1_ANA_RX_RESERVED1                                                           0x11ff
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN                                                      0x1200
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0                                                      0x1201
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1                                                      0x1202
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2                                                      0x1203
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3                                                      0x1204
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4                                                      0x1205
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT                                                       0x1206
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0                                                      0x1207
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1                                                      0x1208
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2                                                      0x1209
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3                                                      0x120a
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4                                                      0x120b
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5                                                      0x120c
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x120d
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x120e
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0                                                     0x120f
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN                                                      0x1210
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0                                                      0x1211
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1                                                      0x1212
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2                                                      0x1213
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT                                                       0x1214
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0                                                      0x1215
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1                                                      0x1216
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x1217
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x1218
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x1219
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x121a
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0                                                     0x121b
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6                                                      0x121c
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5                                                      0x121d
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1                                                     0x121e
+#define ixDPCSSYS_CR4_LANE2_DIG_ASIC_OCLA                                                              0x121f
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1220
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1221
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1222
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1223
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1224
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1225
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1226
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1227
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1228
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1229
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x122a
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x122b
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x122c
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x122d
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x122e
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x122f
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1230
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1231
+#define ixDPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL                                                           0x1232
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x1240
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x1241
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x1242
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x1243
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x1245
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x1246
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x1247
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x1248
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x1249
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x124a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x124b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x124c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x124d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x124e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x124f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x1250
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL                                                           0x1251
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR                                                           0x1252
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0                                                       0x1253
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1                                                       0x1254
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2                                                       0x1255
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3                                                       0x1256
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4                                                       0x1257
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT                                                            0x1258
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ                                                           0x1259
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x125a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x125b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x1260
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x1261
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x1262
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x1263
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x1264
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x1265
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x1266
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x1267
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x1268
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x1269
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x126a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x126b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x126c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x126d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x126e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x126f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x1270
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x1271
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x1272
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x1273
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x1274
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x1275
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x1276
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x1277
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x1278
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x1279
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x127a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x127b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x127c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x127d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x127e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x127f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1                                                       0x1280
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK                                                       0x1281
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0                                                     0x1282
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1                                                     0x1283
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0                                                      0x1284
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1                                                      0x1285
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1                                                      0x1286
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0                                                     0x1287
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1                                                     0x1288
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2                                                     0x1289
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3                                                     0x128a
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4                                                     0x128b
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5                                                     0x128c
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6                                                     0x128d
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x128e
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2                                                     0x128f
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3                                                     0x1290
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4                                                     0x1291
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5                                                     0x1292
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2                                                      0x1293
+#define ixDPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP                                                      0x1294
+#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL                                                        0x1295
+#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL                                                    0x1296
+#define ixDPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x1297
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT                                                        0x12a0
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x12a1
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x12a2
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x12a3
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x12a4
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x12a5
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x12a6
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x12a7
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x12a8
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x12a9
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x12aa
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x12ab
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x12ac
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x12ad
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL                                                             0x12ae
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL                                                        0x12af
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x12b0
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x12b1
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA                                                     0x12b2
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE                                                        0x12b3
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE                                                           0x12b4
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL                                                     0x12b5
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x12b6
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x12b7
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x12b8
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x12b9
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x12ba
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0                                                           0x12bb
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1                                                           0x12bc
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x12bd
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x12be
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT                                                      0x12bf
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x12c0
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x12c1
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x12c2
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x12c3
+#define ixDPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2                                                      0x12c4
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS                                                           0x12e0
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD                                                            0x12e1
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS                                                             0x12e2
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB1                                                                0x12e3
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_ATB2                                                                0x12e4
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC                                                             0x12e5
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1                                                           0x12e6
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE                                                           0x12e7
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL                                                      0x12e8
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK                                                            0x12e9
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC1                                                               0x12ea
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC2                                                               0x12eb
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_MISC3                                                               0x12ec
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED2                                                           0x12ed
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED3                                                           0x12ee
+#define ixDPCSSYS_CR4_LANE2_ANA_TX_RESERVED4                                                           0x12ef
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_1                                                               0x12f0
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CLK_2                                                               0x12f1
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CDR_DES                                                             0x12f2
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL                                                            0x12f3
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1                                                           0x12f4
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2                                                           0x12f5
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_SQ                                                                  0x12f6
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL1                                                                0x12f7
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_CAL2                                                                0x12f8
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF                                                          0x12f9
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1                                                           0x12fa
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2                                                           0x12fb
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3                                                           0x12fc
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4                                                           0x12fd
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC                                                             0x12fe
+#define ixDPCSSYS_CR4_LANE2_ANA_RX_RESERVED1                                                           0x12ff
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN                                                      0x1300
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0                                                      0x1301
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1                                                      0x1302
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2                                                      0x1303
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3                                                      0x1304
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4                                                      0x1305
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT                                                       0x1306
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0                                                     0x130f
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN                                                      0x1310
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0                                                      0x1311
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1                                                      0x1312
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2                                                      0x1313
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT                                                       0x1314
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0                                                     0x131b
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5                                                      0x131d
+#define ixDPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1                                                     0x131e
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x1320
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x1321
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x1322
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x1323
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x1324
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x1325
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x1326
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x1327
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x1328
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x1329
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x132a
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x132b
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x132c
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x132d
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x132e
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x132f
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x1330
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x1331
+#define ixDPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL                                                           0x1332
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1                                                       0x1380
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK                                                       0x1381
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0                                                     0x1382
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1                                                     0x1383
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0                                                      0x1384
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1                                                      0x1385
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1                                                      0x1386
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0                                                     0x1387
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1                                                     0x1388
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2                                                     0x1389
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3                                                     0x138a
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4                                                     0x138b
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5                                                     0x138c
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6                                                     0x138d
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x138e
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2                                                     0x138f
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3                                                     0x1390
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4                                                     0x1391
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5                                                     0x1392
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2                                                      0x1393
+#define ixDPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP                                                      0x1394
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT                                                        0x13a0
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x13a1
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x13a2
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x13a3
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x13a4
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x13a5
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x13a6
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x13a7
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x13a8
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0                                                           0x13bb
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x13c2
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x13c3
+#define ixDPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2                                                      0x13c4
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS                                                           0x13e0
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD                                                            0x13e1
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS                                                             0x13e2
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB1                                                                0x13e3
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_ATB2                                                                0x13e4
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC                                                             0x13e5
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1                                                           0x13e6
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE                                                           0x13e7
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL                                                      0x13e8
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK                                                            0x13e9
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC1                                                               0x13ea
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC2                                                               0x13eb
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_MISC3                                                               0x13ec
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED2                                                           0x13ed
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED3                                                           0x13ee
+#define ixDPCSSYS_CR4_LANE3_ANA_TX_RESERVED4                                                           0x13ef
+#define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL                                                               0x2000
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN                                                         0x2001
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN                                                      0x2002
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0                                               0x2003
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN                                                         0x2004
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN                                                      0x2005
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0                                               0x2006
+#define ixDPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND                                                      0x2007
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1                                               0x2008
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1                                               0x2009
+#define ixDPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1                                                             0x200a
+#define ixDPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL                                                        0x200b
+#define ixDPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE                                                           0x200c
+#define ixDPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE                                                        0x200d
+#define ixDPCSSYS_CR4_RAWCMN_DIG_OCLA                                                                  0x200e
+#define ixDPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD                                                          0x200f
+#define ixDPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE                                                       0x2010
+#define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1                                                          0x2011
+#define ixDPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2                                                          0x2012
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0                                                0x2020
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0                                              0x2021
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0                                              0x2022
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1                                                0x2023
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1                                              0x2024
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1                                              0x2025
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2                                                0x2026
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2                                              0x2027
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2                                              0x2028
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3                                                0x2029
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3                                              0x202a
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3                                              0x202b
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4                                                0x202c
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4                                              0x202d
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4                                              0x202e
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5                                                0x202f
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5                                              0x2030
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5                                              0x2031
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6                                                0x2032
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6                                              0x2033
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6                                              0x2034
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7                                                0x2035
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7                                              0x2036
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7                                              0x2037
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG                                                   0x2038
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN                                                    0x2039
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT                                                   0x203a
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN                                                   0x203b
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS                                                    0x203c
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN                                                   0x203d
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT                                               0x203e
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD                                                0x203f
+#define ixDPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1                                                0x2040
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN                                                   0x3000
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3001
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN                                                    0x3002
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3003
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT                                                   0x3004
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN                                                   0x3005
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3006
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3007
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3008
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN                                                    0x3009
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1                                                  0x300a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2                                                  0x300b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3                                                  0x300c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4                                                  0x300d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT                                                  0x300e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT                                                   0x300f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3010
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3011
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3012
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3013
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3014
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER                                                  0x3015
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1                                                   0x3016
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2                                                   0x3017
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3018
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3019
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x301a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x301b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x301c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x301d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x301e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL                                                   0x301f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL                                                    0x3020
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON                                                    0x3021
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON                                                      0x3022
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3023
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT                                                   0x3024
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3025
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3026
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3027
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3028
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3029
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x302a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x302b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP                                                        0x302c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE                                                0x302d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET                                                   0x302e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP                                                   0x302f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3030
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3031
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3032
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3033
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3034
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3035
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3036
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3037
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS                                                      0x3038
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK                                                         0x3039
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS                                                    0x303a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS                                                   0x303b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA                                                            0x303c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x303d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x303e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x303f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3040
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3041
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3042
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3043
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3044
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3045
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3046
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3047
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3048
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3049
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x304a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x304b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x304c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK                                                    0x304d
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x304e
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x304f
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3050
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3051
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3052
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3053
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3054
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3055
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3056
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3057
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3058
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3059
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x305a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x305b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3060
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3061
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3062
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN                                                   0x3063
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3064
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN                                                    0x3065
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3066
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN                                                    0x3067
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3068
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3069
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x306a
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x306b
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x306c
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL                                                   0x3080
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL                                                   0x3081
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3082
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA                                                         0x3083
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA                                                    0x3084
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL                                                   0x30a0
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x30a1
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x30a2
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x30a3
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x30a4
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA                                                    0x30a5
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x30c0
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x30c1
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x30c2
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x30c3
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x30c4
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x30c5
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x30c6
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x30c7
+#define ixDPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x30c8
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN                                                   0x3100
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3101
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN                                                    0x3102
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3103
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT                                                   0x3104
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN                                                   0x3105
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3106
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3107
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3108
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN                                                    0x3109
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1                                                  0x310a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2                                                  0x310b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3                                                  0x310c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4                                                  0x310d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT                                                  0x310e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT                                                   0x310f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3110
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3111
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3112
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3113
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3114
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER                                                  0x3115
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1                                                   0x3116
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2                                                   0x3117
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3118
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3119
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x311a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x311b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x311c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x311d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x311e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL                                                   0x311f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL                                                    0x3120
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON                                                    0x3121
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON                                                      0x3122
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3123
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT                                                   0x3124
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3125
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3126
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3127
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3128
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3129
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x312a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x312b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP                                                        0x312c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE                                                0x312d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET                                                   0x312e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP                                                   0x312f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3130
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3131
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3132
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3133
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3134
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3135
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3136
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3137
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS                                                      0x3138
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK                                                         0x3139
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS                                                    0x313a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS                                                   0x313b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA                                                            0x313c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x313d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x313e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x313f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3140
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3141
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3142
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3143
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3144
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3145
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3146
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3147
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3148
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3149
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x314a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x314b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x314c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK                                                    0x314d
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x314e
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x314f
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3150
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3151
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3152
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3153
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3154
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3155
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3156
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3157
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3158
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3159
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x315a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x315b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3160
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3161
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3162
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN                                                   0x3163
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3164
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN                                                    0x3165
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3166
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN                                                    0x3167
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3168
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3169
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x316a
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x316b
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x316c
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL                                                   0x3180
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL                                                   0x3181
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3182
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA                                                         0x3183
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA                                                    0x3184
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL                                                   0x31a0
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x31a1
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x31a2
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x31a3
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x31a4
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA                                                    0x31a5
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x31c0
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x31c1
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x31c2
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x31c3
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x31c4
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x31c5
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x31c6
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x31c7
+#define ixDPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x31c8
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN                                                   0x3200
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3201
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN                                                    0x3202
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3203
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT                                                   0x3204
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN                                                   0x3205
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3206
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3207
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3208
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN                                                    0x3209
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1                                                  0x320a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2                                                  0x320b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3                                                  0x320c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4                                                  0x320d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT                                                  0x320e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT                                                   0x320f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3210
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3211
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3212
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3213
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3214
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER                                                  0x3215
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1                                                   0x3216
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2                                                   0x3217
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3218
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3219
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x321a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x321b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x321c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x321d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x321e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL                                                   0x321f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL                                                    0x3220
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON                                                    0x3221
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON                                                      0x3222
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3223
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT                                                   0x3224
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3225
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3226
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3227
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3228
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3229
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x322a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x322b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP                                                        0x322c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE                                                0x322d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET                                                   0x322e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP                                                   0x322f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3230
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3231
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3232
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3233
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3234
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3235
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3236
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3237
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS                                                      0x3238
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK                                                         0x3239
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS                                                    0x323a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS                                                   0x323b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA                                                            0x323c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x323d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x323e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x323f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3240
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3241
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3242
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3243
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3244
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3245
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3246
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3247
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3248
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3249
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x324a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x324b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x324c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK                                                    0x324d
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x324e
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x324f
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3250
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3251
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3252
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3253
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3254
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3255
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3256
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3257
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3258
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3259
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x325a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x325b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3260
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3261
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3262
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN                                                   0x3263
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3264
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN                                                    0x3265
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3266
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN                                                    0x3267
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3268
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3269
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x326a
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x326b
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x326c
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL                                                   0x3280
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL                                                   0x3281
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3282
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA                                                         0x3283
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA                                                    0x3284
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL                                                   0x32a0
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x32a1
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x32a2
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x32a3
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x32a4
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA                                                    0x32a5
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x32c0
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x32c1
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x32c2
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x32c3
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x32c4
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x32c5
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x32c6
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x32c7
+#define ixDPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x32c8
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN                                                   0x3300
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1                                                 0x3301
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN                                                    0x3302
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT                                                  0x3303
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT                                                   0x3304
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN                                                   0x3305
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1                                                 0x3306
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2                                                 0x3307
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3                                                 0x3308
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN                                                    0x3309
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1                                                  0x330a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2                                                  0x330b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3                                                  0x330c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4                                                  0x330d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT                                                  0x330e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT                                                   0x330f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK                                                 0x3310
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM                                                 0x3311
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR                                                 0x3312
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR                                                0x3313
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR                                                0x3314
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER                                                  0x3315
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1                                                   0x3316
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2                                                   0x3317
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN                                                  0x3318
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0x3319
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0x331a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0x331b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1                                                0x331c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0x331d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0x331e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL                                                   0x331f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL                                                    0x3320
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON                                                    0x3321
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON                                                      0x3322
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL                                             0x3323
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT                                                   0x3324
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL                                                 0x3325
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL                                                 0x3326
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL                                              0x3327
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL                                              0x3328
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL                                                  0x3329
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT                                               0x332a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT                                               0x332b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP                                                        0x332c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE                                                0x332d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET                                                   0x332e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP                                                   0x332f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT                                                0x3330
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL                                                 0x3331
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS                                              0x3332
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0x3333
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT                                              0x3334
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0x3335
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0x3336
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0x3337
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS                                                      0x3338
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK                                                         0x3339
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS                                                    0x333a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS                                                   0x333b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA                                                            0x333c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0x333d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS                                              0x333e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0x333f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ                                               0x3340
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ                                                0x3341
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0x3342
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0x3343
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0x3344
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0x3345
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0x3346
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0x3347
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0x3348
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0x3349
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0x334a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0x334b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0x334c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK                                                    0x334d
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2                                                  0x334e
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0x334f
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0x3350
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0x3351
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0x3352
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0x3353
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0x3354
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0x3355
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0x3356
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0x3357
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ                                                0x3358
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0x3359
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0x335a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0x335b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN                                                 0x3360
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT                                                0x3361
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN                                                  0x3362
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN                                                   0x3363
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT                                                  0x3364
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN                                                    0x3365
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT                                                  0x3366
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN                                                    0x3367
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL                                               0x3368
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1                                                 0x3369
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN                                                 0x336a
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT                                                0x336b
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0x336c
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL                                                   0x3380
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL                                                   0x3381
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0x3382
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA                                                         0x3383
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA                                                    0x3384
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL                                                   0x33a0
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0x33a1
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0x33a2
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0x33a3
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0x33a4
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA                                                    0x33a5
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0x33c0
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0x33c1
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0x33c2
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0x33c3
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0x33c4
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0x33c5
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0x33c6
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2                                                0x33c7
+#define ixDPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2                                                 0x33c8
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST                                                0x4000
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST                                               0x4001
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ                                                       0x4002
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM                                                     0x4003
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4004
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4005
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4006
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL                                                 0x4007
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL                                                  0x4008
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN                                                    0x4009
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP                                                    0x400a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x400b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x400c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x400d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x400e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x400f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4010
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4011
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4012
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST                                               0x4013
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE                                                0x4014
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE                                                0x4015
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE                                                  0x4016
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT                                                      0x4017
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA                                                      0x4018
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE                                                     0x4019
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1                                                 0x401a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE                                                    0x401b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS                                                       0x401c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2                                                 0x401d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3                                                 0x401e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4                                                 0x401f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5                                                 0x4020
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN                                              0x4021
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD                                               0x4022
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4023
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0                                                       0x4024
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1                                                       0x4025
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2                                                       0x4026
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3                                                       0x4027
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4                                                       0x4028
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5                                                       0x4029
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6                                                       0x402a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7                                                       0x402b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE                                                     0x402c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2                                                     0x402d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x402e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN                                                     0x402f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL                                                  0x4030
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL                                              0x4031
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_STATS                                                            0x4032
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1                                                    0x4033
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2                                                    0x4034
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3                                                    0x4035
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL                                                    0x4036
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE                                                0x4037
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE                                                0x4038
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN                                                    0x4039
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE                                                    0x403a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE                                                  0x403b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE                                                 0x403c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x403d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x403e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x403f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4040
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4041
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4042
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4043
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4044
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR                                                 0x4045
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA                                                 0x4046
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT                                                      0x4047
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL                                                      0x4048
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD                                                  0x4049
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN                                                    0x404a
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG                                                     0x404b
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG                                                   0x404c
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG                                                  0x404d
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x404e
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN                                                0x404f
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG                                                 0x4050
+#define ixDPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG                                                    0x4051
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST                                                0x4100
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST                                               0x4101
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ                                                       0x4102
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM                                                     0x4103
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4104
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4105
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4106
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL                                                 0x4107
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL                                                  0x4108
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN                                                    0x4109
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP                                                    0x410a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x410b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x410c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x410d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x410e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x410f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4110
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4111
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4112
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST                                               0x4113
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE                                                0x4114
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE                                                0x4115
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE                                                  0x4116
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT                                                      0x4117
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA                                                      0x4118
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE                                                     0x4119
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1                                                 0x411a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE                                                    0x411b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS                                                       0x411c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2                                                 0x411d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3                                                 0x411e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4                                                 0x411f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5                                                 0x4120
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN                                              0x4121
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD                                               0x4122
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4123
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0                                                       0x4124
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1                                                       0x4125
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2                                                       0x4126
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3                                                       0x4127
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4                                                       0x4128
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5                                                       0x4129
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6                                                       0x412a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7                                                       0x412b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE                                                     0x412c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2                                                     0x412d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x412e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN                                                     0x412f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL                                                  0x4130
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL                                              0x4131
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_STATS                                                            0x4132
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1                                                    0x4133
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2                                                    0x4134
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3                                                    0x4135
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL                                                    0x4136
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE                                                0x4137
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE                                                0x4138
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN                                                    0x4139
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE                                                    0x413a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE                                                  0x413b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE                                                 0x413c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x413d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x413e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x413f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4140
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4141
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4142
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4143
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4144
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR                                                 0x4145
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA                                                 0x4146
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT                                                      0x4147
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL                                                      0x4148
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD                                                  0x4149
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN                                                    0x414a
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG                                                     0x414b
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG                                                   0x414c
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG                                                  0x414d
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x414e
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN                                                0x414f
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG                                                 0x4150
+#define ixDPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG                                                    0x4151
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST                                                0x4200
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST                                               0x4201
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ                                                       0x4202
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM                                                     0x4203
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4204
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4205
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4206
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL                                                 0x4207
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL                                                  0x4208
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN                                                    0x4209
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP                                                    0x420a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x420b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x420c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x420d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x420e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x420f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4210
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4211
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4212
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST                                               0x4213
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE                                                0x4214
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE                                                0x4215
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE                                                  0x4216
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT                                                      0x4217
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA                                                      0x4218
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE                                                     0x4219
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1                                                 0x421a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE                                                    0x421b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS                                                       0x421c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2                                                 0x421d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3                                                 0x421e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4                                                 0x421f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5                                                 0x4220
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN                                              0x4221
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD                                               0x4222
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4223
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0                                                       0x4224
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1                                                       0x4225
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2                                                       0x4226
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3                                                       0x4227
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4                                                       0x4228
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5                                                       0x4229
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6                                                       0x422a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7                                                       0x422b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE                                                     0x422c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2                                                     0x422d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x422e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN                                                     0x422f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL                                                  0x4230
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL                                              0x4231
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_STATS                                                            0x4232
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1                                                    0x4233
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2                                                    0x4234
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3                                                    0x4235
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL                                                    0x4236
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE                                                0x4237
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE                                                0x4238
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN                                                    0x4239
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE                                                    0x423a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE                                                  0x423b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE                                                 0x423c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x423d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x423e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x423f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4240
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4241
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4242
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4243
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4244
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR                                                 0x4245
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA                                                 0x4246
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT                                                      0x4247
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL                                                      0x4248
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD                                                  0x4249
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN                                                    0x424a
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG                                                     0x424b
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG                                                   0x424c
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG                                                  0x424d
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x424e
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN                                                0x424f
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG                                                 0x4250
+#define ixDPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG                                                    0x4251
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST                                                0x4300
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST                                               0x4301
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ                                                       0x4302
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM                                                     0x4303
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x4304
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x4305
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x4306
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL                                                 0x4307
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL                                                  0x4308
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN                                                    0x4309
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP                                                    0x430a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x430b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x430c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x430d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x430e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x430f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x4310
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x4311
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x4312
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST                                               0x4313
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE                                                0x4314
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE                                                0x4315
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE                                                  0x4316
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT                                                      0x4317
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA                                                      0x4318
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE                                                     0x4319
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1                                                 0x431a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE                                                    0x431b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS                                                       0x431c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2                                                 0x431d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3                                                 0x431e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4                                                 0x431f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5                                                 0x4320
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN                                              0x4321
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD                                               0x4322
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x4323
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0                                                       0x4324
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1                                                       0x4325
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2                                                       0x4326
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3                                                       0x4327
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4                                                       0x4328
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5                                                       0x4329
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6                                                       0x432a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7                                                       0x432b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE                                                     0x432c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2                                                     0x432d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x432e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN                                                     0x432f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL                                                  0x4330
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL                                              0x4331
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_STATS                                                            0x4332
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1                                                    0x4333
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2                                                    0x4334
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3                                                    0x4335
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL                                                    0x4336
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE                                                0x4337
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE                                                0x4338
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN                                                    0x4339
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE                                                    0x433a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE                                                  0x433b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE                                                 0x433c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x433d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x433e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x433f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x4340
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x4341
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x4342
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x4343
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x4344
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR                                                 0x4345
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA                                                 0x4346
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT                                                      0x4347
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL                                                      0x4348
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD                                                  0x4349
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN                                                    0x434a
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG                                                     0x434b
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG                                                   0x434c
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG                                                  0x434d
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x434e
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN                                                0x434f
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG                                                 0x4350
+#define ixDPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG                                                    0x4351
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST                                                0x7000
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST                                               0x7001
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ                                                       0x7002
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM                                                     0x7003
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST                                         0x7004
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST                                         0x7005
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST                                          0x7006
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL                                                 0x7007
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL                                                  0x7008
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN                                                    0x7009
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP                                                    0x700a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST                                     0x700b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST                                      0x700c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST                                      0x700d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST                                       0x700e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST                                        0x700f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST                                         0x7010
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST                                         0x7011
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST                                          0x7012
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST                                               0x7013
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE                                                0x7014
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE                                                0x7015
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE                                                  0x7016
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT                                                      0x7017
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA                                                      0x7018
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE                                                     0x7019
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1                                                 0x701a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE                                                    0x701b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS                                                       0x701c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2                                                 0x701d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3                                                 0x701e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4                                                 0x701f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5                                                 0x7020
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN                                              0x7021
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD                                               0x7022
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS                                          0x7023
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0                                                       0x7024
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1                                                       0x7025
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2                                                       0x7026
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3                                                       0x7027
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4                                                       0x7028
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5                                                       0x7029
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6                                                       0x702a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7                                                       0x702b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE                                                     0x702c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2                                                     0x702d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS                                          0x702e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN                                                     0x702f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL                                                  0x7030
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL                                              0x7031
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_STATS                                                            0x7032
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1                                                    0x7033
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2                                                    0x7034
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3                                                    0x7035
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL                                                    0x7036
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE                                                0x7037
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE                                                0x7038
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN                                                    0x7039
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE                                                    0x703a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE                                                  0x703b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE                                                 0x703c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0                                            0x703d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0                                            0x703e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0                                            0x703f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0                                            0x7040
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1                                            0x7041
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1                                            0x7042
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1                                            0x7043
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1                                            0x7044
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR                                                 0x7045
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA                                                 0x7046
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT                                                      0x7047
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL                                                      0x7048
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD                                                  0x7049
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN                                                    0x704a
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG                                                     0x704b
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG                                                   0x704c
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG                                                  0x704d
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN                                           0x704e
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN                                                0x704f
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG                                                 0x7050
+#define ixDPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG                                                    0x7051
+#define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_LO                                                               0x8000
+#define ixDPCSSYS_CR4_SUPX_DIG_IDCODE_HI                                                               0x8001
+#define ixDPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN                                                          0x8002
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN                                                   0x8003
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN                                                  0x8004
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN                                                   0x8005
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN                                                  0x8006
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0                                                         0x8007
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1                                                         0x8008
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2                                                         0x8009
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1                                                        0x800a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2                                                        0x800b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1                                                    0x800c
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2                                                    0x800d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3                                                         0x800e
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4                                                         0x800f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5                                                         0x8010
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN                                                        0x8011
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN                                                     0x8012
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0                                                         0x8013
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1                                                         0x8014
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2                                                         0x8015
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1                                                        0x8016
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2                                                        0x8017
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1                                                    0x8018
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2                                                    0x8019
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3                                                         0x801a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4                                                         0x801b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5                                                         0x801c
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN                                                        0x801d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN                                                     0x801e
+#define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN                                                             0x801f
+#define ixDPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN                                                       0x8020
+#define ixDPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT                                                            0x8021
+#define ixDPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN                                                             0x8022
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0                                                         0x8024
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1                                                         0x8025
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2                                                         0x8026
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3                                                         0x8027
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4                                                         0x8028
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5                                                         0x8029
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6                                                         0x802a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0                                                         0x802b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1                                                         0x802c
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2                                                         0x802d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3                                                         0x802e
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4                                                         0x802f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5                                                         0x8030
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6                                                         0x8031
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN                                                   0x8032
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN                                                  0x8033
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN                                                   0x8034
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN                                                  0x8035
+#define ixDPCSSYS_CR4_SUPX_DIG_ASIC_IN                                                                 0x8036
+#define ixDPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN                                                             0x8037
+#define ixDPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN                                                         0x8038
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN                                                        0x8039
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN                                                     0x803a
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN                                                        0x803b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN                                                     0x803c
+#define ixDPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL                                                          0x8040
+#define ixDPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL                                                              0x8041
+#define ixDPCSSYS_CR4_SUPX_ANA_BG1                                                                     0x8042
+#define ixDPCSSYS_CR4_SUPX_ANA_BG2                                                                     0x8043
+#define ixDPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS                                                         0x8044
+#define ixDPCSSYS_CR4_SUPX_ANA_BG3                                                                     0x8045
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1                                                             0x8046
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2                                                             0x8047
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD                                                              0x8048
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1                                                              0x8049
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2                                                              0x804a
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3                                                              0x804b
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1                                                              0x804c
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2                                                              0x804d
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3                                                              0x804e
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4                                                              0x804f
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5                                                              0x8050
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1                                                         0x8051
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2                                                         0x8052
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1                                                             0x8053
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2                                                             0x8054
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD                                                              0x8055
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1                                                              0x8056
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2                                                              0x8057
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3                                                              0x8058
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1                                                              0x8059
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2                                                              0x805a
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3                                                              0x805b
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4                                                              0x805c
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5                                                              0x805d
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1                                                         0x805e
+#define ixDPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2                                                         0x805f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD                                            0x8061
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT                                                 0x8062
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x8063
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8064
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8065
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8066
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8067
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL                                             0x8068
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8069
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE                                               0x806b
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD                                            0x806d
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT                                                 0x806e
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE                                    0x806f
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK                                     0x8070
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS                                          0x8071
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE                              0x8072
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2                            0x8073
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL                                             0x8074
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT                                     0x8075
+#define ixDPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE                                               0x8077
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0                                                 0x8078
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1                                                 0x8079
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2                                                 0x807a
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0                                                0x807b
+#define ixDPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD                                                       0x807c
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG                                                            0x8081
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_STAT                                                              0x8082
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL                                                        0x8083
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL                                                      0x8084
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL                                                      0x8085
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT                                                           0x8086
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT                                                         0x8087
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT                                                         0x8088
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0                                                       0x8089
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1                                                       0x808a
+#define ixDPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE                                                       0x808b
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0                                                    0x808c
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1                                                    0x808d
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2                                                    0x808e
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0                                                    0x808f
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1                                                    0x8090
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2                                                    0x8091
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT                                                      0x8092
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_STAT                                                                0x8093
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT                                                         0x8094
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT                                                 0x8095
+#define ixDPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT                                                 0x8096
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN                                                      0x9000
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0                                                      0x9001
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1                                                      0x9002
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2                                                      0x9003
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3                                                      0x9004
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4                                                      0x9005
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT                                                       0x9006
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0                                                      0x9007
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1                                                      0x9008
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2                                                      0x9009
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3                                                      0x900a
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4                                                      0x900b
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5                                                      0x900c
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0                                                   0x900d
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1                                                   0x900e
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0                                                     0x900f
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN                                                      0x9010
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0                                                      0x9011
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1                                                      0x9012
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2                                                      0x9013
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT                                                       0x9014
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0                                                      0x9015
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1                                                      0x9016
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0                                                   0x9017
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1                                                   0x9018
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0                                              0x9019
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1                                              0x901a
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0                                                     0x901b
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6                                                      0x901c
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5                                                      0x901d
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1                                                     0x901e
+#define ixDPCSSYS_CR4_LANEX_DIG_ASIC_OCLA                                                              0x901f
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0                                                 0x9020
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S                                                0x9021
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1                                                 0x9022
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2                                                 0x9023
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0                                              0x9024
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1                                              0x9025
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2                                              0x9026
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3                                              0x9027
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4                                              0x9028
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5                                              0x9029
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR                                             0x902a
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA                                             0x902b
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL                                                 0x902c
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE                                                0x902d
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL                                                  0x902e
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK                                                  0x902f
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR                                                 0x9030
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0                                                  0x9031
+#define ixDPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL                                                           0x9032
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0                                                 0x9040
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S                                                0x9041
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1                                                 0x9042
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2                                                 0x9043
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1                                              0x9045
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2                                              0x9046
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3                                              0x9047
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0                                            0x9048
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1                                            0x9049
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2                                            0x904a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0                                            0x904b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1                                            0x904c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0                                                0x904d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1                                                0x904e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2                                                0x904f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK                                             0x9050
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL                                                           0x9051
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR                                                           0x9052
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0                                                       0x9053
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1                                                       0x9054
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2                                                       0x9055
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3                                                       0x9056
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4                                                       0x9057
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT                                                            0x9058
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ                                                           0x9059
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0                                                   0x905a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1                                                   0x905b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0                                                  0x9060
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1                                                  0x9061
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2                                                  0x9062
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3                                                  0x9063
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4                                                  0x9064
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5                                                  0x9065
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6                                                  0x9066
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7                                                  0x9067
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8                                                  0x9068
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9                                                  0x9069
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG                                                0x906a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS                                                  0x906b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS                                                  0x906c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS                                                 0x906d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS                                             0x906e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS                                             0x906f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS                                             0x9070
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS                                             0x9071
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS                                             0x9072
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST                                     0x9073
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST                                      0x9074
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN                                         0x9075
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD                                          0x9076
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST                                    0x9077
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST                                     0x9078
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL                                          0x9079
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET                                                  0x907a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1                                              0x907b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2                                              0x907c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3                                              0x907d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR                                                0x907e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA                                                0x907f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1                                                       0x9080
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK                                                       0x9081
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0                                                     0x9082
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1                                                     0x9083
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0                                                      0x9084
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1                                                      0x9085
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1                                                      0x9086
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0                                                     0x9087
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1                                                     0x9088
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2                                                     0x9089
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3                                                     0x908a
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4                                                     0x908b
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5                                                     0x908c
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6                                                     0x908d
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL                                               0x908e
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2                                                     0x908f
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3                                                     0x9090
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4                                                     0x9091
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5                                                     0x9092
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2                                                      0x9093
+#define ixDPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP                                                      0x9094
+#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL                                                        0x9095
+#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL                                                    0x9096
+#define ixDPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT                                         0x9097
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT                                                        0x90a0
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT                                              0x90a1
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT                                          0x90a2
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0                                                   0x90a3
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1                                                   0x90a4
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2                                                   0x90a5
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3                                                   0x90a6
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4                                                   0x90a7
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5                                                   0x90a8
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT                                                    0x90a9
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT                                                    0x90aa
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0                                                  0x90ab
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1                                                  0x90ac
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2                                                  0x90ad
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL                                                             0x90ae
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL                                                        0x90af
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD                                                   0x90b0
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL                                                    0x90b1
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA                                                     0x90b2
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE                                                        0x90b3
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE                                                           0x90b4
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL                                                     0x90b5
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST                                             0x90b6
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN                                                 0x90b7
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN                                             0x90b8
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE                                      0x90b9
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK                                            0x90ba
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0                                                           0x90bb
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1                                                           0x90bc
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT                                              0x90bd
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT                                          0x90be
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT                                                      0x90bf
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1                                                  0x90c0
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2                                                  0x90c1
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT                                                0x90c2
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2                                              0x90c3
+#define ixDPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2                                                      0x90c4
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS                                                           0x90e0
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD                                                            0x90e1
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS                                                             0x90e2
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB1                                                                0x90e3
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_ATB2                                                                0x90e4
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC                                                             0x90e5
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1                                                           0x90e6
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE                                                           0x90e7
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL                                                      0x90e8
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK                                                            0x90e9
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC1                                                               0x90ea
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC2                                                               0x90eb
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_MISC3                                                               0x90ec
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED2                                                           0x90ed
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED3                                                           0x90ee
+#define ixDPCSSYS_CR4_LANEX_ANA_TX_RESERVED4                                                           0x90ef
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_1                                                               0x90f0
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CLK_2                                                               0x90f1
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CDR_DES                                                             0x90f2
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL                                                            0x90f3
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1                                                           0x90f4
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2                                                           0x90f5
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_SQ                                                                  0x90f6
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL1                                                                0x90f7
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_CAL2                                                                0x90f8
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF                                                          0x90f9
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1                                                           0x90fa
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2                                                           0x90fb
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3                                                           0x90fc
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4                                                           0x90fd
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC                                                             0x90fe
+#define ixDPCSSYS_CR4_LANEX_ANA_RX_RESERVED1                                                           0x90ff
+#define ixDPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0                                                        0xa000
+#define ixDPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0                                                        0xc000
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN                                                   0xe000
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1                                                 0xe001
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN                                                    0xe002
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT                                                  0xe003
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT                                                   0xe004
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN                                                   0xe005
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1                                                 0xe006
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2                                                 0xe007
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3                                                 0xe008
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN                                                    0xe009
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1                                                  0xe00a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2                                                  0xe00b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3                                                  0xe00c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4                                                  0xe00d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT                                                  0xe00e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT                                                   0xe00f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK                                                 0xe010
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM                                                 0xe011
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR                                                 0xe012
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR                                                0xe013
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR                                                0xe014
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER                                                  0xe015
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1                                                   0xe016
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2                                                   0xe017
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN                                                  0xe018
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN                                       0xe019
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN                                       0xe01a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN                                            0xe01b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1                                                0xe01c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1                                              0xe01d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2                                              0xe01e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL                                                   0xe01f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL                                                    0xe020
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON                                                    0xe021
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON                                                      0xe022
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL                                             0xe023
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT                                                   0xe024
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL                                                 0xe025
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL                                                 0xe026
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL                                              0xe027
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL                                              0xe028
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL                                                  0xe029
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT                                               0xe02a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT                                               0xe02b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP                                                        0xe02c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE                                                0xe02d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET                                                   0xe02e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP                                                   0xe02f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT                                                0xe030
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL                                                 0xe031
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS                                              0xe032
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT                                          0xe033
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT                                              0xe034
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL                                           0xe035
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL                                          0xe036
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL                                            0xe037
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS                                                      0xe038
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK                                                         0xe039
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS                                                    0xe03a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS                                                   0xe03b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA                                                            0xe03c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG                                               0xe03d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS                                              0xe03e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET                                              0xe03f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ                                               0xe040
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ                                                0xe041
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ                                                  0xe042
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ                                                 0xe043
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ                                               0xe044
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ                                            0xe045
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ                                            0xe046
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR                                            0xe047
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR                                              0xe048
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR                                             0xe049
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR                                           0xe04a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR                                        0xe04b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR                                        0xe04c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK                                                    0xe04d
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2                                                  0xe04e
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ                                          0xe04f
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR                                      0xe050
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ                                          0xe051
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ                                          0xe052
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR                                      0xe053
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR                                      0xe054
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ                                    0xe055
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR                                0xe056
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ                                               0xe057
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ                                                0xe058
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ                                                  0xe059
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR                                            0xe05a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR                                              0xe05b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN                                                 0xe060
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT                                                0xe061
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN                                                  0xe062
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN                                                   0xe063
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT                                                  0xe064
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN                                                    0xe065
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT                                                  0xe066
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN                                                    0xe067
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL                                               0xe068
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1                                                 0xe069
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN                                                 0xe06a
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT                                                0xe06b
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT                                            0xe06c
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL                                                   0xe080
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL                                                   0xe081
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS                                           0xe082
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA                                                         0xe083
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA                                                    0xe084
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL                                                   0xe0a0
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL                                              0xe0a1
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL                                          0xe0a2
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS                                           0xe0a3
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS                                            0xe0a4
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA                                                    0xe0a5
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN                                               0xe0c0
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN                                               0xe0c1
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1                                             0xe0c2
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP                                             0xe0c3
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1                                             0xe0c4
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2                                             0xe0c5
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3                                             0xe0c6
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2                                                0xe0c7
+#define ixDPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2                                                 0xe0c8
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h
new file mode 100644
index 000000000000..068f3b16a56b
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_0_sh_mask.h
@@ -0,0 +1,103385 @@
+/*
+ * Copyright (C) 2020  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _dpcs_4_2_0_SH_MASK_HEADER
+#define _dpcs_4_2_0_SH_MASK_HEADER
+
+
+// addressBlock: dpcssys_dpcssys_cr0_dispdec
+//DPCSSYS_CR0_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR0_DPCSSYS_CR_DATA
+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr1_dispdec
+//DPCSSYS_CR1_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR1_DPCSSYS_CR_DATA
+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr2_dispdec
+//DPCSSYS_CR2_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR2_DPCSSYS_CR_DATA
+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr3_dispdec
+//DPCSSYS_CR3_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR3_DPCSSYS_CR_DATA
+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_dpcssys_cr4_dispdec
+//DPCSSYS_CR4_DPCSSYS_CR_ADDR
+#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
+#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
+//DPCSSYS_CR4_DPCSSYS_CR_DATA
+#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
+#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL
+
+
+// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
+//PWRSEQ0_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ0_PANEL_PWRSEQ_CNTL
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ0_PANEL_PWRSEQ_STATE
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ0_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ0_BL_PWM_CNTL
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ0_BL_PWM_CNTL2
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ0_BL_PWM_PERIOD_CNTL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ0_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ0_PWRSEQ_SPARE
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
+//PWRSEQ1_DC_GPIO_PWRSEQ_EN
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_MASK
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
+//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
+#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
+//PWRSEQ1_PANEL_PWRSEQ_CNTL
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
+#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
+//PWRSEQ1_PANEL_PWRSEQ_STATE
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
+#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY1
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
+//PWRSEQ1_PANEL_PWRSEQ_DELAY2
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
+#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
+//PWRSEQ1_BL_PWM_CNTL
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
+#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
+#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
+#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
+//PWRSEQ1_BL_PWM_CNTL2
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
+#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
+//PWRSEQ1_BL_PWM_PERIOD_CNTL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
+#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
+//PWRSEQ1_BL_PWM_GRP1_REG_LOCK
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
+#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
+//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
+#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
+//PWRSEQ1_PWRSEQ_SPARE
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
+#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
+//RDPCSTX0_RDPCSTX_CNTL
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX0_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX0_RDPCS_TX_CR_ADDR
+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX0_RDPCS_TX_CR_DATA
+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX0_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX0_RDPCSTX_SCRATCH
+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX0_RDPCSTX_SPARE
+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX0_RDPCSTX_CNTL2
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX0_RDPCSTX_PHY_CNTL0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX0_RDPCSTX_PHY_CNTL2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX0_RDPCSTX_PHY_CNTL3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL5
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX0_RDPCSTX_PHY_CNTL9
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX0_RDPCSTX_PHY_CNTL11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX0_RDPCSTX_PHY_CNTL13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE1
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE2
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX0_RDPCSTX_PHY_FUSE3
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX0_RDPCSTX_PHY_CNTL15
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL16
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX0_RDPCSTX_PHY_CNTL17
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX0_RDPCS_CNTL3
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
+//RDPCSTX1_RDPCSTX_CNTL
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX1_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX1_RDPCS_TX_CR_ADDR
+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX1_RDPCS_TX_CR_DATA
+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX1_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX1_RDPCSTX_SCRATCH
+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX1_RDPCSTX_SPARE
+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX1_RDPCSTX_CNTL2
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX1_RDPCSTX_PHY_CNTL0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX1_RDPCSTX_PHY_CNTL2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX1_RDPCSTX_PHY_CNTL3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL5
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX1_RDPCSTX_PHY_CNTL9
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX1_RDPCSTX_PHY_CNTL11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX1_RDPCSTX_PHY_CNTL13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE1
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE2
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX1_RDPCSTX_PHY_FUSE3
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX1_RDPCSTX_PHY_CNTL15
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL16
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX1_RDPCSTX_PHY_CNTL17
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX1_RDPCS_CNTL3
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
+//RDPCSTX2_RDPCSTX_CNTL
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX2_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX2_RDPCS_TX_CR_ADDR
+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX2_RDPCS_TX_CR_DATA
+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX2_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX2_RDPCSTX_SCRATCH
+#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX2_RDPCSTX_SPARE
+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX2_RDPCSTX_CNTL2
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX2_RDPCSTX_PHY_CNTL0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX2_RDPCSTX_PHY_CNTL2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX2_RDPCSTX_PHY_CNTL3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL5
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX2_RDPCSTX_PHY_CNTL9
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX2_RDPCSTX_PHY_CNTL11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX2_RDPCSTX_PHY_CNTL13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE1
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE2
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX2_RDPCSTX_PHY_FUSE3
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX2_RDPCSTX_PHY_CNTL15
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL16
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX2_RDPCSTX_PHY_CNTL17
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX2_RDPCS_CNTL3
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
+//RDPCSTX3_RDPCSTX_CNTL
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX3_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX3_RDPCS_TX_CR_ADDR
+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX3_RDPCS_TX_CR_DATA
+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX3_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX3_RDPCSTX_SCRATCH
+#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX3_RDPCSTX_SPARE
+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX3_RDPCSTX_CNTL2
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX3_RDPCSTX_PHY_CNTL0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX3_RDPCSTX_PHY_CNTL2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX3_RDPCSTX_PHY_CNTL3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL5
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX3_RDPCSTX_PHY_CNTL9
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX3_RDPCSTX_PHY_CNTL11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX3_RDPCSTX_PHY_CNTL13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE1
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE2
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX3_RDPCSTX_PHY_FUSE3
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX3_RDPCSTX_PHY_CNTL15
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL16
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX3_RDPCSTX_PHY_CNTL17
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX3_RDPCS_CNTL3
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
+//RDPCSTX4_RDPCSTX_CNTL
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
+#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
+#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
+//RDPCSTX4_RDPCSTX_CLOCK_CNTL
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
+#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
+//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
+#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
+//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
+//RDPCSTX4_RDPCS_TX_CR_ADDR
+#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
+#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
+//RDPCSTX4_RDPCS_TX_CR_DATA
+#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
+#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
+//RDPCSTX4_RDPCS_TX_SRAM_CNTL
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
+#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
+//RDPCSTX4_RDPCSTX_SCRATCH
+#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
+#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
+//RDPCSTX4_RDPCSTX_SPARE
+#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
+#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
+//RDPCSTX4_RDPCSTX_CNTL2
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
+#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
+//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
+//RDPCSTX4_RDPCSTX_PHY_CNTL0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
+//RDPCSTX4_RDPCSTX_PHY_CNTL2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
+//RDPCSTX4_RDPCSTX_PHY_CNTL3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL5
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
+//RDPCSTX4_RDPCSTX_PHY_CNTL9
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
+//RDPCSTX4_RDPCSTX_PHY_CNTL11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
+//RDPCSTX4_RDPCSTX_PHY_CNTL13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE1
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE2
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
+//RDPCSTX4_RDPCSTX_PHY_FUSE3
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
+#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
+//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
+#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
+//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
+//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
+#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
+//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
+#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
+//RDPCSTX4_RDPCSTX_PHY_CNTL15
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL16
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
+//RDPCSTX4_RDPCSTX_PHY_CNTL17
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
+#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
+//RDPCSTX4_RDPCS_CNTL3
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
+#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
+//RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
+//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
+#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_dispdec
+//DC_GENERICA
+#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
+#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
+#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
+#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DC_GENERICB
+#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
+#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
+#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
+#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
+#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
+#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
+//DCIO_CLOCK_CNTL
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
+#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
+#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
+//DC_REF_CLK_CNTL
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
+#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
+#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
+//UNIPHYA_LINK_CNTL
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYA_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYA_CHANNEL_XBAR_CNTL
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYB_LINK_CNTL
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYB_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYB_CHANNEL_XBAR_CNTL
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYC_LINK_CNTL
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYC_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYC_CHANNEL_XBAR_CNTL
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYD_LINK_CNTL
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYD_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYD_CHANNEL_XBAR_CNTL
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//UNIPHYE_LINK_CNTL
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL__SHIFT                                                      0x10
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
+#define UNIPHYE_LINK_CNTL__UNIPHY_LINK_PWRSEQ_SEL_MASK                                                        0x00010000L
+//UNIPHYE_CHANNEL_XBAR_CNTL
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
+#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
+//DCIO_WRCMD_DELAY
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
+#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
+//DC_PINSTRAPS
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
+#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
+#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
+//INTERCEPT_STATE
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE__SHIFT                                                 0x4
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE__SHIFT                                                 0x5
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE__SHIFT                                                 0x6
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE__SHIFT                                                 0x7
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE__SHIFT                                                 0x8
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE__SHIFT                                                 0x9
+#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
+#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
+#define INTERCEPT_STATE__RDPCS_TX_DC0_INTERCEPTB_STATE_MASK                                                   0x00000010L
+#define INTERCEPT_STATE__RDPCS_TX_DC1_INTERCEPTB_STATE_MASK                                                   0x00000020L
+#define INTERCEPT_STATE__RDPCS_TX_DC2_INTERCEPTB_STATE_MASK                                                   0x00000040L
+#define INTERCEPT_STATE__RDPCS_TX_DC3_INTERCEPTB_STATE_MASK                                                   0x00000080L
+#define INTERCEPT_STATE__RDPCS_TX_DC4_INTERCEPTB_STATE_MASK                                                   0x00000100L
+#define INTERCEPT_STATE__RDPCS_TX_DC5_INTERCEPTB_STATE_MASK                                                   0x00000200L
+//DCIO_BL_PWM_FRAME_START_DISP_SEL
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
+#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
+//DCIO_GSL_GENLK_PAD_CNTL
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
+#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
+//DCIO_GSL_SWAPLOCK_PAD_CNTL
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
+#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
+//DCIO_SOFT_RESET
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x1
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x2
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x3
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x4
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0x5
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x6
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0x7
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x8
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0x9
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0xa
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xb
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0xc
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xd
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
+#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
+#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000002L
+#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000004L
+#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000008L
+#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000010L
+#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000020L
+#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000040L
+#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000080L
+#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000100L
+#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00000200L
+#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000400L
+#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00000800L
+#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00001000L
+#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00002000L
+#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
+#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L
+
+
+// addressBlock: dpcssys_dcio_dcio_chip_dispdec
+//DC_GPIO_GENERIC_MASK
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
+#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
+//DC_GPIO_GENERIC_A
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
+//DC_GPIO_GENERIC_EN
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
+#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
+//DC_GPIO_GENERIC_Y
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
+#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
+//DC_GPIO_DDC1_MASK
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC1_A
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC1_EN
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC1_Y
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_MASK
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC2_A
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC2_EN
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC2_Y
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_MASK
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC3_A
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC3_EN
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC3_Y
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_MASK
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC4_A
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC4_EN
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC4_Y
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_MASK
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
+#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
+#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
+#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
+#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
+#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
+//DC_GPIO_DDC5_A
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
+//DC_GPIO_DDC5_EN
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
+#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
+//DC_GPIO_DDC5_Y
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
+#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
+//DC_GPIO_DDCVGA_MASK
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
+#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
+#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
+#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
+#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
+//DC_GPIO_DDCVGA_A
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
+//DC_GPIO_DDCVGA_EN
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
+#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
+//DC_GPIO_DDCVGA_Y
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
+#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
+//DC_GPIO_GENLK_MASK
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
+#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
+//DC_GPIO_GENLK_A
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
+//DC_GPIO_GENLK_EN
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
+#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
+#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
+//DC_GPIO_GENLK_Y
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
+#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
+#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
+//DC_GPIO_HPD_MASK
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
+#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
+//DC_GPIO_HPD_A
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
+//DC_GPIO_HPD_EN
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
+#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
+#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
+#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
+#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
+#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
+#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
+#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
+#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
+#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
+#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
+#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
+#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
+#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
+#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
+#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
+#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
+#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
+#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
+#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
+#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
+//DC_GPIO_HPD_Y
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
+#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
+//DC_GPIO_PWRSEQ0_EN
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_PAD_STRENGTH_1
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
+#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
+#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
+//DC_GPIO_PAD_STRENGTH_2
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
+#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
+#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
+#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
+//PHY_AUX_CNTL
+#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
+#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
+#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
+#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
+#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
+#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
+#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
+#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
+//DC_GPIO_PWRSEQ1_EN
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
+#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
+//DC_GPIO_TX12_EN
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
+#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
+//DC_GPIO_AUX_CTRL_0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
+#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
+//DC_GPIO_AUX_CTRL_1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
+#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
+//DC_GPIO_AUX_CTRL_2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
+#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
+//DC_GPIO_RXEN
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
+#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
+#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
+#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
+#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
+#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
+#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
+#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
+//DC_GPIO_PULLUPEN
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
+#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
+#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
+#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
+//DC_GPIO_AUX_CTRL_3
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
+#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
+#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
+#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
+#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
+#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
+#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
+#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
+#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
+#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
+#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
+#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
+#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
+#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
+#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
+#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
+#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
+#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
+//DC_GPIO_AUX_CTRL_4
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
+#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
+#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
+#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
+#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
+#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
+#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
+//DC_GPIO_AUX_CTRL_5
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
+#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
+#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
+#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
+#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
+#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
+#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
+#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
+#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
+#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
+#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
+#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
+#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
+#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
+//AUXI2C_PAD_ALL_PWR_OK
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
+#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
+#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
+
+
+// addressBlock: dpcssys_cr0_rdpcstxcrind
+//DPCSSYS_CR0_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_BG1
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR0_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR0_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_BG2
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR0_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR0_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR0_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR0_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_BG3
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_BG1
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR0_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_BG2
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR0_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR0_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR0_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR0_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_BG3
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR0_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr1_rdpcstxcrind
+//DPCSSYS_CR1_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_BG1
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR1_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR1_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_BG2
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR1_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR1_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR1_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR1_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_BG3
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_BG1
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR1_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_BG2
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR1_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR1_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR1_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR1_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_BG3
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR1_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr2_rdpcstxcrind
+//DPCSSYS_CR2_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_BG1
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR2_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR2_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_BG2
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR2_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR2_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR2_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR2_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_BG3
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_BG1
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR2_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_BG2
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR2_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR2_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR2_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR2_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_BG3
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR2_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr3_rdpcstxcrind
+//DPCSSYS_CR3_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_BG1
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR3_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR3_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_BG2
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR3_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR3_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR3_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR3_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_BG3
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_BG1
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR3_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_BG2
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR3_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR3_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR3_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR3_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_BG3
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR3_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+// addressBlock: dpcssys_cr4_rdpcstxcrind
+//DPCSSYS_CR4_SUP_DIG_IDCODE_LO
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__data__SHIFT                                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_IDCODE_HI
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__data__SHIFT                                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__data_MASK                                                              0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x000001F0L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x000000C0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000600L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x00007F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x00008000L
+//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x00000078L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x000000FCL
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x00000700L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x00003800L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x00000700L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x00000060L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x00000300L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x00000FFFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0x0000FFFFL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x000001FEL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x0000001CL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x00000038L
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0x0000FFFEL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                          0x1
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                     0x3
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                         0x4
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                           0x6
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                           0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                            0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                      0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                       0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                           0x00000030L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                         0x0
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                    0x3
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                    0x5
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                                           0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                      0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_BG1
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                      0x0
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                      0x5
+#define DPCSSYS_CR4_SUP_ANA_BG1__rt_vref_sel__SHIFT                                                           0x7
+#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vbg_vref_MASK                                                        0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vphud_vref_MASK                                                      0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_BG1__NC4_MASK                                                                     0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_BG1__sup_sel_vpll_ref_MASK                                                        0x00000060L
+#define DPCSSYS_CR4_SUP_ANA_BG1__rt_vref_sel_MASK                                                             0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_BG2
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_bypass_bg__SHIFT                                                         0x0
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_chop_en__SHIFT                                                           0x1
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_temp_meas__SHIFT                                                         0x2
+#define DPCSSYS_CR4_SUP_ANA_BG2__vphud_selref__SHIFT                                                          0x3
+#define DPCSSYS_CR4_SUP_ANA_BG2__atb_ext_meas_en__SHIFT                                                       0x4
+#define DPCSSYS_CR4_SUP_ANA_BG2__rt_tx_offset_en__SHIFT                                                       0x5
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                 0x6
+#define DPCSSYS_CR4_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_bypass_bg_MASK                                                           0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_chop_en_MASK                                                             0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_temp_meas_MASK                                                           0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_BG2__vphud_selref_MASK                                                            0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_BG2__atb_ext_meas_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_BG2__rt_tx_offset_en_MASK                                                         0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                         0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                   0x7
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                  0x0000007FL
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                     0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_BG3
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
+#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                  0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4_MASK                                                                   0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__vbg_en_MASK                                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                  0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                    0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_boost__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__pr_bypass_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__test_boost_MASK                                                      0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                     0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                        0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                     0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                      0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                                       0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                                          0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__atb_select__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                     0x0000007FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__atb_select_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                      0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                     0x0000000FL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                 0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                   0x0000000CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                       0x000000F0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                   0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                  0x00000003L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                      0x0000007CL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                     0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                      0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                  0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                        0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                     0x000000E0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                 0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                         0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                              0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                           0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                          0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                                0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                       0x2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                       0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                         0x00000004L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                    0x00000008L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                         0x000000C0L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                          0x1
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                         0x6
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                             0x00000001L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                            0x0000003EL
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                           0x00000040L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x000003E0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x00003F00L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x00000FC0L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0x0000FFE0L
+//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x00000003L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x000001FFL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x0000001FL
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x00000038L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x00000C00L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x00000F00L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0x0000F000L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x000001F0L
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x0000000FL
+#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x00000200L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x00008000L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x00003F80L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x00000006L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x00003FF0L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_SUP_DIG_ANA_STAT
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0x0000FFFCL
+//DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x00000002L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x00000004L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x00000008L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x00000010L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x00000300L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0x0000F800L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x0000003FL
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x00000100L
+#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CLK_1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CLK_2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_SQ
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CAL1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_CAL2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CLK_1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CLK_2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_SQ
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CAL1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_CAL2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x0000001CL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x00000070L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__data__SHIFT                                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__data_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x000007FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0x0000F000L
+//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x00000300L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x00000800L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0x0000E000L
+//DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x00001E00L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x00002000L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x00004000L
+#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x00008000L
+//DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__data__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__data_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0x0000FFF0L
+//DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__data__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__data_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWCMN_DIG_OCLA
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x000000E0L
+#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE
+#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__data__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__data_MASK                                                     0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0x0000FFFFL
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x00000080L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0x0000FF80L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x00000008L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x0000001FL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__data_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__data_MASK                                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__data_MASK                                                  0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__data_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__data_MASK                                    0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__data_MASK                                     0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__data_MASK                                      0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__data_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__data_MASK                                        0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__data_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__data_MASK                                              0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__data_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x00001C00L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0x0000E000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x00001FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__data_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x00000800L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x00004000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x00000FFFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0x0000F000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x0000000FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x00000100L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x00000200L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x00000800L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x00004000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_STATS
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x00000007L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x00000030L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x00000200L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x00001000L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0x0000E000L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x00000010L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x00000020L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x00000007L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x00000038L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0x0000FF80L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x0000003FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__data_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__data__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__data_MASK                                                0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__data_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x000003FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0x0000FC00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__data__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__data_MASK                                                   0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x000000FFL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0x0000FF00L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x00000003L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x00000004L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0x0000FFF8L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x0000001FL
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x000003E0L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__data__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__data_MASK                                                  0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_IDCODE_LO
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__data__SHIFT                                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_IDCODE_HI
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__data__SHIFT                                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__data_MASK                                                             0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x000001F0L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000600L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x00007F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x00000078L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x000000FCL
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x00000700L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x00003800L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x00000070L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x00000700L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x00000300L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x00000FFFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0x0000FFFFL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x000001FEL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x0000001CL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x00000007L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x00000038L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0x0000C000L
+//DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start__SHIFT                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg__SHIFT                                    0x3
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost__SHIFT                                        0x4
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref__SHIFT                                          0x6
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_atb_select_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_meas_vreg_MASK                                           0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_ovrd_fast_start_MASK                                     0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_fast_start_reg_MASK                                      0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_vreg_boost_MASK                                          0x00000030L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__pscaler_hyst_ref_MASK                                            0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                                        0x0
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en__SHIFT                                                   0x3
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                                   0x4
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                                   0x6
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                                     0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_vp4o8_en_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__pscaler_vreg_fb_div_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_BG1
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vbg_vref__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vphud_vref__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vpll_ref__SHIFT                                                     0x5
+#define DPCSSYS_CR4_SUPX_ANA_BG1__rt_vref_sel__SHIFT                                                          0x7
+#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vbg_vref_MASK                                                       0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vphud_vref_MASK                                                     0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4_MASK                                                                    0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__sup_sel_vpll_ref_MASK                                                       0x00000060L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__rt_vref_sel_MASK                                                            0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_BG2
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_bypass_bg__SHIFT                                                        0x0
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_chop_en__SHIFT                                                          0x1
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_temp_meas__SHIFT                                                        0x2
+#define DPCSSYS_CR4_SUPX_ANA_BG2__vphud_selref__SHIFT                                                         0x3
+#define DPCSSYS_CR4_SUPX_ANA_BG2__atb_ext_meas_en__SHIFT                                                      0x4
+#define DPCSSYS_CR4_SUPX_ANA_BG2__rt_tx_offset_en__SHIFT                                                      0x5
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_sel_tx_swing_vref__SHIFT                                                0x6
+#define DPCSSYS_CR4_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl__SHIFT                                      0x7
+#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_bypass_bg_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_chop_en_MASK                                                            0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_temp_meas_MASK                                                          0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__vphud_selref_MASK                                                           0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__atb_ext_meas_en_MASK                                                        0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__rt_tx_offset_en_MASK                                                        0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__sup_sel_tx_swing_vref_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__pscaler_vreg_override_ring_ctrl_MASK                                        0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_atb_sw_MASK                                                 0x0000007FL
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__sup_tie_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_BG3
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_cal_vref__SHIFT                                                  0x2
+#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
+#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_vco_tc_vref_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_BG3__sup_sel_rx_cal_vref_MASK                                                    0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt__SHIFT                                            0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__test_vreg_div__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__vbg_en__SHIFT                                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__count_sel_lock__SHIFT                                               0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__phase_sel_lock__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_gear_rc_filt_MASK                                              0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__ovrd_test_rc_filt_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__test_vreg_div_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__vbg_en_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__count_sel_lock_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__phase_sel_lock_MASK                                                 0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__pr_bypass__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__gearshift_reg__SHIFT                                                0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_lock_gear__SHIFT                                               0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__en_cal_spo__SHIFT                                                   0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_boost__SHIFT                                                   0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_pr_bypass_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__pr_bypass_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__ovrd_gearshift_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__gearshift_reg_MASK                                                  0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_lock_gear_MASK                                                 0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__en_cal_spo_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__test_boost_MASK                                                     0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                                    0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                                       0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                                    0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                                     0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                                         0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__atb_select__SHIFT                                                    0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__meas_iv_wrap_MASK                                                    0x0000007FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__atb_select_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__meas_iv_pll__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__meas_iv_pll_MASK                                                     0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__meas_iv_bias__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning__SHIFT                                              0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__meas_iv_bias_MASK                                                    0x0000000FL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__ctr_upll_tunning_MASK                                                0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_icp_int__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_en__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg__SHIFT                                                0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll__SHIFT                                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_icp_int_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_en_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_vref_vmarg_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__ctr_cp_pll_MASK                                                      0x000000F0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__ctr_regs_pll_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll__SHIFT                                               0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap__SHIFT                                                  0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_regs_cp_pll_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_spo_pll_MASK                                                     0x0000007CL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__ctr_vint_cap_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x__SHIFT                                                     0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg__SHIFT                                                   0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref__SHIFT                                               0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_test_casc__SHIFT                                                 0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter__SHIFT                                                  0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_8x_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_fil_reg_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_cp_prop_ref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_doubler_gain_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_test_casc_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__ctr_rc_fiter_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con__SHIFT                                                0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override__SHIFT                                        0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override__SHIFT                                        0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal__SHIFT                                       0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal__SHIFT                                              0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved__SHIFT                                             0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_standby_mode_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_leg_sr_con_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_vreg_ring_override_MASK                                          0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_spo_speed_override_MASK                                          0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_bypass_lock_spo_cal_MASK                                         0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_lock_spo_cal_MASK                                                0x00000060L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__ctr_upll_reserved_MASK                                               0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass__SHIFT                                      0x2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass__SHIFT                                 0x3
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass__SHIFT                                    0x4
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_ref_fbk_bypass_MASK                                         0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_bypass_tx_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_bypass_MASK                                        0x00000004L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_clk_pmix_bypass_MASK                                   0x00000008L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_right_bypass_MASK                                      0x00000010L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_vreg_left_bypass_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__ctr_left_right_gain_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved__SHIFT                                         0x1
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz__SHIFT                                        0x6
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div4__SHIFT                                                 0x7
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_mode_90_MASK                                            0x00000001L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_dll_reserved_MASK                                           0x0000003EL
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div24_dsq_enz_MASK                                          0x00000040L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__ctr_div4_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0x0000FF00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x000003E0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x00003F00L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x00000FC0L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0x0000FFE0L
+//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x00000003L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0x0000FFF8L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x000001FFL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x000000FFL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x0000001FL
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x00000038L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x00000C00L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0x0000FFC0L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x00000F00L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0x0000F000L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x000001F0L
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x0000000FL
+#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x00000200L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x00000800L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x00001000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x000003FFL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0x0000FC00L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x00003F80L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0x0000C000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x00000006L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x00003FF0L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_SUPX_DIG_ANA_STAT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0x0000FFFCL
+//DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x00000002L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x00000004L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x00000010L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x00000020L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x00000300L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0x0000F800L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x0000003FL
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x00000040L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x00000100L
+#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x000000E0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x000003F0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x00001F80L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x00000030L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x00000C00L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x000000C0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x00000700L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x0000007EL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x00000FC0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x00000060L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x00000180L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x00000600L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x00007F80L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x000000FEL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x000000C0L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x00006000L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x00007FE0L
+#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x00001F80L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x000000FCL
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x00000F00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x00003000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x000001E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x00003C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x00007800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0x0000FFF8L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0x0000FFE0L
+//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x0000000CL
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x000001FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x00001C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x00003FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x000007FEL
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x00003C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x00000700L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x00000F80L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x00000F00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x00007C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x000001C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x00000E00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x00007000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0x0000FFE0L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x00001C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x00000FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x00007C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0x0000FC00L
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x00003C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x0000003EL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x000007C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x000003C0L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x00001C00L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x00000180L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x00000038L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x00007FFFL
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0x0000FFF8L
+//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x00000C00L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x000003FFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x00001800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x00007FFEL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x00001F80L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x000001FFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0x0000FFFFL
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0x0000FFF0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x00000006L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x00001FF8L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x000003E0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x00006000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x0000001FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0x0000FFE0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x00000780L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x000000F8L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x00000006L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x00000FF0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0x0000C000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x0000000FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x000000F0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0x0000FE00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x0000007FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0x0000FF80L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x00001FFFL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x0000003FL
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0x0000FF80L
+//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0x0000FFFCL
+//DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x00000030L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x00000040L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x00000600L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0x0000F000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x000003F0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00000400L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x00000800L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x00000FC0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x00001000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x00000003L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x00001FE0L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x00002000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x00004000L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x00008000L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x00000007L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x00000020L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0x0000FFC0L
+//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x00000002L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0x0000FFE0L
+//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                              0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_mux_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__meas_atb_cal_comp_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                                0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                              0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int__SHIFT                                             0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                                  0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                               0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                              0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                                0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__data_en_reg_int_MASK                                               0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                                    0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                                 0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__atb_s_enable__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                                0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__atb_s_enable_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__tx_alt_ringo_MASK                                                   0x00000070L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                                  0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_ATB1
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_gd__SHIFT                                                     0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vddh__SHIFT                                                   0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_rxdetref__SHIFT                                               0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vptx__SHIFT                                                   0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_regref__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg__SHIFT                                                   0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vph_half__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_gd_MASK                                                       0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vddh_MASK                                                     0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_rxdetref_MASK                                                 0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vptx_MASK                                                     0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__override_regref_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_drv_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vreg_MASK                                                     0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__meas_atb_vph_half_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_ATB2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_vcm__SHIFT                                                    0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm__SHIFT                                            0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff__SHIFT                                          0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txm__SHIFT                                                    0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txp__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_rxdetref__SHIFT                                               0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__lfps_high_priority__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__osc_div4_en__SHIFT                                                     0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_vcm_MASK                                                      0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_cm_MASK                                              0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_cal_vdac_diff_MASK                                            0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txm_MASK                                                      0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_txp_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__meas_atb_rxdetref_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__lfps_high_priority_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__osc_div4_en_MASK                                                       0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__dcc_dac_reg_MASK                                                    0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg__SHIFT                                        0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_sel_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_sel_reg_MASK                                         0x0000001CL
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_ctrl_en_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__dcc_dac_ctrl_en_reg_MASK                                          0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__ovrd_dcc_dac_reg_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__term_code_reg_70__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__term_code_reg_70_MASK                                             0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term__SHIFT                                      0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term__SHIFT                                       0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code__SHIFT                                        0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98__SHIFT                                      0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__vreg_boost_1_MASK                                            0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_update_term_MASK                                        0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__update_term_reg_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_reset_term_MASK                                         0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__reset_term_reg_MASK                                          0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__ovrd_term_code_MASK                                          0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__term_code_reg_98_MASK                                        0x000000C0L
+#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                               0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                                  0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                                            0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                              0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                             0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                                            0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__vreg_boost_0_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                                 0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                                    0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                              0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                                0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                               0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                              0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_MISC1
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range__SHIFT                                        0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg__SHIFT                                         0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_vref_sel__SHIFT                                                  0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__vref_sel_reg__SHIFT                                                   0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txm__SHIFT                                                  0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txp__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__meas_atb_cal_clk_align_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_dcc_dac_ctrl_range_MASK                                          0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__dcc_dac_ctrl_range_reg_MASK                                           0x0000000CL
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__ovrd_vref_sel_MASK                                                    0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__vref_sel_reg_MASK                                                     0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txm_MASK                                                    0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__force_atb_txp_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_MISC2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_peaking_lvl__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl__SHIFT                                              0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_slew_en__SHIFT                                                     0x3
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_post__SHIFT                                                    0x4
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_pre__SHIFT                                                     0x5
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vreg_en_byp__SHIFT                                                 0x6
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_peaking_lvl_MASK                                                   0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__vreg_cp_gain_ctrl_MASK                                                0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_slew_en_MASK                                                       0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_post_MASK                                                      0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__en_inv_pre_MASK                                                       0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vreg_en_byp_MASK                                                   0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__tx_vdriver_pulldn_en_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_MISC3
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl__SHIFT                                         0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_dcc_lowv__SHIFT                                                    0x1
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_vreg_ovrd_ring_ctrl_MASK                                           0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__tx_dcc_lowv_MASK                                                      0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x000000FCL
+#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CLK_1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code__SHIFT                                           0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias__SHIFT                                         0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__override_cdr_en__SHIFT                                                0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__ovrd_clk_en__SHIFT                                                    0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__clk_en_reg__SHIFT                                                     0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_startup_code_MASK                                             0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_temp_comp_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__cdr_vco_use_uncal_bias_MASK                                           0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__override_cdr_en_MASK                                                  0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__ovrd_clk_en_MASK                                                      0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__clk_en_reg_MASK                                                       0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CLK_2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg__SHIFT                                            0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust__SHIFT                                           0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk__SHIFT                                           0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__iq_phase_adjust_reg_MASK                                              0x0000001FL
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_iq_phase_adjust_MASK                                             0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__rx_loopback_clk_reg_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__ovrd_rx_loopback_clk_MASK                                             0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__word_clk_en_reg__SHIFT                                              0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_odd_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_even_reg__SHIFT                                               0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__ovrd_word_clk_en_MASK                                               0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__word_clk_en_reg_MASK                                                0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_odd_reg_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__phdet_even_reg_MASK                                                 0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__sigdet_vref_ext_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x000000E0L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                                        0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                                          0x0000000FL
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                                          0x000000F0L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                               0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                                 0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel__SHIFT                                                 0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en__SHIFT                                              0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                                   0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__afe_cm_sel_MASK                                                   0x00000030L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__att_pulldn_en_MASK                                                0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                                 0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                                           0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                                            0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                                            0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start__SHIFT                                            0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg__SHIFT                                             0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                             0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                              0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                             0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                              0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__ovrd_fast_start_MASK                                              0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__fast_start_reg_MASK                                               0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_SQ
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg__SHIFT                                                  0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp__SHIFT                                                 0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg__SHIFT                                                 0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh__SHIFT                                                0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__afe_loopback_sel__SHIFT                                                  0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_resp_reg_MASK                                                    0x00000003L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_resp_MASK                                                   0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x00000018L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__sq_ctrl_tresh_reg_MASK                                                   0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__ovrd_sq_ctrl_tresh_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__afe_loopback_sel_MASK                                                    0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CAL1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__dfe_taps_en_reg__SHIFT                                                 0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__dfe_taps_en_reg_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_dfe_taps_en_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__cal_muxb_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__ovrd_cal_muxb_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_CAL2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__afe_pd_eq_offset__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal__SHIFT                                             0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel__SHIFT                                               0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__afe_pd_eq_offset_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_idacs_use_uncal_MASK                                               0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__cal_muxa_sel_reg_MASK                                                  0x0000007CL
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__ovrd_cal_muxa_sel_MASK                                                 0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_vco__SHIFT                                       0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                                       0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc__SHIFT                                       0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl__SHIFT                                       0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz__SHIFT                                       0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg__SHIFT                                        0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_vco_MASK                                         0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                                         0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__override_regref_iqc_MASK                                         0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__boost_regref_iqc_MASK                                            0x00000018L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_slicer_ctrl_MASK                                         0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__ovrd_rx_term_ac_dcz_MASK                                         0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__rx_term_ac_dcz_reg_MASK                                          0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__master_atb_en__SHIFT                                              0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp__SHIFT                                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd__SHIFT                                                0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco__SHIFT                                          0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk__SHIFT                                          0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc__SHIFT                                          0x5
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl__SHIFT                                           0x6
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass__SHIFT                                         0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__master_atb_en_MASK                                                0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vp_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_gd_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_vco_MASK                                            0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_clk_MASK                                            0x00000010L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__meas_atb_vreg_iqc_MASK                                            0x00000020L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__regs_fb_div_ctrl_MASK                                             0x00000040L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__rx_vreg_clk_bypass_MASK                                           0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx__SHIFT                                                0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__meas_atb_rx_MASK                                                  0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd__SHIFT                                        0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u__SHIFT                                0x1
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco__SHIFT                                    0x2
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc__SHIFT                                      0x3
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux__SHIFT                                           0x4
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl__SHIFT                                 0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_gd_MASK                                          0x00000001L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_viref_200u_MASK                                  0x00000002L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_vibias_cdr_vco_MASK                                      0x00000004L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cdr_vco_vosc_MASK                                        0x00000008L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__meas_atb_cal_mux_MASK                                             0x00000070L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__rx_vreg_override_ring_ctrl_MASK                                   0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref__SHIFT                                          0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__meas_atb_cal_vref_MASK                                            0x0000007FL
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x00000080L
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref__SHIFT                                             0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__frc_atb_cal_vref_MASK                                               0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0x0000FF00L
+//DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x000000FFL
+#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0x0000FF00L
+//DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0
+#define DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWMEM_DIG_ROM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0
+#define DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA__SHIFT                                                    0x0
+#define DPCSSYS_CR4_RAWMEM_DIG_RAM_CMN0_B0_R0__DATA_MASK                                                      0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x000000E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x00000F00L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x00000060L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x00000380L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0x0000FFE0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x00000030L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0x0000C000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x00001FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x00000006L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x00000060L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0x0000FF80L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x00001FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x00000078L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x00000780L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x000007F8L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x000000FFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0x0000FFF0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x00000038L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0x0000FFC0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x000000FFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x00001F00L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x00000FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0x0000FFFFL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x0000001FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x000000E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x00007000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x0000000FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0x0000FFF0L
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0x0000FE00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x0000000CL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x00000040L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0x0000FF80L
+//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x0000001EL
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x000007E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0x0000F800L
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0x0000FFF8L
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x000001FFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0x0000FE00L
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x0000001FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0x0000FFE0L
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0x0000FFFEL
+//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x00000007L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0x0000FFF0L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x000000C0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x00000018L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x000000E0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x000000F0L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x00000003L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x00000070L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x00000100L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x00000200L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x00000400L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x00000800L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x00001000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0x0000E000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x00001FFFL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x00002000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x00004000L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x00008000L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x0000007FL
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x00000080L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0x0000FF00L
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0x0000FFFCL
+//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x00000001L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x00000002L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x00000004L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x00000008L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x00000010L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x00000020L
+#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0x0000FFC0L
+
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h
new file mode 100644
index 000000000000..dfacc6b5d89d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_offset.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_1_OFFSET_HEADER
+#define _mp_13_0_1_OFFSET_HEADER
+
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+// base address: 0x0
+#define regMP0_SMN_C2PMSG_32                                                                            0x0060
+#define regMP0_SMN_C2PMSG_32_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_33                                                                            0x0061
+#define regMP0_SMN_C2PMSG_33_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_34                                                                            0x0062
+#define regMP0_SMN_C2PMSG_34_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_35                                                                            0x0063
+#define regMP0_SMN_C2PMSG_35_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_36                                                                            0x0064
+#define regMP0_SMN_C2PMSG_36_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_37                                                                            0x0065
+#define regMP0_SMN_C2PMSG_37_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_38                                                                            0x0066
+#define regMP0_SMN_C2PMSG_38_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_39                                                                            0x0067
+#define regMP0_SMN_C2PMSG_39_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_40                                                                            0x0068
+#define regMP0_SMN_C2PMSG_40_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_41                                                                            0x0069
+#define regMP0_SMN_C2PMSG_41_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_42                                                                            0x006a
+#define regMP0_SMN_C2PMSG_42_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_43                                                                            0x006b
+#define regMP0_SMN_C2PMSG_43_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_44                                                                            0x006c
+#define regMP0_SMN_C2PMSG_44_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_45                                                                            0x006d
+#define regMP0_SMN_C2PMSG_45_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_46                                                                            0x006e
+#define regMP0_SMN_C2PMSG_46_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_47                                                                            0x006f
+#define regMP0_SMN_C2PMSG_47_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_48                                                                            0x0070
+#define regMP0_SMN_C2PMSG_48_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_49                                                                            0x0071
+#define regMP0_SMN_C2PMSG_49_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_50                                                                            0x0072
+#define regMP0_SMN_C2PMSG_50_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_51                                                                            0x0073
+#define regMP0_SMN_C2PMSG_51_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_52                                                                            0x0074
+#define regMP0_SMN_C2PMSG_52_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_53                                                                            0x0075
+#define regMP0_SMN_C2PMSG_53_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_54                                                                            0x0076
+#define regMP0_SMN_C2PMSG_54_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_55                                                                            0x0077
+#define regMP0_SMN_C2PMSG_55_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_56                                                                            0x0078
+#define regMP0_SMN_C2PMSG_56_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_57                                                                            0x0079
+#define regMP0_SMN_C2PMSG_57_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_58                                                                            0x007a
+#define regMP0_SMN_C2PMSG_58_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_59                                                                            0x007b
+#define regMP0_SMN_C2PMSG_59_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_60                                                                            0x007c
+#define regMP0_SMN_C2PMSG_60_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_61                                                                            0x007d
+#define regMP0_SMN_C2PMSG_61_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_62                                                                            0x007e
+#define regMP0_SMN_C2PMSG_62_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_63                                                                            0x007f
+#define regMP0_SMN_C2PMSG_63_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_64                                                                            0x0080
+#define regMP0_SMN_C2PMSG_64_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_65                                                                            0x0081
+#define regMP0_SMN_C2PMSG_65_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_66                                                                            0x0082
+#define regMP0_SMN_C2PMSG_66_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_67                                                                            0x0083
+#define regMP0_SMN_C2PMSG_67_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_68                                                                            0x0084
+#define regMP0_SMN_C2PMSG_68_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_69                                                                            0x0085
+#define regMP0_SMN_C2PMSG_69_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_70                                                                            0x0086
+#define regMP0_SMN_C2PMSG_70_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_71                                                                            0x0087
+#define regMP0_SMN_C2PMSG_71_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_72                                                                            0x0088
+#define regMP0_SMN_C2PMSG_72_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_73                                                                            0x0089
+#define regMP0_SMN_C2PMSG_73_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_74                                                                            0x008a
+#define regMP0_SMN_C2PMSG_74_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_75                                                                            0x008b
+#define regMP0_SMN_C2PMSG_75_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_76                                                                            0x008c
+#define regMP0_SMN_C2PMSG_76_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_77                                                                            0x008d
+#define regMP0_SMN_C2PMSG_77_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_78                                                                            0x008e
+#define regMP0_SMN_C2PMSG_78_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_79                                                                            0x008f
+#define regMP0_SMN_C2PMSG_79_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_80                                                                            0x0090
+#define regMP0_SMN_C2PMSG_80_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_81                                                                            0x0091
+#define regMP0_SMN_C2PMSG_81_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_82                                                                            0x0092
+#define regMP0_SMN_C2PMSG_82_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_83                                                                            0x0093
+#define regMP0_SMN_C2PMSG_83_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_84                                                                            0x0094
+#define regMP0_SMN_C2PMSG_84_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_85                                                                            0x0095
+#define regMP0_SMN_C2PMSG_85_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_86                                                                            0x0096
+#define regMP0_SMN_C2PMSG_86_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_87                                                                            0x0097
+#define regMP0_SMN_C2PMSG_87_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_88                                                                            0x0098
+#define regMP0_SMN_C2PMSG_88_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_89                                                                            0x0099
+#define regMP0_SMN_C2PMSG_89_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_90                                                                            0x009a
+#define regMP0_SMN_C2PMSG_90_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_91                                                                            0x009b
+#define regMP0_SMN_C2PMSG_91_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_92                                                                            0x009c
+#define regMP0_SMN_C2PMSG_92_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_93                                                                            0x009d
+#define regMP0_SMN_C2PMSG_93_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_94                                                                            0x009e
+#define regMP0_SMN_C2PMSG_94_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_95                                                                            0x009f
+#define regMP0_SMN_C2PMSG_95_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_96                                                                            0x00a0
+#define regMP0_SMN_C2PMSG_96_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_97                                                                            0x00a1
+#define regMP0_SMN_C2PMSG_97_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_98                                                                            0x00a2
+#define regMP0_SMN_C2PMSG_98_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_99                                                                            0x00a3
+#define regMP0_SMN_C2PMSG_99_BASE_IDX                                                                   0
+#define regMP0_SMN_C2PMSG_100                                                                           0x00a4
+#define regMP0_SMN_C2PMSG_100_BASE_IDX                                                                  0
+#define regMP0_SMN_C2PMSG_101                                                                           0x00a5
+#define regMP0_SMN_C2PMSG_101_BASE_IDX                                                                  0
+#define regMP0_SMN_C2PMSG_102                                                                           0x00a6
+#define regMP0_SMN_C2PMSG_102_BASE_IDX                                                                  0
+#define regMP0_SMN_C2PMSG_103                                                                           0x00a7
+#define regMP0_SMN_C2PMSG_103_BASE_IDX                                                                  0
+#define regMP0_SMN_IH_CREDIT                                                                            0x00c1
+#define regMP0_SMN_IH_CREDIT_BASE_IDX                                                                   0
+#define regMP0_SMN_IH_SW_INT                                                                            0x00c2
+#define regMP0_SMN_IH_SW_INT_BASE_IDX                                                                   0
+#define regMP0_SMN_IH_SW_INT_CTRL                                                                       0x00c3
+#define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+// base address: 0x0
+#define regMP1_SMN_C2PMSG_32                                                                            0x0260
+#define regMP1_SMN_C2PMSG_32_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_33                                                                            0x0261
+#define regMP1_SMN_C2PMSG_33_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_34                                                                            0x0262
+#define regMP1_SMN_C2PMSG_34_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_35                                                                            0x0263
+#define regMP1_SMN_C2PMSG_35_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_36                                                                            0x0264
+#define regMP1_SMN_C2PMSG_36_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_37                                                                            0x0265
+#define regMP1_SMN_C2PMSG_37_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_38                                                                            0x0266
+#define regMP1_SMN_C2PMSG_38_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_39                                                                            0x0267
+#define regMP1_SMN_C2PMSG_39_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_40                                                                            0x0268
+#define regMP1_SMN_C2PMSG_40_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_41                                                                            0x0269
+#define regMP1_SMN_C2PMSG_41_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_42                                                                            0x026a
+#define regMP1_SMN_C2PMSG_42_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_43                                                                            0x026b
+#define regMP1_SMN_C2PMSG_43_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_44                                                                            0x026c
+#define regMP1_SMN_C2PMSG_44_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_45                                                                            0x026d
+#define regMP1_SMN_C2PMSG_45_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_46                                                                            0x026e
+#define regMP1_SMN_C2PMSG_46_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_47                                                                            0x026f
+#define regMP1_SMN_C2PMSG_47_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_48                                                                            0x0270
+#define regMP1_SMN_C2PMSG_48_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_49                                                                            0x0271
+#define regMP1_SMN_C2PMSG_49_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_50                                                                            0x0272
+#define regMP1_SMN_C2PMSG_50_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_51                                                                            0x0273
+#define regMP1_SMN_C2PMSG_51_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_52                                                                            0x0274
+#define regMP1_SMN_C2PMSG_52_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_53                                                                            0x0275
+#define regMP1_SMN_C2PMSG_53_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_54                                                                            0x0276
+#define regMP1_SMN_C2PMSG_54_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_55                                                                            0x0277
+#define regMP1_SMN_C2PMSG_55_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_56                                                                            0x0278
+#define regMP1_SMN_C2PMSG_56_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_57                                                                            0x0279
+#define regMP1_SMN_C2PMSG_57_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_58                                                                            0x027a
+#define regMP1_SMN_C2PMSG_58_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_59                                                                            0x027b
+#define regMP1_SMN_C2PMSG_59_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_60                                                                            0x027c
+#define regMP1_SMN_C2PMSG_60_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_61                                                                            0x027d
+#define regMP1_SMN_C2PMSG_61_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_62                                                                            0x027e
+#define regMP1_SMN_C2PMSG_62_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_63                                                                            0x027f
+#define regMP1_SMN_C2PMSG_63_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_64                                                                            0x0280
+#define regMP1_SMN_C2PMSG_64_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_65                                                                            0x0281
+#define regMP1_SMN_C2PMSG_65_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_66                                                                            0x0282
+#define regMP1_SMN_C2PMSG_66_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_67                                                                            0x0283
+#define regMP1_SMN_C2PMSG_67_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_68                                                                            0x0284
+#define regMP1_SMN_C2PMSG_68_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_69                                                                            0x0285
+#define regMP1_SMN_C2PMSG_69_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_70                                                                            0x0286
+#define regMP1_SMN_C2PMSG_70_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_71                                                                            0x0287
+#define regMP1_SMN_C2PMSG_71_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_72                                                                            0x0288
+#define regMP1_SMN_C2PMSG_72_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_73                                                                            0x0289
+#define regMP1_SMN_C2PMSG_73_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_74                                                                            0x028a
+#define regMP1_SMN_C2PMSG_74_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_75                                                                            0x028b
+#define regMP1_SMN_C2PMSG_75_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_76                                                                            0x028c
+#define regMP1_SMN_C2PMSG_76_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_77                                                                            0x028d
+#define regMP1_SMN_C2PMSG_77_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_78                                                                            0x028e
+#define regMP1_SMN_C2PMSG_78_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_79                                                                            0x028f
+#define regMP1_SMN_C2PMSG_79_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_80                                                                            0x0290
+#define regMP1_SMN_C2PMSG_80_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_81                                                                            0x0291
+#define regMP1_SMN_C2PMSG_81_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_82                                                                            0x0292
+#define regMP1_SMN_C2PMSG_82_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_83                                                                            0x0293
+#define regMP1_SMN_C2PMSG_83_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_84                                                                            0x0294
+#define regMP1_SMN_C2PMSG_84_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_85                                                                            0x0295
+#define regMP1_SMN_C2PMSG_85_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_86                                                                            0x0296
+#define regMP1_SMN_C2PMSG_86_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_87                                                                            0x0297
+#define regMP1_SMN_C2PMSG_87_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_88                                                                            0x0298
+#define regMP1_SMN_C2PMSG_88_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_89                                                                            0x0299
+#define regMP1_SMN_C2PMSG_89_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_90                                                                            0x029a
+#define regMP1_SMN_C2PMSG_90_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_91                                                                            0x029b
+#define regMP1_SMN_C2PMSG_91_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_92                                                                            0x029c
+#define regMP1_SMN_C2PMSG_92_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_93                                                                            0x029d
+#define regMP1_SMN_C2PMSG_93_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_94                                                                            0x029e
+#define regMP1_SMN_C2PMSG_94_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_95                                                                            0x029f
+#define regMP1_SMN_C2PMSG_95_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_96                                                                            0x02a0
+#define regMP1_SMN_C2PMSG_96_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_97                                                                            0x02a1
+#define regMP1_SMN_C2PMSG_97_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_98                                                                            0x02a2
+#define regMP1_SMN_C2PMSG_98_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_99                                                                            0x02a3
+#define regMP1_SMN_C2PMSG_99_BASE_IDX                                                                   0
+#define regMP1_SMN_C2PMSG_100                                                                           0x02a4
+#define regMP1_SMN_C2PMSG_100_BASE_IDX                                                                  0
+#define regMP1_SMN_C2PMSG_101                                                                           0x02a5
+#define regMP1_SMN_C2PMSG_101_BASE_IDX                                                                  0
+#define regMP1_SMN_C2PMSG_102                                                                           0x02a6
+#define regMP1_SMN_C2PMSG_102_BASE_IDX                                                                  0
+#define regMP1_SMN_C2PMSG_103                                                                           0x02a7
+#define regMP1_SMN_C2PMSG_103_BASE_IDX                                                                  0
+#define regMP1_SMN_IH_CREDIT                                                                            0x02c1
+#define regMP1_SMN_IH_CREDIT_BASE_IDX                                                                   0
+#define regMP1_SMN_IH_SW_INT                                                                            0x02c2
+#define regMP1_SMN_IH_SW_INT_BASE_IDX                                                                   0
+#define regMP1_SMN_IH_SW_INT_CTRL                                                                       0x02c3
+#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX                                                              0
+#define regMP1_SMN_FPS_CNT                                                                              0x02c4
+#define regMP1_SMN_FPS_CNT_BASE_IDX                                                                     0
+#define regMP1_SMN_EXT_SCRATCH0                                                                         0x0340
+#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH1                                                                         0x0341
+#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH2                                                                         0x0342
+#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH3                                                                         0x0343
+#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH4                                                                         0x0344
+#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH5                                                                         0x0345
+#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH6                                                                         0x0346
+#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX                                                                0
+#define regMP1_SMN_EXT_SCRATCH7                                                                         0x0347
+#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX                                                                0
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h
new file mode 100644
index 000000000000..2d5e8b58e693
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_1_sh_mask.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ *
+ */
+#ifndef _mp_13_0_1_SH_MASK_HEADER
+#define _mp_13_0_1_SH_MASK_HEADER
+
+
+// addressBlock: mp_SmuMp0_SmnDec
+//MP0_SMN_C2PMSG_32
+#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_33
+#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_34
+#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_35
+#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_36
+#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_37
+#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_38
+#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_39
+#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_40
+#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_41
+#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_42
+#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_43
+#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_44
+#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_45
+#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_46
+#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_47
+#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_48
+#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_49
+#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_50
+#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_51
+#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_52
+#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_53
+#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_54
+#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_55
+#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_56
+#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_57
+#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_58
+#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_59
+#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_60
+#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_61
+#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_62
+#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_63
+#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_64
+#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_65
+#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_66
+#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_67
+#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_68
+#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_69
+#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_70
+#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_71
+#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_72
+#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_73
+#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_74
+#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_75
+#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_76
+#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_77
+#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_78
+#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_79
+#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_80
+#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_81
+#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_82
+#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_83
+#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_84
+#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_85
+#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_86
+#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_87
+#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_88
+#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_89
+#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_90
+#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_91
+#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_92
+#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_93
+#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_94
+#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_95
+#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_96
+#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_97
+#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_98
+#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_99
+#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
+#define MP0_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP0_SMN_C2PMSG_100
+#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_101
+#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_102
+#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_C2PMSG_103
+#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
+#define MP0_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP0_SMN_IH_CREDIT
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
+#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
+#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
+#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
+//MP0_SMN_IH_SW_INT
+#define MP0_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
+#define MP0_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
+#define MP0_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
+#define MP0_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
+//MP0_SMN_IH_SW_INT_CTRL
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
+#define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
+#define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
+
+
+// addressBlock: mp_SmuMp1Pub_CruDec
+//MP1_FIRMWARE_FLAGS
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT                                                         0x0
+#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT                                                                   0x1
+#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK                                                           0x00000001L
+#define MP1_FIRMWARE_FLAGS__RESERVED_MASK                                                                     0xFFFFFFFEL
+
+
+// addressBlock: mp_SmuMp1_SmnDec
+//MP1_SMN_C2PMSG_32
+#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_32__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_33
+#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_33__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_34
+#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_34__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_35
+#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_35__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_36
+#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_36__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_37
+#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_37__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_38
+#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_38__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_39
+#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_39__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_40
+#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_40__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_41
+#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_41__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_42
+#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_42__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_43
+#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_43__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_44
+#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_44__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_45
+#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_45__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_46
+#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_46__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_47
+#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_47__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_48
+#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_48__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_49
+#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_49__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_50
+#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_50__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_51
+#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_51__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_52
+#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_52__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_53
+#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_53__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_54
+#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_54__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_55
+#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_55__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_56
+#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_56__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_57
+#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_57__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_58
+#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_58__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_59
+#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_59__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_60
+#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_60__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_61
+#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_61__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_62
+#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_62__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_63
+#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_63__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_64
+#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_64__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_65
+#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_65__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_66
+#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_66__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_67
+#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_67__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_68
+#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_68__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_69
+#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_69__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_70
+#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_70__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_71
+#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_71__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_72
+#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_72__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_73
+#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_73__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_74
+#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_74__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_75
+#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_75__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_76
+#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_76__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_77
+#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_77__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_78
+#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_78__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_79
+#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_79__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_80
+#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_80__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_81
+#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_81__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_82
+#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_82__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_83
+#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_83__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_84
+#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_84__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_85
+#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_85__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_86
+#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_86__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_87
+#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_87__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_88
+#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_88__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_89
+#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_89__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_90
+#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_90__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_91
+#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_91__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_92
+#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_92__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_93
+#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_93__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_94
+#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_94__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_95
+#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_95__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_96
+#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_96__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_97
+#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_97__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_98
+#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_98__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_99
+#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT                                                                     0x0
+#define MP1_SMN_C2PMSG_99__CONTENT_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_C2PMSG_100
+#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_100__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_101
+#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_101__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_102
+#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_102__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_C2PMSG_103
+#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT                                                                    0x0
+#define MP1_SMN_C2PMSG_103__CONTENT_MASK                                                                      0xFFFFFFFFL
+//MP1_SMN_IH_CREDIT
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT                                                                0x0
+#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT                                                                   0x10
+#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK                                                                  0x00000003L
+#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK                                                                     0x00FF0000L
+//MP1_SMN_IH_SW_INT
+#define MP1_SMN_IH_SW_INT__ID__SHIFT                                                                          0x0
+#define MP1_SMN_IH_SW_INT__VALID__SHIFT                                                                       0x8
+#define MP1_SMN_IH_SW_INT__ID_MASK                                                                            0x000000FFL
+#define MP1_SMN_IH_SW_INT__VALID_MASK                                                                         0x00000100L
+//MP1_SMN_IH_SW_INT_CTRL
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT                                                               0x0
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT                                                                0x8
+#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK                                                                 0x00000001L
+#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK                                                                  0x00000100L
+//MP1_SMN_FPS_CNT
+#define MP1_SMN_FPS_CNT__COUNT__SHIFT                                                                         0x0
+#define MP1_SMN_FPS_CNT__COUNT_MASK                                                                           0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH0
+#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH0__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH1
+#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH1__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH2
+#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH2__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH3
+#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH3__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH4
+#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH4__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH5
+#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH5__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH6
+#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH6__DATA_MASK                                                                       0xFFFFFFFFL
+//MP1_SMN_EXT_SCRATCH7
+#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT                                                                     0x0
+#define MP1_SMN_EXT_SCRATCH7__DATA_MASK                                                                       0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index 28deecc2f990..3811e58dd857 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -883,7 +883,8 @@ struct  atom_bracket_layout_record
 };
 
 enum atom_display_device_tag_def{
-  ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002,  //an embedded display is either an LVDS or eDP signal type of display
+  ATOM_DISPLAY_LCD1_SUPPORT            = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
+  ATOM_DISPLAY_LCD2_SUPPORT			       = 0x0020, //second edp device tag 0x0020 for backward compability
   ATOM_DISPLAY_DFP1_SUPPORT            = 0x0008,
   ATOM_DISPLAY_DFP2_SUPPORT            = 0x0080,
   ATOM_DISPLAY_DFP3_SUPPORT            = 0x0200,
@@ -1413,6 +1414,59 @@ struct atom_integrated_system_info_v2_1
 
 };
 
+struct atom_n6_display_phy_tuning_set {
+	uint8_t display_signal_type;
+	uint8_t phy_sel;
+	uint8_t preset_level;
+	uint8_t reserved1;
+	uint32_t reserved2;
+	uint32_t speed_upto;
+	uint8_t tx_vboost_level;
+	uint8_t tx_vreg_v2i;
+	uint8_t tx_vregdrv_byp;
+	uint8_t tx_term_cntl;
+	uint8_t tx_peak_level;
+	uint8_t tx_slew_en;
+	uint8_t tx_eq_pre;
+	uint8_t tx_eq_main;
+	uint8_t tx_eq_post;
+	uint8_t tx_en_inv_pre;
+	uint8_t tx_en_inv_post;
+	uint8_t reserved3;
+	uint32_t reserved4;
+	uint32_t reserved5;
+	uint32_t reserved6;
+};
+
+struct atom_display_phy_tuning_info {
+	struct atom_common_table_header table_header;
+	struct atom_n6_display_phy_tuning_set disp_phy_tuning[1];
+};
+
+struct atom_integrated_system_info_v2_2
+{
+	struct  atom_common_table_header  table_header;
+	uint32_t  vbios_misc;                       //enum of atom_system_vbiosmisc_def
+	uint32_t  gpucapinfo;                       //enum of atom_system_gpucapinf_def
+	uint32_t  system_config;
+	uint32_t  cpucapinfo;
+	uint16_t  gpuclk_ss_percentage;             //unit of 0.001%,   1000 mean 1%
+	uint16_t  gpuclk_ss_type;
+	uint16_t  dpphy_override;                   // bit vector, enum of atom_sysinfo_dpphy_override_def
+	uint8_t   memorytype;                       // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
+	uint8_t   umachannelnumber;                 // number of memory channels
+	uint8_t   htc_hyst_limit;
+	uint8_t   htc_tmp_limit;
+	uint8_t   reserved1;
+	uint8_t   reserved2;
+	struct edp_info_table edp1_info;
+	struct edp_info_table edp2_info;
+	uint32_t  reserved3[8];
+	struct atom_external_display_connection_info extdispconninfo;
+
+	uint32_t  reserved4[189];
+};
+
 // system_config
 enum atom_system_vbiosmisc_def{
   INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index b1cd52a9d684..9f73a2f586d8 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -124,6 +124,8 @@ enum amd_pp_sensors {
 	AMDGPU_PP_SENSOR_VCE_POWER,
 	AMDGPU_PP_SENSOR_UVD_POWER,
 	AMDGPU_PP_SENSOR_GPU_POWER,
+	AMDGPU_PP_SENSOR_SS_APU_SHARE,
+	AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 	AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 	AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
@@ -192,6 +194,48 @@ enum pp_df_cstate {
 	DF_CSTATE_ALLOW,
 };
 
+/**
+ * DOC: amdgpu_pp_power
+ *
+ * APU power is managed to system-level requirements through the PPT
+ * (package power tracking) feature. PPT is intended to limit power to the
+ * requirements of the power source and could be dynamically updated to
+ * maximize APU performance within the system power budget.
+ *
+ * Two types of power measurement can be requested, where supported, with
+ * :c:type:`enum pp_power_type <pp_power_type>`.
+ */
+
+/**
+ * enum pp_power_limit_level - Used to query the power limits
+ *
+ * @PP_PWR_LIMIT_MIN: Minimum Power Limit
+ * @PP_PWR_LIMIT_CURRENT: Current Power Limit
+ * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
+ * @PP_PWR_LIMIT_MAX: Maximum Power Limit
+ */
+enum pp_power_limit_level
+{
+	PP_PWR_LIMIT_MIN = -1,
+	PP_PWR_LIMIT_CURRENT,
+	PP_PWR_LIMIT_DEFAULT,
+	PP_PWR_LIMIT_MAX,
+};
+
+/**
+ * enum pp_power_type - Used to specify the type of the requested power
+ *
+ * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
+ * moving average of APU power (default ~5000 ms).
+ * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
+ * where supported.
+ */
+enum pp_power_type
+{
+	PP_PWR_TYPE_SUSTAINED,
+	PP_PWR_TYPE_FAST,
+};
+
 #define PP_GROUP_MASK        0xF0000000
 #define PP_GROUP_SHIFT       28
 
@@ -291,8 +335,9 @@ struct amd_pm_funcs {
 				uint32_t block_type, bool gate);
 	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 	int (*set_power_limit)(void *handle, uint32_t n);
-	int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit,
-			bool default_limit);
+	int (*get_power_limit)(void *handle, uint32_t *limit,
+			enum pp_power_limit_level pp_limit_level,
+			enum pp_power_type power_type);
 	int (*get_power_profile_mode)(void *handle, char *buf);
 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 	int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
diff --git a/drivers/gpu/drm/amd/include/yellow_carp_offset.h b/drivers/gpu/drm/amd/include/yellow_carp_offset.h
new file mode 100644
index 000000000000..76b9eb3f441d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/yellow_carp_offset.h
@@ -0,0 +1,1366 @@
+#ifndef YELLOW_CARP_OFFSET_H
+#define YELLOW_CARP_OFFSET_H
+
+
+#define MAX_INSTANCE                                        7
+#define MAX_SEGMENT                                         6
+
+
+struct IP_BASE_INSTANCE
+{
+    unsigned int segment[MAX_SEGMENT];
+};
+
+struct IP_BASE
+{
+    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
+};
+
+
+static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
+                                        { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
+                                        { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
+                                        { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
+                                        { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
+                                        { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
+                                        { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0x00000260, 0x00000280, 0x0240B400, 0x02413C00, 0x02416000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x02447800, 0x00C00000, 0x03640000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE PCIE_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } },
+                                        { { 0x02411C00, 0x04480000, 0, 0, 0, 0 } },
+                                        { { 0x02412000, 0x044C0000, 0, 0, 0, 0 } },
+                                        { { 0x02412400, 0x04500000, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } },
+                                        { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0x02425C00, 0, 0 } },
+                                        { { 0x00094000, 0x000D4000, 0x02426000, 0x02426400, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } },
+                                        { { 0, 0, 0, 0, 0, 0 } } } };
+
+
+#define ACP_BASE__INST0_SEG0                       0x02403800
+#define ACP_BASE__INST0_SEG1                       0x00480000
+#define ACP_BASE__INST0_SEG2                       0
+#define ACP_BASE__INST0_SEG3                       0
+#define ACP_BASE__INST0_SEG4                       0
+#define ACP_BASE__INST0_SEG5                       0
+
+#define ACP_BASE__INST1_SEG0                       0
+#define ACP_BASE__INST1_SEG1                       0
+#define ACP_BASE__INST1_SEG2                       0
+#define ACP_BASE__INST1_SEG3                       0
+#define ACP_BASE__INST1_SEG4                       0
+#define ACP_BASE__INST1_SEG5                       0
+
+#define ACP_BASE__INST2_SEG0                       0
+#define ACP_BASE__INST2_SEG1                       0
+#define ACP_BASE__INST2_SEG2                       0
+#define ACP_BASE__INST2_SEG3                       0
+#define ACP_BASE__INST2_SEG4                       0
+#define ACP_BASE__INST2_SEG5                       0
+
+#define ACP_BASE__INST3_SEG0                       0
+#define ACP_BASE__INST3_SEG1                       0
+#define ACP_BASE__INST3_SEG2                       0
+#define ACP_BASE__INST3_SEG3                       0
+#define ACP_BASE__INST3_SEG4                       0
+#define ACP_BASE__INST3_SEG5                       0
+
+#define ACP_BASE__INST4_SEG0                       0
+#define ACP_BASE__INST4_SEG1                       0
+#define ACP_BASE__INST4_SEG2                       0
+#define ACP_BASE__INST4_SEG3                       0
+#define ACP_BASE__INST4_SEG4                       0
+#define ACP_BASE__INST4_SEG5                       0
+
+#define ACP_BASE__INST5_SEG0                       0
+#define ACP_BASE__INST5_SEG1                       0
+#define ACP_BASE__INST5_SEG2                       0
+#define ACP_BASE__INST5_SEG3                       0
+#define ACP_BASE__INST5_SEG4                       0
+#define ACP_BASE__INST5_SEG5                       0
+
+#define ACP_BASE__INST6_SEG0                       0
+#define ACP_BASE__INST6_SEG1                       0
+#define ACP_BASE__INST6_SEG2                       0
+#define ACP_BASE__INST6_SEG3                       0
+#define ACP_BASE__INST6_SEG4                       0
+#define ACP_BASE__INST6_SEG5                       0
+
+#define ATHUB_BASE__INST0_SEG0                     0x00000C00
+#define ATHUB_BASE__INST0_SEG1                     0x00013300
+#define ATHUB_BASE__INST0_SEG2                     0x02408C00
+#define ATHUB_BASE__INST0_SEG3                     0
+#define ATHUB_BASE__INST0_SEG4                     0
+#define ATHUB_BASE__INST0_SEG5                     0
+
+#define ATHUB_BASE__INST1_SEG0                     0
+#define ATHUB_BASE__INST1_SEG1                     0
+#define ATHUB_BASE__INST1_SEG2                     0
+#define ATHUB_BASE__INST1_SEG3                     0
+#define ATHUB_BASE__INST1_SEG4                     0
+#define ATHUB_BASE__INST1_SEG5                     0
+
+#define ATHUB_BASE__INST2_SEG0                     0
+#define ATHUB_BASE__INST2_SEG1                     0
+#define ATHUB_BASE__INST2_SEG2                     0
+#define ATHUB_BASE__INST2_SEG3                     0
+#define ATHUB_BASE__INST2_SEG4                     0
+#define ATHUB_BASE__INST2_SEG5                     0
+
+#define ATHUB_BASE__INST3_SEG0                     0
+#define ATHUB_BASE__INST3_SEG1                     0
+#define ATHUB_BASE__INST3_SEG2                     0
+#define ATHUB_BASE__INST3_SEG3                     0
+#define ATHUB_BASE__INST3_SEG4                     0
+#define ATHUB_BASE__INST3_SEG5                     0
+
+#define ATHUB_BASE__INST4_SEG0                     0
+#define ATHUB_BASE__INST4_SEG1                     0
+#define ATHUB_BASE__INST4_SEG2                     0
+#define ATHUB_BASE__INST4_SEG3                     0
+#define ATHUB_BASE__INST4_SEG4                     0
+#define ATHUB_BASE__INST4_SEG5                     0
+
+#define ATHUB_BASE__INST5_SEG0                     0
+#define ATHUB_BASE__INST5_SEG1                     0
+#define ATHUB_BASE__INST5_SEG2                     0
+#define ATHUB_BASE__INST5_SEG3                     0
+#define ATHUB_BASE__INST5_SEG4                     0
+#define ATHUB_BASE__INST5_SEG5                     0
+
+#define ATHUB_BASE__INST6_SEG0                     0
+#define ATHUB_BASE__INST6_SEG1                     0
+#define ATHUB_BASE__INST6_SEG2                     0
+#define ATHUB_BASE__INST6_SEG3                     0
+#define ATHUB_BASE__INST6_SEG4                     0
+#define ATHUB_BASE__INST6_SEG5                     0
+
+#define CLK_BASE__INST0_SEG0                       0x00016C00
+#define CLK_BASE__INST0_SEG1                       0x02401800
+#define CLK_BASE__INST0_SEG2                       0
+#define CLK_BASE__INST0_SEG3                       0
+#define CLK_BASE__INST0_SEG4                       0
+#define CLK_BASE__INST0_SEG5                       0
+
+#define CLK_BASE__INST1_SEG0                       0x00016E00
+#define CLK_BASE__INST1_SEG1                       0x02401C00
+#define CLK_BASE__INST1_SEG2                       0
+#define CLK_BASE__INST1_SEG3                       0
+#define CLK_BASE__INST1_SEG4                       0
+#define CLK_BASE__INST1_SEG5                       0
+
+#define CLK_BASE__INST2_SEG0                       0x00017000
+#define CLK_BASE__INST2_SEG1                       0x02402000
+#define CLK_BASE__INST2_SEG2                       0
+#define CLK_BASE__INST2_SEG3                       0
+#define CLK_BASE__INST2_SEG4                       0
+#define CLK_BASE__INST2_SEG5                       0
+
+#define CLK_BASE__INST3_SEG0                       0x00017200
+#define CLK_BASE__INST3_SEG1                       0x02402400
+#define CLK_BASE__INST3_SEG2                       0
+#define CLK_BASE__INST3_SEG3                       0
+#define CLK_BASE__INST3_SEG4                       0
+#define CLK_BASE__INST3_SEG5                       0
+
+#define CLK_BASE__INST4_SEG0                       0x0001B000
+#define CLK_BASE__INST4_SEG1                       0x0242D800
+#define CLK_BASE__INST4_SEG2                       0
+#define CLK_BASE__INST4_SEG3                       0
+#define CLK_BASE__INST4_SEG4                       0
+#define CLK_BASE__INST4_SEG5                       0
+
+#define CLK_BASE__INST5_SEG0                       0x0001B200
+#define CLK_BASE__INST5_SEG1                       0x0242DC00
+#define CLK_BASE__INST5_SEG2                       0
+#define CLK_BASE__INST5_SEG3                       0
+#define CLK_BASE__INST5_SEG4                       0
+#define CLK_BASE__INST5_SEG5                       0
+
+#define CLK_BASE__INST6_SEG0                       0x0001B400
+#define CLK_BASE__INST6_SEG1                       0x0242E000
+#define CLK_BASE__INST6_SEG2                       0
+#define CLK_BASE__INST6_SEG3                       0
+#define CLK_BASE__INST6_SEG4                       0
+#define CLK_BASE__INST6_SEG5                       0
+
+#define DBGU_IO_BASE__INST0_SEG0                   0x000001E0
+#define DBGU_IO_BASE__INST0_SEG1                   0x00000260
+#define DBGU_IO_BASE__INST0_SEG2                   0x00000280
+#define DBGU_IO_BASE__INST0_SEG3                   0x0240B400
+#define DBGU_IO_BASE__INST0_SEG4                   0x02413C00
+#define DBGU_IO_BASE__INST0_SEG5                   0x02416000
+
+#define DBGU_IO_BASE__INST1_SEG0                   0
+#define DBGU_IO_BASE__INST1_SEG1                   0
+#define DBGU_IO_BASE__INST1_SEG2                   0
+#define DBGU_IO_BASE__INST1_SEG3                   0
+#define DBGU_IO_BASE__INST1_SEG4                   0
+#define DBGU_IO_BASE__INST1_SEG5                   0
+
+#define DBGU_IO_BASE__INST2_SEG0                   0
+#define DBGU_IO_BASE__INST2_SEG1                   0
+#define DBGU_IO_BASE__INST2_SEG2                   0
+#define DBGU_IO_BASE__INST2_SEG3                   0
+#define DBGU_IO_BASE__INST2_SEG4                   0
+#define DBGU_IO_BASE__INST2_SEG5                   0
+
+#define DBGU_IO_BASE__INST3_SEG0                   0
+#define DBGU_IO_BASE__INST3_SEG1                   0
+#define DBGU_IO_BASE__INST3_SEG2                   0
+#define DBGU_IO_BASE__INST3_SEG3                   0
+#define DBGU_IO_BASE__INST3_SEG4                   0
+#define DBGU_IO_BASE__INST3_SEG5                   0
+
+#define DBGU_IO_BASE__INST4_SEG0                   0
+#define DBGU_IO_BASE__INST4_SEG1                   0
+#define DBGU_IO_BASE__INST4_SEG2                   0
+#define DBGU_IO_BASE__INST4_SEG3                   0
+#define DBGU_IO_BASE__INST4_SEG4                   0
+#define DBGU_IO_BASE__INST4_SEG5                   0
+
+#define DBGU_IO_BASE__INST5_SEG0                   0
+#define DBGU_IO_BASE__INST5_SEG1                   0
+#define DBGU_IO_BASE__INST5_SEG2                   0
+#define DBGU_IO_BASE__INST5_SEG3                   0
+#define DBGU_IO_BASE__INST5_SEG4                   0
+#define DBGU_IO_BASE__INST5_SEG5                   0
+
+#define DBGU_IO_BASE__INST6_SEG0                   0
+#define DBGU_IO_BASE__INST6_SEG1                   0
+#define DBGU_IO_BASE__INST6_SEG2                   0
+#define DBGU_IO_BASE__INST6_SEG3                   0
+#define DBGU_IO_BASE__INST6_SEG4                   0
+#define DBGU_IO_BASE__INST6_SEG5                   0
+
+#define DCN_BASE__INST0_SEG0                       0x00000012
+#define DCN_BASE__INST0_SEG1                       0x000000C0
+#define DCN_BASE__INST0_SEG2                       0x000034C0
+#define DCN_BASE__INST0_SEG3                       0x00009000
+#define DCN_BASE__INST0_SEG4                       0x02403C00
+#define DCN_BASE__INST0_SEG5                       0
+
+#define DCN_BASE__INST1_SEG0                       0
+#define DCN_BASE__INST1_SEG1                       0
+#define DCN_BASE__INST1_SEG2                       0
+#define DCN_BASE__INST1_SEG3                       0
+#define DCN_BASE__INST1_SEG4                       0
+#define DCN_BASE__INST1_SEG5                       0
+
+#define DCN_BASE__INST2_SEG0                       0
+#define DCN_BASE__INST2_SEG1                       0
+#define DCN_BASE__INST2_SEG2                       0
+#define DCN_BASE__INST2_SEG3                       0
+#define DCN_BASE__INST2_SEG4                       0
+#define DCN_BASE__INST2_SEG5                       0
+
+#define DCN_BASE__INST3_SEG0                       0
+#define DCN_BASE__INST3_SEG1                       0
+#define DCN_BASE__INST3_SEG2                       0
+#define DCN_BASE__INST3_SEG3                       0
+#define DCN_BASE__INST3_SEG4                       0
+#define DCN_BASE__INST3_SEG5                       0
+
+#define DCN_BASE__INST4_SEG0                       0
+#define DCN_BASE__INST4_SEG1                       0
+#define DCN_BASE__INST4_SEG2                       0
+#define DCN_BASE__INST4_SEG3                       0
+#define DCN_BASE__INST4_SEG4                       0
+#define DCN_BASE__INST4_SEG5                       0
+
+#define DCN_BASE__INST5_SEG0                       0
+#define DCN_BASE__INST5_SEG1                       0
+#define DCN_BASE__INST5_SEG2                       0
+#define DCN_BASE__INST5_SEG3                       0
+#define DCN_BASE__INST5_SEG4                       0
+#define DCN_BASE__INST5_SEG5                       0
+
+#define DCN_BASE__INST6_SEG0                       0
+#define DCN_BASE__INST6_SEG1                       0
+#define DCN_BASE__INST6_SEG2                       0
+#define DCN_BASE__INST6_SEG3                       0
+#define DCN_BASE__INST6_SEG4                       0
+#define DCN_BASE__INST6_SEG5                       0
+
+#define DPCS_BASE__INST0_SEG0                      0x00000012
+#define DPCS_BASE__INST0_SEG1                      0x000000C0
+#define DPCS_BASE__INST0_SEG2                      0x000034C0
+#define DPCS_BASE__INST0_SEG3                      0x00009000
+#define DPCS_BASE__INST0_SEG4                      0x02403C00
+#define DPCS_BASE__INST0_SEG5                      0
+
+#define DPCS_BASE__INST1_SEG0                      0
+#define DPCS_BASE__INST1_SEG1                      0
+#define DPCS_BASE__INST1_SEG2                      0
+#define DPCS_BASE__INST1_SEG3                      0
+#define DPCS_BASE__INST1_SEG4                      0
+#define DPCS_BASE__INST1_SEG5                      0
+
+#define DPCS_BASE__INST2_SEG0                      0
+#define DPCS_BASE__INST2_SEG1                      0
+#define DPCS_BASE__INST2_SEG2                      0
+#define DPCS_BASE__INST2_SEG3                      0
+#define DPCS_BASE__INST2_SEG4                      0
+#define DPCS_BASE__INST2_SEG5                      0
+
+#define DPCS_BASE__INST3_SEG0                      0
+#define DPCS_BASE__INST3_SEG1                      0
+#define DPCS_BASE__INST3_SEG2                      0
+#define DPCS_BASE__INST3_SEG3                      0
+#define DPCS_BASE__INST3_SEG4                      0
+#define DPCS_BASE__INST3_SEG5                      0
+
+#define DPCS_BASE__INST4_SEG0                      0
+#define DPCS_BASE__INST4_SEG1                      0
+#define DPCS_BASE__INST4_SEG2                      0
+#define DPCS_BASE__INST4_SEG3                      0
+#define DPCS_BASE__INST4_SEG4                      0
+#define DPCS_BASE__INST4_SEG5                      0
+
+#define DPCS_BASE__INST5_SEG0                      0
+#define DPCS_BASE__INST5_SEG1                      0
+#define DPCS_BASE__INST5_SEG2                      0
+#define DPCS_BASE__INST5_SEG3                      0
+#define DPCS_BASE__INST5_SEG4                      0
+#define DPCS_BASE__INST5_SEG5                      0
+
+#define DPCS_BASE__INST6_SEG0                      0
+#define DPCS_BASE__INST6_SEG1                      0
+#define DPCS_BASE__INST6_SEG2                      0
+#define DPCS_BASE__INST6_SEG3                      0
+#define DPCS_BASE__INST6_SEG4                      0
+#define DPCS_BASE__INST6_SEG5                      0
+
+#define DF_BASE__INST0_SEG0                        0x00007000
+#define DF_BASE__INST0_SEG1                        0x0240B800
+#define DF_BASE__INST0_SEG2                        0x02447800
+#define DF_BASE__INST0_SEG3                        0x00C00000
+#define DF_BASE__INST0_SEG4                        0x03640000
+#define DF_BASE__INST0_SEG5                        0
+
+#define DF_BASE__INST1_SEG0                        0
+#define DF_BASE__INST1_SEG1                        0
+#define DF_BASE__INST1_SEG2                        0
+#define DF_BASE__INST1_SEG3                        0
+#define DF_BASE__INST1_SEG4                        0
+#define DF_BASE__INST1_SEG5                        0
+
+#define DF_BASE__INST2_SEG0                        0
+#define DF_BASE__INST2_SEG1                        0
+#define DF_BASE__INST2_SEG2                        0
+#define DF_BASE__INST2_SEG3                        0
+#define DF_BASE__INST2_SEG4                        0
+#define DF_BASE__INST2_SEG5                        0
+
+#define DF_BASE__INST3_SEG0                        0
+#define DF_BASE__INST3_SEG1                        0
+#define DF_BASE__INST3_SEG2                        0
+#define DF_BASE__INST3_SEG3                        0
+#define DF_BASE__INST3_SEG4                        0
+#define DF_BASE__INST3_SEG5                        0
+
+#define DF_BASE__INST4_SEG0                        0
+#define DF_BASE__INST4_SEG1                        0
+#define DF_BASE__INST4_SEG2                        0
+#define DF_BASE__INST4_SEG3                        0
+#define DF_BASE__INST4_SEG4                        0
+#define DF_BASE__INST4_SEG5                        0
+
+#define DF_BASE__INST5_SEG0                        0
+#define DF_BASE__INST5_SEG1                        0
+#define DF_BASE__INST5_SEG2                        0
+#define DF_BASE__INST5_SEG3                        0
+#define DF_BASE__INST5_SEG4                        0
+#define DF_BASE__INST5_SEG5                        0
+
+#define DF_BASE__INST6_SEG0                        0
+#define DF_BASE__INST6_SEG1                        0
+#define DF_BASE__INST6_SEG2                        0
+#define DF_BASE__INST6_SEG3                        0
+#define DF_BASE__INST6_SEG4                        0
+#define DF_BASE__INST6_SEG5                        0
+
+#define FCH_BASE__INST0_SEG0                       0x0240C000
+#define FCH_BASE__INST0_SEG1                       0x00B40000
+#define FCH_BASE__INST0_SEG2                       0x11000000
+#define FCH_BASE__INST0_SEG3                       0
+#define FCH_BASE__INST0_SEG4                       0
+#define FCH_BASE__INST0_SEG5                       0
+
+#define FCH_BASE__INST1_SEG0                       0
+#define FCH_BASE__INST1_SEG1                       0
+#define FCH_BASE__INST1_SEG2                       0
+#define FCH_BASE__INST1_SEG3                       0
+#define FCH_BASE__INST1_SEG4                       0
+#define FCH_BASE__INST1_SEG5                       0
+
+#define FCH_BASE__INST2_SEG0                       0
+#define FCH_BASE__INST2_SEG1                       0
+#define FCH_BASE__INST2_SEG2                       0
+#define FCH_BASE__INST2_SEG3                       0
+#define FCH_BASE__INST2_SEG4                       0
+#define FCH_BASE__INST2_SEG5                       0
+
+#define FCH_BASE__INST3_SEG0                       0
+#define FCH_BASE__INST3_SEG1                       0
+#define FCH_BASE__INST3_SEG2                       0
+#define FCH_BASE__INST3_SEG3                       0
+#define FCH_BASE__INST3_SEG4                       0
+#define FCH_BASE__INST3_SEG5                       0
+
+#define FCH_BASE__INST4_SEG0                       0
+#define FCH_BASE__INST4_SEG1                       0
+#define FCH_BASE__INST4_SEG2                       0
+#define FCH_BASE__INST4_SEG3                       0
+#define FCH_BASE__INST4_SEG4                       0
+#define FCH_BASE__INST4_SEG5                       0
+
+#define FCH_BASE__INST5_SEG0                       0
+#define FCH_BASE__INST5_SEG1                       0
+#define FCH_BASE__INST5_SEG2                       0
+#define FCH_BASE__INST5_SEG3                       0
+#define FCH_BASE__INST5_SEG4                       0
+#define FCH_BASE__INST5_SEG5                       0
+
+#define FCH_BASE__INST6_SEG0                       0
+#define FCH_BASE__INST6_SEG1                       0
+#define FCH_BASE__INST6_SEG2                       0
+#define FCH_BASE__INST6_SEG3                       0
+#define FCH_BASE__INST6_SEG4                       0
+#define FCH_BASE__INST6_SEG5                       0
+
+#define FUSE_BASE__INST0_SEG0                      0x00017400
+#define FUSE_BASE__INST0_SEG1                      0x02401400
+#define FUSE_BASE__INST0_SEG2                      0
+#define FUSE_BASE__INST0_SEG3                      0
+#define FUSE_BASE__INST0_SEG4                      0
+#define FUSE_BASE__INST0_SEG5                      0
+
+#define FUSE_BASE__INST1_SEG0                      0
+#define FUSE_BASE__INST1_SEG1                      0
+#define FUSE_BASE__INST1_SEG2                      0
+#define FUSE_BASE__INST1_SEG3                      0
+#define FUSE_BASE__INST1_SEG4                      0
+#define FUSE_BASE__INST1_SEG5                      0
+
+#define FUSE_BASE__INST2_SEG0                      0
+#define FUSE_BASE__INST2_SEG1                      0
+#define FUSE_BASE__INST2_SEG2                      0
+#define FUSE_BASE__INST2_SEG3                      0
+#define FUSE_BASE__INST2_SEG4                      0
+#define FUSE_BASE__INST2_SEG5                      0
+
+#define FUSE_BASE__INST3_SEG0                      0
+#define FUSE_BASE__INST3_SEG1                      0
+#define FUSE_BASE__INST3_SEG2                      0
+#define FUSE_BASE__INST3_SEG3                      0
+#define FUSE_BASE__INST3_SEG4                      0
+#define FUSE_BASE__INST3_SEG5                      0
+
+#define FUSE_BASE__INST4_SEG0                      0
+#define FUSE_BASE__INST4_SEG1                      0
+#define FUSE_BASE__INST4_SEG2                      0
+#define FUSE_BASE__INST4_SEG3                      0
+#define FUSE_BASE__INST4_SEG4                      0
+#define FUSE_BASE__INST4_SEG5                      0
+
+#define FUSE_BASE__INST5_SEG0                      0
+#define FUSE_BASE__INST5_SEG1                      0
+#define FUSE_BASE__INST5_SEG2                      0
+#define FUSE_BASE__INST5_SEG3                      0
+#define FUSE_BASE__INST5_SEG4                      0
+#define FUSE_BASE__INST5_SEG5                      0
+
+#define FUSE_BASE__INST6_SEG0                      0
+#define FUSE_BASE__INST6_SEG1                      0
+#define FUSE_BASE__INST6_SEG2                      0
+#define FUSE_BASE__INST6_SEG3                      0
+#define FUSE_BASE__INST6_SEG4                      0
+#define FUSE_BASE__INST6_SEG5                      0
+
+#define GC_BASE__INST0_SEG0                        0x00001260
+#define GC_BASE__INST0_SEG1                        0x0000A000
+#define GC_BASE__INST0_SEG2                        0x02402C00
+#define GC_BASE__INST0_SEG3                        0
+#define GC_BASE__INST0_SEG4                        0
+#define GC_BASE__INST0_SEG5                        0
+
+#define GC_BASE__INST1_SEG0                        0
+#define GC_BASE__INST1_SEG1                        0
+#define GC_BASE__INST1_SEG2                        0
+#define GC_BASE__INST1_SEG3                        0
+#define GC_BASE__INST1_SEG4                        0
+#define GC_BASE__INST1_SEG5                        0
+
+#define GC_BASE__INST2_SEG0                        0
+#define GC_BASE__INST2_SEG1                        0
+#define GC_BASE__INST2_SEG2                        0
+#define GC_BASE__INST2_SEG3                        0
+#define GC_BASE__INST2_SEG4                        0
+#define GC_BASE__INST2_SEG5                        0
+
+#define GC_BASE__INST3_SEG0                        0
+#define GC_BASE__INST3_SEG1                        0
+#define GC_BASE__INST3_SEG2                        0
+#define GC_BASE__INST3_SEG3                        0
+#define GC_BASE__INST3_SEG4                        0
+#define GC_BASE__INST3_SEG5                        0
+
+#define GC_BASE__INST4_SEG0                        0
+#define GC_BASE__INST4_SEG1                        0
+#define GC_BASE__INST4_SEG2                        0
+#define GC_BASE__INST4_SEG3                        0
+#define GC_BASE__INST4_SEG4                        0
+#define GC_BASE__INST4_SEG5                        0
+
+#define GC_BASE__INST5_SEG0                        0
+#define GC_BASE__INST5_SEG1                        0
+#define GC_BASE__INST5_SEG2                        0
+#define GC_BASE__INST5_SEG3                        0
+#define GC_BASE__INST5_SEG4                        0
+#define GC_BASE__INST5_SEG5                        0
+
+#define GC_BASE__INST6_SEG0                        0
+#define GC_BASE__INST6_SEG1                        0
+#define GC_BASE__INST6_SEG2                        0
+#define GC_BASE__INST6_SEG3                        0
+#define GC_BASE__INST6_SEG4                        0
+#define GC_BASE__INST6_SEG5                        0
+
+#define HDP_BASE__INST0_SEG0                       0x00000F20
+#define HDP_BASE__INST0_SEG1                       0x0240A400
+#define HDP_BASE__INST0_SEG2                       0
+#define HDP_BASE__INST0_SEG3                       0
+#define HDP_BASE__INST0_SEG4                       0
+#define HDP_BASE__INST0_SEG5                       0
+
+#define HDP_BASE__INST1_SEG0                       0
+#define HDP_BASE__INST1_SEG1                       0
+#define HDP_BASE__INST1_SEG2                       0
+#define HDP_BASE__INST1_SEG3                       0
+#define HDP_BASE__INST1_SEG4                       0
+#define HDP_BASE__INST1_SEG5                       0
+
+#define HDP_BASE__INST2_SEG0                       0
+#define HDP_BASE__INST2_SEG1                       0
+#define HDP_BASE__INST2_SEG2                       0
+#define HDP_BASE__INST2_SEG3                       0
+#define HDP_BASE__INST2_SEG4                       0
+#define HDP_BASE__INST2_SEG5                       0
+
+#define HDP_BASE__INST3_SEG0                       0
+#define HDP_BASE__INST3_SEG1                       0
+#define HDP_BASE__INST3_SEG2                       0
+#define HDP_BASE__INST3_SEG3                       0
+#define HDP_BASE__INST3_SEG4                       0
+#define HDP_BASE__INST3_SEG5                       0
+
+#define HDP_BASE__INST4_SEG0                       0
+#define HDP_BASE__INST4_SEG1                       0
+#define HDP_BASE__INST4_SEG2                       0
+#define HDP_BASE__INST4_SEG3                       0
+#define HDP_BASE__INST4_SEG4                       0
+#define HDP_BASE__INST4_SEG5                       0
+
+#define HDP_BASE__INST5_SEG0                       0
+#define HDP_BASE__INST5_SEG1                       0
+#define HDP_BASE__INST5_SEG2                       0
+#define HDP_BASE__INST5_SEG3                       0
+#define HDP_BASE__INST5_SEG4                       0
+#define HDP_BASE__INST5_SEG5                       0
+
+#define HDP_BASE__INST6_SEG0                       0
+#define HDP_BASE__INST6_SEG1                       0
+#define HDP_BASE__INST6_SEG2                       0
+#define HDP_BASE__INST6_SEG3                       0
+#define HDP_BASE__INST6_SEG4                       0
+#define HDP_BASE__INST6_SEG5                       0
+
+#define IOHC0_BASE__INST0_SEG0                     0x00010000
+#define IOHC0_BASE__INST0_SEG1                     0x02406000
+#define IOHC0_BASE__INST0_SEG2                     0x04EC0000
+#define IOHC0_BASE__INST0_SEG3                     0
+#define IOHC0_BASE__INST0_SEG4                     0
+#define IOHC0_BASE__INST0_SEG5                     0
+
+#define IOHC0_BASE__INST1_SEG0                     0
+#define IOHC0_BASE__INST1_SEG1                     0
+#define IOHC0_BASE__INST1_SEG2                     0
+#define IOHC0_BASE__INST1_SEG3                     0
+#define IOHC0_BASE__INST1_SEG4                     0
+#define IOHC0_BASE__INST1_SEG5                     0
+
+#define IOHC0_BASE__INST2_SEG0                     0
+#define IOHC0_BASE__INST2_SEG1                     0
+#define IOHC0_BASE__INST2_SEG2                     0
+#define IOHC0_BASE__INST2_SEG3                     0
+#define IOHC0_BASE__INST2_SEG4                     0
+#define IOHC0_BASE__INST2_SEG5                     0
+
+#define IOHC0_BASE__INST3_SEG0                     0
+#define IOHC0_BASE__INST3_SEG1                     0
+#define IOHC0_BASE__INST3_SEG2                     0
+#define IOHC0_BASE__INST3_SEG3                     0
+#define IOHC0_BASE__INST3_SEG4                     0
+#define IOHC0_BASE__INST3_SEG5                     0
+
+#define IOHC0_BASE__INST4_SEG0                     0
+#define IOHC0_BASE__INST4_SEG1                     0
+#define IOHC0_BASE__INST4_SEG2                     0
+#define IOHC0_BASE__INST4_SEG3                     0
+#define IOHC0_BASE__INST4_SEG4                     0
+#define IOHC0_BASE__INST4_SEG5                     0
+
+#define IOHC0_BASE__INST5_SEG0                     0
+#define IOHC0_BASE__INST5_SEG1                     0
+#define IOHC0_BASE__INST5_SEG2                     0
+#define IOHC0_BASE__INST5_SEG3                     0
+#define IOHC0_BASE__INST5_SEG4                     0
+#define IOHC0_BASE__INST5_SEG5                     0
+
+#define IOHC0_BASE__INST6_SEG0                     0
+#define IOHC0_BASE__INST6_SEG1                     0
+#define IOHC0_BASE__INST6_SEG2                     0
+#define IOHC0_BASE__INST6_SEG3                     0
+#define IOHC0_BASE__INST6_SEG4                     0
+#define IOHC0_BASE__INST6_SEG5                     0
+
+#define MMHUB_BASE__INST0_SEG0                     0x00013200
+#define MMHUB_BASE__INST0_SEG1                     0x0001A000
+#define MMHUB_BASE__INST0_SEG2                     0x02408800
+#define MMHUB_BASE__INST0_SEG3                     0
+#define MMHUB_BASE__INST0_SEG4                     0
+#define MMHUB_BASE__INST0_SEG5                     0
+
+#define MMHUB_BASE__INST1_SEG0                     0
+#define MMHUB_BASE__INST1_SEG1                     0
+#define MMHUB_BASE__INST1_SEG2                     0
+#define MMHUB_BASE__INST1_SEG3                     0
+#define MMHUB_BASE__INST1_SEG4                     0
+#define MMHUB_BASE__INST1_SEG5                     0
+
+#define MMHUB_BASE__INST2_SEG0                     0
+#define MMHUB_BASE__INST2_SEG1                     0
+#define MMHUB_BASE__INST2_SEG2                     0
+#define MMHUB_BASE__INST2_SEG3                     0
+#define MMHUB_BASE__INST2_SEG4                     0
+#define MMHUB_BASE__INST2_SEG5                     0
+
+#define MMHUB_BASE__INST3_SEG0                     0
+#define MMHUB_BASE__INST3_SEG1                     0
+#define MMHUB_BASE__INST3_SEG2                     0
+#define MMHUB_BASE__INST3_SEG3                     0
+#define MMHUB_BASE__INST3_SEG4                     0
+#define MMHUB_BASE__INST3_SEG5                     0
+
+#define MMHUB_BASE__INST4_SEG0                     0
+#define MMHUB_BASE__INST4_SEG1                     0
+#define MMHUB_BASE__INST4_SEG2                     0
+#define MMHUB_BASE__INST4_SEG3                     0
+#define MMHUB_BASE__INST4_SEG4                     0
+#define MMHUB_BASE__INST4_SEG5                     0
+
+#define MMHUB_BASE__INST5_SEG0                     0
+#define MMHUB_BASE__INST5_SEG1                     0
+#define MMHUB_BASE__INST5_SEG2                     0
+#define MMHUB_BASE__INST5_SEG3                     0
+#define MMHUB_BASE__INST5_SEG4                     0
+#define MMHUB_BASE__INST5_SEG5                     0
+
+#define MMHUB_BASE__INST6_SEG0                     0
+#define MMHUB_BASE__INST6_SEG1                     0
+#define MMHUB_BASE__INST6_SEG2                     0
+#define MMHUB_BASE__INST6_SEG3                     0
+#define MMHUB_BASE__INST6_SEG4                     0
+#define MMHUB_BASE__INST6_SEG5                     0
+
+#define MP0_BASE__INST0_SEG0                       0x00016000
+#define MP0_BASE__INST0_SEG1                       0x0243FC00
+#define MP0_BASE__INST0_SEG2                       0x00DC0000
+#define MP0_BASE__INST0_SEG3                       0x00E00000
+#define MP0_BASE__INST0_SEG4                       0x00E40000
+#define MP0_BASE__INST0_SEG5                       0
+
+#define MP0_BASE__INST1_SEG0                       0
+#define MP0_BASE__INST1_SEG1                       0
+#define MP0_BASE__INST1_SEG2                       0
+#define MP0_BASE__INST1_SEG3                       0
+#define MP0_BASE__INST1_SEG4                       0
+#define MP0_BASE__INST1_SEG5                       0
+
+#define MP0_BASE__INST2_SEG0                       0
+#define MP0_BASE__INST2_SEG1                       0
+#define MP0_BASE__INST2_SEG2                       0
+#define MP0_BASE__INST2_SEG3                       0
+#define MP0_BASE__INST2_SEG4                       0
+#define MP0_BASE__INST2_SEG5                       0
+
+#define MP0_BASE__INST3_SEG0                       0
+#define MP0_BASE__INST3_SEG1                       0
+#define MP0_BASE__INST3_SEG2                       0
+#define MP0_BASE__INST3_SEG3                       0
+#define MP0_BASE__INST3_SEG4                       0
+#define MP0_BASE__INST3_SEG5                       0
+
+#define MP0_BASE__INST4_SEG0                       0
+#define MP0_BASE__INST4_SEG1                       0
+#define MP0_BASE__INST4_SEG2                       0
+#define MP0_BASE__INST4_SEG3                       0
+#define MP0_BASE__INST4_SEG4                       0
+#define MP0_BASE__INST4_SEG5                       0
+
+#define MP0_BASE__INST5_SEG0                       0
+#define MP0_BASE__INST5_SEG1                       0
+#define MP0_BASE__INST5_SEG2                       0
+#define MP0_BASE__INST5_SEG3                       0
+#define MP0_BASE__INST5_SEG4                       0
+#define MP0_BASE__INST5_SEG5                       0
+
+#define MP0_BASE__INST6_SEG0                       0
+#define MP0_BASE__INST6_SEG1                       0
+#define MP0_BASE__INST6_SEG2                       0
+#define MP0_BASE__INST6_SEG3                       0
+#define MP0_BASE__INST6_SEG4                       0
+#define MP0_BASE__INST6_SEG5                       0
+
+#define MP1_BASE__INST0_SEG0                       0x00016000
+#define MP1_BASE__INST0_SEG1                       0x0243FC00
+#define MP1_BASE__INST0_SEG2                       0x00DC0000
+#define MP1_BASE__INST0_SEG3                       0x00E00000
+#define MP1_BASE__INST0_SEG4                       0x00E40000
+#define MP1_BASE__INST0_SEG5                       0
+
+#define MP1_BASE__INST1_SEG0                       0
+#define MP1_BASE__INST1_SEG1                       0
+#define MP1_BASE__INST1_SEG2                       0
+#define MP1_BASE__INST1_SEG3                       0
+#define MP1_BASE__INST1_SEG4                       0
+#define MP1_BASE__INST1_SEG5                       0
+
+#define MP1_BASE__INST2_SEG0                       0
+#define MP1_BASE__INST2_SEG1                       0
+#define MP1_BASE__INST2_SEG2                       0
+#define MP1_BASE__INST2_SEG3                       0
+#define MP1_BASE__INST2_SEG4                       0
+#define MP1_BASE__INST2_SEG5                       0
+
+#define MP1_BASE__INST3_SEG0                       0
+#define MP1_BASE__INST3_SEG1                       0
+#define MP1_BASE__INST3_SEG2                       0
+#define MP1_BASE__INST3_SEG3                       0
+#define MP1_BASE__INST3_SEG4                       0
+#define MP1_BASE__INST3_SEG5                       0
+
+#define MP1_BASE__INST4_SEG0                       0
+#define MP1_BASE__INST4_SEG1                       0
+#define MP1_BASE__INST4_SEG2                       0
+#define MP1_BASE__INST4_SEG3                       0
+#define MP1_BASE__INST4_SEG4                       0
+#define MP1_BASE__INST4_SEG5                       0
+
+#define MP1_BASE__INST5_SEG0                       0
+#define MP1_BASE__INST5_SEG1                       0
+#define MP1_BASE__INST5_SEG2                       0
+#define MP1_BASE__INST5_SEG3                       0
+#define MP1_BASE__INST5_SEG4                       0
+#define MP1_BASE__INST5_SEG5                       0
+
+#define MP1_BASE__INST6_SEG0                       0
+#define MP1_BASE__INST6_SEG1                       0
+#define MP1_BASE__INST6_SEG2                       0
+#define MP1_BASE__INST6_SEG3                       0
+#define MP1_BASE__INST6_SEG4                       0
+#define MP1_BASE__INST6_SEG5                       0
+
+#define MP2_BASE__INST0_SEG0                       0x00016000
+#define MP2_BASE__INST0_SEG1                       0x0243FC00
+#define MP2_BASE__INST0_SEG2                       0x00DC0000
+#define MP2_BASE__INST0_SEG3                       0x00E00000
+#define MP2_BASE__INST0_SEG4                       0x00E40000
+#define MP2_BASE__INST0_SEG5                       0
+
+#define MP2_BASE__INST1_SEG0                       0
+#define MP2_BASE__INST1_SEG1                       0
+#define MP2_BASE__INST1_SEG2                       0
+#define MP2_BASE__INST1_SEG3                       0
+#define MP2_BASE__INST1_SEG4                       0
+#define MP2_BASE__INST1_SEG5                       0
+
+#define MP2_BASE__INST2_SEG0                       0
+#define MP2_BASE__INST2_SEG1                       0
+#define MP2_BASE__INST2_SEG2                       0
+#define MP2_BASE__INST2_SEG3                       0
+#define MP2_BASE__INST2_SEG4                       0
+#define MP2_BASE__INST2_SEG5                       0
+
+#define MP2_BASE__INST3_SEG0                       0
+#define MP2_BASE__INST3_SEG1                       0
+#define MP2_BASE__INST3_SEG2                       0
+#define MP2_BASE__INST3_SEG3                       0
+#define MP2_BASE__INST3_SEG4                       0
+#define MP2_BASE__INST3_SEG5                       0
+
+#define MP2_BASE__INST4_SEG0                       0
+#define MP2_BASE__INST4_SEG1                       0
+#define MP2_BASE__INST4_SEG2                       0
+#define MP2_BASE__INST4_SEG3                       0
+#define MP2_BASE__INST4_SEG4                       0
+#define MP2_BASE__INST4_SEG5                       0
+
+#define MP2_BASE__INST5_SEG0                       0
+#define MP2_BASE__INST5_SEG1                       0
+#define MP2_BASE__INST5_SEG2                       0
+#define MP2_BASE__INST5_SEG3                       0
+#define MP2_BASE__INST5_SEG4                       0
+#define MP2_BASE__INST5_SEG5                       0
+
+#define MP2_BASE__INST6_SEG0                       0
+#define MP2_BASE__INST6_SEG1                       0
+#define MP2_BASE__INST6_SEG2                       0
+#define MP2_BASE__INST6_SEG3                       0
+#define MP2_BASE__INST6_SEG4                       0
+#define MP2_BASE__INST6_SEG5                       0
+
+#define NBIO_BASE__INST0_SEG0                      0x00000000
+#define NBIO_BASE__INST0_SEG1                      0x00000014
+#define NBIO_BASE__INST0_SEG2                      0x00000D20
+#define NBIO_BASE__INST0_SEG3                      0x00010400
+#define NBIO_BASE__INST0_SEG4                      0x0241B000
+#define NBIO_BASE__INST0_SEG5                      0x04040000
+
+#define NBIO_BASE__INST1_SEG0                      0
+#define NBIO_BASE__INST1_SEG1                      0
+#define NBIO_BASE__INST1_SEG2                      0
+#define NBIO_BASE__INST1_SEG3                      0
+#define NBIO_BASE__INST1_SEG4                      0
+#define NBIO_BASE__INST1_SEG5                      0
+
+#define NBIO_BASE__INST2_SEG0                      0
+#define NBIO_BASE__INST2_SEG1                      0
+#define NBIO_BASE__INST2_SEG2                      0
+#define NBIO_BASE__INST2_SEG3                      0
+#define NBIO_BASE__INST2_SEG4                      0
+#define NBIO_BASE__INST2_SEG5                      0
+
+#define NBIO_BASE__INST3_SEG0                      0
+#define NBIO_BASE__INST3_SEG1                      0
+#define NBIO_BASE__INST3_SEG2                      0
+#define NBIO_BASE__INST3_SEG3                      0
+#define NBIO_BASE__INST3_SEG4                      0
+#define NBIO_BASE__INST3_SEG5                      0
+
+#define NBIO_BASE__INST4_SEG0                      0
+#define NBIO_BASE__INST4_SEG1                      0
+#define NBIO_BASE__INST4_SEG2                      0
+#define NBIO_BASE__INST4_SEG3                      0
+#define NBIO_BASE__INST4_SEG4                      0
+#define NBIO_BASE__INST4_SEG5                      0
+
+#define NBIO_BASE__INST5_SEG0                      0
+#define NBIO_BASE__INST5_SEG1                      0
+#define NBIO_BASE__INST5_SEG2                      0
+#define NBIO_BASE__INST5_SEG3                      0
+#define NBIO_BASE__INST5_SEG4                      0
+#define NBIO_BASE__INST5_SEG5                      0
+
+#define NBIO_BASE__INST6_SEG0                      0
+#define NBIO_BASE__INST6_SEG1                      0
+#define NBIO_BASE__INST6_SEG2                      0
+#define NBIO_BASE__INST6_SEG3                      0
+#define NBIO_BASE__INST6_SEG4                      0
+#define NBIO_BASE__INST6_SEG5                      0
+
+#define OSSSYS_BASE__INST0_SEG0                    0x000010A0
+#define OSSSYS_BASE__INST0_SEG1                    0x0240A000
+#define OSSSYS_BASE__INST0_SEG2                    0
+#define OSSSYS_BASE__INST0_SEG3                    0
+#define OSSSYS_BASE__INST0_SEG4                    0
+#define OSSSYS_BASE__INST0_SEG5                    0
+
+#define OSSSYS_BASE__INST1_SEG0                    0
+#define OSSSYS_BASE__INST1_SEG1                    0
+#define OSSSYS_BASE__INST1_SEG2                    0
+#define OSSSYS_BASE__INST1_SEG3                    0
+#define OSSSYS_BASE__INST1_SEG4                    0
+#define OSSSYS_BASE__INST1_SEG5                    0
+
+#define OSSSYS_BASE__INST2_SEG0                    0
+#define OSSSYS_BASE__INST2_SEG1                    0
+#define OSSSYS_BASE__INST2_SEG2                    0
+#define OSSSYS_BASE__INST2_SEG3                    0
+#define OSSSYS_BASE__INST2_SEG4                    0
+#define OSSSYS_BASE__INST2_SEG5                    0
+
+#define OSSSYS_BASE__INST3_SEG0                    0
+#define OSSSYS_BASE__INST3_SEG1                    0
+#define OSSSYS_BASE__INST3_SEG2                    0
+#define OSSSYS_BASE__INST3_SEG3                    0
+#define OSSSYS_BASE__INST3_SEG4                    0
+#define OSSSYS_BASE__INST3_SEG5                    0
+
+#define OSSSYS_BASE__INST4_SEG0                    0
+#define OSSSYS_BASE__INST4_SEG1                    0
+#define OSSSYS_BASE__INST4_SEG2                    0
+#define OSSSYS_BASE__INST4_SEG3                    0
+#define OSSSYS_BASE__INST4_SEG4                    0
+#define OSSSYS_BASE__INST4_SEG5                    0
+
+#define OSSSYS_BASE__INST5_SEG0                    0
+#define OSSSYS_BASE__INST5_SEG1                    0
+#define OSSSYS_BASE__INST5_SEG2                    0
+#define OSSSYS_BASE__INST5_SEG3                    0
+#define OSSSYS_BASE__INST5_SEG4                    0
+#define OSSSYS_BASE__INST5_SEG5                    0
+
+#define OSSSYS_BASE__INST6_SEG0                    0
+#define OSSSYS_BASE__INST6_SEG1                    0
+#define OSSSYS_BASE__INST6_SEG2                    0
+#define OSSSYS_BASE__INST6_SEG3                    0
+#define OSSSYS_BASE__INST6_SEG4                    0
+#define OSSSYS_BASE__INST6_SEG5                    0
+
+#define PCIE_BASE__INST0_SEG0                      0x02411800
+#define PCIE_BASE__INST0_SEG1                      0x04440000
+#define PCIE_BASE__INST0_SEG2                      0
+#define PCIE_BASE__INST0_SEG3                      0
+#define PCIE_BASE__INST0_SEG4                      0
+#define PCIE_BASE__INST0_SEG5                      0
+
+#define PCIE_BASE__INST1_SEG0                      0x02411C00
+#define PCIE_BASE__INST1_SEG1                      0x04480000
+#define PCIE_BASE__INST1_SEG2                      0
+#define PCIE_BASE__INST1_SEG3                      0
+#define PCIE_BASE__INST1_SEG4                      0
+#define PCIE_BASE__INST1_SEG5                      0
+
+#define PCIE_BASE__INST2_SEG0                      0x02412000
+#define PCIE_BASE__INST2_SEG1                      0x044C0000
+#define PCIE_BASE__INST2_SEG2                      0
+#define PCIE_BASE__INST2_SEG3                      0
+#define PCIE_BASE__INST2_SEG4                      0
+#define PCIE_BASE__INST2_SEG5                      0
+
+#define PCIE_BASE__INST3_SEG0                      0x02412400
+#define PCIE_BASE__INST3_SEG1                      0x04500000
+#define PCIE_BASE__INST3_SEG2                      0
+#define PCIE_BASE__INST3_SEG3                      0
+#define PCIE_BASE__INST3_SEG4                      0
+#define PCIE_BASE__INST3_SEG5                      0
+
+#define PCIE_BASE__INST4_SEG0                      0
+#define PCIE_BASE__INST4_SEG1                      0
+#define PCIE_BASE__INST4_SEG2                      0
+#define PCIE_BASE__INST4_SEG3                      0
+#define PCIE_BASE__INST4_SEG4                      0
+#define PCIE_BASE__INST4_SEG5                      0
+
+#define PCIE_BASE__INST5_SEG0                      0
+#define PCIE_BASE__INST5_SEG1                      0
+#define PCIE_BASE__INST5_SEG2                      0
+#define PCIE_BASE__INST5_SEG3                      0
+#define PCIE_BASE__INST5_SEG4                      0
+#define PCIE_BASE__INST5_SEG5                      0
+
+#define PCIE_BASE__INST6_SEG0                      0
+#define PCIE_BASE__INST6_SEG1                      0
+#define PCIE_BASE__INST6_SEG2                      0
+#define PCIE_BASE__INST6_SEG3                      0
+#define PCIE_BASE__INST6_SEG4                      0
+#define PCIE_BASE__INST6_SEG5                      0
+
+#define SDMA0_BASE__INST0_SEG0                     0x00001260
+#define SDMA0_BASE__INST0_SEG1                     0x0000A000
+#define SDMA0_BASE__INST0_SEG2                     0x02402C00
+#define SDMA0_BASE__INST0_SEG3                     0
+#define SDMA0_BASE__INST0_SEG4                     0
+#define SDMA0_BASE__INST0_SEG5                     0
+
+#define SDMA0_BASE__INST1_SEG0                     0
+#define SDMA0_BASE__INST1_SEG1                     0
+#define SDMA0_BASE__INST1_SEG2                     0
+#define SDMA0_BASE__INST1_SEG3                     0
+#define SDMA0_BASE__INST1_SEG4                     0
+#define SDMA0_BASE__INST1_SEG5                     0
+
+#define SDMA0_BASE__INST2_SEG0                     0
+#define SDMA0_BASE__INST2_SEG1                     0
+#define SDMA0_BASE__INST2_SEG2                     0
+#define SDMA0_BASE__INST2_SEG3                     0
+#define SDMA0_BASE__INST2_SEG4                     0
+#define SDMA0_BASE__INST2_SEG5                     0
+
+#define SDMA0_BASE__INST3_SEG0                     0
+#define SDMA0_BASE__INST3_SEG1                     0
+#define SDMA0_BASE__INST3_SEG2                     0
+#define SDMA0_BASE__INST3_SEG3                     0
+#define SDMA0_BASE__INST3_SEG4                     0
+#define SDMA0_BASE__INST3_SEG5                     0
+
+#define SDMA0_BASE__INST4_SEG0                     0
+#define SDMA0_BASE__INST4_SEG1                     0
+#define SDMA0_BASE__INST4_SEG2                     0
+#define SDMA0_BASE__INST4_SEG3                     0
+#define SDMA0_BASE__INST4_SEG4                     0
+#define SDMA0_BASE__INST4_SEG5                     0
+
+#define SDMA0_BASE__INST5_SEG0                     0
+#define SDMA0_BASE__INST5_SEG1                     0
+#define SDMA0_BASE__INST5_SEG2                     0
+#define SDMA0_BASE__INST5_SEG3                     0
+#define SDMA0_BASE__INST5_SEG4                     0
+#define SDMA0_BASE__INST5_SEG5                     0
+
+#define SDMA0_BASE__INST6_SEG0                     0
+#define SDMA0_BASE__INST6_SEG1                     0
+#define SDMA0_BASE__INST6_SEG2                     0
+#define SDMA0_BASE__INST6_SEG3                     0
+#define SDMA0_BASE__INST6_SEG4                     0
+#define SDMA0_BASE__INST6_SEG5                     0
+
+#define SMUIO_BASE__INST0_SEG0                     0x00016800
+#define SMUIO_BASE__INST0_SEG1                     0x00016A00
+#define SMUIO_BASE__INST0_SEG2                     0x02401000
+#define SMUIO_BASE__INST0_SEG3                     0x00440000
+#define SMUIO_BASE__INST0_SEG4                     0
+#define SMUIO_BASE__INST0_SEG5                     0
+
+#define SMUIO_BASE__INST1_SEG0                     0x0001BC00
+#define SMUIO_BASE__INST1_SEG1                     0x0242D400
+#define SMUIO_BASE__INST1_SEG2                     0
+#define SMUIO_BASE__INST1_SEG3                     0
+#define SMUIO_BASE__INST1_SEG4                     0
+#define SMUIO_BASE__INST1_SEG5                     0
+
+#define SMUIO_BASE__INST2_SEG0                     0
+#define SMUIO_BASE__INST2_SEG1                     0
+#define SMUIO_BASE__INST2_SEG2                     0
+#define SMUIO_BASE__INST2_SEG3                     0
+#define SMUIO_BASE__INST2_SEG4                     0
+#define SMUIO_BASE__INST2_SEG5                     0
+
+#define SMUIO_BASE__INST3_SEG0                     0
+#define SMUIO_BASE__INST3_SEG1                     0
+#define SMUIO_BASE__INST3_SEG2                     0
+#define SMUIO_BASE__INST3_SEG3                     0
+#define SMUIO_BASE__INST3_SEG4                     0
+#define SMUIO_BASE__INST3_SEG5                     0
+
+#define SMUIO_BASE__INST4_SEG0                     0
+#define SMUIO_BASE__INST4_SEG1                     0
+#define SMUIO_BASE__INST4_SEG2                     0
+#define SMUIO_BASE__INST4_SEG3                     0
+#define SMUIO_BASE__INST4_SEG4                     0
+#define SMUIO_BASE__INST4_SEG5                     0
+
+#define SMUIO_BASE__INST5_SEG0                     0
+#define SMUIO_BASE__INST5_SEG1                     0
+#define SMUIO_BASE__INST5_SEG2                     0
+#define SMUIO_BASE__INST5_SEG3                     0
+#define SMUIO_BASE__INST5_SEG4                     0
+#define SMUIO_BASE__INST5_SEG5                     0
+
+#define SMUIO_BASE__INST6_SEG0                     0
+#define SMUIO_BASE__INST6_SEG1                     0
+#define SMUIO_BASE__INST6_SEG2                     0
+#define SMUIO_BASE__INST6_SEG3                     0
+#define SMUIO_BASE__INST6_SEG4                     0
+#define SMUIO_BASE__INST6_SEG5                     0
+
+#define THM_BASE__INST0_SEG0                       0x00016600
+#define THM_BASE__INST0_SEG1                       0x02400C00
+#define THM_BASE__INST0_SEG2                       0
+#define THM_BASE__INST0_SEG3                       0
+#define THM_BASE__INST0_SEG4                       0
+#define THM_BASE__INST0_SEG5                       0
+
+#define THM_BASE__INST1_SEG0                       0
+#define THM_BASE__INST1_SEG1                       0
+#define THM_BASE__INST1_SEG2                       0
+#define THM_BASE__INST1_SEG3                       0
+#define THM_BASE__INST1_SEG4                       0
+#define THM_BASE__INST1_SEG5                       0
+
+#define THM_BASE__INST2_SEG0                       0
+#define THM_BASE__INST2_SEG1                       0
+#define THM_BASE__INST2_SEG2                       0
+#define THM_BASE__INST2_SEG3                       0
+#define THM_BASE__INST2_SEG4                       0
+#define THM_BASE__INST2_SEG5                       0
+
+#define THM_BASE__INST3_SEG0                       0
+#define THM_BASE__INST3_SEG1                       0
+#define THM_BASE__INST3_SEG2                       0
+#define THM_BASE__INST3_SEG3                       0
+#define THM_BASE__INST3_SEG4                       0
+#define THM_BASE__INST3_SEG5                       0
+
+#define THM_BASE__INST4_SEG0                       0
+#define THM_BASE__INST4_SEG1                       0
+#define THM_BASE__INST4_SEG2                       0
+#define THM_BASE__INST4_SEG3                       0
+#define THM_BASE__INST4_SEG4                       0
+#define THM_BASE__INST4_SEG5                       0
+
+#define THM_BASE__INST5_SEG0                       0
+#define THM_BASE__INST5_SEG1                       0
+#define THM_BASE__INST5_SEG2                       0
+#define THM_BASE__INST5_SEG3                       0
+#define THM_BASE__INST5_SEG4                       0
+#define THM_BASE__INST5_SEG5                       0
+
+#define THM_BASE__INST6_SEG0                       0
+#define THM_BASE__INST6_SEG1                       0
+#define THM_BASE__INST6_SEG2                       0
+#define THM_BASE__INST6_SEG3                       0
+#define THM_BASE__INST6_SEG4                       0
+#define THM_BASE__INST6_SEG5                       0
+
+#define UMC_BASE__INST0_SEG0                       0x00014000
+#define UMC_BASE__INST0_SEG1                       0x00054000
+#define UMC_BASE__INST0_SEG2                       0x02425800
+#define UMC_BASE__INST0_SEG3                       0x02425C00
+#define UMC_BASE__INST0_SEG4                       0
+#define UMC_BASE__INST0_SEG5                       0
+
+#define UMC_BASE__INST1_SEG0                       0x00094000
+#define UMC_BASE__INST1_SEG1                       0x000D4000
+#define UMC_BASE__INST1_SEG2                       0x02426000
+#define UMC_BASE__INST1_SEG3                       0x02426400
+#define UMC_BASE__INST1_SEG4                       0
+#define UMC_BASE__INST1_SEG5                       0
+
+#define UMC_BASE__INST2_SEG0                       0
+#define UMC_BASE__INST2_SEG1                       0
+#define UMC_BASE__INST2_SEG2                       0
+#define UMC_BASE__INST2_SEG3                       0
+#define UMC_BASE__INST2_SEG4                       0
+#define UMC_BASE__INST2_SEG5                       0
+
+#define UMC_BASE__INST3_SEG0                       0
+#define UMC_BASE__INST3_SEG1                       0
+#define UMC_BASE__INST3_SEG2                       0
+#define UMC_BASE__INST3_SEG3                       0
+#define UMC_BASE__INST3_SEG4                       0
+#define UMC_BASE__INST3_SEG5                       0
+
+#define UMC_BASE__INST4_SEG0                       0
+#define UMC_BASE__INST4_SEG1                       0
+#define UMC_BASE__INST4_SEG2                       0
+#define UMC_BASE__INST4_SEG3                       0
+#define UMC_BASE__INST4_SEG4                       0
+#define UMC_BASE__INST4_SEG5                       0
+
+#define UMC_BASE__INST5_SEG0                       0
+#define UMC_BASE__INST5_SEG1                       0
+#define UMC_BASE__INST5_SEG2                       0
+#define UMC_BASE__INST5_SEG3                       0
+#define UMC_BASE__INST5_SEG4                       0
+#define UMC_BASE__INST5_SEG5                       0
+
+#define UMC_BASE__INST6_SEG0                       0
+#define UMC_BASE__INST6_SEG1                       0
+#define UMC_BASE__INST6_SEG2                       0
+#define UMC_BASE__INST6_SEG3                       0
+#define UMC_BASE__INST6_SEG4                       0
+#define UMC_BASE__INST6_SEG5                       0
+
+#define VCN_BASE__INST0_SEG0                       0x00007800
+#define VCN_BASE__INST0_SEG1                       0x00007E00
+#define VCN_BASE__INST0_SEG2                       0x02403000
+#define VCN_BASE__INST0_SEG3                       0
+#define VCN_BASE__INST0_SEG4                       0
+#define VCN_BASE__INST0_SEG5                       0
+
+#define VCN_BASE__INST1_SEG0                       0
+#define VCN_BASE__INST1_SEG1                       0
+#define VCN_BASE__INST1_SEG2                       0
+#define VCN_BASE__INST1_SEG3                       0
+#define VCN_BASE__INST1_SEG4                       0
+#define VCN_BASE__INST1_SEG5                       0
+
+#define VCN_BASE__INST2_SEG0                       0
+#define VCN_BASE__INST2_SEG1                       0
+#define VCN_BASE__INST2_SEG2                       0
+#define VCN_BASE__INST2_SEG3                       0
+#define VCN_BASE__INST2_SEG4                       0
+#define VCN_BASE__INST2_SEG5                       0
+
+#define VCN_BASE__INST3_SEG0                       0
+#define VCN_BASE__INST3_SEG1                       0
+#define VCN_BASE__INST3_SEG2                       0
+#define VCN_BASE__INST3_SEG3                       0
+#define VCN_BASE__INST3_SEG4                       0
+#define VCN_BASE__INST3_SEG5                       0
+
+#define VCN_BASE__INST4_SEG0                       0
+#define VCN_BASE__INST4_SEG1                       0
+#define VCN_BASE__INST4_SEG2                       0
+#define VCN_BASE__INST4_SEG3                       0
+#define VCN_BASE__INST4_SEG4                       0
+#define VCN_BASE__INST4_SEG5                       0
+
+#define VCN_BASE__INST5_SEG0                       0
+#define VCN_BASE__INST5_SEG1                       0
+#define VCN_BASE__INST5_SEG2                       0
+#define VCN_BASE__INST5_SEG3                       0
+#define VCN_BASE__INST5_SEG4                       0
+#define VCN_BASE__INST5_SEG5                       0
+
+#define VCN_BASE__INST6_SEG0                       0
+#define VCN_BASE__INST6_SEG1                       0
+#define VCN_BASE__INST6_SEG2                       0
+#define VCN_BASE__INST6_SEG3                       0
+#define VCN_BASE__INST6_SEG4                       0
+#define VCN_BASE__INST6_SEG5                       0
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index f48132bc089d..b2335a1d3f98 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1817,6 +1817,190 @@ out:
 	return size;
 }
 
+/**
+ * DOC: smartshift_apu_power
+ *
+ * The amdgpu driver provides a sysfs API for reporting APU power
+ * share if it supports smartshift. The value is expressed as
+ * the proportion of stapm limit where stapm limit is the total APU
+ * power limit. The result is in percentage. If APU power is 130% of
+ * STAPM, then APU is using 30% of the dGPU's headroom.
+ */
+
+static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
+					       char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	uint32_t ss_power, size;
+	int r = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	r = pm_runtime_get_sync(ddev->dev);
+	if (r < 0) {
+		pm_runtime_put_autosuspend(ddev->dev);
+		return r;
+	}
+
+	r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+				   (void *)&ss_power, &size);
+	if (r)
+		goto out;
+
+	r = sysfs_emit(buf, "%u%%\n", ss_power);
+
+out:
+	pm_runtime_mark_last_busy(ddev->dev);
+	pm_runtime_put_autosuspend(ddev->dev);
+	return r;
+}
+
+/**
+ * DOC: smartshift_dgpu_power
+ *
+ * The amdgpu driver provides a sysfs API for reporting the dGPU power
+ * share if the device is in HG and supports smartshift. The value
+ * is expressed as the proportion of stapm limit where stapm limit
+ * is the total APU power limit. The value is in percentage. If dGPU
+ * power is 20% higher than STAPM power(120%), it's using 20% of the
+ * APU's power headroom.
+ */
+
+static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
+						char *buf)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	uint32_t ss_power, size;
+	int r = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	r = pm_runtime_get_sync(ddev->dev);
+	if (r < 0) {
+		pm_runtime_put_autosuspend(ddev->dev);
+		return r;
+	}
+
+	r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+				   (void *)&ss_power, &size);
+
+	if (r)
+		goto out;
+
+	r = sysfs_emit(buf, "%u%%\n", ss_power);
+
+out:
+	pm_runtime_mark_last_busy(ddev->dev);
+	pm_runtime_put_autosuspend(ddev->dev);
+	return r;
+}
+
+/**
+ * DOC: smartshift_bias
+ *
+ * The amdgpu driver provides a sysfs API for reporting the
+ * smartshift(SS2.0) bias level. The value ranges from -100 to 100
+ * and the default is 0. -100 sets maximum preference to APU
+ * and 100 sets max perference to dGPU.
+ */
+
+static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
+					  struct device_attribute *attr,
+					  char *buf)
+{
+	int r = 0;
+
+	r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
+
+	return r;
+}
+
+static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
+					  struct device_attribute *attr,
+					  const char *buf, size_t count)
+{
+	struct drm_device *ddev = dev_get_drvdata(dev);
+	struct amdgpu_device *adev = drm_to_adev(ddev);
+	int r = 0;
+	int bias = 0;
+
+	if (amdgpu_in_reset(adev))
+		return -EPERM;
+	if (adev->in_suspend && !adev->in_runpm)
+		return -EPERM;
+
+	r = pm_runtime_get_sync(ddev->dev);
+	if (r < 0) {
+		pm_runtime_put_autosuspend(ddev->dev);
+		return r;
+	}
+
+	r = kstrtoint(buf, 10, &bias);
+	if (r)
+		goto out;
+
+	if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
+		bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
+	else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
+		bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
+
+	amdgpu_smartshift_bias = bias;
+	r = count;
+
+	/* TODO: upadte bias level with SMU message */
+
+out:
+	pm_runtime_mark_last_busy(ddev->dev);
+	pm_runtime_put_autosuspend(ddev->dev);
+	return r;
+}
+
+
+static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
+				uint32_t mask, enum amdgpu_device_attr_states *states)
+{
+	uint32_t ss_power, size;
+
+	if (!amdgpu_acpi_is_power_shift_control_supported())
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if ((adev->flags & AMD_IS_PX) &&
+		 !amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+
+	return 0;
+}
+
+static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
+			       uint32_t mask, enum amdgpu_device_attr_states *states)
+{
+	uint32_t ss_power, size;
+
+	if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+	else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
+		 (void *)&ss_power, &size))
+		*states = ATTR_STATE_UNSUPPORTED;
+
+	return 0;
+}
+
 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
 	AMDGPU_DEVICE_ATTR_RW(power_dpm_state,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
 	AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
@@ -1843,6 +2027,12 @@ static struct amdgpu_device_attr amdgpu_device_attrs[] = {
 	AMDGPU_DEVICE_ATTR_RO(unique_id,				ATTR_FLAG_BASIC),
 	AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,		ATTR_FLAG_BASIC),
 	AMDGPU_DEVICE_ATTR_RO(gpu_metrics,				ATTR_FLAG_BASIC),
+	AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,			ATTR_FLAG_BASIC,
+			      .attr_update = ss_power_attr_update),
+	AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,			ATTR_FLAG_BASIC,
+			      .attr_update = ss_power_attr_update),
+	AMDGPU_DEVICE_ATTR_RW(smartshift_bias,				ATTR_FLAG_BASIC,
+			      .attr_update = ss_bias_attr_update),
 };
 
 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
@@ -2717,9 +2907,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-	int limit_type = to_sensor_dev_attr(attr)->index;
-	uint32_t limit = limit_type << 24;
-	uint32_t max_limit = 0;
+	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+	enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_MAX;
+	uint32_t limit;
 	ssize_t size;
 	int r;
 
@@ -2734,16 +2924,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 		return r;
 	}
 
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
+					      pp_limit_level, power_type);
+	else
+		r = -ENODATA;
+
+	if (!r)
 		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, &max_limit, true);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000);
-	} else {
+	else
 		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2757,8 +2947,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-	int limit_type = to_sensor_dev_attr(attr)->index;
-	uint32_t limit = limit_type << 24;
+	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+	enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_CURRENT;
+	uint32_t limit;
 	ssize_t size;
 	int r;
 
@@ -2773,16 +2964,16 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
 		return r;
 	}
 
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, NULL, false);
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
+					      pp_limit_level, power_type);
+	else
+		r = -ENODATA;
+
+	if (!r)
 		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
+	else
 		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2796,8 +2987,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
 {
 	struct amdgpu_device *adev = dev_get_drvdata(dev);
 	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
-	int limit_type = to_sensor_dev_attr(attr)->index;
-	uint32_t limit = limit_type << 24;
+	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
+	enum pp_power_limit_level pp_limit_level = PP_PWR_LIMIT_DEFAULT;
+	uint32_t limit;
 	ssize_t size;
 	int r;
 
@@ -2812,16 +3004,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
 		return r;
 	}
 
-	if (is_support_sw_smu(adev)) {
-		smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
-		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else if (pp_funcs && pp_funcs->get_power_limit) {
-		pp_funcs->get_power_limit(adev->powerplay.pp_handle,
-				&limit, NULL, true);
+	if (pp_funcs && pp_funcs->get_power_limit)
+		r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
+					      pp_limit_level, power_type);
+	else
+		r = -ENODATA;
+
+	if (!r)
 		size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
-	} else {
+	else
 		size = snprintf(buf, PAGE_SIZE, "\n");
-	}
 
 	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
 	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 523f9d2982e9..2f7f688424aa 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1218,6 +1218,8 @@ typedef enum {
 	METRICS_CURR_FANSPEED,
 	METRICS_VOLTAGE_VDDSOC,
 	METRICS_VOLTAGE_VDDGFX,
+	METRICS_SS_APU_SHARE,
+	METRICS_SS_DGPU_SHARE,
 } MetricsMember_t;
 
 enum smu_cmn2asic_mapping_type {
@@ -1260,9 +1262,10 @@ enum smu_cmn2asic_mapping_type {
 	[profile] = {1, (workload)}
 
 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
-int smu_get_power_limit(struct smu_context *smu,
+int smu_get_power_limit(void *handle,
 			uint32_t *limit,
-			enum smu_ppt_limit_level limit_level);
+			enum pp_power_limit_level pp_limit_level,
+			enum pp_power_type pp_power_type);
 
 bool smu_mode1_reset_is_support(struct smu_context *smu);
 bool smu_mode2_reset_is_support(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h
new file mode 100644
index 000000000000..25540cb28208
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu13_driver_if_yellow_carp.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU13_DRIVER_IF_YELLOW_CARP_H__
+#define __SMU13_DRIVER_IF_YELLOW_CARP_H__
+
+// *** IMPORTANT ***
+// SMU TEAM: Always increment the interface version if
+// any structure is changed in this file
+#define SMU13_DRIVER_IF_VERSION 4
+
+typedef struct {
+  int32_t value;
+  uint32_t numFractionalBits;
+} FloatInIntFormat_t;
+
+typedef enum {
+  DSPCLK_DCFCLK = 0,
+  DSPCLK_DISPCLK,
+  DSPCLK_PIXCLK,
+  DSPCLK_PHYCLK,
+  DSPCLK_COUNT,
+} DSPCLK_e;
+
+typedef struct {
+  uint16_t Freq; // in MHz
+  uint16_t Vid;  // min voltage in SVI3 VID
+} DisplayClockTable_t;
+
+typedef struct {
+  uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
+  uint16_t MinMclk;
+  uint16_t MaxMclk;
+
+  uint8_t  WmSetting;
+  uint8_t  WmType;  // Used for normal pstate change or memory retraining
+  uint8_t  Padding[2];
+} WatermarkRowGeneric_t;
+
+#define NUM_WM_RANGES 4
+#define WM_PSTATE_CHG 0
+#define WM_RETRAINING 1
+
+typedef enum {
+  WM_SOCCLK = 0,
+  WM_DCFCLK,
+  WM_COUNT,
+} WM_CLOCK_e;
+
+typedef struct {
+  // Watermarks
+  WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
+
+  uint32_t MmHubPadding[7]; // SMU internal use
+} Watermarks_t;
+
+typedef enum {
+  CUSTOM_DPM_SETTING_GFXCLK,
+  CUSTOM_DPM_SETTING_CCLK,
+  CUSTOM_DPM_SETTING_FCLK_CCX,
+  CUSTOM_DPM_SETTING_FCLK_GFX,
+  CUSTOM_DPM_SETTING_FCLK_STALLS,
+  CUSTOM_DPM_SETTING_LCLK,
+  CUSTOM_DPM_SETTING_COUNT,
+} CUSTOM_DPM_SETTING_e;
+
+typedef struct {
+  uint8_t             ActiveHystLimit;
+  uint8_t             IdleHystLimit;
+  uint8_t             FPS;
+  uint8_t             MinActiveFreqType;
+  FloatInIntFormat_t  MinActiveFreq;
+  FloatInIntFormat_t  PD_Data_limit;
+  FloatInIntFormat_t  PD_Data_time_constant;
+  FloatInIntFormat_t  PD_Data_error_coeff;
+  FloatInIntFormat_t  PD_Data_error_rate_coeff;
+} DpmActivityMonitorCoeffExt_t;
+
+typedef struct {
+  DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
+} CustomDpmSettings_t;
+
+#define NUM_DCFCLK_DPM_LEVELS   8
+#define NUM_DISPCLK_DPM_LEVELS  8
+#define NUM_DPPCLK_DPM_LEVELS   8
+#define NUM_SOCCLK_DPM_LEVELS   8
+#define NUM_VCN_DPM_LEVELS      8
+#define NUM_SOC_VOLTAGE_LEVELS  8
+#define NUM_DF_PSTATE_LEVELS    4
+
+typedef struct {
+  uint32_t FClk;
+  uint32_t MemClk;
+  uint32_t Voltage;
+  uint8_t  WckRatio;
+  uint8_t  Spare[3];
+} DfPstateTable_t;
+
+//Freq in MHz
+//Voltage in milli volts with 2 fractional bits
+typedef struct {
+  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
+  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
+  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
+  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
+  uint32_t VClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t DClocks[NUM_VCN_DPM_LEVELS];
+  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
+  DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
+
+  uint8_t  NumDcfClkLevelsEnabled;
+  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
+  uint8_t  NumSocClkLevelsEnabled;
+  uint8_t  VcnClkLevelsEnabled;     //Applies to both Vclk and Dclk
+  uint8_t  NumDfPstatesEnabled;
+  uint8_t  spare[3];
+
+  uint32_t MinGfxClk;
+  uint32_t MaxGfxClk;
+} DpmClocks_t;
+
+
+// Throttler Status Bitmask
+#define THROTTLER_STATUS_BIT_SPL            0
+#define THROTTLER_STATUS_BIT_FPPT           1
+#define THROTTLER_STATUS_BIT_SPPT           2
+#define THROTTLER_STATUS_BIT_SPPT_APU       3
+#define THROTTLER_STATUS_BIT_THM_CORE       4
+#define THROTTLER_STATUS_BIT_THM_GFX        5
+#define THROTTLER_STATUS_BIT_THM_SOC        6
+#define THROTTLER_STATUS_BIT_TDC_VDD        7
+#define THROTTLER_STATUS_BIT_TDC_SOC        8
+#define THROTTLER_STATUS_BIT_PROCHOT_CPU    9
+#define THROTTLER_STATUS_BIT_PROCHOT_GFX   10
+#define THROTTLER_STATUS_BIT_EDC_CPU       11
+#define THROTTLER_STATUS_BIT_EDC_GFX       12
+
+typedef struct {
+  uint16_t GfxclkFrequency;             //[MHz]
+  uint16_t SocclkFrequency;             //[MHz]
+  uint16_t VclkFrequency;               //[MHz]
+  uint16_t DclkFrequency;               //[MHz]
+  uint16_t MemclkFrequency;             //[MHz]
+  uint16_t spare;
+
+  uint16_t GfxActivity;                 //[centi]
+  uint16_t UvdActivity;                 //[centi]
+
+  uint16_t Voltage[2];                  //[mV] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Current[2];                  //[mA] indices: VDDCR_VDD, VDDCR_SOC
+  uint16_t Power[2];                    //[mW] indices: VDDCR_VDD, VDDCR_SOC
+
+  //3rd party tools in Windows need this info in the case of APUs
+  uint16_t CoreFrequency[8];            //[MHz]
+  uint16_t CorePower[8];                //[mW]
+  uint16_t CoreTemperature[8];          //[centi-Celsius]
+  uint16_t L3Frequency;                 //[MHz]
+  uint16_t L3Temperature;               //[centi-Celsius]
+
+  uint16_t GfxTemperature;              //[centi-Celsius]
+  uint16_t SocTemperature;              //[centi-Celsius]
+  uint16_t ThrottlerStatus;
+
+  uint16_t CurrentSocketPower;          //[mW]
+  uint16_t StapmOpnLimit;               //[W]
+  uint16_t StapmCurrentLimit;           //[W]
+  uint32_t ApuPower;                    //[mW]
+  uint32_t dGpuPower;                   //[mW]
+
+  uint16_t VddTdcValue;                 //[mA]
+  uint16_t SocTdcValue;                 //[mA]
+  uint16_t VddEdcValue;                 //[mA]
+  uint16_t SocEdcValue;                 //[mA]
+
+  uint16_t InfrastructureCpuMaxFreq;    //[MHz]
+  uint16_t InfrastructureGfxMaxFreq;    //[MHz]
+
+  uint16_t SkinTemp;
+  uint16_t DeviceState;
+} SmuMetrics_t;
+
+
+// Workload bits
+#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0
+#define WORKLOAD_PPLIB_VIDEO_BIT          2
+#define WORKLOAD_PPLIB_VR_BIT             3
+#define WORKLOAD_PPLIB_COMPUTE_BIT        4
+#define WORKLOAD_PPLIB_CUSTOM_BIT         5
+#define WORKLOAD_PPLIB_COUNT              6
+
+#define TABLE_BIOS_IF               0 // Called by BIOS
+#define TABLE_WATERMARKS            1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM            2 // Called by Driver
+#define TABLE_SPARE1                3
+#define TABLE_DPMCLOCKS             4 // Called by Driver and VBIOS
+#define TABLE_MOMENTARY_PM          5 // Called by Tools
+#define TABLE_MODERN_STDBY          6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS           7 // Called by Driver
+#define TABLE_INFRASTRUCTURE_LIMITS 8
+#define TABLE_COUNT                 9
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h
new file mode 100644
index 000000000000..b6c976a4d578
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __SMU_V13_0_1_H__
+#define __SMU_V13_0_1_H__
+
+#include "amdgpu_smu.h"
+
+#define SMU13_0_1_DRIVER_IF_VERSION_INV 0xFFFFFFFF
+#define SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP 0x3
+
+/* MP Apertures */
+#define MP0_Public			0x03800000
+#define MP0_SRAM			0x03900000
+#define MP1_Public			0x03b00000
+#define MP1_SRAM			0x03c00004
+
+/* address block */
+#define smnMP1_FIRMWARE_FLAGS		0x3010024
+
+
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
+int smu_v13_0_1_check_fw_status(struct smu_context *smu);
+
+int smu_v13_0_1_check_fw_version(struct smu_context *smu);
+
+int smu_v13_0_1_fini_smc_tables(struct smu_context *smu);
+
+int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu);
+
+int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu);
+
+int smu_v13_0_1_set_driver_table_location(struct smu_context *smu);
+
+int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable);
+#endif
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
new file mode 100644
index 000000000000..5627de734246
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_pmfw.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMU_V13_0_1_PMFW_H__
+#define __SMU_V13_0_1_PMFW_H__
+
+#include "smu13_driver_if_yellow_carp.h"
+
+#pragma pack(push, 1)
+
+#define ENABLE_DEBUG_FEATURES
+
+// Firmware features 
+// Feature Control Defines
+#define FEATURE_CCLK_DPM_BIT                 0
+#define FEATURE_FAN_CONTROLLER_BIT           1
+#define FEATURE_DATA_CALCULATION_BIT         2
+#define FEATURE_PPT_BIT                      3
+#define FEATURE_TDC_BIT                      4
+#define FEATURE_THERMAL_BIT                  5
+#define FEATURE_FIT_BIT                      6
+#define FEATURE_EDC_BIT                      7
+#define FEATURE_PLL_POWER_DOWN_BIT           8
+#define FEATURE_ULV_BIT                      9
+#define FEATURE_VDDOFF_BIT                  10
+#define FEATURE_VCN_DPM_BIT                 11
+#define FEATURE_CSTATE_BOOST_BIT            12
+#define FEATURE_FCLK_DPM_BIT                13
+#define FEATURE_SOCCLK_DPM_BIT              14
+#define FEATURE_MP0CLK_DPM_BIT              15
+#define FEATURE_LCLK_DPM_BIT                16
+#define FEATURE_SHUBCLK_DPM_BIT             17
+#define FEATURE_DCFCLK_DPM_BIT              18
+#define FEATURE_GFX_DPM_BIT                 19
+#define FEATURE_DS_GFXCLK_BIT               20
+#define FEATURE_DS_SOCCLK_BIT               21
+#define FEATURE_DS_LCLK_BIT                 22
+#define FEATURE_DS_DCFCLK_BIT               23
+#define FEATURE_DS_SHUBCLK_BIT              24
+#define FEATURE_GFX_TEMP_VMIN_BIT           25
+#define FEATURE_ZSTATES_BIT                 26
+#define FEATURE_WHISPER_MODE_BIT            27
+#define FEATURE_DS_FCLK_BIT                 28
+#define FEATURE_DS_SMNCLK_BIT               29
+#define FEATURE_DS_MP1CLK_BIT               30
+#define FEATURE_DS_MP0CLK_BIT               31
+#define FEATURE_CLK_LOW_POWER_BIT           32
+#define FEATURE_FUSE_PG_BIT                 33
+#define FEATURE_GFX_DEM_BIT                 34
+#define FEATURE_PSI_BIT                     35
+#define FEATURE_PROCHOT_BIT                 36
+#define FEATURE_CPUOFF_BIT                  37
+#define FEATURE_STAPM_BIT                   38
+#define FEATURE_S0I3_BIT                    39
+#define FEATURE_DF_LIGHT_CSTATE             40   // shift the order or DFCstate annd DF light Cstate
+#define FEATURE_PERF_LIMIT_BIT              41
+#define FEATURE_CORE_DLDO_BIT               42
+#define FEATURE_RSMU_LOW_POWER_BIT          43
+#define FEATURE_SMN_LOW_POWER_BIT           44
+#define FEATURE_THM_LOW_POWER_BIT           45
+#define FEATURE_SMUIO_LOW_POWER_BIT         46
+#define FEATURE_MP1_LOW_POWER_BIT           47
+#define FEATURE_DS_VCN_BIT                  48
+#define FEATURE_CPPC_BIT                    49
+#define FEATURE_CPPC_PREFERRED_CORES        50
+#define FEATURE_SMART_SHIFT_BIT             51
+#define FEATURE_DF_CSTATES_BIT              52
+#define FEATURE_MSMU_LOW_POWER_BIT          53
+#define FEATURE_SOC_VOLTAGE_MON_BIT         54
+#define FEATURE_ATHUB_PG_BIT                55
+#define FEATURE_VDDOFF_ECO_BIT              56
+#define FEATURE_ZSTATES_ECO_BIT             57
+#define FEATURE_CC6_BIT                     58
+#define FEATURE_DS_UMCCLK_BIT               59
+#define FEATURE_DS_HSPCLK_BIT               60 
+#define NUM_FEATURES                        61
+
+typedef struct {
+  // MP1_EXT_SCRATCH0
+  uint32_t DpmHandlerID         : 8;
+  uint32_t ActivityMonitorID    : 8;
+  uint32_t DpmTimerID           : 8;
+  uint32_t DpmHubID             : 4;
+  uint32_t DpmHubTask           : 4;
+  // MP1_EXT_SCRATCH1
+  uint32_t GfxoffStatus         : 8;
+  uint32_t GfxStatus            : 2;
+  uint32_t CpuOff               : 2;
+  uint32_t VddOff               : 1;
+  uint32_t InUlv                : 1;
+  uint32_t InWhisperMode        : 1;
+  uint32_t spare0               : 1;
+  uint32_t ZstateStatus         : 4;
+  uint32_t spare1               :12;
+  // MP1_EXT_SCRATCH2
+  uint32_t P2JobHandler         :24;
+  uint32_t RsmuPmiP2FinishedCnt : 8;
+  // MP1_EXT_SCRATCH3
+  uint32_t PostCode             :32;
+  // MP1_EXT_SCRATCH4
+  uint32_t MsgPortBusy          :15;
+  uint32_t RsmuPmiP1Pending     : 1;
+  uint32_t DfCstateExitPending  : 1;
+  uint32_t Pc6EntryPending      : 1;
+  uint32_t Pc6ExitPending       : 1;
+  uint32_t WarmResetPending     : 1;
+  uint32_t Mp0ClkPending        : 1;
+  uint32_t spare2               : 3;
+  uint32_t RsmuPmiP2PendingCnt  : 8;
+  // MP1_EXT_SCRATCH5
+  uint32_t IdleMask             :32;
+  // MP1_EXT_SCRATCH6 = RTOS threads' status
+  // MP1_EXT_SCRATCH7 = RTOS Current Job
+} FwStatus_t;
+
+
+#pragma pack(pop)
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
new file mode 100644
index 000000000000..1d3447991d0c
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SMU_13_0_1_PPSMC_H
+#define SMU_13_0_1_PPSMC_H
+
+/** @def PPS_PMFW_IF_VER 
+* PPS (PPLib) to PMFW IF version 1.0
+*/
+#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor 
+
+/** @defgroup ResponseCodes PMFW Response Codes: 
+*  @{
+*/
+#define PPSMC_Result_OK                    0x1  ///< Message Response OK 
+#define PPSMC_Result_Failed                0xFF ///< Message Response Failed 
+#define PPSMC_Result_UnknownCmd            0xFE ///< Message Response Unknown Command 
+#define PPSMC_Result_CmdRejectedPrereq     0xFD ///< Message Response Command Failed Prerequisite
+#define PPSMC_Result_CmdRejectedBusy       0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
+/** @}*/
+
+/** @defgroup definitions Message definitions
+*  @{
+*/
+#define PPSMC_MSG_TestMessage                   0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team 
+#define PPSMC_MSG_GetSmuVersion                 0x02 ///< Get PMFW version
+#define PPSMC_MSG_GetDriverIfVersion            0x03 ///< Get PMFW_DRIVER_IF version
+#define PPSMC_MSG_EnableGfxOff                  0x04 ///< Enable GFXOFF
+#define PPSMC_MSG_DisableGfxOff                 0x05 ///< Disable GFXOFF
+#define PPSMC_MSG_PowerDownVcn                  0x06 ///< Power down VCN
+#define PPSMC_MSG_PowerUpVcn                    0x07 ///< Power up VCN; VCN is power gated by default
+#define PPSMC_MSG_SetHardMinVcn                 0x08 ///< For wireless display
+#define PPSMC_MSG_SetSoftMinGfxclk              0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
+#define PPSMC_MSG_ActiveProcessNotify           0x0A ///< Set active work load type
+#define PPSMC_MSG_ForcePowerDownGfx             0x0B ///< Force power down GFX, i.e. enter GFXOFF
+#define PPSMC_MSG_PrepareMp1ForUnload           0x0C ///< Prepare PMFW for GFX driver unload
+#define PPSMC_MSG_SetDriverDramAddrHigh         0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
+#define PPSMC_MSG_SetDriverDramAddrLow          0x0E ///< Set low 32 bits of DRAM address for Driver table transfer 
+#define PPSMC_MSG_TransferTableSmu2Dram         0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM
+#define PPSMC_MSG_TransferTableDram2Smu         0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM
+#define PPSMC_MSG_GfxDeviceDriverReset          0x11 ///< Request GFX mode 2 reset
+#define PPSMC_MSG_GetEnabledSmuFeatures         0x12 ///< Get enabled features in PMFW
+#define PPSMC_MSG_SetHardMinSocclkByFreq        0x13 ///< Set hard min for SOC CLK
+#define PPSMC_MSG_SetSoftMinFclk                0x14 ///< Set hard min for FCLK
+#define PPSMC_MSG_SetSoftMinVcn                 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_SPARE0                        0x16 ///< Spared
+#define PPSMC_MSG_GetGfxclkFrequency            0x17 ///< Get GFX clock frequency
+#define PPSMC_MSG_GetFclkFrequency              0x18 ///< Get FCLK frequency
+#define PPSMC_MSG_AllowGfxOff                   0x19 ///< Inform PMFW of allowing GFXOFF entry
+#define PPSMC_MSG_DisallowGfxOff                0x1A ///< Inform PMFW of disallowing GFXOFF entry
+#define PPSMC_MSG_SetSoftMaxGfxClk              0x1B ///< Set soft max for GFX CLK
+#define PPSMC_MSG_SetHardMinGfxClk              0x1C ///< Set hard min for GFX CLK
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x1D ///< Set soft max for SOC CLK
+#define PPSMC_MSG_SetSoftMaxFclkByFreq          0x1E ///< Set soft max for FCLK
+#define PPSMC_MSG_SetSoftMaxVcn                 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_SetPowerLimitPercentage       0x20 ///< Set power limit percentage
+#define PPSMC_MSG_PowerDownJpeg                 0x21 ///< Power down Jpeg
+#define PPSMC_MSG_PowerUpJpeg                   0x22 ///< Power up Jpeg; VCN is power gated by default
+#define PPSMC_MSG_SetHardMinFclkByFreq          0x23 ///< Set hard min for FCLK
+#define PPSMC_MSG_SetSoftMinSocclkByFreq        0x24 ///< Set soft min for SOC CLK
+#define PPSMC_MSG_AllowZstates                  0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
+#define PPSMC_MSG_DisallowZstates               0x26 ///< Inform PMFW of disallowing Zstate entry, i.e. there is Miracast activity
+#define PPSMC_MSG_RequestActiveWgp              0x27 ///< Request GFX active WGP number
+#define PPSMC_MSG_QueryActiveWgp                0x28 ///< Query the anumber of active WGP number
+#define PPSMC_Message_Count                     0x29 ///< Total number of PPS messages
+/** @}*/
+ 
+/** @enum Mode_Reset_e 
+* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset 
+*/ 
+typedef enum {
+  MODE1_RESET = 1,  ///< Mode reset type 1
+  MODE2_RESET = 2   ///< Mode reset type 2
+} Mode_Reset_e;    
+/** @}*/
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index c73504e998e5..d2a38246a78a 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1035,31 +1035,42 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
 }
 
 static int pp_get_power_limit(void *handle, uint32_t *limit,
-		uint32_t *max_limit, bool default_limit)
+			      enum pp_power_limit_level pp_limit_level,
+			      enum pp_power_type power_type)
 {
 	struct pp_hwmgr *hwmgr = handle;
+	int ret = 0;
 
 	if (!hwmgr || !hwmgr->pm_en ||!limit)
 		return -EINVAL;
 
+	if (power_type != PP_PWR_TYPE_SUSTAINED)
+		return -EOPNOTSUPP;
+
 	mutex_lock(&hwmgr->smu_lock);
 
-	if (default_limit) {
-		*limit = hwmgr->default_power_limit;
-		if (max_limit) {
-			*max_limit = *limit;
+	switch (pp_limit_level) {
+		case PP_PWR_LIMIT_CURRENT:
+			*limit = hwmgr->power_limit;
+			break;
+		case PP_PWR_LIMIT_DEFAULT:
+			*limit = hwmgr->default_power_limit;
+			break;
+		case PP_PWR_LIMIT_MAX:
+			*limit = hwmgr->default_power_limit;
 			if (hwmgr->od_enabled) {
-				*max_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
-				*max_limit /= 100;
+				*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
+				*limit /= 100;
 			}
-		}
+			break;
+		default:
+			ret = -EOPNOTSUPP;
+			break;
 	}
-	else
-		*limit = hwmgr->power_limit;
 
 	mutex_unlock(&hwmgr->smu_lock);
 
-	return 0;
+	return ret;
 }
 
 static int pp_display_configuration_change(void *handle,
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
index 8f71f6a4bb49..43c3f6e755e7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
@@ -831,6 +831,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 		break;
 	case AMD_DPM_FORCED_LEVEL_MANUAL:
 		data->fine_grain_enabled = 1;
+		break;
 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 	default:
 		break;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 285849cef9f2..b4ea8b233240 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -35,6 +35,7 @@
 #include "renoir_ppt.h"
 #include "vangogh_ppt.h"
 #include "aldebaran_ppt.h"
+#include "yellow_carp_ppt.h"
 #include "amd_pcie.h"
 
 /*
@@ -584,6 +585,9 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 	case CHIP_VANGOGH:
 		vangogh_set_ppt_funcs(smu);
 		break;
+	case CHIP_YELLOW_CARP:
+		yellow_carp_set_ppt_funcs(smu);
+		break;
 	default:
 		return -EINVAL;
 	}
@@ -667,6 +671,9 @@ static int smu_late_init(void *handle)
 		return ret;
 	}
 
+	if (adev->asic_type == CHIP_YELLOW_CARP)
+		return 0;
+
 	if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
 		ret = smu_set_default_od_settings(smu);
 		if (ret) {
@@ -2166,16 +2173,57 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
 	return ret;
 }
 
-int smu_get_power_limit(struct smu_context *smu,
+/**
+ * smu_get_power_limit - Request one of the SMU Power Limits
+ *
+ * @handle: pointer to smu context
+ * @limit: requested limit is written back to this variable
+ * @pp_limit_level: &pp_power_limit_level which limit of the power to return
+ * @pp_power_type: &pp_power_type type of power
+ * Return:  0 on success, <0 on error
+ *
+ */
+int smu_get_power_limit(void *handle,
 			uint32_t *limit,
-			enum smu_ppt_limit_level limit_level)
+			enum pp_power_limit_level pp_limit_level,
+			enum pp_power_type pp_power_type)
 {
-	uint32_t limit_type = *limit >> 24;
+	struct smu_context *smu = handle;
+	enum smu_ppt_limit_level limit_level;
+	uint32_t limit_type;
 	int ret = 0;
 
 	if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 		return -EOPNOTSUPP;
 
+	switch(pp_power_type) {
+	case PP_PWR_TYPE_SUSTAINED:
+		limit_type = SMU_DEFAULT_PPT_LIMIT;
+		break;
+	case PP_PWR_TYPE_FAST:
+		limit_type = SMU_FAST_PPT_LIMIT;
+		break;
+	default:
+		return -EOPNOTSUPP;
+		break;
+	}
+
+	switch(pp_limit_level){
+	case PP_PWR_LIMIT_CURRENT:
+		limit_level = SMU_PPT_LIMIT_CURRENT;
+		break;
+	case PP_PWR_LIMIT_DEFAULT:
+		limit_level = SMU_PPT_LIMIT_DEFAULT;
+		break;
+	case PP_PWR_LIMIT_MAX:
+		limit_level = SMU_PPT_LIMIT_MAX;
+		break;
+	case PP_PWR_LIMIT_MIN:
+	default:
+		return -EOPNOTSUPP;
+		break;
+	}
+
 	mutex_lock(&smu->mutex);
 
 	if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
@@ -2962,6 +3010,8 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
 	.get_fan_control_mode    = smu_get_fan_control_mode,
 	.set_fan_speed_percent   = smu_set_fan_speed_percent,
 	.get_fan_speed_percent   = smu_get_fan_speed_percent,
+	.force_clock_level       = smu_force_ppclk_levels,
+	.print_clock_levels      = smu_print_ppclk_levels,
 	.force_performance_level = smu_force_performance_level,
 	.read_sensor             = smu_read_sensor,
 	.get_performance_level   = smu_get_performance_level,
@@ -2974,38 +3024,37 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
 	.switch_power_profile    = smu_switch_power_profile,
 	/* export to amdgpu */
 	.dispatch_tasks          = smu_handle_dpm_task,
+	.load_firmware           = smu_load_microcode,
 	.set_powergating_by_smu  = smu_dpm_set_power_gate,
 	.set_power_limit         = smu_set_power_limit,
+	.get_power_limit         = smu_get_power_limit,
+	.get_power_profile_mode  = smu_get_power_profile_mode,
+	.set_power_profile_mode  = smu_set_power_profile_mode,
 	.odn_edit_dpm_table      = smu_od_edit_dpm_table,
 	.set_mp1_state           = smu_set_mp1_state,
+	.gfx_state_change_set    = smu_gfx_state_change_set,
 	/* export to DC */
-	.get_sclk                = smu_get_sclk,
-	.get_mclk                = smu_get_mclk,
-	.enable_mgpu_fan_boost   = smu_enable_mgpu_fan_boost,
-	.get_asic_baco_capability = smu_get_baco_capability,
-	.set_asic_baco_state     = smu_baco_set_state,
-	.get_ppfeature_status    = smu_sys_get_pp_feature_mask,
-	.set_ppfeature_status    = smu_sys_set_pp_feature_mask,
-	.asic_reset_mode_2       = smu_mode2_reset,
-	.set_df_cstate           = smu_set_df_cstate,
-	.set_xgmi_pstate         = smu_set_xgmi_pstate,
-	.get_gpu_metrics         = smu_sys_get_gpu_metrics,
-	.set_power_profile_mode  = smu_set_power_profile_mode,
-	.get_power_profile_mode  = smu_get_power_profile_mode,
-	.force_clock_level       = smu_force_ppclk_levels,
-	.print_clock_levels      = smu_print_ppclk_levels,
-	.get_uclk_dpm_states     = smu_get_uclk_dpm_states,
-	.get_dpm_clock_table     = smu_get_dpm_clock_table,
-	.display_configuration_change        = smu_display_configuration_change,
-	.get_clock_by_type_with_latency      = smu_get_clock_by_type_with_latency,
-	.display_clock_voltage_request       = smu_display_clock_voltage_request,
-	.set_active_display_count            = smu_set_display_count,
-	.set_min_deep_sleep_dcefclk          = smu_set_deep_sleep_dcefclk,
+	.get_sclk                         = smu_get_sclk,
+	.get_mclk                         = smu_get_mclk,
+	.display_configuration_change     = smu_display_configuration_change,
+	.get_clock_by_type_with_latency   = smu_get_clock_by_type_with_latency,
+	.display_clock_voltage_request    = smu_display_clock_voltage_request,
+	.enable_mgpu_fan_boost            = smu_enable_mgpu_fan_boost,
+	.set_active_display_count         = smu_set_display_count,
+	.set_min_deep_sleep_dcefclk       = smu_set_deep_sleep_dcefclk,
+	.get_asic_baco_capability         = smu_get_baco_capability,
+	.set_asic_baco_state              = smu_baco_set_state,
+	.get_ppfeature_status             = smu_sys_get_pp_feature_mask,
+	.set_ppfeature_status             = smu_sys_set_pp_feature_mask,
+	.asic_reset_mode_2                = smu_mode2_reset,
+	.set_df_cstate                    = smu_set_df_cstate,
+	.set_xgmi_pstate                  = smu_set_xgmi_pstate,
+	.get_gpu_metrics                  = smu_sys_get_gpu_metrics,
 	.set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,
 	.display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
 	.get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,
-	.load_firmware           = smu_load_microcode,
-	.gfx_state_change_set    = smu_gfx_state_change_set,
+	.get_uclk_dpm_states              = smu_get_uclk_dpm_states,
+	.get_dpm_clock_table              = smu_get_dpm_clock_table,
 	.get_smu_prv_buf_details = smu_get_prv_buffer_details,
 };
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 1735a96dd307..5959019f51ad 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -380,16 +380,31 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
 	return 0;
 }
 
-static int arcturus_check_powerplay_table(struct smu_context *smu)
+static void arcturus_check_bxco_support(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t val;
 
 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
+	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
+		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+		smu_baco->platform_support =
+			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+									false;
+	}
+}
+
+static int arcturus_check_powerplay_table(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	struct smu_11_0_powerplay_table *powerplay_table =
+		table_context->power_play_table;
+
+	arcturus_check_bxco_support(smu);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -2147,18 +2162,6 @@ static void arcturus_get_unique_id(struct smu_context *smu)
 	sprintf(adev->serial, "%llx", id);
 }
 
-static bool arcturus_is_baco_supported(struct smu_context *smu)
-{
-	struct amdgpu_device *adev = smu->adev;
-	uint32_t val;
-
-	if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev))
-		return false;
-
-	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
-}
-
 static int arcturus_set_df_cstate(struct smu_context *smu,
 				  enum pp_df_cstate state)
 {
@@ -2393,7 +2396,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-	.baco_is_support= arcturus_is_baco_supported,
+	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
 	.baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 78fe13183e8b..74a8c676e22c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -340,19 +340,34 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
 	return 0;
 }
 
-static int navi10_check_powerplay_table(struct smu_context *smu)
+static void navi10_check_bxco_support(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t val;
+
+	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
+	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
+		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+		smu_baco->platform_support =
+			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+									false;
+	}
+}
+
+static int navi10_check_powerplay_table(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	struct smu_11_0_powerplay_table *powerplay_table =
+		table_context->power_play_table;
 
 	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
 		smu->dc_controlled_by_gpio = true;
 
-	if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
+	navi10_check_bxco_support(smu);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -2242,18 +2257,6 @@ static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
 	return 0;
 }
 
-static bool navi10_is_baco_supported(struct smu_context *smu)
-{
-	struct amdgpu_device *adev = smu->adev;
-	uint32_t val;
-
-	if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
-		return false;
-
-	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
-}
-
 static int navi10_set_default_od_settings(struct smu_context *smu)
 {
 	OverDriveTable_t *od_table =
@@ -3089,7 +3092,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-	.baco_is_support= navi10_is_baco_supported,
+	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
 	.baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 75acdb80c499..f01e919e1f89 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -323,19 +323,34 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 	return 0;
 }
 
-static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 {
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_11_0_7_powerplay_table *powerplay_table =
 		table_context->power_play_table;
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t val;
+
+	if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
+	    powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
+		val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
+		smu_baco->platform_support =
+			(val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
+									false;
+	}
+}
+
+static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
+{
+	struct smu_table_context *table_context = &smu->smu_table;
+	struct smu_11_0_7_powerplay_table *powerplay_table =
+		table_context->power_play_table;
 
 	if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 		smu->dc_controlled_by_gpio = true;
 
-	if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
+	sienna_cichlid_check_bxco_support(smu);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
@@ -2085,18 +2100,6 @@ static int sienna_cichlid_run_btc(struct smu_context *smu)
 	return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 }
 
-static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
-{
-	struct amdgpu_device *adev = smu->adev;
-	uint32_t val;
-
-	if (amdgpu_sriov_vf(adev) || (!smu_v11_0_baco_is_support(smu)))
-		return false;
-
-	val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
-	return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : false;
-}
-
 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
@@ -3869,7 +3872,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
 	.register_irq_handler = smu_v11_0_register_irq_handler,
 	.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
 	.get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
-	.baco_is_support= sienna_cichlid_is_baco_supported,
+	.baco_is_support = smu_v11_0_baco_is_support,
 	.baco_get_state = smu_v11_0_baco_get_state,
 	.baco_set_state = smu_v11_0_baco_set_state,
 	.baco_enter = smu_v11_0_baco_enter,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 362696208fd8..e1e1c268f661 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1483,7 +1483,7 @@ bool smu_v11_0_baco_is_support(struct smu_context *smu)
 {
 	struct smu_baco_context *smu_baco = &smu->smu_baco;
 
-	if (!smu_baco->platform_support)
+	if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
 		return false;
 
 	/* Arcturus does not support this bit mask */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
index 652b4e554378..9b3a8503f5cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
@@ -23,7 +23,7 @@
 # Makefile for the 'smu manager' sub-component of powerplay.
 # It provides the smu management services for the driver.
 
-SMU13_MGR = smu_v13_0.o aldebaran_ppt.o
+SMU13_MGR = smu_v13_0.o aldebaran_ppt.o smu_v13_0_1.o yellow_carp_ppt.o
 
 AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR))
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 7a1abb3d6a7a..6ee9c4186f02 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -355,13 +355,6 @@ static int aldebaran_check_powerplay_table(struct smu_context *smu)
 	struct smu_table_context *table_context = &smu->smu_table;
 	struct smu_13_0_powerplay_table *powerplay_table =
 		table_context->power_play_table;
-	struct smu_baco_context *smu_baco = &smu->smu_baco;
-
-	mutex_lock(&smu_baco->mutex);
-	if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO ||
-	    powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO)
-		smu_baco->platform_support = true;
-	mutex_unlock(&smu_baco->mutex);
 
 	table_context->thermal_controller_type =
 		powerplay_table->thermal_controller_type;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c
new file mode 100644
index 000000000000..61917b49f2bf
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+//#include <linux/reboot.h>
+
+#define SWSMU_CODE_LAYER_L3
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v13_0_1.h"
+#include "soc15_common.h"
+#include "smu_cmn.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "amdgpu_atombios.h"
+#include "atom.h"
+
+#include "asic_reg/mp/mp_13_0_1_offset.h"
+#include "asic_reg/mp/mp_13_0_1_sh_mask.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+int smu_v13_0_1_check_fw_status(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t mp1_fw_flags;
+
+	mp1_fw_flags = RREG32_PCIE(MP1_Public |
+				   (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
+
+	if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
+	    MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
+		return 0;
+
+	return -EIO;
+}
+
+int smu_v13_0_1_check_fw_version(struct smu_context *smu)
+{
+	uint32_t if_version = 0xff, smu_version = 0xff;
+	uint16_t smu_major;
+	uint8_t smu_minor, smu_debug;
+	int ret = 0;
+
+	ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
+	if (ret)
+		return ret;
+
+	smu_major = (smu_version >> 16) & 0xffff;
+	smu_minor = (smu_version >> 8) & 0xff;
+	smu_debug = (smu_version >> 0) & 0xff;
+
+	switch (smu->adev->asic_type) {
+	case CHIP_YELLOW_CARP:
+		smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP;
+		break;
+
+	default:
+		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
+		smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_INV;
+		break;
+	}
+
+	dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
+			 smu_version, smu_major, smu_minor, smu_debug);
+
+	/*
+	 * 1. if_version mismatch is not critical as our fw is designed
+	 * to be backward compatible.
+	 * 2. New fw usually brings some optimizations. But that's visible
+	 * only on the paired driver.
+	 * Considering above, we just leave user a warning message instead
+	 * of halt driver loading.
+	 */
+	if (if_version != smu->smc_driver_if_version) {
+		dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
+			 "smu fw version = 0x%08x (%d.%d.%d)\n",
+			 smu->smc_driver_if_version, if_version,
+			 smu_version, smu_major, smu_minor, smu_debug);
+		dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
+	}
+
+	return ret;
+}
+
+int smu_v13_0_1_fini_smc_tables(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	kfree(smu_table->clocks_table);
+	smu_table->clocks_table = NULL;
+
+	kfree(smu_table->metrics_table);
+	smu_table->metrics_table = NULL;
+
+	kfree(smu_table->watermarks_table);
+	smu_table->watermarks_table = NULL;
+
+	return 0;
+}
+
+static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev,
+						uint8_t clk_id,
+						uint8_t syspll_id,
+						uint32_t *clk_freq)
+{
+	struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
+	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
+	int ret, index;
+
+	input.clk_id = clk_id;
+	input.syspll_id = syspll_id;
+	input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+	index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+					    getsmuclockinfo);
+
+	ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+					(uint32_t *)&input);
+	if (ret)
+		return -EINVAL;
+
+	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+	*clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+
+	return 0;
+}
+
+int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu)
+{
+	int ret, index;
+	uint16_t size;
+	uint8_t frev, crev;
+	struct atom_common_table_header *header;
+	struct atom_firmware_info_v3_4 *v_3_4;
+	struct atom_firmware_info_v3_3 *v_3_3;
+	struct atom_firmware_info_v3_1 *v_3_1;
+
+	index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+					    firmwareinfo);
+
+	ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
+					     (uint8_t **)&header);
+	if (ret)
+		return ret;
+
+	if (header->format_revision != 3) {
+		dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
+		return -EINVAL;
+	}
+
+	switch (header->content_revision) {
+	case 0:
+	case 1:
+	case 2:
+		v_3_1 = (struct atom_firmware_info_v3_1 *)header;
+		smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
+		smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
+		smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
+		smu->smu_table.boot_values.socclk = 0;
+		smu->smu_table.boot_values.dcefclk = 0;
+		smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
+		smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
+		smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
+		smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
+		smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
+		break;
+	case 3:
+		v_3_3 = (struct atom_firmware_info_v3_3 *)header;
+		smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
+		smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
+		smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
+		smu->smu_table.boot_values.socclk = 0;
+		smu->smu_table.boot_values.dcefclk = 0;
+		smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
+		smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
+		smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
+		smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
+		smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
+		break;
+	case 4:
+	default:
+		v_3_4 = (struct atom_firmware_info_v3_4 *)header;
+		smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
+		smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
+		smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
+		smu->smu_table.boot_values.socclk = 0;
+		smu->smu_table.boot_values.dcefclk = 0;
+		smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
+		smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
+		smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
+		smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
+		smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
+		break;
+	}
+
+	smu->smu_table.boot_values.format_revision = header->format_revision;
+	smu->smu_table.boot_values.content_revision = header->content_revision;
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.socclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.dcefclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_ECLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.eclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_VCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.vclk);
+
+	smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+					(uint8_t)SMU11_SYSPLL0_DCLK_ID,
+					(uint8_t)0,
+					&smu->smu_table.boot_values.dclk);
+
+	if ((smu->smu_table.boot_values.format_revision == 3) &&
+	    (smu->smu_table.boot_values.content_revision >= 2))
+		smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
+						(uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
+						(uint8_t)SMU11_SYSPLL1_2_ID,
+						&smu->smu_table.boot_values.fclk);
+
+	return 0;
+}
+
+int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
+}
+
+int smu_v13_0_1_set_driver_table_location(struct smu_context *smu)
+{
+	struct smu_table *driver_table = &smu->smu_table.driver_table;
+	int ret = 0;
+
+	if (!driver_table->mc_address)
+		return 0;
+
+	ret = smu_cmn_send_smc_msg_with_param(smu,
+			SMU_MSG_SetDriverDramAddrHigh,
+			upper_32_bits(driver_table->mc_address),
+			NULL);
+
+	if (ret)
+		return ret;
+
+	ret = smu_cmn_send_smc_msg_with_param(smu,
+			SMU_MSG_SetDriverDramAddrLow,
+			lower_32_bits(driver_table->mc_address),
+			NULL);
+
+	return ret;
+}
+
+int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+	struct amdgpu_device *adev = smu->adev;
+
+	switch (adev->asic_type) {
+	case CHIP_YELLOW_CARP:
+		if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
+			return 0;
+		if (enable)
+			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
+		else
+			ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
new file mode 100644
index 000000000000..0cd7902d5172
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -0,0 +1,1210 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define SWSMU_CODE_LAYER_L2
+
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v13_0_1.h"
+#include "smu13_driver_if_yellow_carp.h"
+#include "yellow_carp_ppt.h"
+#include "smu_v13_0_1_ppsmc.h"
+#include "smu_v13_0_1_pmfw.h"
+#include "smu_cmn.h"
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE ( \
+	FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
+	FEATURE_MASK(FEATURE_VCN_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_FCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_LCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)	 | \
+	FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
+	FEATURE_MASK(FEATURE_GFX_DPM_BIT))
+
+static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
+	MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,			1),
+	MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,		1),
+	MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,		1),
+	MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,			1),
+	MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,			1),
+	MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,		1),
+	MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,			1),
+	MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,			1),
+	MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,		1),
+	MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,		1),
+	MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,      1),
+	MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,	1),
+	MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,		1),
+	MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,	1),
+	MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,	1),
+	MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,		1),
+	MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,	1),
+	MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,	1),
+	MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,		1),
+	MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,		1),
+	MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,		1),
+	MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,		1),
+	MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,		1),
+	MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,	1),
+	MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,		1),
+	MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,		1),
+	MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,	1),
+	MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,		1),
+	MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,			1),
+	MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,		1),
+	MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,	1),
+};
+
+static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
+	FEA_MAP(CCLK_DPM),
+	FEA_MAP(FAN_CONTROLLER),
+	FEA_MAP(PPT),
+	FEA_MAP(TDC),
+	FEA_MAP(THERMAL),
+	FEA_MAP(ULV),
+	FEA_MAP(VCN_DPM),
+	FEA_MAP_REVERSE(FCLK),
+	FEA_MAP_REVERSE(SOCCLK),
+	FEA_MAP(LCLK_DPM),
+	FEA_MAP(SHUBCLK_DPM),
+	FEA_MAP(DCFCLK_DPM),
+	FEA_MAP_HALF_REVERSE(GFX),
+	FEA_MAP(DS_GFXCLK),
+	FEA_MAP(DS_SOCCLK),
+	FEA_MAP(DS_LCLK),
+	FEA_MAP(DS_DCFCLK),
+	FEA_MAP(DS_FCLK),
+	FEA_MAP(DS_MP1CLK),
+	FEA_MAP(DS_MP0CLK),
+	FEA_MAP(GFX_DEM),
+	FEA_MAP(PSI),
+	FEA_MAP(PROCHOT),
+	FEA_MAP(CPUOFF),
+	FEA_MAP(STAPM),
+	FEA_MAP(S0I3),
+	FEA_MAP(PERF_LIMIT),
+	FEA_MAP(CORE_DLDO),
+	FEA_MAP(RSMU_LOW_POWER),
+	FEA_MAP(SMN_LOW_POWER),
+	FEA_MAP(THM_LOW_POWER),
+	FEA_MAP(SMUIO_LOW_POWER),
+	FEA_MAP(MP1_LOW_POWER),
+	FEA_MAP(DS_VCN),
+	FEA_MAP(CPPC),
+	FEA_MAP(DF_CSTATES),
+	FEA_MAP(MSMU_LOW_POWER),
+	FEA_MAP(ATHUB_PG),
+};
+
+static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
+	TAB_MAP_VALID(WATERMARKS),
+	TAB_MAP_VALID(SMU_METRICS),
+	TAB_MAP_VALID(CUSTOM_DPM),
+	TAB_MAP_VALID(DPMCLOCKS),
+};
+
+static struct cmn2asic_mapping yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,		WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,		WORKLOAD_PPLIB_VIDEO_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,			WORKLOAD_PPLIB_VR_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,		WORKLOAD_PPLIB_COMPUTE_BIT),
+	WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,		WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+	
+static int yellow_carp_init_smc_tables(struct smu_context *smu)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+	struct smu_table *tables = smu_table->tables;
+
+	SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+	SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+		PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
+
+	smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
+	if (!smu_table->clocks_table)
+		goto err0_out;
+
+	smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+	if (!smu_table->metrics_table)
+		goto err1_out;
+	smu_table->metrics_time = 0;
+
+	smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
+	if (!smu_table->watermarks_table)
+		goto err2_out;
+
+	smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
+	smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
+	if (!smu_table->gpu_metrics_table)
+		goto err3_out;
+
+	return 0;
+
+err3_out:
+	kfree(smu_table->watermarks_table);
+err2_out:
+	kfree(smu_table->metrics_table);
+err1_out:
+	kfree(smu_table->clocks_table);
+err0_out:
+	return -ENOMEM;
+}
+
+static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
+{
+	struct smu_feature *feature = &smu->smu_feature;
+	uint32_t feature_mask[2];
+	int ret = 0;
+
+	if (!en)
+		ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
+
+	bitmap_zero(feature->enabled, feature->feature_num);
+	bitmap_zero(feature->supported, feature->feature_num);
+
+	if (!en)
+		return ret;
+
+	ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+	if (ret)
+		return ret;
+
+	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
+		    feature->feature_num);
+	bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
+		    feature->feature_num);
+
+	return 0;
+}
+
+static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+
+	/* vcn dpm on is a prerequisite for vcn power gate messages */
+	if (enable)
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
+						      0, NULL);
+	else
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
+						      0, NULL);
+
+	return ret;
+}
+
+static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
+{
+	int ret = 0;
+
+	if (enable)
+		ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
+						      0, NULL);
+	else
+		ret = smu_cmn_send_smc_msg_with_param(smu,
+						      SMU_MSG_PowerDownJpeg, 0,
+						      NULL);
+
+	return ret;
+}
+
+
+static bool yellow_carp_is_dpm_running(struct smu_context *smu)
+{
+	int ret = 0;
+	uint32_t feature_mask[2];
+	uint64_t feature_enabled;
+
+	ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
+
+	if (ret)
+		return false;
+
+	feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
+
+	return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
+static int yellow_carp_post_smu_init(struct smu_context *smu)
+{
+	struct amdgpu_device *adev = smu->adev;
+	int ret = 0;
+
+	/* allow message will be sent after enable message on Yellow Carp*/
+	ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
+	if (ret)
+		dev_err(adev->dev, "Failed to Enable GfxOff!\n");
+	return ret;
+}
+
+static int yellow_carp_mode_reset(struct smu_context *smu, int type)
+{
+	int ret = 0, index = 0;
+
+	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+				SMU_MSG_GfxDeviceDriverReset);
+	if (index < 0)
+		return index == -EACCES ? 0 : index;
+
+	mutex_lock(&smu->message_lock);
+
+	ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
+
+	mutex_unlock(&smu->message_lock);
+
+	mdelay(10);
+
+	return ret;
+}
+
+static int yellow_carp_mode2_reset(struct smu_context *smu)
+{
+	return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
+}
+
+static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
+							MetricsMember_t member,
+							uint32_t *value)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+
+	SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+	int ret = 0;
+
+	mutex_lock(&smu->metrics_lock);
+
+	ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
+	if (ret) {
+		mutex_unlock(&smu->metrics_lock);
+		return ret;
+	}
+
+	switch (member) {
+	case METRICS_AVERAGE_GFXCLK:
+		*value = metrics->GfxclkFrequency;
+		break;
+	case METRICS_AVERAGE_SOCCLK:
+		*value = metrics->SocclkFrequency;
+		break;
+	case METRICS_AVERAGE_VCLK:
+		*value = metrics->VclkFrequency;
+		break;
+	case METRICS_AVERAGE_DCLK:
+		*value = metrics->DclkFrequency;
+		break;
+	case METRICS_AVERAGE_UCLK:
+		*value = metrics->MemclkFrequency;
+		break;
+	case METRICS_AVERAGE_GFXACTIVITY:
+		*value = metrics->GfxActivity / 100;
+		break;
+	case METRICS_AVERAGE_VCNACTIVITY:
+		*value = metrics->UvdActivity;
+		break;
+	case METRICS_AVERAGE_SOCKETPOWER:
+		*value = (metrics->CurrentSocketPower << 8) / 1000;
+		break;
+	case METRICS_TEMPERATURE_EDGE:
+		*value = metrics->GfxTemperature / 100 *
+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+		break;
+	case METRICS_TEMPERATURE_HOTSPOT:
+		*value = metrics->SocTemperature / 100 *
+		SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+		break;
+	case METRICS_THROTTLER_STATUS:
+		*value = metrics->ThrottlerStatus;
+		break;
+	case METRICS_VOLTAGE_VDDGFX:
+		*value = metrics->Voltage[0];
+		break;
+	case METRICS_VOLTAGE_VDDSOC:
+		*value = metrics->Voltage[1];
+		break;
+	default:
+		*value = UINT_MAX;
+		break;
+	}
+
+	mutex_unlock(&smu->metrics_lock);
+
+	return ret;
+}
+
+static int yellow_carp_read_sensor(struct smu_context *smu,
+					enum amd_pp_sensors sensor,
+					void *data, uint32_t *size)
+{
+	int ret = 0;
+
+	if (!data || !size)
+		return -EINVAL;
+
+	mutex_lock(&smu->sensor_lock);
+	switch (sensor) {
+	case AMDGPU_PP_SENSOR_GPU_LOAD:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_GFXACTIVITY,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GPU_POWER:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_SOCKETPOWER,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_EDGE_TEMP:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_TEMPERATURE_EDGE,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_TEMPERATURE_HOTSPOT,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GFX_MCLK:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_UCLK,
+								(uint32_t *)data);
+		*(uint32_t *)data *= 100;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_GFX_SCLK:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_AVERAGE_GFXCLK,
+								(uint32_t *)data);
+		*(uint32_t *)data *= 100;
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_VDDGFX:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_VOLTAGE_VDDGFX,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	case AMDGPU_PP_SENSOR_VDDNB:
+		ret = yellow_carp_get_smu_metrics_data(smu,
+								METRICS_VOLTAGE_VDDSOC,
+								(uint32_t *)data);
+		*size = 4;
+		break;
+	default:
+		ret = -EOPNOTSUPP;
+		break;
+	}
+	mutex_unlock(&smu->sensor_lock);
+
+	return ret;
+}
+
+static int yellow_carp_set_watermarks_table(struct smu_context *smu,
+				struct pp_smu_wm_range_sets *clock_ranges)
+{
+	int i;
+	int ret = 0;
+	Watermarks_t *table = smu->smu_table.watermarks_table;
+
+	if (!table || !clock_ranges)
+		return -EINVAL;
+
+	if (clock_ranges) {
+		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
+			clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
+			return -EINVAL;
+
+		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
+			table->WatermarkRow[WM_DCFCLK][i].MinClock =
+				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MaxClock =
+				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MinMclk =
+				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
+			table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
+				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
+
+			table->WatermarkRow[WM_DCFCLK][i].WmSetting =
+				clock_ranges->reader_wm_sets[i].wm_inst;
+		}
+
+		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
+			table->WatermarkRow[WM_SOCCLK][i].MinClock =
+				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MaxClock =
+				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MinMclk =
+				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
+			table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
+				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
+
+			table->WatermarkRow[WM_SOCCLK][i].WmSetting =
+				clock_ranges->writer_wm_sets[i].wm_inst;
+		}
+
+		smu->watermarks_bitmap |= WATERMARKS_EXIST;
+	}
+
+	/* pass data to smu controller */
+	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+		ret = smu_cmn_write_watermarks_table(smu);
+		if (ret) {
+			dev_err(smu->adev->dev, "Failed to update WMTABLE!");
+			return ret;
+		}
+		smu->watermarks_bitmap |= WATERMARKS_LOADED;
+	}
+
+	return 0;
+}
+
+static int yellow_carp_get_power_profile_mode(struct smu_context *smu,
+						char *buf)
+{
+	static const char *profile_name[] = {
+					"BOOTUP_DEFAULT",
+					"3D_FULL_SCREEN",
+					"POWER_SAVING",
+					"VIDEO",
+					"VR",
+					"COMPUTE",
+					"CUSTOM"};
+	uint32_t i, size = 0;
+	int16_t workload_type = 0;
+
+	if (!buf)
+		return -EINVAL;
+
+	for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+		/*
+		 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT.
+		 * Not all profile modes are supported on yellow carp.
+		 */
+		workload_type = smu_cmn_to_asic_specific_index(smu,
+							       CMN2ASIC_MAPPING_WORKLOAD,
+							       i);
+
+		if (workload_type < 0)
+			continue;
+
+		size += sprintf(buf + size, "%2d %14s%s\n",
+			i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
+	}
+
+	return size;
+}
+
+static int yellow_carp_set_power_profile_mode(struct smu_context *smu,
+						long *input, uint32_t size)
+{
+	int workload_type, ret;
+	uint32_t profile_mode = input[size];
+
+	if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+		dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
+		return -EINVAL;
+	}
+
+	if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
+			profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
+		return 0;
+
+	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+	workload_type = smu_cmn_to_asic_specific_index(smu,
+						       CMN2ASIC_MAPPING_WORKLOAD,
+						       profile_mode);
+	if (workload_type < 0) {
+		dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on YELLOWCARP\n",
+					profile_mode);
+		return -EINVAL;
+	}
+
+	ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
+				    1 << workload_type,
+				    NULL);
+	if (ret) {
+		dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
+					workload_type);
+		return ret;
+	}
+
+	smu->power_profile_mode = profile_mode;
+
+	return 0;
+}
+
+static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
+						void **table)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+	struct gpu_metrics_v2_1 *gpu_metrics =
+		(struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
+	SmuMetrics_t metrics;
+	int ret = 0;
+
+	ret = smu_cmn_get_metrics_table(smu, &metrics, true);
+	if (ret)
+		return ret;
+
+	smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
+
+	gpu_metrics->temperature_gfx = metrics.GfxTemperature;
+	gpu_metrics->temperature_soc = metrics.SocTemperature;
+	memcpy(&gpu_metrics->temperature_core[0],
+		&metrics.CoreTemperature[0],
+		sizeof(uint16_t) * 8);
+	gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
+
+	gpu_metrics->average_gfx_activity = metrics.GfxActivity;
+	gpu_metrics->average_mm_activity = metrics.UvdActivity;
+
+	gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
+	gpu_metrics->average_gfx_power = metrics.Power[0];
+	gpu_metrics->average_soc_power = metrics.Power[1];
+	memcpy(&gpu_metrics->average_core_power[0],
+		&metrics.CorePower[0],
+		sizeof(uint16_t) * 8);
+
+	gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
+	gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
+	gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
+	gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
+	gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
+	gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
+
+	memcpy(&gpu_metrics->current_coreclk[0],
+		&metrics.CoreFrequency[0],
+		sizeof(uint16_t) * 8);
+	gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
+
+	gpu_metrics->throttle_status = metrics.ThrottlerStatus;
+
+	gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
+
+	*table = (void *)gpu_metrics;
+
+	return sizeof(struct gpu_metrics_v2_1);
+}
+
+static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
+					long input[], uint32_t size)
+{
+	struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
+	int ret = 0;
+
+	/* Only allowed in manual mode */
+	if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
+		return -EINVAL;
+
+	switch (type) {
+	case PP_OD_EDIT_SCLK_VDDC_TABLE:
+		if (size != 2) {
+			dev_err(smu->adev->dev, "Input parameter number not correct\n");
+			return -EINVAL;
+		}
+
+		if (input[0] == 0) {
+			if (input[1] < smu->gfx_default_hard_min_freq) {
+				dev_warn(smu->adev->dev,
+					"Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
+					input[1], smu->gfx_default_hard_min_freq);
+				return -EINVAL;
+			}
+			smu->gfx_actual_hard_min_freq = input[1];
+		} else if (input[0] == 1) {
+			if (input[1] > smu->gfx_default_soft_max_freq) {
+				dev_warn(smu->adev->dev,
+					"Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
+					input[1], smu->gfx_default_soft_max_freq);
+				return -EINVAL;
+			}
+			smu->gfx_actual_soft_max_freq = input[1];
+		} else {
+			return -EINVAL;
+		}
+		break;
+	case PP_OD_RESTORE_DEFAULT_TABLE:
+		if (size != 0) {
+			dev_err(smu->adev->dev, "Input parameter number not correct\n");
+			return -EINVAL;
+		} else {
+			smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+			smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+		}
+		break;
+	case PP_OD_COMMIT_DPM_TABLE:
+		if (size != 0) {
+			dev_err(smu->adev->dev, "Input parameter number not correct\n");
+			return -EINVAL;
+		} else {
+			if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
+				dev_err(smu->adev->dev,
+					"The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
+					smu->gfx_actual_hard_min_freq,
+					smu->gfx_actual_soft_max_freq);
+				return -EINVAL;
+			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
+									smu->gfx_actual_hard_min_freq, NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set hard min sclk failed!");
+				return ret;
+			}
+
+			ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
+									smu->gfx_actual_soft_max_freq, NULL);
+			if (ret) {
+				dev_err(smu->adev->dev, "Set soft max sclk failed!");
+				return ret;
+			}
+		}
+		break;
+	default:
+		return -ENOSYS;
+	}
+
+	return ret;
+}
+
+static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t *value)
+{
+	MetricsMember_t member_type;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+		member_type = METRICS_AVERAGE_SOCCLK;
+		break;
+	case SMU_VCLK:
+	    member_type = METRICS_AVERAGE_VCLK;
+		break;
+	case SMU_DCLK:
+		member_type = METRICS_AVERAGE_DCLK;
+		break;
+	case SMU_MCLK:
+		member_type = METRICS_AVERAGE_UCLK;
+		break;
+	case SMU_FCLK:
+		return smu_cmn_send_smc_msg_with_param(smu,
+				SMU_MSG_GetFclkFrequency, 0, value);
+	default:
+		return -EINVAL;
+	}
+
+	return yellow_carp_get_smu_metrics_data(smu, member_type, value);
+}
+
+static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t *count)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+		*count = clk_table->NumSocClkLevelsEnabled;
+		break;
+	case SMU_VCLK:
+		*count = clk_table->VcnClkLevelsEnabled;
+		break;
+	case SMU_DCLK:
+		*count = clk_table->VcnClkLevelsEnabled;
+		break;
+	case SMU_MCLK:
+		*count = clk_table->NumDfPstatesEnabled;
+		break;
+	case SMU_FCLK:
+		*count = clk_table->NumDfPstatesEnabled;
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
+						enum smu_clk_type clk_type,
+						uint32_t dpm_level,
+						uint32_t *freq)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+	if (!clk_table || clk_type >= SMU_CLK_COUNT)
+		return -EINVAL;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+		if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->SocClocks[dpm_level];
+		break;
+	case SMU_VCLK:
+		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->VClocks[dpm_level];
+		break;
+	case SMU_DCLK:
+		if (dpm_level >= clk_table->VcnClkLevelsEnabled)
+			return -EINVAL;
+		*freq = clk_table->DClocks[dpm_level];
+		break;
+	case SMU_UCLK:
+	case SMU_MCLK:
+		if (dpm_level >= clk_table->NumDfPstatesEnabled)
+			return -EINVAL;
+		*freq = clk_table->DfPstateTable[dpm_level].MemClk;
+		break;
+	case SMU_FCLK:
+		if (dpm_level >= clk_table->NumDfPstatesEnabled)
+			return -EINVAL;
+		*freq = clk_table->DfPstateTable[dpm_level].FClk;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
+						enum smu_clk_type clk_type)
+{
+	enum smu_feature_mask feature_id = 0;
+
+	switch (clk_type) {
+	case SMU_MCLK:
+	case SMU_UCLK:
+	case SMU_FCLK:
+		feature_id = SMU_FEATURE_DPM_FCLK_BIT;
+		break;
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
+		break;
+	case SMU_SOCCLK:
+		feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
+		break;
+	case SMU_VCLK:
+	case SMU_DCLK:
+		feature_id = SMU_FEATURE_VCN_DPM_BIT;
+		break;
+	default:
+		return true;
+	}
+
+	return smu_cmn_feature_is_enabled(smu, feature_id);
+}
+
+static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
+							enum smu_clk_type clk_type,
+							uint32_t *min,
+							uint32_t *max)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+	uint32_t clock_limit;
+	uint32_t max_dpm_level, min_dpm_level;
+	int ret = 0;
+
+	if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
+		switch (clk_type) {
+		case SMU_MCLK:
+		case SMU_UCLK:
+			clock_limit = smu->smu_table.boot_values.uclk;
+			break;
+		case SMU_FCLK:
+			clock_limit = smu->smu_table.boot_values.fclk;
+			break;
+		case SMU_GFXCLK:
+		case SMU_SCLK:
+			clock_limit = smu->smu_table.boot_values.gfxclk;
+			break;
+		case SMU_SOCCLK:
+			clock_limit = smu->smu_table.boot_values.socclk;
+			break;
+		case SMU_VCLK:
+			clock_limit = smu->smu_table.boot_values.vclk;
+			break;
+		case SMU_DCLK:
+			clock_limit = smu->smu_table.boot_values.dclk;
+			break;
+		default:
+			clock_limit = 0;
+			break;
+		}
+
+		/* clock in Mhz unit */
+		if (min)
+			*min = clock_limit / 100;
+		if (max)
+			*max = clock_limit / 100;
+
+		return 0;
+	}
+
+	if (max) {
+		switch (clk_type) {
+		case SMU_GFXCLK:
+		case SMU_SCLK:
+			*max = clk_table->MaxGfxClk;
+			break;
+		case SMU_MCLK:
+		case SMU_UCLK:
+		case SMU_FCLK:
+			max_dpm_level = 0;
+			break;
+		case SMU_SOCCLK:
+			max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
+			break;
+		case SMU_VCLK:
+		case SMU_DCLK:
+			max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
+			break;
+		default:
+			ret = -EINVAL;
+			goto failed;
+		}
+
+		if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
+			ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
+			if (ret)
+				goto failed;
+		}
+	}
+
+	if (min) {
+		switch (clk_type) {
+		case SMU_GFXCLK:
+		case SMU_SCLK:
+			*min = clk_table->MinGfxClk;
+			break;
+		case SMU_MCLK:
+		case SMU_UCLK:
+		case SMU_FCLK:
+			min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
+			break;
+		case SMU_SOCCLK:
+			min_dpm_level = 0;
+			break;
+		case SMU_VCLK:
+		case SMU_DCLK:
+			min_dpm_level = 0;
+			break;
+		default:
+			ret = -EINVAL;
+			goto failed;
+		}
+
+		if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
+			ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
+			if (ret)
+				goto failed;
+		}
+	}
+
+failed:
+	return ret;
+}
+
+static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
+							enum smu_clk_type clk_type,
+							uint32_t min,
+							uint32_t max)
+{
+	enum smu_message_type msg_set_min, msg_set_max;
+	int ret = 0;
+
+	if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
+		return -EINVAL;
+
+	switch (clk_type) {
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		msg_set_min = SMU_MSG_SetHardMinGfxClk;
+		msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
+		break;
+	case SMU_FCLK:
+		msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
+		msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
+		break;
+	case SMU_SOCCLK:
+		msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
+		msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
+		break;
+	case SMU_VCLK:
+	case SMU_DCLK:
+		msg_set_min = SMU_MSG_SetHardMinVcn;
+		msg_set_max = SMU_MSG_SetSoftMaxVcn;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
+	if (ret)
+		goto out;
+
+	ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
+	if (ret)
+		goto out;
+
+out:
+	return ret;
+}
+
+static int yellow_carp_print_clk_levels(struct smu_context *smu,
+				enum smu_clk_type clk_type, char *buf)
+{
+	int i, size = 0, ret = 0;
+	uint32_t cur_value = 0, value = 0, count = 0;
+
+	switch (clk_type) {
+	case SMU_OD_SCLK:
+		size = sprintf(buf, "%s:\n", "OD_SCLK");
+		size += sprintf(buf + size, "0: %10uMhz\n",
+		(smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
+		size += sprintf(buf + size, "1: %10uMhz\n",
+		(smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
+		break;
+	case SMU_OD_RANGE:
+		size = sprintf(buf, "%s:\n", "OD_RANGE");
+		size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
+						smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
+		break;
+	case SMU_SOCCLK:
+	case SMU_VCLK:
+	case SMU_DCLK:
+	case SMU_MCLK:
+	case SMU_FCLK:
+		ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
+		if (ret)
+			goto print_clk_out;
+
+		ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
+		if (ret)
+			goto print_clk_out;
+
+		for (i = 0; i < count; i++) {
+			ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value);
+			if (ret)
+				goto print_clk_out;
+
+			size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+					cur_value == value ? "*" : "");
+		}
+		break;
+	default:
+		break;
+	}
+
+print_clk_out:
+	return size;
+}
+
+static int yellow_carp_force_clk_levels(struct smu_context *smu,
+				enum smu_clk_type clk_type, uint32_t mask)
+{
+	uint32_t soft_min_level = 0, soft_max_level = 0;
+	uint32_t min_freq = 0, max_freq = 0;
+	int ret = 0;
+
+	soft_min_level = mask ? (ffs(mask) - 1) : 0;
+	soft_max_level = mask ? (fls(mask) - 1) : 0;
+
+	switch (clk_type) {
+	case SMU_SOCCLK:
+	case SMU_FCLK:
+	case SMU_VCLK:
+	case SMU_DCLK:
+		ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
+		if (ret)
+			goto force_level_out;
+
+		ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
+		if (ret)
+			goto force_level_out;
+
+		ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
+		if (ret)
+			goto force_level_out;
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+force_level_out:
+	return ret;
+}
+
+static int yellow_carp_set_performance_level(struct smu_context *smu,
+						enum amd_dpm_forced_level level)
+{
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t sclk_min = 0, sclk_max = 0;
+	uint32_t fclk_min = 0, fclk_max = 0;
+	uint32_t socclk_min = 0, socclk_max = 0;
+	int ret = 0;
+
+	switch (level) {
+	case AMD_DPM_FORCED_LEVEL_HIGH:
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
+		sclk_min = sclk_max;
+		fclk_min = fclk_max;
+		socclk_min = socclk_max;
+		break;
+	case AMD_DPM_FORCED_LEVEL_LOW:
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
+		sclk_max = sclk_min;
+		fclk_max = fclk_min;
+		socclk_max = socclk_min;
+		break;
+	case AMD_DPM_FORCED_LEVEL_AUTO:
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
+		yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
+		break;
+	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+		/* Temporarily do nothing since the optimal clocks haven't been provided yet */
+		break;
+	case AMD_DPM_FORCED_LEVEL_MANUAL:
+	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+		return 0;
+	default:
+		dev_err(adev->dev, "Invalid performance level %d\n", level);
+		return -EINVAL;
+	}
+
+	if (sclk_min && sclk_max) {
+		ret = yellow_carp_set_soft_freq_limited_range(smu,
+							    SMU_SCLK,
+							    sclk_min,
+							    sclk_max);
+		if (ret)
+			return ret;
+
+		smu->gfx_actual_hard_min_freq = sclk_min;
+		smu->gfx_actual_soft_max_freq = sclk_max;
+	}
+
+	if (fclk_min && fclk_max) {
+		ret = yellow_carp_set_soft_freq_limited_range(smu,
+							    SMU_FCLK,
+							    fclk_min,
+							    fclk_max);
+		if (ret)
+			return ret;
+	}
+
+	if (socclk_min && socclk_max) {
+		ret = yellow_carp_set_soft_freq_limited_range(smu,
+							    SMU_SOCCLK,
+							    socclk_min,
+							    socclk_max);
+		if (ret)
+			return ret;
+	}
+
+	return ret;
+}
+
+static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
+{
+	DpmClocks_t *clk_table = smu->smu_table.clocks_table;
+
+	smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
+	smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
+	smu->gfx_actual_hard_min_freq = 0;
+	smu->gfx_actual_soft_max_freq = 0;
+
+	return 0;
+}
+
+static const struct pptable_funcs yellow_carp_ppt_funcs = {
+	.check_fw_status = smu_v13_0_1_check_fw_status,
+	.check_fw_version = smu_v13_0_1_check_fw_version,
+	.init_smc_tables = yellow_carp_init_smc_tables,
+	.fini_smc_tables = smu_v13_0_1_fini_smc_tables,
+	.get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values,
+	.system_features_control = yellow_carp_system_features_control,
+	.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
+	.send_smc_msg = smu_cmn_send_smc_msg,
+	.dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
+	.dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
+	.set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables,
+	.read_sensor = yellow_carp_read_sensor,
+	.is_dpm_running = yellow_carp_is_dpm_running,
+	.set_watermarks_table = yellow_carp_set_watermarks_table,
+	.get_power_profile_mode = yellow_carp_get_power_profile_mode,
+	.set_power_profile_mode = yellow_carp_set_power_profile_mode,
+	.get_gpu_metrics = yellow_carp_get_gpu_metrics,
+	.get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
+	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
+	.set_driver_table_location = smu_v13_0_1_set_driver_table_location,
+	.gfx_off_control = smu_v13_0_1_gfx_off_control,
+	.post_init = yellow_carp_post_smu_init,
+	.mode2_reset = yellow_carp_mode2_reset,
+	.get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
+	.od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
+	.print_clk_levels = yellow_carp_print_clk_levels,
+	.force_clk_levels = yellow_carp_force_clk_levels,
+	.set_performance_level = yellow_carp_set_performance_level,
+	.set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
+};
+
+void yellow_carp_set_ppt_funcs(struct smu_context *smu)
+{
+	smu->ppt_funcs = &yellow_carp_ppt_funcs;
+	smu->message_map = yellow_carp_message_map;
+	smu->feature_map = yellow_carp_feature_mask_map;
+	smu->table_map = yellow_carp_table_map;
+	smu->workload_map = yellow_carp_workload_map;
+	smu->is_apu = true;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
new file mode 100644
index 000000000000..b3ad8352c68a
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __YELLOW_CARP_PPT_H__
+#define __YELLOW_CARP_PPT_H__
+
+extern void yellow_carp_set_ppt_funcs(struct smu_context *smu);
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 1f5b1a5c0a09..2ea86919d953 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -152,9 +152,11 @@ int radeon_uvd_init(struct radeon_device *rdev)
 
 			rdev->uvd.fw_header_present = true;
 
-			family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
-			version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
-			version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
+			family_id = (__force u32)(hdr->ucode_version) & 0xff;
+			version_major = (le32_to_cpu((__force __le32)(hdr->ucode_version))
+							 >> 24) & 0xff;
+			version_minor = (le32_to_cpu((__force __le32)(hdr->ucode_version))
+							 >> 8) & 0xff;
 			DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n",
 				 version_major, version_minor, family_id);
 
@@ -286,7 +288,7 @@ int radeon_uvd_resume(struct radeon_device *rdev)
 	if (rdev->uvd.vcpu_bo == NULL)
 		return -EINVAL;
 
-	memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
+	memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size);
 
 	size = radeon_bo_size(rdev->uvd.vcpu_bo);
 	size -= rdev->uvd_fw->size;
@@ -294,7 +296,7 @@ int radeon_uvd_resume(struct radeon_device *rdev)
 	ptr = rdev->uvd.cpu_addr;
 	ptr += rdev->uvd_fw->size;
 
-	memset(ptr, 0, size);
+	memset_io((void __iomem *)ptr, 0, size);
 
 	return 0;
 }
@@ -791,17 +793,17 @@ int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
 		return r;
 
 	/* stitch together an UVD create msg */
-	writel(cpu_to_le32(0x00000de4), &msg[0]);
+	writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
 	writel(0x0, (void __iomem *)&msg[1]);
-	writel(cpu_to_le32(handle), &msg[2]);
+	writel((__force u32)cpu_to_le32(handle), &msg[2]);
 	writel(0x0, &msg[3]);
 	writel(0x0, &msg[4]);
 	writel(0x0, &msg[5]);
 	writel(0x0, &msg[6]);
-	writel(cpu_to_le32(0x00000780), &msg[7]);
-	writel(cpu_to_le32(0x00000440), &msg[8]);
+	writel((__force u32)cpu_to_le32(0x00000780), &msg[7]);
+	writel((__force u32)cpu_to_le32(0x00000440), &msg[8]);
 	writel(0x0, &msg[9]);
-	writel(cpu_to_le32(0x01b37000), &msg[10]);
+	writel((__force u32)cpu_to_le32(0x01b37000), &msg[10]);
 	for (i = 11; i < 1024; ++i)
 		writel(0x0, &msg[i]);
 
@@ -827,9 +829,9 @@ int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
 		return r;
 
 	/* stitch together an UVD destroy msg */
-	writel(cpu_to_le32(0x00000de4), &msg[0]);
-	writel(cpu_to_le32(0x00000002), &msg[1]);
-	writel(cpu_to_le32(handle), &msg[2]);
+	writel((__force u32)cpu_to_le32(0x00000de4), &msg[0]);
+	writel((__force u32)cpu_to_le32(0x00000002), &msg[1]);
+	writel((__force u32)cpu_to_le32(handle), &msg[2]);
 	writel(0x0, &msg[3]);
 	for (i = 4; i < 1024; ++i)
 		writel(0x0, &msg[i]);
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
index 02f703ec4230..0bf0ad869eb9 100644
--- a/include/drm/amd_asic_type.h
+++ b/include/drm/amd_asic_type.h
@@ -60,6 +60,7 @@ enum amd_asic_type {
 	CHIP_VANGOGH,	/* 31 */
 	CHIP_DIMGREY_CAVEFISH,	/* 32 */
 	CHIP_BEIGE_GOBY,	/* 33 */
+	CHIP_YELLOW_CARP,	/* 34 */
 	CHIP_LAST,
 };
 
diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h
index 8f1350e599eb..1701c2128a5c 100644
--- a/include/drm/drm_atomic.h
+++ b/include/drm/drm_atomic.h
@@ -898,6 +898,10 @@ void drm_state_dump(struct drm_device *dev, struct drm_printer *p);
 /**
  * for_each_new_plane_in_state_reverse - other than only tracking new state,
  * it's the same as for_each_oldnew_plane_in_state_reverse
+ * @__state: &struct drm_atomic_state pointer
+ * @plane: &struct drm_plane iteration cursor
+ * @new_plane_state: &struct drm_plane_state iteration cursor for the new state
+ * @__i: int iteration cursor, for macro-internal use
  */
 #define for_each_new_plane_in_state_reverse(__state, plane, new_plane_state, __i) \
 	for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1);	\
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 91a23187902e..0cbd1540aeac 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -1134,6 +1134,7 @@ struct drm_amdgpu_info_video_caps {
 #define AMDGPU_FAMILY_RV			142 /* Raven */
 #define AMDGPU_FAMILY_NV			143 /* Navi10 */
 #define AMDGPU_FAMILY_VGH			144 /* Van Gogh */
+#define AMDGPU_FAMILY_YC			146 /* Yellow Carp */
 
 #if defined(__cplusplus)
 }
author	Dave Airlie <airlied@redhat.com>	2021-06-10 13:47:12 +1000
committer	Dave Airlie <airlied@redhat.com>	2021-06-10 13:47:13 +1000
commit	c707b73f0cfb1acc94a20389aecde65e6385349b (patch)
tree	be2d0069c38a87c4f2e6c4d3e7097d5ee672a3bb
parent	Merge tag 'drm-intel-next-2021-06-09' of git://anongit.freedesktop.org/drm/drm-intel into drm-next (diff)
parent	drm/amdgpu/vcn: drop gfxoff control for VCN2+ (diff)
download	linux-dev-c707b73f0cfb1acc94a20389aecde65e6385349b.tar.xz linux-dev-c707b73f0cfb1acc94a20389aecde65e6385349b.zip